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comparison Common/Drivers/STM32F4xx_HAL_DRIVER_v120/Src/stm32f4xx_hal_tim.c @ 38:5f11787b4f42
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author | heinrichsweikamp |
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date | Sat, 28 Apr 2018 11:52:34 +0200 |
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1 /** | |
2 ****************************************************************************** | |
3 * @file stm32f4xx_hal_tim.c | |
4 * @author MCD Application Team | |
5 * @version V1.2.0 | |
6 * @date 26-December-2014 | |
7 * @brief TIM HAL module driver. | |
8 * This file provides firmware functions to manage the following | |
9 * functionalities of the Timer (TIM) peripheral: | |
10 * + Time Base Initialization | |
11 * + Time Base Start | |
12 * + Time Base Start Interruption | |
13 * + Time Base Start DMA | |
14 * + Time Output Compare/PWM Initialization | |
15 * + Time Output Compare/PWM Channel Configuration | |
16 * + Time Output Compare/PWM Start | |
17 * + Time Output Compare/PWM Start Interruption | |
18 * + Time Output Compare/PWM Start DMA | |
19 * + Time Input Capture Initialization | |
20 * + Time Input Capture Channel Configuration | |
21 * + Time Input Capture Start | |
22 * + Time Input Capture Start Interruption | |
23 * + Time Input Capture Start DMA | |
24 * + Time One Pulse Initialization | |
25 * + Time One Pulse Channel Configuration | |
26 * + Time One Pulse Start | |
27 * + Time Encoder Interface Initialization | |
28 * + Time Encoder Interface Start | |
29 * + Time Encoder Interface Start Interruption | |
30 * + Time Encoder Interface Start DMA | |
31 * + Commutation Event configuration with Interruption and DMA | |
32 * + Time OCRef clear configuration | |
33 * + Time External Clock configuration | |
34 @verbatim | |
35 ============================================================================== | |
36 ##### TIMER Generic features ##### | |
37 ============================================================================== | |
38 [..] The Timer features include: | |
39 (#) 16-bit up, down, up/down auto-reload counter. | |
40 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the | |
41 counter clock frequency either by any factor between 1 and 65536. | |
42 (#) Up to 4 independent channels for: | |
43 (++) Input Capture | |
44 (++) Output Compare | |
45 (++) PWM generation (Edge and Center-aligned Mode) | |
46 (++) One-pulse mode output | |
47 | |
48 ##### How to use this driver ##### | |
49 ============================================================================== | |
50 [..] | |
51 (#) Initialize the TIM low level resources by implementing the following functions | |
52 depending from feature used : | |
53 (++) Time Base : HAL_TIM_Base_MspInit() | |
54 (++) Input Capture : HAL_TIM_IC_MspInit() | |
55 (++) Output Compare : HAL_TIM_OC_MspInit() | |
56 (++) PWM generation : HAL_TIM_PWM_MspInit() | |
57 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() | |
58 (++) Encoder mode output : HAL_TIM_Encoder_MspInit() | |
59 | |
60 (#) Initialize the TIM low level resources : | |
61 (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE(); | |
62 (##) TIM pins configuration | |
63 (+++) Enable the clock for the TIM GPIOs using the following function: | |
64 __GPIOx_CLK_ENABLE(); | |
65 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); | |
66 | |
67 (#) The external Clock can be configured, if needed (the default clock is the | |
68 internal clock from the APBx), using the following function: | |
69 HAL_TIM_ConfigClockSource, the clock configuration should be done before | |
70 any start function. | |
71 | |
72 (#) Configure the TIM in the desired functioning mode using one of the | |
73 initialization function of this driver: | |
74 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base | |
75 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an | |
76 Output Compare signal. | |
77 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a | |
78 PWM signal. | |
79 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an | |
80 external signal. | |
81 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer | |
82 in One Pulse Mode. | |
83 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. | |
84 | |
85 (#) Activate the TIM peripheral using one of the start functions depending from the feature used: | |
86 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() | |
87 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() | |
88 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() | |
89 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() | |
90 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() | |
91 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). | |
92 | |
93 (#) The DMA Burst is managed with the two following functions: | |
94 HAL_TIM_DMABurst_WriteStart() | |
95 HAL_TIM_DMABurst_ReadStart() | |
96 | |
97 @endverbatim | |
98 ****************************************************************************** | |
99 * @attention | |
100 * | |
101 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> | |
102 * | |
103 * Redistribution and use in source and binary forms, with or without modification, | |
104 * are permitted provided that the following conditions are met: | |
105 * 1. Redistributions of source code must retain the above copyright notice, | |
106 * this list of conditions and the following disclaimer. | |
107 * 2. Redistributions in binary form must reproduce the above copyright notice, | |
108 * this list of conditions and the following disclaimer in the documentation | |
109 * and/or other materials provided with the distribution. | |
110 * 3. Neither the name of STMicroelectronics nor the names of its contributors | |
111 * may be used to endorse or promote products derived from this software | |
112 * without specific prior written permission. | |
113 * | |
114 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
115 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
116 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
117 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE | |
118 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
119 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
120 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER | |
121 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | |
122 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
123 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
124 * | |
125 ****************************************************************************** | |
126 */ | |
127 | |
128 /* Includes ------------------------------------------------------------------*/ | |
129 #include "stm32f4xx_hal.h" | |
130 | |
131 /** @addtogroup STM32F4xx_HAL_Driver | |
132 * @{ | |
133 */ | |
134 | |
135 /** @defgroup TIM TIM | |
136 * @brief TIM HAL module driver | |
137 * @{ | |
138 */ | |
139 | |
140 #ifdef HAL_TIM_MODULE_ENABLED | |
141 | |
142 /* Private typedef -----------------------------------------------------------*/ | |
143 /* Private define ------------------------------------------------------------*/ | |
144 /* Private macro -------------------------------------------------------------*/ | |
145 /* Private variables ---------------------------------------------------------*/ | |
146 /** @addtogroup TIM_Private_Functions | |
147 * @{ | |
148 */ | |
149 /* Private function prototypes -----------------------------------------------*/ | |
150 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); | |
151 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); | |
152 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); | |
153 | |
154 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); | |
155 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, | |
156 uint32_t TIM_ICFilter); | |
157 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); | |
158 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, | |
159 uint32_t TIM_ICFilter); | |
160 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, | |
161 uint32_t TIM_ICFilter); | |
162 | |
163 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, | |
164 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); | |
165 | |
166 static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t TIM_ITRx); | |
167 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); | |
168 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); | |
169 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, | |
170 TIM_SlaveConfigTypeDef * sSlaveConfig); | |
171 /** | |
172 * @} | |
173 */ | |
174 | |
175 /* Exported functions --------------------------------------------------------*/ | |
176 /** @defgroup TIM_Exported_Functions TIM Exported Functions | |
177 * @{ | |
178 */ | |
179 | |
180 /** @defgroup TIM_Exported_Functions_Group1 Time Base functions | |
181 * @brief Time Base functions | |
182 * | |
183 @verbatim | |
184 ============================================================================== | |
185 ##### Time Base functions ##### | |
186 ============================================================================== | |
187 [..] | |
188 This section provides functions allowing to: | |
189 (+) Initialize and configure the TIM base. | |
190 (+) De-initialize the TIM base. | |
191 (+) Start the Time Base. | |
192 (+) Stop the Time Base. | |
193 (+) Start the Time Base and enable interrupt. | |
194 (+) Stop the Time Base and disable interrupt. | |
195 (+) Start the Time Base and enable DMA transfer. | |
196 (+) Stop the Time Base and disable DMA transfer. | |
197 | |
198 @endverbatim | |
199 * @{ | |
200 */ | |
201 /** | |
202 * @brief Initializes the TIM Time base Unit according to the specified | |
203 * parameters in the TIM_HandleTypeDef and create the associated handle. | |
204 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
205 * the configuration information for TIM module. | |
206 * @retval HAL status | |
207 */ | |
208 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) | |
209 { | |
210 /* Check the TIM handle allocation */ | |
211 if(htim == NULL) | |
212 { | |
213 return HAL_ERROR; | |
214 } | |
215 | |
216 /* Check the parameters */ | |
217 assert_param(IS_TIM_INSTANCE(htim->Instance)); | |
218 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); | |
219 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); | |
220 | |
221 if(htim->State == HAL_TIM_STATE_RESET) | |
222 { | |
223 /* Init the low level hardware : GPIO, CLOCK, NVIC */ | |
224 HAL_TIM_Base_MspInit(htim); | |
225 } | |
226 | |
227 /* Set the TIM state */ | |
228 htim->State= HAL_TIM_STATE_BUSY; | |
229 | |
230 /* Set the Time Base configuration */ | |
231 TIM_Base_SetConfig(htim->Instance, &htim->Init); | |
232 | |
233 /* Initialize the TIM state*/ | |
234 htim->State= HAL_TIM_STATE_READY; | |
235 | |
236 return HAL_OK; | |
237 } | |
238 | |
239 /** | |
240 * @brief DeInitializes the TIM Base peripheral | |
241 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
242 * the configuration information for TIM module. | |
243 * @retval HAL status | |
244 */ | |
245 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) | |
246 { | |
247 /* Check the parameters */ | |
248 assert_param(IS_TIM_INSTANCE(htim->Instance)); | |
249 | |
250 htim->State = HAL_TIM_STATE_BUSY; | |
251 | |
252 /* Disable the TIM Peripheral Clock */ | |
253 __HAL_TIM_DISABLE(htim); | |
254 | |
255 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ | |
256 HAL_TIM_Base_MspDeInit(htim); | |
257 | |
258 /* Change TIM state */ | |
259 htim->State = HAL_TIM_STATE_RESET; | |
260 | |
261 /* Release Lock */ | |
262 __HAL_UNLOCK(htim); | |
263 | |
264 return HAL_OK; | |
265 } | |
266 | |
267 /** | |
268 * @brief Initializes the TIM Base MSP. | |
269 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
270 * the configuration information for TIM module. | |
271 * @retval None | |
272 */ | |
273 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) | |
274 { | |
275 /* NOTE : This function Should not be modified, when the callback is needed, | |
276 the HAL_TIM_Base_MspInit could be implemented in the user file | |
277 */ | |
278 } | |
279 | |
280 /** | |
281 * @brief DeInitializes TIM Base MSP. | |
282 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
283 * the configuration information for TIM module. | |
284 * @retval None | |
285 */ | |
286 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) | |
287 { | |
288 /* NOTE : This function Should not be modified, when the callback is needed, | |
289 the HAL_TIM_Base_MspDeInit could be implemented in the user file | |
290 */ | |
291 } | |
292 | |
293 /** | |
294 * @brief Starts the TIM Base generation. | |
295 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
296 * the configuration information for TIM module. | |
297 * @retval HAL status | |
298 */ | |
299 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) | |
300 { | |
301 /* Check the parameters */ | |
302 assert_param(IS_TIM_INSTANCE(htim->Instance)); | |
303 | |
304 /* Set the TIM state */ | |
305 htim->State= HAL_TIM_STATE_BUSY; | |
306 | |
307 /* Enable the Peripheral */ | |
308 __HAL_TIM_ENABLE(htim); | |
309 | |
310 /* Change the TIM state*/ | |
311 htim->State= HAL_TIM_STATE_READY; | |
312 | |
313 /* Return function status */ | |
314 return HAL_OK; | |
315 } | |
316 | |
317 /** | |
318 * @brief Stops the TIM Base generation. | |
319 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
320 * the configuration information for TIM module. | |
321 * @retval HAL status | |
322 */ | |
323 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) | |
324 { | |
325 /* Check the parameters */ | |
326 assert_param(IS_TIM_INSTANCE(htim->Instance)); | |
327 | |
328 /* Set the TIM state */ | |
329 htim->State= HAL_TIM_STATE_BUSY; | |
330 | |
331 /* Disable the Peripheral */ | |
332 __HAL_TIM_DISABLE(htim); | |
333 | |
334 /* Change the TIM state*/ | |
335 htim->State= HAL_TIM_STATE_READY; | |
336 | |
337 /* Return function status */ | |
338 return HAL_OK; | |
339 } | |
340 | |
341 /** | |
342 * @brief Starts the TIM Base generation in interrupt mode. | |
343 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
344 * the configuration information for TIM module. | |
345 * @retval HAL status | |
346 */ | |
347 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) | |
348 { | |
349 /* Check the parameters */ | |
350 assert_param(IS_TIM_INSTANCE(htim->Instance)); | |
351 | |
352 /* Enable the TIM Update interrupt */ | |
353 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); | |
354 | |
355 /* Enable the Peripheral */ | |
356 __HAL_TIM_ENABLE(htim); | |
357 | |
358 /* Return function status */ | |
359 return HAL_OK; | |
360 } | |
361 | |
362 /** | |
363 * @brief Stops the TIM Base generation in interrupt mode. | |
364 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
365 * the configuration information for TIM module. | |
366 * @retval HAL status | |
367 */ | |
368 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) | |
369 { | |
370 /* Check the parameters */ | |
371 assert_param(IS_TIM_INSTANCE(htim->Instance)); | |
372 /* Disable the TIM Update interrupt */ | |
373 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); | |
374 | |
375 /* Disable the Peripheral */ | |
376 __HAL_TIM_DISABLE(htim); | |
377 | |
378 /* Return function status */ | |
379 return HAL_OK; | |
380 } | |
381 | |
382 /** | |
383 * @brief Starts the TIM Base generation in DMA mode. | |
384 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
385 * the configuration information for TIM module. | |
386 * @param pData: The source Buffer address. | |
387 * @param Length: The length of data to be transferred from memory to peripheral. | |
388 * @retval HAL status | |
389 */ | |
390 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) | |
391 { | |
392 /* Check the parameters */ | |
393 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); | |
394 | |
395 if((htim->State == HAL_TIM_STATE_BUSY)) | |
396 { | |
397 return HAL_BUSY; | |
398 } | |
399 else if((htim->State == HAL_TIM_STATE_READY)) | |
400 { | |
401 if((pData == 0 ) && (Length > 0)) | |
402 { | |
403 return HAL_ERROR; | |
404 } | |
405 else | |
406 { | |
407 htim->State = HAL_TIM_STATE_BUSY; | |
408 } | |
409 } | |
410 /* Set the DMA Period elapsed callback */ | |
411 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; | |
412 | |
413 /* Set the DMA error callback */ | |
414 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; | |
415 | |
416 /* Enable the DMA Stream */ | |
417 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length); | |
418 | |
419 /* Enable the TIM Update DMA request */ | |
420 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); | |
421 | |
422 /* Enable the Peripheral */ | |
423 __HAL_TIM_ENABLE(htim); | |
424 | |
425 /* Return function status */ | |
426 return HAL_OK; | |
427 } | |
428 | |
429 /** | |
430 * @brief Stops the TIM Base generation in DMA mode. | |
431 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
432 * the configuration information for TIM module. | |
433 * @retval HAL status | |
434 */ | |
435 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) | |
436 { | |
437 /* Check the parameters */ | |
438 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); | |
439 | |
440 /* Disable the TIM Update DMA request */ | |
441 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); | |
442 | |
443 /* Disable the Peripheral */ | |
444 __HAL_TIM_DISABLE(htim); | |
445 | |
446 /* Change the htim state */ | |
447 htim->State = HAL_TIM_STATE_READY; | |
448 | |
449 /* Return function status */ | |
450 return HAL_OK; | |
451 } | |
452 /** | |
453 * @} | |
454 */ | |
455 | |
456 /** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions | |
457 * @brief Time Output Compare functions | |
458 * | |
459 @verbatim | |
460 ============================================================================== | |
461 ##### Time Output Compare functions ##### | |
462 ============================================================================== | |
463 [..] | |
464 This section provides functions allowing to: | |
465 (+) Initialize and configure the TIM Output Compare. | |
466 (+) De-initialize the TIM Output Compare. | |
467 (+) Start the Time Output Compare. | |
468 (+) Stop the Time Output Compare. | |
469 (+) Start the Time Output Compare and enable interrupt. | |
470 (+) Stop the Time Output Compare and disable interrupt. | |
471 (+) Start the Time Output Compare and enable DMA transfer. | |
472 (+) Stop the Time Output Compare and disable DMA transfer. | |
473 | |
474 @endverbatim | |
475 * @{ | |
476 */ | |
477 /** | |
478 * @brief Initializes the TIM Output Compare according to the specified | |
479 * parameters in the TIM_HandleTypeDef and create the associated handle. | |
480 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
481 * the configuration information for TIM module. | |
482 * @retval HAL status | |
483 */ | |
484 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) | |
485 { | |
486 /* Check the TIM handle allocation */ | |
487 if(htim == NULL) | |
488 { | |
489 return HAL_ERROR; | |
490 } | |
491 | |
492 /* Check the parameters */ | |
493 assert_param(IS_TIM_INSTANCE(htim->Instance)); | |
494 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); | |
495 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); | |
496 | |
497 if(htim->State == HAL_TIM_STATE_RESET) | |
498 { | |
499 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ | |
500 HAL_TIM_OC_MspInit(htim); | |
501 } | |
502 | |
503 /* Set the TIM state */ | |
504 htim->State= HAL_TIM_STATE_BUSY; | |
505 | |
506 /* Init the base time for the Output Compare */ | |
507 TIM_Base_SetConfig(htim->Instance, &htim->Init); | |
508 | |
509 /* Initialize the TIM state*/ | |
510 htim->State= HAL_TIM_STATE_READY; | |
511 | |
512 return HAL_OK; | |
513 } | |
514 | |
515 /** | |
516 * @brief DeInitializes the TIM peripheral | |
517 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
518 * the configuration information for TIM module. | |
519 * @retval HAL status | |
520 */ | |
521 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) | |
522 { | |
523 /* Check the parameters */ | |
524 assert_param(IS_TIM_INSTANCE(htim->Instance)); | |
525 | |
526 htim->State = HAL_TIM_STATE_BUSY; | |
527 | |
528 /* Disable the TIM Peripheral Clock */ | |
529 __HAL_TIM_DISABLE(htim); | |
530 | |
531 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ | |
532 HAL_TIM_OC_MspDeInit(htim); | |
533 | |
534 /* Change TIM state */ | |
535 htim->State = HAL_TIM_STATE_RESET; | |
536 | |
537 /* Release Lock */ | |
538 __HAL_UNLOCK(htim); | |
539 | |
540 return HAL_OK; | |
541 } | |
542 | |
543 /** | |
544 * @brief Initializes the TIM Output Compare MSP. | |
545 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
546 * the configuration information for TIM module. | |
547 * @retval None | |
548 */ | |
549 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) | |
550 { | |
551 /* NOTE : This function Should not be modified, when the callback is needed, | |
552 the HAL_TIM_OC_MspInit could be implemented in the user file | |
553 */ | |
554 } | |
555 | |
556 /** | |
557 * @brief DeInitializes TIM Output Compare MSP. | |
558 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
559 * the configuration information for TIM module. | |
560 * @retval None | |
561 */ | |
562 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) | |
563 { | |
564 /* NOTE : This function Should not be modified, when the callback is needed, | |
565 the HAL_TIM_OC_MspDeInit could be implemented in the user file | |
566 */ | |
567 } | |
568 | |
569 /** | |
570 * @brief Starts the TIM Output Compare signal generation. | |
571 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
572 * the configuration information for TIM module. | |
573 * @param Channel: TIM Channel to be enabled. | |
574 * This parameter can be one of the following values: | |
575 * @arg TIM_CHANNEL_1: TIM Channel 1 selected | |
576 * @arg TIM_CHANNEL_2: TIM Channel 2 selected | |
577 * @arg TIM_CHANNEL_3: TIM Channel 3 selected | |
578 * @arg TIM_CHANNEL_4: TIM Channel 4 selected | |
579 * @retval HAL status | |
580 */ | |
581 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) | |
582 { | |
583 /* Check the parameters */ | |
584 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); | |
585 | |
586 /* Enable the Output compare channel */ | |
587 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); | |
588 | |
589 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) | |
590 { | |
591 /* Enable the main output */ | |
592 __HAL_TIM_MOE_ENABLE(htim); | |
593 } | |
594 | |
595 /* Enable the Peripheral */ | |
596 __HAL_TIM_ENABLE(htim); | |
597 | |
598 /* Return function status */ | |
599 return HAL_OK; | |
600 } | |
601 | |
602 /** | |
603 * @brief Stops the TIM Output Compare signal generation. | |
604 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
605 * the configuration information for TIM module. | |
606 * @param Channel: TIM Channel to be disabled. | |
607 * This parameter can be one of the following values: | |
608 * @arg TIM_CHANNEL_1: TIM Channel 1 selected | |
609 * @arg TIM_CHANNEL_2: TIM Channel 2 selected | |
610 * @arg TIM_CHANNEL_3: TIM Channel 3 selected | |
611 * @arg TIM_CHANNEL_4: TIM Channel 4 selected | |
612 * @retval HAL status | |
613 */ | |
614 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) | |
615 { | |
616 /* Check the parameters */ | |
617 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); | |
618 | |
619 /* Disable the Output compare channel */ | |
620 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); | |
621 | |
622 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) | |
623 { | |
624 /* Disable the Main Output */ | |
625 __HAL_TIM_MOE_DISABLE(htim); | |
626 } | |
627 | |
628 /* Disable the Peripheral */ | |
629 __HAL_TIM_DISABLE(htim); | |
630 | |
631 /* Return function status */ | |
632 return HAL_OK; | |
633 } | |
634 | |
635 /** | |
636 * @brief Starts the TIM Output Compare signal generation in interrupt mode. | |
637 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
638 * the configuration information for TIM module. | |
639 * @param Channel: TIM Channel to be enabled. | |
640 * This parameter can be one of the following values: | |
641 * @arg TIM_CHANNEL_1: TIM Channel 1 selected | |
642 * @arg TIM_CHANNEL_2: TIM Channel 2 selected | |
643 * @arg TIM_CHANNEL_3: TIM Channel 3 selected | |
644 * @arg TIM_CHANNEL_4: TIM Channel 4 selected | |
645 * @retval HAL status | |
646 */ | |
647 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) | |
648 { | |
649 /* Check the parameters */ | |
650 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); | |
651 | |
652 switch (Channel) | |
653 { | |
654 case TIM_CHANNEL_1: | |
655 { | |
656 /* Enable the TIM Capture/Compare 1 interrupt */ | |
657 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); | |
658 } | |
659 break; | |
660 | |
661 case TIM_CHANNEL_2: | |
662 { | |
663 /* Enable the TIM Capture/Compare 2 interrupt */ | |
664 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); | |
665 } | |
666 break; | |
667 | |
668 case TIM_CHANNEL_3: | |
669 { | |
670 /* Enable the TIM Capture/Compare 3 interrupt */ | |
671 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); | |
672 } | |
673 break; | |
674 | |
675 case TIM_CHANNEL_4: | |
676 { | |
677 /* Enable the TIM Capture/Compare 4 interrupt */ | |
678 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); | |
679 } | |
680 break; | |
681 | |
682 default: | |
683 break; | |
684 } | |
685 | |
686 /* Enable the Output compare channel */ | |
687 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); | |
688 | |
689 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) | |
690 { | |
691 /* Enable the main output */ | |
692 __HAL_TIM_MOE_ENABLE(htim); | |
693 } | |
694 | |
695 /* Enable the Peripheral */ | |
696 __HAL_TIM_ENABLE(htim); | |
697 | |
698 /* Return function status */ | |
699 return HAL_OK; | |
700 } | |
701 | |
702 /** | |
703 * @brief Stops the TIM Output Compare signal generation in interrupt mode. | |
704 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
705 * the configuration information for TIM module. | |
706 * @param Channel: TIM Channel to be disabled. | |
707 * This parameter can be one of the following values: | |
708 * @arg TIM_CHANNEL_1: TIM Channel 1 selected | |
709 * @arg TIM_CHANNEL_2: TIM Channel 2 selected | |
710 * @arg TIM_CHANNEL_3: TIM Channel 3 selected | |
711 * @arg TIM_CHANNEL_4: TIM Channel 4 selected | |
712 * @retval HAL status | |
713 */ | |
714 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) | |
715 { | |
716 /* Check the parameters */ | |
717 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); | |
718 | |
719 switch (Channel) | |
720 { | |
721 case TIM_CHANNEL_1: | |
722 { | |
723 /* Disable the TIM Capture/Compare 1 interrupt */ | |
724 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); | |
725 } | |
726 break; | |
727 | |
728 case TIM_CHANNEL_2: | |
729 { | |
730 /* Disable the TIM Capture/Compare 2 interrupt */ | |
731 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); | |
732 } | |
733 break; | |
734 | |
735 case TIM_CHANNEL_3: | |
736 { | |
737 /* Disable the TIM Capture/Compare 3 interrupt */ | |
738 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); | |
739 } | |
740 break; | |
741 | |
742 case TIM_CHANNEL_4: | |
743 { | |
744 /* Disable the TIM Capture/Compare 4 interrupt */ | |
745 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); | |
746 } | |
747 break; | |
748 | |
749 default: | |
750 break; | |
751 } | |
752 | |
753 /* Disable the Output compare channel */ | |
754 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); | |
755 | |
756 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) | |
757 { | |
758 /* Disable the Main Output */ | |
759 __HAL_TIM_MOE_DISABLE(htim); | |
760 } | |
761 | |
762 /* Disable the Peripheral */ | |
763 __HAL_TIM_DISABLE(htim); | |
764 | |
765 /* Return function status */ | |
766 return HAL_OK; | |
767 } | |
768 | |
769 /** | |
770 * @brief Starts the TIM Output Compare signal generation in DMA mode. | |
771 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
772 * the configuration information for TIM module. | |
773 * @param Channel: TIM Channel to be enabled. | |
774 * This parameter can be one of the following values: | |
775 * @arg TIM_CHANNEL_1: TIM Channel 1 selected | |
776 * @arg TIM_CHANNEL_2: TIM Channel 2 selected | |
777 * @arg TIM_CHANNEL_3: TIM Channel 3 selected | |
778 * @arg TIM_CHANNEL_4: TIM Channel 4 selected | |
779 * @param pData: The source Buffer address. | |
780 * @param Length: The length of data to be transferred from memory to TIM peripheral | |
781 * @retval HAL status | |
782 */ | |
783 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) | |
784 { | |
785 /* Check the parameters */ | |
786 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); | |
787 | |
788 if((htim->State == HAL_TIM_STATE_BUSY)) | |
789 { | |
790 return HAL_BUSY; | |
791 } | |
792 else if((htim->State == HAL_TIM_STATE_READY)) | |
793 { | |
794 if(((uint32_t)pData == 0 ) && (Length > 0)) | |
795 { | |
796 return HAL_ERROR; | |
797 } | |
798 else | |
799 { | |
800 htim->State = HAL_TIM_STATE_BUSY; | |
801 } | |
802 } | |
803 switch (Channel) | |
804 { | |
805 case TIM_CHANNEL_1: | |
806 { | |
807 /* Set the DMA Period elapsed callback */ | |
808 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; | |
809 | |
810 /* Set the DMA error callback */ | |
811 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; | |
812 | |
813 /* Enable the DMA Stream */ | |
814 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); | |
815 | |
816 /* Enable the TIM Capture/Compare 1 DMA request */ | |
817 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); | |
818 } | |
819 break; | |
820 | |
821 case TIM_CHANNEL_2: | |
822 { | |
823 /* Set the DMA Period elapsed callback */ | |
824 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; | |
825 | |
826 /* Set the DMA error callback */ | |
827 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; | |
828 | |
829 /* Enable the DMA Stream */ | |
830 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); | |
831 | |
832 /* Enable the TIM Capture/Compare 2 DMA request */ | |
833 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); | |
834 } | |
835 break; | |
836 | |
837 case TIM_CHANNEL_3: | |
838 { | |
839 /* Set the DMA Period elapsed callback */ | |
840 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; | |
841 | |
842 /* Set the DMA error callback */ | |
843 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; | |
844 | |
845 /* Enable the DMA Stream */ | |
846 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); | |
847 | |
848 /* Enable the TIM Capture/Compare 3 DMA request */ | |
849 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); | |
850 } | |
851 break; | |
852 | |
853 case TIM_CHANNEL_4: | |
854 { | |
855 /* Set the DMA Period elapsed callback */ | |
856 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; | |
857 | |
858 /* Set the DMA error callback */ | |
859 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; | |
860 | |
861 /* Enable the DMA Stream */ | |
862 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); | |
863 | |
864 /* Enable the TIM Capture/Compare 4 DMA request */ | |
865 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); | |
866 } | |
867 break; | |
868 | |
869 default: | |
870 break; | |
871 } | |
872 | |
873 /* Enable the Output compare channel */ | |
874 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); | |
875 | |
876 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) | |
877 { | |
878 /* Enable the main output */ | |
879 __HAL_TIM_MOE_ENABLE(htim); | |
880 } | |
881 | |
882 /* Enable the Peripheral */ | |
883 __HAL_TIM_ENABLE(htim); | |
884 | |
885 /* Return function status */ | |
886 return HAL_OK; | |
887 } | |
888 | |
889 /** | |
890 * @brief Stops the TIM Output Compare signal generation in DMA mode. | |
891 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
892 * the configuration information for TIM module. | |
893 * @param Channel: TIM Channel to be disabled. | |
894 * This parameter can be one of the following values: | |
895 * @arg TIM_CHANNEL_1: TIM Channel 1 selected | |
896 * @arg TIM_CHANNEL_2: TIM Channel 2 selected | |
897 * @arg TIM_CHANNEL_3: TIM Channel 3 selected | |
898 * @arg TIM_CHANNEL_4: TIM Channel 4 selected | |
899 * @retval HAL status | |
900 */ | |
901 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) | |
902 { | |
903 /* Check the parameters */ | |
904 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); | |
905 | |
906 switch (Channel) | |
907 { | |
908 case TIM_CHANNEL_1: | |
909 { | |
910 /* Disable the TIM Capture/Compare 1 DMA request */ | |
911 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); | |
912 } | |
913 break; | |
914 | |
915 case TIM_CHANNEL_2: | |
916 { | |
917 /* Disable the TIM Capture/Compare 2 DMA request */ | |
918 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); | |
919 } | |
920 break; | |
921 | |
922 case TIM_CHANNEL_3: | |
923 { | |
924 /* Disable the TIM Capture/Compare 3 DMA request */ | |
925 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); | |
926 } | |
927 break; | |
928 | |
929 case TIM_CHANNEL_4: | |
930 { | |
931 /* Disable the TIM Capture/Compare 4 interrupt */ | |
932 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); | |
933 } | |
934 break; | |
935 | |
936 default: | |
937 break; | |
938 } | |
939 | |
940 /* Disable the Output compare channel */ | |
941 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); | |
942 | |
943 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) | |
944 { | |
945 /* Disable the Main Output */ | |
946 __HAL_TIM_MOE_DISABLE(htim); | |
947 } | |
948 | |
949 /* Disable the Peripheral */ | |
950 __HAL_TIM_DISABLE(htim); | |
951 | |
952 /* Change the htim state */ | |
953 htim->State = HAL_TIM_STATE_READY; | |
954 | |
955 /* Return function status */ | |
956 return HAL_OK; | |
957 } | |
958 /** | |
959 * @} | |
960 */ | |
961 | |
962 /** @defgroup TIM_Exported_Functions_Group3 Time PWM functions | |
963 * @brief Time PWM functions | |
964 * | |
965 @verbatim | |
966 ============================================================================== | |
967 ##### Time PWM functions ##### | |
968 ============================================================================== | |
969 [..] | |
970 This section provides functions allowing to: | |
971 (+) Initialize and configure the TIM OPWM. | |
972 (+) De-initialize the TIM PWM. | |
973 (+) Start the Time PWM. | |
974 (+) Stop the Time PWM. | |
975 (+) Start the Time PWM and enable interrupt. | |
976 (+) Stop the Time PWM and disable interrupt. | |
977 (+) Start the Time PWM and enable DMA transfer. | |
978 (+) Stop the Time PWM and disable DMA transfer. | |
979 | |
980 @endverbatim | |
981 * @{ | |
982 */ | |
983 /** | |
984 * @brief Initializes the TIM PWM Time Base according to the specified | |
985 * parameters in the TIM_HandleTypeDef and create the associated handle. | |
986 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
987 * the configuration information for TIM module. | |
988 * @retval HAL status | |
989 */ | |
990 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) | |
991 { | |
992 /* Check the TIM handle allocation */ | |
993 if(htim == NULL) | |
994 { | |
995 return HAL_ERROR; | |
996 } | |
997 | |
998 /* Check the parameters */ | |
999 assert_param(IS_TIM_INSTANCE(htim->Instance)); | |
1000 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); | |
1001 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); | |
1002 | |
1003 if(htim->State == HAL_TIM_STATE_RESET) | |
1004 { | |
1005 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ | |
1006 HAL_TIM_PWM_MspInit(htim); | |
1007 } | |
1008 | |
1009 /* Set the TIM state */ | |
1010 htim->State= HAL_TIM_STATE_BUSY; | |
1011 | |
1012 /* Init the base time for the PWM */ | |
1013 TIM_Base_SetConfig(htim->Instance, &htim->Init); | |
1014 | |
1015 /* Initialize the TIM state*/ | |
1016 htim->State= HAL_TIM_STATE_READY; | |
1017 | |
1018 return HAL_OK; | |
1019 } | |
1020 | |
1021 /** | |
1022 * @brief DeInitializes the TIM peripheral | |
1023 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
1024 * the configuration information for TIM module. | |
1025 * @retval HAL status | |
1026 */ | |
1027 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) | |
1028 { | |
1029 /* Check the parameters */ | |
1030 assert_param(IS_TIM_INSTANCE(htim->Instance)); | |
1031 | |
1032 htim->State = HAL_TIM_STATE_BUSY; | |
1033 | |
1034 /* Disable the TIM Peripheral Clock */ | |
1035 __HAL_TIM_DISABLE(htim); | |
1036 | |
1037 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ | |
1038 HAL_TIM_PWM_MspDeInit(htim); | |
1039 | |
1040 /* Change TIM state */ | |
1041 htim->State = HAL_TIM_STATE_RESET; | |
1042 | |
1043 /* Release Lock */ | |
1044 __HAL_UNLOCK(htim); | |
1045 | |
1046 return HAL_OK; | |
1047 } | |
1048 | |
1049 /** | |
1050 * @brief Initializes the TIM PWM MSP. | |
1051 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
1052 * the configuration information for TIM module. | |
1053 * @retval None | |
1054 */ | |
1055 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) | |
1056 { | |
1057 /* NOTE : This function Should not be modified, when the callback is needed, | |
1058 the HAL_TIM_PWM_MspInit could be implemented in the user file | |
1059 */ | |
1060 } | |
1061 | |
1062 /** | |
1063 * @brief DeInitializes TIM PWM MSP. | |
1064 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
1065 * the configuration information for TIM module. | |
1066 * @retval None | |
1067 */ | |
1068 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) | |
1069 { | |
1070 /* NOTE : This function Should not be modified, when the callback is needed, | |
1071 the HAL_TIM_PWM_MspDeInit could be implemented in the user file | |
1072 */ | |
1073 } | |
1074 | |
1075 /** | |
1076 * @brief Starts the PWM signal generation. | |
1077 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
1078 * the configuration information for TIM module. | |
1079 * @param Channel: TIM Channels to be enabled. | |
1080 * This parameter can be one of the following values: | |
1081 * @arg TIM_CHANNEL_1: TIM Channel 1 selected | |
1082 * @arg TIM_CHANNEL_2: TIM Channel 2 selected | |
1083 * @arg TIM_CHANNEL_3: TIM Channel 3 selected | |
1084 * @arg TIM_CHANNEL_4: TIM Channel 4 selected | |
1085 * @retval HAL status | |
1086 */ | |
1087 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) | |
1088 { | |
1089 /* Check the parameters */ | |
1090 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); | |
1091 | |
1092 /* Enable the Capture compare channel */ | |
1093 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); | |
1094 | |
1095 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) | |
1096 { | |
1097 /* Enable the main output */ | |
1098 __HAL_TIM_MOE_ENABLE(htim); | |
1099 } | |
1100 | |
1101 /* Enable the Peripheral */ | |
1102 __HAL_TIM_ENABLE(htim); | |
1103 | |
1104 /* Return function status */ | |
1105 return HAL_OK; | |
1106 } | |
1107 | |
1108 /** | |
1109 * @brief Stops the PWM signal generation. | |
1110 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
1111 * the configuration information for TIM module. | |
1112 * @param Channel: TIM Channels to be disabled. | |
1113 * This parameter can be one of the following values: | |
1114 * @arg TIM_CHANNEL_1: TIM Channel 1 selected | |
1115 * @arg TIM_CHANNEL_2: TIM Channel 2 selected | |
1116 * @arg TIM_CHANNEL_3: TIM Channel 3 selected | |
1117 * @arg TIM_CHANNEL_4: TIM Channel 4 selected | |
1118 * @retval HAL status | |
1119 */ | |
1120 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) | |
1121 { | |
1122 /* Check the parameters */ | |
1123 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); | |
1124 | |
1125 /* Disable the Capture compare channel */ | |
1126 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); | |
1127 | |
1128 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) | |
1129 { | |
1130 /* Disable the Main Output */ | |
1131 __HAL_TIM_MOE_DISABLE(htim); | |
1132 } | |
1133 | |
1134 /* Disable the Peripheral */ | |
1135 __HAL_TIM_DISABLE(htim); | |
1136 | |
1137 /* Change the htim state */ | |
1138 htim->State = HAL_TIM_STATE_READY; | |
1139 | |
1140 /* Return function status */ | |
1141 return HAL_OK; | |
1142 } | |
1143 | |
1144 /** | |
1145 * @brief Starts the PWM signal generation in interrupt mode. | |
1146 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
1147 * the configuration information for TIM module. | |
1148 * @param Channel: TIM Channel to be disabled. | |
1149 * This parameter can be one of the following values: | |
1150 * @arg TIM_CHANNEL_1: TIM Channel 1 selected | |
1151 * @arg TIM_CHANNEL_2: TIM Channel 2 selected | |
1152 * @arg TIM_CHANNEL_3: TIM Channel 3 selected | |
1153 * @arg TIM_CHANNEL_4: TIM Channel 4 selected | |
1154 * @retval HAL status | |
1155 */ | |
1156 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) | |
1157 { | |
1158 /* Check the parameters */ | |
1159 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); | |
1160 | |
1161 switch (Channel) | |
1162 { | |
1163 case TIM_CHANNEL_1: | |
1164 { | |
1165 /* Enable the TIM Capture/Compare 1 interrupt */ | |
1166 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); | |
1167 } | |
1168 break; | |
1169 | |
1170 case TIM_CHANNEL_2: | |
1171 { | |
1172 /* Enable the TIM Capture/Compare 2 interrupt */ | |
1173 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); | |
1174 } | |
1175 break; | |
1176 | |
1177 case TIM_CHANNEL_3: | |
1178 { | |
1179 /* Enable the TIM Capture/Compare 3 interrupt */ | |
1180 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); | |
1181 } | |
1182 break; | |
1183 | |
1184 case TIM_CHANNEL_4: | |
1185 { | |
1186 /* Enable the TIM Capture/Compare 4 interrupt */ | |
1187 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); | |
1188 } | |
1189 break; | |
1190 | |
1191 default: | |
1192 break; | |
1193 } | |
1194 | |
1195 /* Enable the Capture compare channel */ | |
1196 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); | |
1197 | |
1198 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) | |
1199 { | |
1200 /* Enable the main output */ | |
1201 __HAL_TIM_MOE_ENABLE(htim); | |
1202 } | |
1203 | |
1204 /* Enable the Peripheral */ | |
1205 __HAL_TIM_ENABLE(htim); | |
1206 | |
1207 /* Return function status */ | |
1208 return HAL_OK; | |
1209 } | |
1210 | |
1211 /** | |
1212 * @brief Stops the PWM signal generation in interrupt mode. | |
1213 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
1214 * the configuration information for TIM module. | |
1215 * @param Channel: TIM Channels to be disabled. | |
1216 * This parameter can be one of the following values: | |
1217 * @arg TIM_CHANNEL_1: TIM Channel 1 selected | |
1218 * @arg TIM_CHANNEL_2: TIM Channel 2 selected | |
1219 * @arg TIM_CHANNEL_3: TIM Channel 3 selected | |
1220 * @arg TIM_CHANNEL_4: TIM Channel 4 selected | |
1221 * @retval HAL status | |
1222 */ | |
1223 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel) | |
1224 { | |
1225 /* Check the parameters */ | |
1226 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); | |
1227 | |
1228 switch (Channel) | |
1229 { | |
1230 case TIM_CHANNEL_1: | |
1231 { | |
1232 /* Disable the TIM Capture/Compare 1 interrupt */ | |
1233 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); | |
1234 } | |
1235 break; | |
1236 | |
1237 case TIM_CHANNEL_2: | |
1238 { | |
1239 /* Disable the TIM Capture/Compare 2 interrupt */ | |
1240 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); | |
1241 } | |
1242 break; | |
1243 | |
1244 case TIM_CHANNEL_3: | |
1245 { | |
1246 /* Disable the TIM Capture/Compare 3 interrupt */ | |
1247 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); | |
1248 } | |
1249 break; | |
1250 | |
1251 case TIM_CHANNEL_4: | |
1252 { | |
1253 /* Disable the TIM Capture/Compare 4 interrupt */ | |
1254 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); | |
1255 } | |
1256 break; | |
1257 | |
1258 default: | |
1259 break; | |
1260 } | |
1261 | |
1262 /* Disable the Capture compare channel */ | |
1263 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); | |
1264 | |
1265 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) | |
1266 { | |
1267 /* Disable the Main Output */ | |
1268 __HAL_TIM_MOE_DISABLE(htim); | |
1269 } | |
1270 | |
1271 /* Disable the Peripheral */ | |
1272 __HAL_TIM_DISABLE(htim); | |
1273 | |
1274 /* Return function status */ | |
1275 return HAL_OK; | |
1276 } | |
1277 | |
1278 /** | |
1279 * @brief Starts the TIM PWM signal generation in DMA mode. | |
1280 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
1281 * the configuration information for TIM module. | |
1282 * @param Channel: TIM Channels to be enabled. | |
1283 * This parameter can be one of the following values: | |
1284 * @arg TIM_CHANNEL_1: TIM Channel 1 selected | |
1285 * @arg TIM_CHANNEL_2: TIM Channel 2 selected | |
1286 * @arg TIM_CHANNEL_3: TIM Channel 3 selected | |
1287 * @arg TIM_CHANNEL_4: TIM Channel 4 selected | |
1288 * @param pData: The source Buffer address. | |
1289 * @param Length: The length of data to be transferred from memory to TIM peripheral | |
1290 * @retval HAL status | |
1291 */ | |
1292 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) | |
1293 { | |
1294 /* Check the parameters */ | |
1295 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); | |
1296 | |
1297 if((htim->State == HAL_TIM_STATE_BUSY)) | |
1298 { | |
1299 return HAL_BUSY; | |
1300 } | |
1301 else if((htim->State == HAL_TIM_STATE_READY)) | |
1302 { | |
1303 if(((uint32_t)pData == 0 ) && (Length > 0)) | |
1304 { | |
1305 return HAL_ERROR; | |
1306 } | |
1307 else | |
1308 { | |
1309 htim->State = HAL_TIM_STATE_BUSY; | |
1310 } | |
1311 } | |
1312 switch (Channel) | |
1313 { | |
1314 case TIM_CHANNEL_1: | |
1315 { | |
1316 /* Set the DMA Period elapsed callback */ | |
1317 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; | |
1318 | |
1319 /* Set the DMA error callback */ | |
1320 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; | |
1321 | |
1322 /* Enable the DMA Stream */ | |
1323 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); | |
1324 | |
1325 /* Enable the TIM Capture/Compare 1 DMA request */ | |
1326 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); | |
1327 } | |
1328 break; | |
1329 | |
1330 case TIM_CHANNEL_2: | |
1331 { | |
1332 /* Set the DMA Period elapsed callback */ | |
1333 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; | |
1334 | |
1335 /* Set the DMA error callback */ | |
1336 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; | |
1337 | |
1338 /* Enable the DMA Stream */ | |
1339 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); | |
1340 | |
1341 /* Enable the TIM Capture/Compare 2 DMA request */ | |
1342 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); | |
1343 } | |
1344 break; | |
1345 | |
1346 case TIM_CHANNEL_3: | |
1347 { | |
1348 /* Set the DMA Period elapsed callback */ | |
1349 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; | |
1350 | |
1351 /* Set the DMA error callback */ | |
1352 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; | |
1353 | |
1354 /* Enable the DMA Stream */ | |
1355 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); | |
1356 | |
1357 /* Enable the TIM Output Capture/Compare 3 request */ | |
1358 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); | |
1359 } | |
1360 break; | |
1361 | |
1362 case TIM_CHANNEL_4: | |
1363 { | |
1364 /* Set the DMA Period elapsed callback */ | |
1365 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; | |
1366 | |
1367 /* Set the DMA error callback */ | |
1368 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; | |
1369 | |
1370 /* Enable the DMA Stream */ | |
1371 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); | |
1372 | |
1373 /* Enable the TIM Capture/Compare 4 DMA request */ | |
1374 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); | |
1375 } | |
1376 break; | |
1377 | |
1378 default: | |
1379 break; | |
1380 } | |
1381 | |
1382 /* Enable the Capture compare channel */ | |
1383 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); | |
1384 | |
1385 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) | |
1386 { | |
1387 /* Enable the main output */ | |
1388 __HAL_TIM_MOE_ENABLE(htim); | |
1389 } | |
1390 | |
1391 /* Enable the Peripheral */ | |
1392 __HAL_TIM_ENABLE(htim); | |
1393 | |
1394 /* Return function status */ | |
1395 return HAL_OK; | |
1396 } | |
1397 | |
1398 /** | |
1399 * @brief Stops the TIM PWM signal generation in DMA mode. | |
1400 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
1401 * the configuration information for TIM module. | |
1402 * @param Channel: TIM Channels to be disabled. | |
1403 * This parameter can be one of the following values: | |
1404 * @arg TIM_CHANNEL_1: TIM Channel 1 selected | |
1405 * @arg TIM_CHANNEL_2: TIM Channel 2 selected | |
1406 * @arg TIM_CHANNEL_3: TIM Channel 3 selected | |
1407 * @arg TIM_CHANNEL_4: TIM Channel 4 selected | |
1408 * @retval HAL status | |
1409 */ | |
1410 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) | |
1411 { | |
1412 /* Check the parameters */ | |
1413 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); | |
1414 | |
1415 switch (Channel) | |
1416 { | |
1417 case TIM_CHANNEL_1: | |
1418 { | |
1419 /* Disable the TIM Capture/Compare 1 DMA request */ | |
1420 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); | |
1421 } | |
1422 break; | |
1423 | |
1424 case TIM_CHANNEL_2: | |
1425 { | |
1426 /* Disable the TIM Capture/Compare 2 DMA request */ | |
1427 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); | |
1428 } | |
1429 break; | |
1430 | |
1431 case TIM_CHANNEL_3: | |
1432 { | |
1433 /* Disable the TIM Capture/Compare 3 DMA request */ | |
1434 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); | |
1435 } | |
1436 break; | |
1437 | |
1438 case TIM_CHANNEL_4: | |
1439 { | |
1440 /* Disable the TIM Capture/Compare 4 interrupt */ | |
1441 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); | |
1442 } | |
1443 break; | |
1444 | |
1445 default: | |
1446 break; | |
1447 } | |
1448 | |
1449 /* Disable the Capture compare channel */ | |
1450 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); | |
1451 | |
1452 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) | |
1453 { | |
1454 /* Disable the Main Output */ | |
1455 __HAL_TIM_MOE_DISABLE(htim); | |
1456 } | |
1457 | |
1458 /* Disable the Peripheral */ | |
1459 __HAL_TIM_DISABLE(htim); | |
1460 | |
1461 /* Change the htim state */ | |
1462 htim->State = HAL_TIM_STATE_READY; | |
1463 | |
1464 /* Return function status */ | |
1465 return HAL_OK; | |
1466 } | |
1467 /** | |
1468 * @} | |
1469 */ | |
1470 | |
1471 /** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions | |
1472 * @brief Time Input Capture functions | |
1473 * | |
1474 @verbatim | |
1475 ============================================================================== | |
1476 ##### Time Input Capture functions ##### | |
1477 ============================================================================== | |
1478 [..] | |
1479 This section provides functions allowing to: | |
1480 (+) Initialize and configure the TIM Input Capture. | |
1481 (+) De-initialize the TIM Input Capture. | |
1482 (+) Start the Time Input Capture. | |
1483 (+) Stop the Time Input Capture. | |
1484 (+) Start the Time Input Capture and enable interrupt. | |
1485 (+) Stop the Time Input Capture and disable interrupt. | |
1486 (+) Start the Time Input Capture and enable DMA transfer. | |
1487 (+) Stop the Time Input Capture and disable DMA transfer. | |
1488 | |
1489 @endverbatim | |
1490 * @{ | |
1491 */ | |
1492 /** | |
1493 * @brief Initializes the TIM Input Capture Time base according to the specified | |
1494 * parameters in the TIM_HandleTypeDef and create the associated handle. | |
1495 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
1496 * the configuration information for TIM module. | |
1497 * @retval HAL status | |
1498 */ | |
1499 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) | |
1500 { | |
1501 /* Check the TIM handle allocation */ | |
1502 if(htim == NULL) | |
1503 { | |
1504 return HAL_ERROR; | |
1505 } | |
1506 | |
1507 /* Check the parameters */ | |
1508 assert_param(IS_TIM_INSTANCE(htim->Instance)); | |
1509 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); | |
1510 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); | |
1511 | |
1512 if(htim->State == HAL_TIM_STATE_RESET) | |
1513 { | |
1514 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ | |
1515 HAL_TIM_IC_MspInit(htim); | |
1516 } | |
1517 | |
1518 /* Set the TIM state */ | |
1519 htim->State= HAL_TIM_STATE_BUSY; | |
1520 | |
1521 /* Init the base time for the input capture */ | |
1522 TIM_Base_SetConfig(htim->Instance, &htim->Init); | |
1523 | |
1524 /* Initialize the TIM state*/ | |
1525 htim->State= HAL_TIM_STATE_READY; | |
1526 | |
1527 return HAL_OK; | |
1528 } | |
1529 | |
1530 /** | |
1531 * @brief DeInitializes the TIM peripheral | |
1532 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
1533 * the configuration information for TIM module. | |
1534 * @retval HAL status | |
1535 */ | |
1536 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) | |
1537 { | |
1538 /* Check the parameters */ | |
1539 assert_param(IS_TIM_INSTANCE(htim->Instance)); | |
1540 | |
1541 htim->State = HAL_TIM_STATE_BUSY; | |
1542 | |
1543 /* Disable the TIM Peripheral Clock */ | |
1544 __HAL_TIM_DISABLE(htim); | |
1545 | |
1546 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ | |
1547 HAL_TIM_IC_MspDeInit(htim); | |
1548 | |
1549 /* Change TIM state */ | |
1550 htim->State = HAL_TIM_STATE_RESET; | |
1551 | |
1552 /* Release Lock */ | |
1553 __HAL_UNLOCK(htim); | |
1554 | |
1555 return HAL_OK; | |
1556 } | |
1557 | |
1558 /** | |
1559 * @brief Initializes the TIM INput Capture MSP. | |
1560 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
1561 * the configuration information for TIM module. | |
1562 * @retval None | |
1563 */ | |
1564 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) | |
1565 { | |
1566 /* NOTE : This function Should not be modified, when the callback is needed, | |
1567 the HAL_TIM_IC_MspInit could be implemented in the user file | |
1568 */ | |
1569 } | |
1570 | |
1571 /** | |
1572 * @brief DeInitializes TIM Input Capture MSP. | |
1573 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
1574 * the configuration information for TIM module. | |
1575 * @retval None | |
1576 */ | |
1577 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) | |
1578 { | |
1579 /* NOTE : This function Should not be modified, when the callback is needed, | |
1580 the HAL_TIM_IC_MspDeInit could be implemented in the user file | |
1581 */ | |
1582 } | |
1583 | |
1584 /** | |
1585 * @brief Starts the TIM Input Capture measurement. | |
1586 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
1587 * the configuration information for TIM module. | |
1588 * @param Channel: TIM Channels to be enabled. | |
1589 * This parameter can be one of the following values: | |
1590 * @arg TIM_CHANNEL_1: TIM Channel 1 selected | |
1591 * @arg TIM_CHANNEL_2: TIM Channel 2 selected | |
1592 * @arg TIM_CHANNEL_3: TIM Channel 3 selected | |
1593 * @arg TIM_CHANNEL_4: TIM Channel 4 selected | |
1594 * @retval HAL status | |
1595 */ | |
1596 HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel) | |
1597 { | |
1598 /* Check the parameters */ | |
1599 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); | |
1600 | |
1601 /* Enable the Input Capture channel */ | |
1602 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); | |
1603 | |
1604 /* Enable the Peripheral */ | |
1605 __HAL_TIM_ENABLE(htim); | |
1606 | |
1607 /* Return function status */ | |
1608 return HAL_OK; | |
1609 } | |
1610 | |
1611 /** | |
1612 * @brief Stops the TIM Input Capture measurement. | |
1613 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
1614 * the configuration information for TIM module. | |
1615 * @param Channel: TIM Channels to be disabled. | |
1616 * This parameter can be one of the following values: | |
1617 * @arg TIM_CHANNEL_1: TIM Channel 1 selected | |
1618 * @arg TIM_CHANNEL_2: TIM Channel 2 selected | |
1619 * @arg TIM_CHANNEL_3: TIM Channel 3 selected | |
1620 * @arg TIM_CHANNEL_4: TIM Channel 4 selected | |
1621 * @retval HAL status | |
1622 */ | |
1623 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) | |
1624 { | |
1625 /* Check the parameters */ | |
1626 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); | |
1627 | |
1628 /* Disable the Input Capture channel */ | |
1629 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); | |
1630 | |
1631 /* Disable the Peripheral */ | |
1632 __HAL_TIM_DISABLE(htim); | |
1633 | |
1634 /* Return function status */ | |
1635 return HAL_OK; | |
1636 } | |
1637 | |
1638 /** | |
1639 * @brief Starts the TIM Input Capture measurement in interrupt mode. | |
1640 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
1641 * the configuration information for TIM module. | |
1642 * @param Channel: TIM Channels to be enabled. | |
1643 * This parameter can be one of the following values: | |
1644 * @arg TIM_CHANNEL_1: TIM Channel 1 selected | |
1645 * @arg TIM_CHANNEL_2: TIM Channel 2 selected | |
1646 * @arg TIM_CHANNEL_3: TIM Channel 3 selected | |
1647 * @arg TIM_CHANNEL_4: TIM Channel 4 selected | |
1648 * @retval HAL status | |
1649 */ | |
1650 HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel) | |
1651 { | |
1652 /* Check the parameters */ | |
1653 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); | |
1654 | |
1655 switch (Channel) | |
1656 { | |
1657 case TIM_CHANNEL_1: | |
1658 { | |
1659 /* Enable the TIM Capture/Compare 1 interrupt */ | |
1660 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); | |
1661 } | |
1662 break; | |
1663 | |
1664 case TIM_CHANNEL_2: | |
1665 { | |
1666 /* Enable the TIM Capture/Compare 2 interrupt */ | |
1667 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); | |
1668 } | |
1669 break; | |
1670 | |
1671 case TIM_CHANNEL_3: | |
1672 { | |
1673 /* Enable the TIM Capture/Compare 3 interrupt */ | |
1674 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); | |
1675 } | |
1676 break; | |
1677 | |
1678 case TIM_CHANNEL_4: | |
1679 { | |
1680 /* Enable the TIM Capture/Compare 4 interrupt */ | |
1681 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); | |
1682 } | |
1683 break; | |
1684 | |
1685 default: | |
1686 break; | |
1687 } | |
1688 /* Enable the Input Capture channel */ | |
1689 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); | |
1690 | |
1691 /* Enable the Peripheral */ | |
1692 __HAL_TIM_ENABLE(htim); | |
1693 | |
1694 /* Return function status */ | |
1695 return HAL_OK; | |
1696 } | |
1697 | |
1698 /** | |
1699 * @brief Stops the TIM Input Capture measurement in interrupt mode. | |
1700 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
1701 * the configuration information for TIM module. | |
1702 * @param Channel: TIM Channels to be disabled. | |
1703 * This parameter can be one of the following values: | |
1704 * @arg TIM_CHANNEL_1: TIM Channel 1 selected | |
1705 * @arg TIM_CHANNEL_2: TIM Channel 2 selected | |
1706 * @arg TIM_CHANNEL_3: TIM Channel 3 selected | |
1707 * @arg TIM_CHANNEL_4: TIM Channel 4 selected | |
1708 * @retval HAL status | |
1709 */ | |
1710 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) | |
1711 { | |
1712 /* Check the parameters */ | |
1713 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); | |
1714 | |
1715 switch (Channel) | |
1716 { | |
1717 case TIM_CHANNEL_1: | |
1718 { | |
1719 /* Disable the TIM Capture/Compare 1 interrupt */ | |
1720 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); | |
1721 } | |
1722 break; | |
1723 | |
1724 case TIM_CHANNEL_2: | |
1725 { | |
1726 /* Disable the TIM Capture/Compare 2 interrupt */ | |
1727 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); | |
1728 } | |
1729 break; | |
1730 | |
1731 case TIM_CHANNEL_3: | |
1732 { | |
1733 /* Disable the TIM Capture/Compare 3 interrupt */ | |
1734 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); | |
1735 } | |
1736 break; | |
1737 | |
1738 case TIM_CHANNEL_4: | |
1739 { | |
1740 /* Disable the TIM Capture/Compare 4 interrupt */ | |
1741 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); | |
1742 } | |
1743 break; | |
1744 | |
1745 default: | |
1746 break; | |
1747 } | |
1748 | |
1749 /* Disable the Input Capture channel */ | |
1750 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); | |
1751 | |
1752 /* Disable the Peripheral */ | |
1753 __HAL_TIM_DISABLE(htim); | |
1754 | |
1755 /* Return function status */ | |
1756 return HAL_OK; | |
1757 } | |
1758 | |
1759 /** | |
1760 * @brief Starts the TIM Input Capture measurement on in DMA mode. | |
1761 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
1762 * the configuration information for TIM module. | |
1763 * @param Channel: TIM Channels to be enabled. | |
1764 * This parameter can be one of the following values: | |
1765 * @arg TIM_CHANNEL_1: TIM Channel 1 selected | |
1766 * @arg TIM_CHANNEL_2: TIM Channel 2 selected | |
1767 * @arg TIM_CHANNEL_3: TIM Channel 3 selected | |
1768 * @arg TIM_CHANNEL_4: TIM Channel 4 selected | |
1769 * @param pData: The destination Buffer address. | |
1770 * @param Length: The length of data to be transferred from TIM peripheral to memory. | |
1771 * @retval HAL status | |
1772 */ | |
1773 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) | |
1774 { | |
1775 /* Check the parameters */ | |
1776 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); | |
1777 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); | |
1778 | |
1779 if((htim->State == HAL_TIM_STATE_BUSY)) | |
1780 { | |
1781 return HAL_BUSY; | |
1782 } | |
1783 else if((htim->State == HAL_TIM_STATE_READY)) | |
1784 { | |
1785 if((pData == 0 ) && (Length > 0)) | |
1786 { | |
1787 return HAL_ERROR; | |
1788 } | |
1789 else | |
1790 { | |
1791 htim->State = HAL_TIM_STATE_BUSY; | |
1792 } | |
1793 } | |
1794 | |
1795 switch (Channel) | |
1796 { | |
1797 case TIM_CHANNEL_1: | |
1798 { | |
1799 /* Set the DMA Period elapsed callback */ | |
1800 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; | |
1801 | |
1802 /* Set the DMA error callback */ | |
1803 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; | |
1804 | |
1805 /* Enable the DMA Stream */ | |
1806 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); | |
1807 | |
1808 /* Enable the TIM Capture/Compare 1 DMA request */ | |
1809 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); | |
1810 } | |
1811 break; | |
1812 | |
1813 case TIM_CHANNEL_2: | |
1814 { | |
1815 /* Set the DMA Period elapsed callback */ | |
1816 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; | |
1817 | |
1818 /* Set the DMA error callback */ | |
1819 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; | |
1820 | |
1821 /* Enable the DMA Stream */ | |
1822 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length); | |
1823 | |
1824 /* Enable the TIM Capture/Compare 2 DMA request */ | |
1825 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); | |
1826 } | |
1827 break; | |
1828 | |
1829 case TIM_CHANNEL_3: | |
1830 { | |
1831 /* Set the DMA Period elapsed callback */ | |
1832 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; | |
1833 | |
1834 /* Set the DMA error callback */ | |
1835 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; | |
1836 | |
1837 /* Enable the DMA Stream */ | |
1838 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length); | |
1839 | |
1840 /* Enable the TIM Capture/Compare 3 DMA request */ | |
1841 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); | |
1842 } | |
1843 break; | |
1844 | |
1845 case TIM_CHANNEL_4: | |
1846 { | |
1847 /* Set the DMA Period elapsed callback */ | |
1848 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; | |
1849 | |
1850 /* Set the DMA error callback */ | |
1851 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; | |
1852 | |
1853 /* Enable the DMA Stream */ | |
1854 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length); | |
1855 | |
1856 /* Enable the TIM Capture/Compare 4 DMA request */ | |
1857 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); | |
1858 } | |
1859 break; | |
1860 | |
1861 default: | |
1862 break; | |
1863 } | |
1864 | |
1865 /* Enable the Input Capture channel */ | |
1866 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); | |
1867 | |
1868 /* Enable the Peripheral */ | |
1869 __HAL_TIM_ENABLE(htim); | |
1870 | |
1871 /* Return function status */ | |
1872 return HAL_OK; | |
1873 } | |
1874 | |
1875 /** | |
1876 * @brief Stops the TIM Input Capture measurement on in DMA mode. | |
1877 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
1878 * the configuration information for TIM module. | |
1879 * @param Channel: TIM Channels to be disabled. | |
1880 * This parameter can be one of the following values: | |
1881 * @arg TIM_CHANNEL_1: TIM Channel 1 selected | |
1882 * @arg TIM_CHANNEL_2: TIM Channel 2 selected | |
1883 * @arg TIM_CHANNEL_3: TIM Channel 3 selected | |
1884 * @arg TIM_CHANNEL_4: TIM Channel 4 selected | |
1885 * @retval HAL status | |
1886 */ | |
1887 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) | |
1888 { | |
1889 /* Check the parameters */ | |
1890 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); | |
1891 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); | |
1892 | |
1893 switch (Channel) | |
1894 { | |
1895 case TIM_CHANNEL_1: | |
1896 { | |
1897 /* Disable the TIM Capture/Compare 1 DMA request */ | |
1898 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); | |
1899 } | |
1900 break; | |
1901 | |
1902 case TIM_CHANNEL_2: | |
1903 { | |
1904 /* Disable the TIM Capture/Compare 2 DMA request */ | |
1905 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); | |
1906 } | |
1907 break; | |
1908 | |
1909 case TIM_CHANNEL_3: | |
1910 { | |
1911 /* Disable the TIM Capture/Compare 3 DMA request */ | |
1912 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); | |
1913 } | |
1914 break; | |
1915 | |
1916 case TIM_CHANNEL_4: | |
1917 { | |
1918 /* Disable the TIM Capture/Compare 4 DMA request */ | |
1919 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); | |
1920 } | |
1921 break; | |
1922 | |
1923 default: | |
1924 break; | |
1925 } | |
1926 | |
1927 /* Disable the Input Capture channel */ | |
1928 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); | |
1929 | |
1930 /* Disable the Peripheral */ | |
1931 __HAL_TIM_DISABLE(htim); | |
1932 | |
1933 /* Change the htim state */ | |
1934 htim->State = HAL_TIM_STATE_READY; | |
1935 | |
1936 /* Return function status */ | |
1937 return HAL_OK; | |
1938 } | |
1939 /** | |
1940 * @} | |
1941 */ | |
1942 | |
1943 /** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions | |
1944 * @brief Time One Pulse functions | |
1945 * | |
1946 @verbatim | |
1947 ============================================================================== | |
1948 ##### Time One Pulse functions ##### | |
1949 ============================================================================== | |
1950 [..] | |
1951 This section provides functions allowing to: | |
1952 (+) Initialize and configure the TIM One Pulse. | |
1953 (+) De-initialize the TIM One Pulse. | |
1954 (+) Start the Time One Pulse. | |
1955 (+) Stop the Time One Pulse. | |
1956 (+) Start the Time One Pulse and enable interrupt. | |
1957 (+) Stop the Time One Pulse and disable interrupt. | |
1958 (+) Start the Time One Pulse and enable DMA transfer. | |
1959 (+) Stop the Time One Pulse and disable DMA transfer. | |
1960 | |
1961 @endverbatim | |
1962 * @{ | |
1963 */ | |
1964 /** | |
1965 * @brief Initializes the TIM One Pulse Time Base according to the specified | |
1966 * parameters in the TIM_HandleTypeDef and create the associated handle. | |
1967 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
1968 * the configuration information for TIM module. | |
1969 * @param OnePulseMode: Select the One pulse mode. | |
1970 * This parameter can be one of the following values: | |
1971 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. | |
1972 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. | |
1973 * @retval HAL status | |
1974 */ | |
1975 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) | |
1976 { | |
1977 /* Check the TIM handle allocation */ | |
1978 if(htim == NULL) | |
1979 { | |
1980 return HAL_ERROR; | |
1981 } | |
1982 | |
1983 /* Check the parameters */ | |
1984 assert_param(IS_TIM_INSTANCE(htim->Instance)); | |
1985 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); | |
1986 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); | |
1987 assert_param(IS_TIM_OPM_MODE(OnePulseMode)); | |
1988 | |
1989 if(htim->State == HAL_TIM_STATE_RESET) | |
1990 { | |
1991 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ | |
1992 HAL_TIM_OnePulse_MspInit(htim); | |
1993 } | |
1994 | |
1995 /* Set the TIM state */ | |
1996 htim->State= HAL_TIM_STATE_BUSY; | |
1997 | |
1998 /* Configure the Time base in the One Pulse Mode */ | |
1999 TIM_Base_SetConfig(htim->Instance, &htim->Init); | |
2000 | |
2001 /* Reset the OPM Bit */ | |
2002 htim->Instance->CR1 &= ~TIM_CR1_OPM; | |
2003 | |
2004 /* Configure the OPM Mode */ | |
2005 htim->Instance->CR1 |= OnePulseMode; | |
2006 | |
2007 /* Initialize the TIM state*/ | |
2008 htim->State= HAL_TIM_STATE_READY; | |
2009 | |
2010 return HAL_OK; | |
2011 } | |
2012 | |
2013 /** | |
2014 * @brief DeInitializes the TIM One Pulse | |
2015 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
2016 * the configuration information for TIM module. | |
2017 * @retval HAL status | |
2018 */ | |
2019 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) | |
2020 { | |
2021 /* Check the parameters */ | |
2022 assert_param(IS_TIM_INSTANCE(htim->Instance)); | |
2023 | |
2024 htim->State = HAL_TIM_STATE_BUSY; | |
2025 | |
2026 /* Disable the TIM Peripheral Clock */ | |
2027 __HAL_TIM_DISABLE(htim); | |
2028 | |
2029 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ | |
2030 HAL_TIM_OnePulse_MspDeInit(htim); | |
2031 | |
2032 /* Change TIM state */ | |
2033 htim->State = HAL_TIM_STATE_RESET; | |
2034 | |
2035 /* Release Lock */ | |
2036 __HAL_UNLOCK(htim); | |
2037 | |
2038 return HAL_OK; | |
2039 } | |
2040 | |
2041 /** | |
2042 * @brief Initializes the TIM One Pulse MSP. | |
2043 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
2044 * the configuration information for TIM module. | |
2045 * @retval None | |
2046 */ | |
2047 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) | |
2048 { | |
2049 /* NOTE : This function Should not be modified, when the callback is needed, | |
2050 the HAL_TIM_OnePulse_MspInit could be implemented in the user file | |
2051 */ | |
2052 } | |
2053 | |
2054 /** | |
2055 * @brief DeInitializes TIM One Pulse MSP. | |
2056 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
2057 * the configuration information for TIM module. | |
2058 * @retval None | |
2059 */ | |
2060 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) | |
2061 { | |
2062 /* NOTE : This function Should not be modified, when the callback is needed, | |
2063 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file | |
2064 */ | |
2065 } | |
2066 | |
2067 /** | |
2068 * @brief Starts the TIM One Pulse signal generation. | |
2069 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
2070 * the configuration information for TIM module. | |
2071 * @param OutputChannel : TIM Channels to be enabled. | |
2072 * This parameter can be one of the following values: | |
2073 * @arg TIM_CHANNEL_1: TIM Channel 1 selected | |
2074 * @arg TIM_CHANNEL_2: TIM Channel 2 selected | |
2075 * @retval HAL status | |
2076 */ | |
2077 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) | |
2078 { | |
2079 /* Enable the Capture compare and the Input Capture channels | |
2080 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) | |
2081 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and | |
2082 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output | |
2083 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together | |
2084 | |
2085 No need to enable the counter, it's enabled automatically by hardware | |
2086 (the counter starts in response to a stimulus and generate a pulse */ | |
2087 | |
2088 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); | |
2089 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); | |
2090 | |
2091 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) | |
2092 { | |
2093 /* Enable the main output */ | |
2094 __HAL_TIM_MOE_ENABLE(htim); | |
2095 } | |
2096 | |
2097 /* Return function status */ | |
2098 return HAL_OK; | |
2099 } | |
2100 | |
2101 /** | |
2102 * @brief Stops the TIM One Pulse signal generation. | |
2103 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
2104 * the configuration information for TIM module. | |
2105 * @param OutputChannel : TIM Channels to be disable. | |
2106 * This parameter can be one of the following values: | |
2107 * @arg TIM_CHANNEL_1: TIM Channel 1 selected | |
2108 * @arg TIM_CHANNEL_2: TIM Channel 2 selected | |
2109 * @retval HAL status | |
2110 */ | |
2111 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) | |
2112 { | |
2113 /* Disable the Capture compare and the Input Capture channels | |
2114 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) | |
2115 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and | |
2116 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output | |
2117 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ | |
2118 | |
2119 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); | |
2120 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); | |
2121 | |
2122 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) | |
2123 { | |
2124 /* Disable the Main Output */ | |
2125 __HAL_TIM_MOE_DISABLE(htim); | |
2126 } | |
2127 | |
2128 /* Disable the Peripheral */ | |
2129 __HAL_TIM_DISABLE(htim); | |
2130 | |
2131 /* Return function status */ | |
2132 return HAL_OK; | |
2133 } | |
2134 | |
2135 /** | |
2136 * @brief Starts the TIM One Pulse signal generation in interrupt mode. | |
2137 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
2138 * the configuration information for TIM module. | |
2139 * @param OutputChannel : TIM Channels to be enabled. | |
2140 * This parameter can be one of the following values: | |
2141 * @arg TIM_CHANNEL_1: TIM Channel 1 selected | |
2142 * @arg TIM_CHANNEL_2: TIM Channel 2 selected | |
2143 * @retval HAL status | |
2144 */ | |
2145 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) | |
2146 { | |
2147 /* Enable the Capture compare and the Input Capture channels | |
2148 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) | |
2149 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and | |
2150 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output | |
2151 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together | |
2152 | |
2153 No need to enable the counter, it's enabled automatically by hardware | |
2154 (the counter starts in response to a stimulus and generate a pulse */ | |
2155 | |
2156 /* Enable the TIM Capture/Compare 1 interrupt */ | |
2157 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); | |
2158 | |
2159 /* Enable the TIM Capture/Compare 2 interrupt */ | |
2160 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); | |
2161 | |
2162 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); | |
2163 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); | |
2164 | |
2165 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) | |
2166 { | |
2167 /* Enable the main output */ | |
2168 __HAL_TIM_MOE_ENABLE(htim); | |
2169 } | |
2170 | |
2171 /* Return function status */ | |
2172 return HAL_OK; | |
2173 } | |
2174 | |
2175 /** | |
2176 * @brief Stops the TIM One Pulse signal generation in interrupt mode. | |
2177 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
2178 * the configuration information for TIM module. | |
2179 * @param OutputChannel : TIM Channels to be enabled. | |
2180 * This parameter can be one of the following values: | |
2181 * @arg TIM_CHANNEL_1: TIM Channel 1 selected | |
2182 * @arg TIM_CHANNEL_2: TIM Channel 2 selected | |
2183 * @retval HAL status | |
2184 */ | |
2185 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) | |
2186 { | |
2187 /* Disable the TIM Capture/Compare 1 interrupt */ | |
2188 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); | |
2189 | |
2190 /* Disable the TIM Capture/Compare 2 interrupt */ | |
2191 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); | |
2192 | |
2193 /* Disable the Capture compare and the Input Capture channels | |
2194 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) | |
2195 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and | |
2196 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output | |
2197 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ | |
2198 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); | |
2199 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); | |
2200 | |
2201 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) | |
2202 { | |
2203 /* Disable the Main Output */ | |
2204 __HAL_TIM_MOE_DISABLE(htim); | |
2205 } | |
2206 | |
2207 /* Disable the Peripheral */ | |
2208 __HAL_TIM_DISABLE(htim); | |
2209 | |
2210 /* Return function status */ | |
2211 return HAL_OK; | |
2212 } | |
2213 /** | |
2214 * @} | |
2215 */ | |
2216 | |
2217 /** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions | |
2218 * @brief Time Encoder functions | |
2219 * | |
2220 @verbatim | |
2221 ============================================================================== | |
2222 ##### Time Encoder functions ##### | |
2223 ============================================================================== | |
2224 [..] | |
2225 This section provides functions allowing to: | |
2226 (+) Initialize and configure the TIM Encoder. | |
2227 (+) De-initialize the TIM Encoder. | |
2228 (+) Start the Time Encoder. | |
2229 (+) Stop the Time Encoder. | |
2230 (+) Start the Time Encoder and enable interrupt. | |
2231 (+) Stop the Time Encoder and disable interrupt. | |
2232 (+) Start the Time Encoder and enable DMA transfer. | |
2233 (+) Stop the Time Encoder and disable DMA transfer. | |
2234 | |
2235 @endverbatim | |
2236 * @{ | |
2237 */ | |
2238 /** | |
2239 * @brief Initializes the TIM Encoder Interface and create the associated handle. | |
2240 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
2241 * the configuration information for TIM module. | |
2242 * @param sConfig: TIM Encoder Interface configuration structure | |
2243 * @retval HAL status | |
2244 */ | |
2245 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig) | |
2246 { | |
2247 uint32_t tmpsmcr = 0; | |
2248 uint32_t tmpccmr1 = 0; | |
2249 uint32_t tmpccer = 0; | |
2250 | |
2251 /* Check the TIM handle allocation */ | |
2252 if(htim == NULL) | |
2253 { | |
2254 return HAL_ERROR; | |
2255 } | |
2256 | |
2257 /* Check the parameters */ | |
2258 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); | |
2259 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); | |
2260 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); | |
2261 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); | |
2262 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); | |
2263 assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity)); | |
2264 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); | |
2265 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); | |
2266 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); | |
2267 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); | |
2268 | |
2269 if(htim->State == HAL_TIM_STATE_RESET) | |
2270 { | |
2271 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ | |
2272 HAL_TIM_Encoder_MspInit(htim); | |
2273 } | |
2274 | |
2275 /* Set the TIM state */ | |
2276 htim->State= HAL_TIM_STATE_BUSY; | |
2277 | |
2278 /* Reset the SMS bits */ | |
2279 htim->Instance->SMCR &= ~TIM_SMCR_SMS; | |
2280 | |
2281 /* Configure the Time base in the Encoder Mode */ | |
2282 TIM_Base_SetConfig(htim->Instance, &htim->Init); | |
2283 | |
2284 /* Get the TIMx SMCR register value */ | |
2285 tmpsmcr = htim->Instance->SMCR; | |
2286 | |
2287 /* Get the TIMx CCMR1 register value */ | |
2288 tmpccmr1 = htim->Instance->CCMR1; | |
2289 | |
2290 /* Get the TIMx CCER register value */ | |
2291 tmpccer = htim->Instance->CCER; | |
2292 | |
2293 /* Set the encoder Mode */ | |
2294 tmpsmcr |= sConfig->EncoderMode; | |
2295 | |
2296 /* Select the Capture Compare 1 and the Capture Compare 2 as input */ | |
2297 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); | |
2298 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8)); | |
2299 | |
2300 /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ | |
2301 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); | |
2302 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); | |
2303 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8); | |
2304 tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12); | |
2305 | |
2306 /* Set the TI1 and the TI2 Polarities */ | |
2307 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); | |
2308 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); | |
2309 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4); | |
2310 | |
2311 /* Write to TIMx SMCR */ | |
2312 htim->Instance->SMCR = tmpsmcr; | |
2313 | |
2314 /* Write to TIMx CCMR1 */ | |
2315 htim->Instance->CCMR1 = tmpccmr1; | |
2316 | |
2317 /* Write to TIMx CCER */ | |
2318 htim->Instance->CCER = tmpccer; | |
2319 | |
2320 /* Initialize the TIM state*/ | |
2321 htim->State= HAL_TIM_STATE_READY; | |
2322 | |
2323 return HAL_OK; | |
2324 } | |
2325 | |
2326 /** | |
2327 * @brief DeInitializes the TIM Encoder interface | |
2328 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
2329 * the configuration information for TIM module. | |
2330 * @retval HAL status | |
2331 */ | |
2332 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) | |
2333 { | |
2334 /* Check the parameters */ | |
2335 assert_param(IS_TIM_INSTANCE(htim->Instance)); | |
2336 | |
2337 htim->State = HAL_TIM_STATE_BUSY; | |
2338 | |
2339 /* Disable the TIM Peripheral Clock */ | |
2340 __HAL_TIM_DISABLE(htim); | |
2341 | |
2342 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ | |
2343 HAL_TIM_Encoder_MspDeInit(htim); | |
2344 | |
2345 /* Change TIM state */ | |
2346 htim->State = HAL_TIM_STATE_RESET; | |
2347 | |
2348 /* Release Lock */ | |
2349 __HAL_UNLOCK(htim); | |
2350 | |
2351 return HAL_OK; | |
2352 } | |
2353 | |
2354 /** | |
2355 * @brief Initializes the TIM Encoder Interface MSP. | |
2356 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
2357 * the configuration information for TIM module. | |
2358 * @retval None | |
2359 */ | |
2360 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) | |
2361 { | |
2362 /* NOTE : This function Should not be modified, when the callback is needed, | |
2363 the HAL_TIM_Encoder_MspInit could be implemented in the user file | |
2364 */ | |
2365 } | |
2366 | |
2367 /** | |
2368 * @brief DeInitializes TIM Encoder Interface MSP. | |
2369 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
2370 * the configuration information for TIM module. | |
2371 * @retval None | |
2372 */ | |
2373 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) | |
2374 { | |
2375 /* NOTE : This function Should not be modified, when the callback is needed, | |
2376 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file | |
2377 */ | |
2378 } | |
2379 | |
2380 /** | |
2381 * @brief Starts the TIM Encoder Interface. | |
2382 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
2383 * the configuration information for TIM module. | |
2384 * @param Channel: TIM Channels to be enabled. | |
2385 * This parameter can be one of the following values: | |
2386 * @arg TIM_CHANNEL_1: TIM Channel 1 selected | |
2387 * @arg TIM_CHANNEL_2: TIM Channel 2 selected | |
2388 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected | |
2389 * @retval HAL status | |
2390 */ | |
2391 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) | |
2392 { | |
2393 /* Check the parameters */ | |
2394 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); | |
2395 | |
2396 /* Enable the encoder interface channels */ | |
2397 switch (Channel) | |
2398 { | |
2399 case TIM_CHANNEL_1: | |
2400 { | |
2401 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); | |
2402 break; | |
2403 } | |
2404 case TIM_CHANNEL_2: | |
2405 { | |
2406 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); | |
2407 break; | |
2408 } | |
2409 default : | |
2410 { | |
2411 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); | |
2412 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); | |
2413 break; | |
2414 } | |
2415 } | |
2416 /* Enable the Peripheral */ | |
2417 __HAL_TIM_ENABLE(htim); | |
2418 | |
2419 /* Return function status */ | |
2420 return HAL_OK; | |
2421 } | |
2422 | |
2423 /** | |
2424 * @brief Stops the TIM Encoder Interface. | |
2425 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
2426 * the configuration information for TIM module. | |
2427 * @param Channel: TIM Channels to be disabled. | |
2428 * This parameter can be one of the following values: | |
2429 * @arg TIM_CHANNEL_1: TIM Channel 1 selected | |
2430 * @arg TIM_CHANNEL_2: TIM Channel 2 selected | |
2431 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected | |
2432 * @retval HAL status | |
2433 */ | |
2434 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) | |
2435 { | |
2436 /* Check the parameters */ | |
2437 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); | |
2438 | |
2439 /* Disable the Input Capture channels 1 and 2 | |
2440 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ | |
2441 switch (Channel) | |
2442 { | |
2443 case TIM_CHANNEL_1: | |
2444 { | |
2445 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); | |
2446 break; | |
2447 } | |
2448 case TIM_CHANNEL_2: | |
2449 { | |
2450 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); | |
2451 break; | |
2452 } | |
2453 default : | |
2454 { | |
2455 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); | |
2456 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); | |
2457 break; | |
2458 } | |
2459 } | |
2460 /* Disable the Peripheral */ | |
2461 __HAL_TIM_DISABLE(htim); | |
2462 | |
2463 /* Return function status */ | |
2464 return HAL_OK; | |
2465 } | |
2466 | |
2467 /** | |
2468 * @brief Starts the TIM Encoder Interface in interrupt mode. | |
2469 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
2470 * the configuration information for TIM module. | |
2471 * @param Channel: TIM Channels to be enabled. | |
2472 * This parameter can be one of the following values: | |
2473 * @arg TIM_CHANNEL_1: TIM Channel 1 selected | |
2474 * @arg TIM_CHANNEL_2: TIM Channel 2 selected | |
2475 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected | |
2476 * @retval HAL status | |
2477 */ | |
2478 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) | |
2479 { | |
2480 /* Check the parameters */ | |
2481 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); | |
2482 | |
2483 /* Enable the encoder interface channels */ | |
2484 /* Enable the capture compare Interrupts 1 and/or 2 */ | |
2485 switch (Channel) | |
2486 { | |
2487 case TIM_CHANNEL_1: | |
2488 { | |
2489 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); | |
2490 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); | |
2491 break; | |
2492 } | |
2493 case TIM_CHANNEL_2: | |
2494 { | |
2495 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); | |
2496 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); | |
2497 break; | |
2498 } | |
2499 default : | |
2500 { | |
2501 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); | |
2502 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); | |
2503 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); | |
2504 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); | |
2505 break; | |
2506 } | |
2507 } | |
2508 | |
2509 /* Enable the Peripheral */ | |
2510 __HAL_TIM_ENABLE(htim); | |
2511 | |
2512 /* Return function status */ | |
2513 return HAL_OK; | |
2514 } | |
2515 | |
2516 /** | |
2517 * @brief Stops the TIM Encoder Interface in interrupt mode. | |
2518 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
2519 * the configuration information for TIM module. | |
2520 * @param Channel: TIM Channels to be disabled. | |
2521 * This parameter can be one of the following values: | |
2522 * @arg TIM_CHANNEL_1: TIM Channel 1 selected | |
2523 * @arg TIM_CHANNEL_2: TIM Channel 2 selected | |
2524 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected | |
2525 * @retval HAL status | |
2526 */ | |
2527 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) | |
2528 { | |
2529 /* Check the parameters */ | |
2530 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); | |
2531 | |
2532 /* Disable the Input Capture channels 1 and 2 | |
2533 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ | |
2534 if(Channel == TIM_CHANNEL_1) | |
2535 { | |
2536 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); | |
2537 | |
2538 /* Disable the capture compare Interrupts 1 */ | |
2539 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); | |
2540 } | |
2541 else if(Channel == TIM_CHANNEL_2) | |
2542 { | |
2543 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); | |
2544 | |
2545 /* Disable the capture compare Interrupts 2 */ | |
2546 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); | |
2547 } | |
2548 else | |
2549 { | |
2550 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); | |
2551 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); | |
2552 | |
2553 /* Disable the capture compare Interrupts 1 and 2 */ | |
2554 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); | |
2555 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); | |
2556 } | |
2557 | |
2558 /* Disable the Peripheral */ | |
2559 __HAL_TIM_DISABLE(htim); | |
2560 | |
2561 /* Change the htim state */ | |
2562 htim->State = HAL_TIM_STATE_READY; | |
2563 | |
2564 /* Return function status */ | |
2565 return HAL_OK; | |
2566 } | |
2567 | |
2568 /** | |
2569 * @brief Starts the TIM Encoder Interface in DMA mode. | |
2570 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
2571 * the configuration information for TIM module. | |
2572 * @param Channel: TIM Channels to be enabled. | |
2573 * This parameter can be one of the following values: | |
2574 * @arg TIM_CHANNEL_1: TIM Channel 1 selected | |
2575 * @arg TIM_CHANNEL_2: TIM Channel 2 selected | |
2576 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected | |
2577 * @param pData1: The destination Buffer address for IC1. | |
2578 * @param pData2: The destination Buffer address for IC2. | |
2579 * @param Length: The length of data to be transferred from TIM peripheral to memory. | |
2580 * @retval HAL status | |
2581 */ | |
2582 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) | |
2583 { | |
2584 /* Check the parameters */ | |
2585 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); | |
2586 | |
2587 if((htim->State == HAL_TIM_STATE_BUSY)) | |
2588 { | |
2589 return HAL_BUSY; | |
2590 } | |
2591 else if((htim->State == HAL_TIM_STATE_READY)) | |
2592 { | |
2593 if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0)) | |
2594 { | |
2595 return HAL_ERROR; | |
2596 } | |
2597 else | |
2598 { | |
2599 htim->State = HAL_TIM_STATE_BUSY; | |
2600 } | |
2601 } | |
2602 | |
2603 switch (Channel) | |
2604 { | |
2605 case TIM_CHANNEL_1: | |
2606 { | |
2607 /* Set the DMA Period elapsed callback */ | |
2608 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; | |
2609 | |
2610 /* Set the DMA error callback */ | |
2611 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; | |
2612 | |
2613 /* Enable the DMA Stream */ | |
2614 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length); | |
2615 | |
2616 /* Enable the TIM Input Capture DMA request */ | |
2617 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); | |
2618 | |
2619 /* Enable the Peripheral */ | |
2620 __HAL_TIM_ENABLE(htim); | |
2621 | |
2622 /* Enable the Capture compare channel */ | |
2623 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); | |
2624 } | |
2625 break; | |
2626 | |
2627 case TIM_CHANNEL_2: | |
2628 { | |
2629 /* Set the DMA Period elapsed callback */ | |
2630 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; | |
2631 | |
2632 /* Set the DMA error callback */ | |
2633 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; | |
2634 /* Enable the DMA Stream */ | |
2635 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length); | |
2636 | |
2637 /* Enable the TIM Input Capture DMA request */ | |
2638 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); | |
2639 | |
2640 /* Enable the Peripheral */ | |
2641 __HAL_TIM_ENABLE(htim); | |
2642 | |
2643 /* Enable the Capture compare channel */ | |
2644 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); | |
2645 } | |
2646 break; | |
2647 | |
2648 case TIM_CHANNEL_ALL: | |
2649 { | |
2650 /* Set the DMA Period elapsed callback */ | |
2651 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; | |
2652 | |
2653 /* Set the DMA error callback */ | |
2654 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; | |
2655 | |
2656 /* Enable the DMA Stream */ | |
2657 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length); | |
2658 | |
2659 /* Set the DMA Period elapsed callback */ | |
2660 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; | |
2661 | |
2662 /* Set the DMA error callback */ | |
2663 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; | |
2664 | |
2665 /* Enable the DMA Stream */ | |
2666 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length); | |
2667 | |
2668 /* Enable the Peripheral */ | |
2669 __HAL_TIM_ENABLE(htim); | |
2670 | |
2671 /* Enable the Capture compare channel */ | |
2672 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); | |
2673 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); | |
2674 | |
2675 /* Enable the TIM Input Capture DMA request */ | |
2676 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); | |
2677 /* Enable the TIM Input Capture DMA request */ | |
2678 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); | |
2679 } | |
2680 break; | |
2681 | |
2682 default: | |
2683 break; | |
2684 } | |
2685 /* Return function status */ | |
2686 return HAL_OK; | |
2687 } | |
2688 | |
2689 /** | |
2690 * @brief Stops the TIM Encoder Interface in DMA mode. | |
2691 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
2692 * the configuration information for TIM module. | |
2693 * @param Channel: TIM Channels to be enabled. | |
2694 * This parameter can be one of the following values: | |
2695 * @arg TIM_CHANNEL_1: TIM Channel 1 selected | |
2696 * @arg TIM_CHANNEL_2: TIM Channel 2 selected | |
2697 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected | |
2698 * @retval HAL status | |
2699 */ | |
2700 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) | |
2701 { | |
2702 /* Check the parameters */ | |
2703 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); | |
2704 | |
2705 /* Disable the Input Capture channels 1 and 2 | |
2706 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ | |
2707 if(Channel == TIM_CHANNEL_1) | |
2708 { | |
2709 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); | |
2710 | |
2711 /* Disable the capture compare DMA Request 1 */ | |
2712 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); | |
2713 } | |
2714 else if(Channel == TIM_CHANNEL_2) | |
2715 { | |
2716 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); | |
2717 | |
2718 /* Disable the capture compare DMA Request 2 */ | |
2719 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); | |
2720 } | |
2721 else | |
2722 { | |
2723 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); | |
2724 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); | |
2725 | |
2726 /* Disable the capture compare DMA Request 1 and 2 */ | |
2727 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); | |
2728 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); | |
2729 } | |
2730 | |
2731 /* Disable the Peripheral */ | |
2732 __HAL_TIM_DISABLE(htim); | |
2733 | |
2734 /* Change the htim state */ | |
2735 htim->State = HAL_TIM_STATE_READY; | |
2736 | |
2737 /* Return function status */ | |
2738 return HAL_OK; | |
2739 } | |
2740 /** | |
2741 * @} | |
2742 */ | |
2743 | |
2744 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management | |
2745 * @brief IRQ handler management | |
2746 * | |
2747 @verbatim | |
2748 ============================================================================== | |
2749 ##### IRQ handler management ##### | |
2750 ============================================================================== | |
2751 [..] | |
2752 This section provides Timer IRQ handler function. | |
2753 | |
2754 @endverbatim | |
2755 * @{ | |
2756 */ | |
2757 /** | |
2758 * @brief This function handles TIM interrupts requests. | |
2759 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
2760 * the configuration information for TIM module. | |
2761 * @retval None | |
2762 */ | |
2763 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) | |
2764 { | |
2765 /* Capture compare 1 event */ | |
2766 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) | |
2767 { | |
2768 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET) | |
2769 { | |
2770 { | |
2771 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); | |
2772 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; | |
2773 | |
2774 /* Input capture event */ | |
2775 if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00) | |
2776 { | |
2777 HAL_TIM_IC_CaptureCallback(htim); | |
2778 } | |
2779 /* Output compare event */ | |
2780 else | |
2781 { | |
2782 HAL_TIM_OC_DelayElapsedCallback(htim); | |
2783 HAL_TIM_PWM_PulseFinishedCallback(htim); | |
2784 } | |
2785 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; | |
2786 } | |
2787 } | |
2788 } | |
2789 /* Capture compare 2 event */ | |
2790 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) | |
2791 { | |
2792 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET) | |
2793 { | |
2794 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); | |
2795 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; | |
2796 /* Input capture event */ | |
2797 if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00) | |
2798 { | |
2799 HAL_TIM_IC_CaptureCallback(htim); | |
2800 } | |
2801 /* Output compare event */ | |
2802 else | |
2803 { | |
2804 HAL_TIM_OC_DelayElapsedCallback(htim); | |
2805 HAL_TIM_PWM_PulseFinishedCallback(htim); | |
2806 } | |
2807 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; | |
2808 } | |
2809 } | |
2810 /* Capture compare 3 event */ | |
2811 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) | |
2812 { | |
2813 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET) | |
2814 { | |
2815 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); | |
2816 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; | |
2817 /* Input capture event */ | |
2818 if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00) | |
2819 { | |
2820 HAL_TIM_IC_CaptureCallback(htim); | |
2821 } | |
2822 /* Output compare event */ | |
2823 else | |
2824 { | |
2825 HAL_TIM_OC_DelayElapsedCallback(htim); | |
2826 HAL_TIM_PWM_PulseFinishedCallback(htim); | |
2827 } | |
2828 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; | |
2829 } | |
2830 } | |
2831 /* Capture compare 4 event */ | |
2832 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) | |
2833 { | |
2834 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET) | |
2835 { | |
2836 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); | |
2837 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; | |
2838 /* Input capture event */ | |
2839 if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00) | |
2840 { | |
2841 HAL_TIM_IC_CaptureCallback(htim); | |
2842 } | |
2843 /* Output compare event */ | |
2844 else | |
2845 { | |
2846 HAL_TIM_OC_DelayElapsedCallback(htim); | |
2847 HAL_TIM_PWM_PulseFinishedCallback(htim); | |
2848 } | |
2849 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; | |
2850 } | |
2851 } | |
2852 /* TIM Update event */ | |
2853 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) | |
2854 { | |
2855 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET) | |
2856 { | |
2857 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); | |
2858 HAL_TIM_PeriodElapsedCallback(htim); | |
2859 } | |
2860 } | |
2861 /* TIM Break input event */ | |
2862 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) | |
2863 { | |
2864 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET) | |
2865 { | |
2866 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); | |
2867 HAL_TIMEx_BreakCallback(htim); | |
2868 } | |
2869 } | |
2870 /* TIM Trigger detection event */ | |
2871 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) | |
2872 { | |
2873 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET) | |
2874 { | |
2875 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); | |
2876 HAL_TIM_TriggerCallback(htim); | |
2877 } | |
2878 } | |
2879 /* TIM commutation event */ | |
2880 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) | |
2881 { | |
2882 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET) | |
2883 { | |
2884 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); | |
2885 HAL_TIMEx_CommutationCallback(htim); | |
2886 } | |
2887 } | |
2888 } | |
2889 /** | |
2890 * @} | |
2891 */ | |
2892 | |
2893 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions | |
2894 * @brief Peripheral Control functions | |
2895 * | |
2896 @verbatim | |
2897 ============================================================================== | |
2898 ##### Peripheral Control functions ##### | |
2899 ============================================================================== | |
2900 [..] | |
2901 This section provides functions allowing to: | |
2902 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. | |
2903 (+) Configure External Clock source. | |
2904 (+) Configure Complementary channels, break features and dead time. | |
2905 (+) Configure Master and the Slave synchronization. | |
2906 (+) Configure the DMA Burst Mode. | |
2907 | |
2908 @endverbatim | |
2909 * @{ | |
2910 */ | |
2911 | |
2912 /** | |
2913 * @brief Initializes the TIM Output Compare Channels according to the specified | |
2914 * parameters in the TIM_OC_InitTypeDef. | |
2915 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
2916 * the configuration information for TIM module. | |
2917 * @param sConfig: TIM Output Compare configuration structure | |
2918 * @param Channel: TIM Channels to be enabled. | |
2919 * This parameter can be one of the following values: | |
2920 * @arg TIM_CHANNEL_1: TIM Channel 1 selected | |
2921 * @arg TIM_CHANNEL_2: TIM Channel 2 selected | |
2922 * @arg TIM_CHANNEL_3: TIM Channel 3 selected | |
2923 * @arg TIM_CHANNEL_4: TIM Channel 4 selected | |
2924 * @retval HAL status | |
2925 */ | |
2926 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel) | |
2927 { | |
2928 /* Check the parameters */ | |
2929 assert_param(IS_TIM_CHANNELS(Channel)); | |
2930 assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); | |
2931 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); | |
2932 assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity)); | |
2933 assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState)); | |
2934 assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState)); | |
2935 | |
2936 /* Check input state */ | |
2937 __HAL_LOCK(htim); | |
2938 | |
2939 htim->State = HAL_TIM_STATE_BUSY; | |
2940 | |
2941 switch (Channel) | |
2942 { | |
2943 case TIM_CHANNEL_1: | |
2944 { | |
2945 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); | |
2946 /* Configure the TIM Channel 1 in Output Compare */ | |
2947 TIM_OC1_SetConfig(htim->Instance, sConfig); | |
2948 } | |
2949 break; | |
2950 | |
2951 case TIM_CHANNEL_2: | |
2952 { | |
2953 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); | |
2954 /* Configure the TIM Channel 2 in Output Compare */ | |
2955 TIM_OC2_SetConfig(htim->Instance, sConfig); | |
2956 } | |
2957 break; | |
2958 | |
2959 case TIM_CHANNEL_3: | |
2960 { | |
2961 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); | |
2962 /* Configure the TIM Channel 3 in Output Compare */ | |
2963 TIM_OC3_SetConfig(htim->Instance, sConfig); | |
2964 } | |
2965 break; | |
2966 | |
2967 case TIM_CHANNEL_4: | |
2968 { | |
2969 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); | |
2970 /* Configure the TIM Channel 4 in Output Compare */ | |
2971 TIM_OC4_SetConfig(htim->Instance, sConfig); | |
2972 } | |
2973 break; | |
2974 | |
2975 default: | |
2976 break; | |
2977 } | |
2978 htim->State = HAL_TIM_STATE_READY; | |
2979 | |
2980 __HAL_UNLOCK(htim); | |
2981 | |
2982 return HAL_OK; | |
2983 } | |
2984 | |
2985 /** | |
2986 * @brief Initializes the TIM Input Capture Channels according to the specified | |
2987 * parameters in the TIM_IC_InitTypeDef. | |
2988 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
2989 * the configuration information for TIM module. | |
2990 * @param sConfig: TIM Input Capture configuration structure | |
2991 * @param Channel: TIM Channels to be enabled. | |
2992 * This parameter can be one of the following values: | |
2993 * @arg TIM_CHANNEL_1: TIM Channel 1 selected | |
2994 * @arg TIM_CHANNEL_2: TIM Channel 2 selected | |
2995 * @arg TIM_CHANNEL_3: TIM Channel 3 selected | |
2996 * @arg TIM_CHANNEL_4: TIM Channel 4 selected | |
2997 * @retval HAL status | |
2998 */ | |
2999 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel) | |
3000 { | |
3001 /* Check the parameters */ | |
3002 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); | |
3003 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); | |
3004 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); | |
3005 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); | |
3006 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); | |
3007 | |
3008 __HAL_LOCK(htim); | |
3009 | |
3010 htim->State = HAL_TIM_STATE_BUSY; | |
3011 | |
3012 if (Channel == TIM_CHANNEL_1) | |
3013 { | |
3014 /* TI1 Configuration */ | |
3015 TIM_TI1_SetConfig(htim->Instance, | |
3016 sConfig->ICPolarity, | |
3017 sConfig->ICSelection, | |
3018 sConfig->ICFilter); | |
3019 | |
3020 /* Reset the IC1PSC Bits */ | |
3021 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; | |
3022 | |
3023 /* Set the IC1PSC value */ | |
3024 htim->Instance->CCMR1 |= sConfig->ICPrescaler; | |
3025 } | |
3026 else if (Channel == TIM_CHANNEL_2) | |
3027 { | |
3028 /* TI2 Configuration */ | |
3029 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); | |
3030 | |
3031 TIM_TI2_SetConfig(htim->Instance, | |
3032 sConfig->ICPolarity, | |
3033 sConfig->ICSelection, | |
3034 sConfig->ICFilter); | |
3035 | |
3036 /* Reset the IC2PSC Bits */ | |
3037 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; | |
3038 | |
3039 /* Set the IC2PSC value */ | |
3040 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8); | |
3041 } | |
3042 else if (Channel == TIM_CHANNEL_3) | |
3043 { | |
3044 /* TI3 Configuration */ | |
3045 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); | |
3046 | |
3047 TIM_TI3_SetConfig(htim->Instance, | |
3048 sConfig->ICPolarity, | |
3049 sConfig->ICSelection, | |
3050 sConfig->ICFilter); | |
3051 | |
3052 /* Reset the IC3PSC Bits */ | |
3053 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; | |
3054 | |
3055 /* Set the IC3PSC value */ | |
3056 htim->Instance->CCMR2 |= sConfig->ICPrescaler; | |
3057 } | |
3058 else | |
3059 { | |
3060 /* TI4 Configuration */ | |
3061 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); | |
3062 | |
3063 TIM_TI4_SetConfig(htim->Instance, | |
3064 sConfig->ICPolarity, | |
3065 sConfig->ICSelection, | |
3066 sConfig->ICFilter); | |
3067 | |
3068 /* Reset the IC4PSC Bits */ | |
3069 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; | |
3070 | |
3071 /* Set the IC4PSC value */ | |
3072 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8); | |
3073 } | |
3074 | |
3075 htim->State = HAL_TIM_STATE_READY; | |
3076 | |
3077 __HAL_UNLOCK(htim); | |
3078 | |
3079 return HAL_OK; | |
3080 } | |
3081 | |
3082 /** | |
3083 * @brief Initializes the TIM PWM channels according to the specified | |
3084 * parameters in the TIM_OC_InitTypeDef. | |
3085 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
3086 * the configuration information for TIM module. | |
3087 * @param sConfig: TIM PWM configuration structure | |
3088 * @param Channel: TIM Channels to be enabled. | |
3089 * This parameter can be one of the following values: | |
3090 * @arg TIM_CHANNEL_1: TIM Channel 1 selected | |
3091 * @arg TIM_CHANNEL_2: TIM Channel 2 selected | |
3092 * @arg TIM_CHANNEL_3: TIM Channel 3 selected | |
3093 * @arg TIM_CHANNEL_4: TIM Channel 4 selected | |
3094 * @retval HAL status | |
3095 */ | |
3096 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel) | |
3097 { | |
3098 __HAL_LOCK(htim); | |
3099 | |
3100 /* Check the parameters */ | |
3101 assert_param(IS_TIM_CHANNELS(Channel)); | |
3102 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); | |
3103 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); | |
3104 assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity)); | |
3105 assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState)); | |
3106 assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState)); | |
3107 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); | |
3108 | |
3109 htim->State = HAL_TIM_STATE_BUSY; | |
3110 | |
3111 switch (Channel) | |
3112 { | |
3113 case TIM_CHANNEL_1: | |
3114 { | |
3115 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); | |
3116 /* Configure the Channel 1 in PWM mode */ | |
3117 TIM_OC1_SetConfig(htim->Instance, sConfig); | |
3118 | |
3119 /* Set the Preload enable bit for channel1 */ | |
3120 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; | |
3121 | |
3122 /* Configure the Output Fast mode */ | |
3123 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; | |
3124 htim->Instance->CCMR1 |= sConfig->OCFastMode; | |
3125 } | |
3126 break; | |
3127 | |
3128 case TIM_CHANNEL_2: | |
3129 { | |
3130 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); | |
3131 /* Configure the Channel 2 in PWM mode */ | |
3132 TIM_OC2_SetConfig(htim->Instance, sConfig); | |
3133 | |
3134 /* Set the Preload enable bit for channel2 */ | |
3135 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; | |
3136 | |
3137 /* Configure the Output Fast mode */ | |
3138 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; | |
3139 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8; | |
3140 } | |
3141 break; | |
3142 | |
3143 case TIM_CHANNEL_3: | |
3144 { | |
3145 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); | |
3146 /* Configure the Channel 3 in PWM mode */ | |
3147 TIM_OC3_SetConfig(htim->Instance, sConfig); | |
3148 | |
3149 /* Set the Preload enable bit for channel3 */ | |
3150 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; | |
3151 | |
3152 /* Configure the Output Fast mode */ | |
3153 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; | |
3154 htim->Instance->CCMR2 |= sConfig->OCFastMode; | |
3155 } | |
3156 break; | |
3157 | |
3158 case TIM_CHANNEL_4: | |
3159 { | |
3160 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); | |
3161 /* Configure the Channel 4 in PWM mode */ | |
3162 TIM_OC4_SetConfig(htim->Instance, sConfig); | |
3163 | |
3164 /* Set the Preload enable bit for channel4 */ | |
3165 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; | |
3166 | |
3167 /* Configure the Output Fast mode */ | |
3168 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; | |
3169 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8; | |
3170 } | |
3171 break; | |
3172 | |
3173 default: | |
3174 break; | |
3175 } | |
3176 | |
3177 htim->State = HAL_TIM_STATE_READY; | |
3178 | |
3179 __HAL_UNLOCK(htim); | |
3180 | |
3181 return HAL_OK; | |
3182 } | |
3183 | |
3184 /** | |
3185 * @brief Initializes the TIM One Pulse Channels according to the specified | |
3186 * parameters in the TIM_OnePulse_InitTypeDef. | |
3187 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
3188 * the configuration information for TIM module. | |
3189 * @param sConfig: TIM One Pulse configuration structure | |
3190 * @param OutputChannel: TIM Channels to be enabled. | |
3191 * This parameter can be one of the following values: | |
3192 * @arg TIM_CHANNEL_1: TIM Channel 1 selected | |
3193 * @arg TIM_CHANNEL_2: TIM Channel 2 selected | |
3194 * @param InputChannel: TIM Channels to be enabled. | |
3195 * This parameter can be one of the following values: | |
3196 * @arg TIM_CHANNEL_1: TIM Channel 1 selected | |
3197 * @arg TIM_CHANNEL_2: TIM Channel 2 selected | |
3198 * @retval HAL status | |
3199 */ | |
3200 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel) | |
3201 { | |
3202 TIM_OC_InitTypeDef temp1; | |
3203 | |
3204 /* Check the parameters */ | |
3205 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); | |
3206 assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); | |
3207 | |
3208 if(OutputChannel != InputChannel) | |
3209 { | |
3210 __HAL_LOCK(htim); | |
3211 | |
3212 htim->State = HAL_TIM_STATE_BUSY; | |
3213 | |
3214 /* Extract the Output compare configuration from sConfig structure */ | |
3215 temp1.OCMode = sConfig->OCMode; | |
3216 temp1.Pulse = sConfig->Pulse; | |
3217 temp1.OCPolarity = sConfig->OCPolarity; | |
3218 temp1.OCNPolarity = sConfig->OCNPolarity; | |
3219 temp1.OCIdleState = sConfig->OCIdleState; | |
3220 temp1.OCNIdleState = sConfig->OCNIdleState; | |
3221 | |
3222 switch (OutputChannel) | |
3223 { | |
3224 case TIM_CHANNEL_1: | |
3225 { | |
3226 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); | |
3227 | |
3228 TIM_OC1_SetConfig(htim->Instance, &temp1); | |
3229 } | |
3230 break; | |
3231 case TIM_CHANNEL_2: | |
3232 { | |
3233 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); | |
3234 | |
3235 TIM_OC2_SetConfig(htim->Instance, &temp1); | |
3236 } | |
3237 break; | |
3238 default: | |
3239 break; | |
3240 } | |
3241 switch (InputChannel) | |
3242 { | |
3243 case TIM_CHANNEL_1: | |
3244 { | |
3245 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); | |
3246 | |
3247 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, | |
3248 sConfig->ICSelection, sConfig->ICFilter); | |
3249 | |
3250 /* Reset the IC1PSC Bits */ | |
3251 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; | |
3252 | |
3253 /* Select the Trigger source */ | |
3254 htim->Instance->SMCR &= ~TIM_SMCR_TS; | |
3255 htim->Instance->SMCR |= TIM_TS_TI1FP1; | |
3256 | |
3257 /* Select the Slave Mode */ | |
3258 htim->Instance->SMCR &= ~TIM_SMCR_SMS; | |
3259 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; | |
3260 } | |
3261 break; | |
3262 case TIM_CHANNEL_2: | |
3263 { | |
3264 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); | |
3265 | |
3266 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, | |
3267 sConfig->ICSelection, sConfig->ICFilter); | |
3268 | |
3269 /* Reset the IC2PSC Bits */ | |
3270 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; | |
3271 | |
3272 /* Select the Trigger source */ | |
3273 htim->Instance->SMCR &= ~TIM_SMCR_TS; | |
3274 htim->Instance->SMCR |= TIM_TS_TI2FP2; | |
3275 | |
3276 /* Select the Slave Mode */ | |
3277 htim->Instance->SMCR &= ~TIM_SMCR_SMS; | |
3278 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; | |
3279 } | |
3280 break; | |
3281 | |
3282 default: | |
3283 break; | |
3284 } | |
3285 | |
3286 htim->State = HAL_TIM_STATE_READY; | |
3287 | |
3288 __HAL_UNLOCK(htim); | |
3289 | |
3290 return HAL_OK; | |
3291 } | |
3292 else | |
3293 { | |
3294 return HAL_ERROR; | |
3295 } | |
3296 } | |
3297 | |
3298 /** | |
3299 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral | |
3300 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
3301 * the configuration information for TIM module. | |
3302 * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write. | |
3303 * This parameters can be on of the following values: | |
3304 * @arg TIM_DMABASE_CR1 | |
3305 * @arg TIM_DMABASE_CR2 | |
3306 * @arg TIM_DMABASE_SMCR | |
3307 * @arg TIM_DMABASE_DIER | |
3308 * @arg TIM_DMABASE_SR | |
3309 * @arg TIM_DMABASE_EGR | |
3310 * @arg TIM_DMABASE_CCMR1 | |
3311 * @arg TIM_DMABASE_CCMR2 | |
3312 * @arg TIM_DMABASE_CCER | |
3313 * @arg TIM_DMABASE_CNT | |
3314 * @arg TIM_DMABASE_PSC | |
3315 * @arg TIM_DMABASE_ARR | |
3316 * @arg TIM_DMABASE_RCR | |
3317 * @arg TIM_DMABASE_CCR1 | |
3318 * @arg TIM_DMABASE_CCR2 | |
3319 * @arg TIM_DMABASE_CCR3 | |
3320 * @arg TIM_DMABASE_CCR4 | |
3321 * @arg TIM_DMABASE_BDTR | |
3322 * @arg TIM_DMABASE_DCR | |
3323 * @param BurstRequestSrc: TIM DMA Request sources. | |
3324 * This parameters can be on of the following values: | |
3325 * @arg TIM_DMA_UPDATE: TIM update Interrupt source | |
3326 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source | |
3327 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source | |
3328 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source | |
3329 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source | |
3330 * @arg TIM_DMA_COM: TIM Commutation DMA source | |
3331 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source | |
3332 * @param BurstBuffer: The Buffer address. | |
3333 * @param BurstLength: DMA Burst length. This parameter can be one value | |
3334 * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. | |
3335 * @retval HAL status | |
3336 */ | |
3337 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, | |
3338 uint32_t* BurstBuffer, uint32_t BurstLength) | |
3339 { | |
3340 /* Check the parameters */ | |
3341 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); | |
3342 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); | |
3343 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); | |
3344 assert_param(IS_TIM_DMA_LENGTH(BurstLength)); | |
3345 | |
3346 if((htim->State == HAL_TIM_STATE_BUSY)) | |
3347 { | |
3348 return HAL_BUSY; | |
3349 } | |
3350 else if((htim->State == HAL_TIM_STATE_READY)) | |
3351 { | |
3352 if((BurstBuffer == 0 ) && (BurstLength > 0)) | |
3353 { | |
3354 return HAL_ERROR; | |
3355 } | |
3356 else | |
3357 { | |
3358 htim->State = HAL_TIM_STATE_BUSY; | |
3359 } | |
3360 } | |
3361 switch(BurstRequestSrc) | |
3362 { | |
3363 case TIM_DMA_UPDATE: | |
3364 { | |
3365 /* Set the DMA Period elapsed callback */ | |
3366 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; | |
3367 | |
3368 /* Set the DMA error callback */ | |
3369 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; | |
3370 | |
3371 /* Enable the DMA Stream */ | |
3372 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); | |
3373 } | |
3374 break; | |
3375 case TIM_DMA_CC1: | |
3376 { | |
3377 /* Set the DMA Period elapsed callback */ | |
3378 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; | |
3379 | |
3380 /* Set the DMA error callback */ | |
3381 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; | |
3382 | |
3383 /* Enable the DMA Stream */ | |
3384 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); | |
3385 } | |
3386 break; | |
3387 case TIM_DMA_CC2: | |
3388 { | |
3389 /* Set the DMA Period elapsed callback */ | |
3390 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; | |
3391 | |
3392 /* Set the DMA error callback */ | |
3393 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; | |
3394 | |
3395 /* Enable the DMA Stream */ | |
3396 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); | |
3397 } | |
3398 break; | |
3399 case TIM_DMA_CC3: | |
3400 { | |
3401 /* Set the DMA Period elapsed callback */ | |
3402 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; | |
3403 | |
3404 /* Set the DMA error callback */ | |
3405 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; | |
3406 | |
3407 /* Enable the DMA Stream */ | |
3408 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); | |
3409 } | |
3410 break; | |
3411 case TIM_DMA_CC4: | |
3412 { | |
3413 /* Set the DMA Period elapsed callback */ | |
3414 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; | |
3415 | |
3416 /* Set the DMA error callback */ | |
3417 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; | |
3418 | |
3419 /* Enable the DMA Stream */ | |
3420 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); | |
3421 } | |
3422 break; | |
3423 case TIM_DMA_COM: | |
3424 { | |
3425 /* Set the DMA Period elapsed callback */ | |
3426 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; | |
3427 | |
3428 /* Set the DMA error callback */ | |
3429 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; | |
3430 | |
3431 /* Enable the DMA Stream */ | |
3432 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); | |
3433 } | |
3434 break; | |
3435 case TIM_DMA_TRIGGER: | |
3436 { | |
3437 /* Set the DMA Period elapsed callback */ | |
3438 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; | |
3439 | |
3440 /* Set the DMA error callback */ | |
3441 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; | |
3442 | |
3443 /* Enable the DMA Stream */ | |
3444 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); | |
3445 } | |
3446 break; | |
3447 default: | |
3448 break; | |
3449 } | |
3450 /* configure the DMA Burst Mode */ | |
3451 htim->Instance->DCR = BurstBaseAddress | BurstLength; | |
3452 | |
3453 /* Enable the TIM DMA Request */ | |
3454 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); | |
3455 | |
3456 htim->State = HAL_TIM_STATE_READY; | |
3457 | |
3458 /* Return function status */ | |
3459 return HAL_OK; | |
3460 } | |
3461 | |
3462 /** | |
3463 * @brief Stops the TIM DMA Burst mode | |
3464 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
3465 * the configuration information for TIM module. | |
3466 * @param BurstRequestSrc: TIM DMA Request sources to disable | |
3467 * @retval HAL status | |
3468 */ | |
3469 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) | |
3470 { | |
3471 /* Check the parameters */ | |
3472 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); | |
3473 | |
3474 /* Abort the DMA transfer (at least disable the DMA channel) */ | |
3475 switch(BurstRequestSrc) | |
3476 { | |
3477 case TIM_DMA_UPDATE: | |
3478 { | |
3479 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); | |
3480 } | |
3481 break; | |
3482 case TIM_DMA_CC1: | |
3483 { | |
3484 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); | |
3485 } | |
3486 break; | |
3487 case TIM_DMA_CC2: | |
3488 { | |
3489 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); | |
3490 } | |
3491 break; | |
3492 case TIM_DMA_CC3: | |
3493 { | |
3494 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); | |
3495 } | |
3496 break; | |
3497 case TIM_DMA_CC4: | |
3498 { | |
3499 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); | |
3500 } | |
3501 break; | |
3502 case TIM_DMA_COM: | |
3503 { | |
3504 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]); | |
3505 } | |
3506 break; | |
3507 case TIM_DMA_TRIGGER: | |
3508 { | |
3509 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); | |
3510 } | |
3511 break; | |
3512 default: | |
3513 break; | |
3514 } | |
3515 | |
3516 /* Disable the TIM Update DMA request */ | |
3517 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); | |
3518 | |
3519 /* Return function status */ | |
3520 return HAL_OK; | |
3521 } | |
3522 | |
3523 /** | |
3524 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory | |
3525 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
3526 * the configuration information for TIM module. | |
3527 * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read. | |
3528 * This parameters can be on of the following values: | |
3529 * @arg TIM_DMABASE_CR1 | |
3530 * @arg TIM_DMABASE_CR2 | |
3531 * @arg TIM_DMABASE_SMCR | |
3532 * @arg TIM_DMABASE_DIER | |
3533 * @arg TIM_DMABASE_SR | |
3534 * @arg TIM_DMABASE_EGR | |
3535 * @arg TIM_DMABASE_CCMR1 | |
3536 * @arg TIM_DMABASE_CCMR2 | |
3537 * @arg TIM_DMABASE_CCER | |
3538 * @arg TIM_DMABASE_CNT | |
3539 * @arg TIM_DMABASE_PSC | |
3540 * @arg TIM_DMABASE_ARR | |
3541 * @arg TIM_DMABASE_RCR | |
3542 * @arg TIM_DMABASE_CCR1 | |
3543 * @arg TIM_DMABASE_CCR2 | |
3544 * @arg TIM_DMABASE_CCR3 | |
3545 * @arg TIM_DMABASE_CCR4 | |
3546 * @arg TIM_DMABASE_BDTR | |
3547 * @arg TIM_DMABASE_DCR | |
3548 * @param BurstRequestSrc: TIM DMA Request sources. | |
3549 * This parameters can be on of the following values: | |
3550 * @arg TIM_DMA_UPDATE: TIM update Interrupt source | |
3551 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source | |
3552 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source | |
3553 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source | |
3554 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source | |
3555 * @arg TIM_DMA_COM: TIM Commutation DMA source | |
3556 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source | |
3557 * @param BurstBuffer: The Buffer address. | |
3558 * @param BurstLength: DMA Burst length. This parameter can be one value | |
3559 * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. | |
3560 * @retval HAL status | |
3561 */ | |
3562 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, | |
3563 uint32_t *BurstBuffer, uint32_t BurstLength) | |
3564 { | |
3565 /* Check the parameters */ | |
3566 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); | |
3567 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); | |
3568 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); | |
3569 assert_param(IS_TIM_DMA_LENGTH(BurstLength)); | |
3570 | |
3571 if((htim->State == HAL_TIM_STATE_BUSY)) | |
3572 { | |
3573 return HAL_BUSY; | |
3574 } | |
3575 else if((htim->State == HAL_TIM_STATE_READY)) | |
3576 { | |
3577 if((BurstBuffer == 0 ) && (BurstLength > 0)) | |
3578 { | |
3579 return HAL_ERROR; | |
3580 } | |
3581 else | |
3582 { | |
3583 htim->State = HAL_TIM_STATE_BUSY; | |
3584 } | |
3585 } | |
3586 switch(BurstRequestSrc) | |
3587 { | |
3588 case TIM_DMA_UPDATE: | |
3589 { | |
3590 /* Set the DMA Period elapsed callback */ | |
3591 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; | |
3592 | |
3593 /* Set the DMA error callback */ | |
3594 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; | |
3595 | |
3596 /* Enable the DMA Stream */ | |
3597 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); | |
3598 } | |
3599 break; | |
3600 case TIM_DMA_CC1: | |
3601 { | |
3602 /* Set the DMA Period elapsed callback */ | |
3603 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; | |
3604 | |
3605 /* Set the DMA error callback */ | |
3606 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; | |
3607 | |
3608 /* Enable the DMA Stream */ | |
3609 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); | |
3610 } | |
3611 break; | |
3612 case TIM_DMA_CC2: | |
3613 { | |
3614 /* Set the DMA Period elapsed callback */ | |
3615 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; | |
3616 | |
3617 /* Set the DMA error callback */ | |
3618 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; | |
3619 | |
3620 /* Enable the DMA Stream */ | |
3621 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); | |
3622 } | |
3623 break; | |
3624 case TIM_DMA_CC3: | |
3625 { | |
3626 /* Set the DMA Period elapsed callback */ | |
3627 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; | |
3628 | |
3629 /* Set the DMA error callback */ | |
3630 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; | |
3631 | |
3632 /* Enable the DMA Stream */ | |
3633 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); | |
3634 } | |
3635 break; | |
3636 case TIM_DMA_CC4: | |
3637 { | |
3638 /* Set the DMA Period elapsed callback */ | |
3639 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; | |
3640 | |
3641 /* Set the DMA error callback */ | |
3642 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; | |
3643 | |
3644 /* Enable the DMA Stream */ | |
3645 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); | |
3646 } | |
3647 break; | |
3648 case TIM_DMA_COM: | |
3649 { | |
3650 /* Set the DMA Period elapsed callback */ | |
3651 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; | |
3652 | |
3653 /* Set the DMA error callback */ | |
3654 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; | |
3655 | |
3656 /* Enable the DMA Stream */ | |
3657 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); | |
3658 } | |
3659 break; | |
3660 case TIM_DMA_TRIGGER: | |
3661 { | |
3662 /* Set the DMA Period elapsed callback */ | |
3663 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; | |
3664 | |
3665 /* Set the DMA error callback */ | |
3666 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; | |
3667 | |
3668 /* Enable the DMA Stream */ | |
3669 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); | |
3670 } | |
3671 break; | |
3672 default: | |
3673 break; | |
3674 } | |
3675 | |
3676 /* configure the DMA Burst Mode */ | |
3677 htim->Instance->DCR = BurstBaseAddress | BurstLength; | |
3678 | |
3679 /* Enable the TIM DMA Request */ | |
3680 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); | |
3681 | |
3682 htim->State = HAL_TIM_STATE_READY; | |
3683 | |
3684 /* Return function status */ | |
3685 return HAL_OK; | |
3686 } | |
3687 | |
3688 /** | |
3689 * @brief Stop the DMA burst reading | |
3690 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
3691 * the configuration information for TIM module. | |
3692 * @param BurstRequestSrc: TIM DMA Request sources to disable. | |
3693 * @retval HAL status | |
3694 */ | |
3695 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) | |
3696 { | |
3697 /* Check the parameters */ | |
3698 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); | |
3699 | |
3700 /* Abort the DMA transfer (at least disable the DMA channel) */ | |
3701 switch(BurstRequestSrc) | |
3702 { | |
3703 case TIM_DMA_UPDATE: | |
3704 { | |
3705 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); | |
3706 } | |
3707 break; | |
3708 case TIM_DMA_CC1: | |
3709 { | |
3710 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); | |
3711 } | |
3712 break; | |
3713 case TIM_DMA_CC2: | |
3714 { | |
3715 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); | |
3716 } | |
3717 break; | |
3718 case TIM_DMA_CC3: | |
3719 { | |
3720 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); | |
3721 } | |
3722 break; | |
3723 case TIM_DMA_CC4: | |
3724 { | |
3725 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); | |
3726 } | |
3727 break; | |
3728 case TIM_DMA_COM: | |
3729 { | |
3730 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]); | |
3731 } | |
3732 break; | |
3733 case TIM_DMA_TRIGGER: | |
3734 { | |
3735 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); | |
3736 } | |
3737 break; | |
3738 default: | |
3739 break; | |
3740 } | |
3741 | |
3742 /* Disable the TIM Update DMA request */ | |
3743 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); | |
3744 | |
3745 /* Return function status */ | |
3746 return HAL_OK; | |
3747 } | |
3748 | |
3749 /** | |
3750 * @brief Generate a software event | |
3751 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
3752 * the configuration information for TIM module. | |
3753 * @param EventSource: specifies the event source. | |
3754 * This parameter can be one of the following values: | |
3755 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source | |
3756 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source | |
3757 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source | |
3758 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source | |
3759 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source | |
3760 * @arg TIM_EVENTSOURCE_COM: Timer COM event source | |
3761 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source | |
3762 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source | |
3763 * @note TIM6 and TIM7 can only generate an update event. | |
3764 * @note TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1 and TIM8. | |
3765 * @retval HAL status | |
3766 */ | |
3767 | |
3768 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) | |
3769 { | |
3770 /* Check the parameters */ | |
3771 assert_param(IS_TIM_INSTANCE(htim->Instance)); | |
3772 assert_param(IS_TIM_EVENT_SOURCE(EventSource)); | |
3773 | |
3774 /* Process Locked */ | |
3775 __HAL_LOCK(htim); | |
3776 | |
3777 /* Change the TIM state */ | |
3778 htim->State = HAL_TIM_STATE_BUSY; | |
3779 | |
3780 /* Set the event sources */ | |
3781 htim->Instance->EGR = EventSource; | |
3782 | |
3783 /* Change the TIM state */ | |
3784 htim->State = HAL_TIM_STATE_READY; | |
3785 | |
3786 __HAL_UNLOCK(htim); | |
3787 | |
3788 /* Return function status */ | |
3789 return HAL_OK; | |
3790 } | |
3791 | |
3792 /** | |
3793 * @brief Configures the OCRef clear feature | |
3794 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
3795 * the configuration information for TIM module. | |
3796 * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that | |
3797 * contains the OCREF clear feature and parameters for the TIM peripheral. | |
3798 * @param Channel: specifies the TIM Channel. | |
3799 * This parameter can be one of the following values: | |
3800 * @arg TIM_CHANNEL_1: TIM Channel 1 selected | |
3801 * @arg TIM_CHANNEL_2: TIM Channel 2 selected | |
3802 * @arg TIM_CHANNEL_3: TIM Channel 3 selected | |
3803 * @arg TIM_CHANNEL_4: TIM Channel 4 selected | |
3804 * @retval HAL status | |
3805 */ | |
3806 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel) | |
3807 { | |
3808 /* Check the parameters */ | |
3809 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); | |
3810 assert_param(IS_TIM_CHANNELS(Channel)); | |
3811 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); | |
3812 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); | |
3813 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); | |
3814 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); | |
3815 | |
3816 /* Process Locked */ | |
3817 __HAL_LOCK(htim); | |
3818 | |
3819 htim->State = HAL_TIM_STATE_BUSY; | |
3820 | |
3821 if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR) | |
3822 { | |
3823 TIM_ETR_SetConfig(htim->Instance, | |
3824 sClearInputConfig->ClearInputPrescaler, | |
3825 sClearInputConfig->ClearInputPolarity, | |
3826 sClearInputConfig->ClearInputFilter); | |
3827 } | |
3828 | |
3829 switch (Channel) | |
3830 { | |
3831 case TIM_CHANNEL_1: | |
3832 { | |
3833 if(sClearInputConfig->ClearInputState != RESET) | |
3834 { | |
3835 /* Enable the Ocref clear feature for Channel 1 */ | |
3836 htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE; | |
3837 } | |
3838 else | |
3839 { | |
3840 /* Disable the Ocref clear feature for Channel 1 */ | |
3841 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE; | |
3842 } | |
3843 } | |
3844 break; | |
3845 case TIM_CHANNEL_2: | |
3846 { | |
3847 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); | |
3848 if(sClearInputConfig->ClearInputState != RESET) | |
3849 { | |
3850 /* Enable the Ocref clear feature for Channel 2 */ | |
3851 htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE; | |
3852 } | |
3853 else | |
3854 { | |
3855 /* Disable the Ocref clear feature for Channel 2 */ | |
3856 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE; | |
3857 } | |
3858 } | |
3859 break; | |
3860 case TIM_CHANNEL_3: | |
3861 { | |
3862 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); | |
3863 if(sClearInputConfig->ClearInputState != RESET) | |
3864 { | |
3865 /* Enable the Ocref clear feature for Channel 3 */ | |
3866 htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE; | |
3867 } | |
3868 else | |
3869 { | |
3870 /* Disable the Ocref clear feature for Channel 3 */ | |
3871 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE; | |
3872 } | |
3873 } | |
3874 break; | |
3875 case TIM_CHANNEL_4: | |
3876 { | |
3877 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); | |
3878 if(sClearInputConfig->ClearInputState != RESET) | |
3879 { | |
3880 /* Enable the Ocref clear feature for Channel 4 */ | |
3881 htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE; | |
3882 } | |
3883 else | |
3884 { | |
3885 /* Disable the Ocref clear feature for Channel 4 */ | |
3886 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE; | |
3887 } | |
3888 } | |
3889 break; | |
3890 default: | |
3891 break; | |
3892 } | |
3893 | |
3894 htim->State = HAL_TIM_STATE_READY; | |
3895 | |
3896 __HAL_UNLOCK(htim); | |
3897 | |
3898 return HAL_OK; | |
3899 } | |
3900 | |
3901 /** | |
3902 * @brief Configures the clock source to be used | |
3903 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
3904 * the configuration information for TIM module. | |
3905 * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that | |
3906 * contains the clock source information for the TIM peripheral. | |
3907 * @retval HAL status | |
3908 */ | |
3909 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig) | |
3910 { | |
3911 uint32_t tmpsmcr = 0; | |
3912 | |
3913 /* Process Locked */ | |
3914 __HAL_LOCK(htim); | |
3915 | |
3916 htim->State = HAL_TIM_STATE_BUSY; | |
3917 | |
3918 /* Check the parameters */ | |
3919 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); | |
3920 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); | |
3921 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); | |
3922 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); | |
3923 | |
3924 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ | |
3925 tmpsmcr = htim->Instance->SMCR; | |
3926 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); | |
3927 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); | |
3928 htim->Instance->SMCR = tmpsmcr; | |
3929 | |
3930 switch (sClockSourceConfig->ClockSource) | |
3931 { | |
3932 case TIM_CLOCKSOURCE_INTERNAL: | |
3933 { | |
3934 assert_param(IS_TIM_INSTANCE(htim->Instance)); | |
3935 /* Disable slave mode to clock the prescaler directly with the internal clock */ | |
3936 htim->Instance->SMCR &= ~TIM_SMCR_SMS; | |
3937 } | |
3938 break; | |
3939 | |
3940 case TIM_CLOCKSOURCE_ETRMODE1: | |
3941 { | |
3942 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance)); | |
3943 /* Configure the ETR Clock source */ | |
3944 TIM_ETR_SetConfig(htim->Instance, | |
3945 sClockSourceConfig->ClockPrescaler, | |
3946 sClockSourceConfig->ClockPolarity, | |
3947 sClockSourceConfig->ClockFilter); | |
3948 /* Get the TIMx SMCR register value */ | |
3949 tmpsmcr = htim->Instance->SMCR; | |
3950 /* Reset the SMS and TS Bits */ | |
3951 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); | |
3952 /* Select the External clock mode1 and the ETRF trigger */ | |
3953 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); | |
3954 /* Write to TIMx SMCR */ | |
3955 htim->Instance->SMCR = tmpsmcr; | |
3956 } | |
3957 break; | |
3958 | |
3959 case TIM_CLOCKSOURCE_ETRMODE2: | |
3960 { | |
3961 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance)); | |
3962 /* Configure the ETR Clock source */ | |
3963 TIM_ETR_SetConfig(htim->Instance, | |
3964 sClockSourceConfig->ClockPrescaler, | |
3965 sClockSourceConfig->ClockPolarity, | |
3966 sClockSourceConfig->ClockFilter); | |
3967 /* Enable the External clock mode2 */ | |
3968 htim->Instance->SMCR |= TIM_SMCR_ECE; | |
3969 } | |
3970 break; | |
3971 | |
3972 case TIM_CLOCKSOURCE_TI1: | |
3973 { | |
3974 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); | |
3975 TIM_TI1_ConfigInputStage(htim->Instance, | |
3976 sClockSourceConfig->ClockPolarity, | |
3977 sClockSourceConfig->ClockFilter); | |
3978 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); | |
3979 } | |
3980 break; | |
3981 case TIM_CLOCKSOURCE_TI2: | |
3982 { | |
3983 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); | |
3984 TIM_TI2_ConfigInputStage(htim->Instance, | |
3985 sClockSourceConfig->ClockPolarity, | |
3986 sClockSourceConfig->ClockFilter); | |
3987 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); | |
3988 } | |
3989 break; | |
3990 case TIM_CLOCKSOURCE_TI1ED: | |
3991 { | |
3992 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); | |
3993 TIM_TI1_ConfigInputStage(htim->Instance, | |
3994 sClockSourceConfig->ClockPolarity, | |
3995 sClockSourceConfig->ClockFilter); | |
3996 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); | |
3997 } | |
3998 break; | |
3999 case TIM_CLOCKSOURCE_ITR0: | |
4000 { | |
4001 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); | |
4002 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0); | |
4003 } | |
4004 break; | |
4005 case TIM_CLOCKSOURCE_ITR1: | |
4006 { | |
4007 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); | |
4008 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1); | |
4009 } | |
4010 break; | |
4011 case TIM_CLOCKSOURCE_ITR2: | |
4012 { | |
4013 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); | |
4014 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2); | |
4015 } | |
4016 break; | |
4017 case TIM_CLOCKSOURCE_ITR3: | |
4018 { | |
4019 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); | |
4020 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3); | |
4021 } | |
4022 break; | |
4023 | |
4024 default: | |
4025 break; | |
4026 } | |
4027 htim->State = HAL_TIM_STATE_READY; | |
4028 | |
4029 __HAL_UNLOCK(htim); | |
4030 | |
4031 return HAL_OK; | |
4032 } | |
4033 | |
4034 /** | |
4035 * @brief Selects the signal connected to the TI1 input: direct from CH1_input | |
4036 * or a XOR combination between CH1_input, CH2_input & CH3_input | |
4037 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
4038 * the configuration information for TIM module. | |
4039 * @param TI1_Selection: Indicate whether or not channel 1 is connected to the | |
4040 * output of a XOR gate. | |
4041 * This parameter can be one of the following values: | |
4042 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input | |
4043 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 | |
4044 * pins are connected to the TI1 input (XOR combination) | |
4045 * @retval HAL status | |
4046 */ | |
4047 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) | |
4048 { | |
4049 uint32_t tmpcr2 = 0; | |
4050 | |
4051 /* Check the parameters */ | |
4052 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); | |
4053 assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); | |
4054 | |
4055 /* Get the TIMx CR2 register value */ | |
4056 tmpcr2 = htim->Instance->CR2; | |
4057 | |
4058 /* Reset the TI1 selection */ | |
4059 tmpcr2 &= ~TIM_CR2_TI1S; | |
4060 | |
4061 /* Set the TI1 selection */ | |
4062 tmpcr2 |= TI1_Selection; | |
4063 | |
4064 /* Write to TIMxCR2 */ | |
4065 htim->Instance->CR2 = tmpcr2; | |
4066 | |
4067 return HAL_OK; | |
4068 } | |
4069 | |
4070 /** | |
4071 * @brief Configures the TIM in Slave mode | |
4072 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
4073 * the configuration information for TIM module. | |
4074 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that | |
4075 * contains the selected trigger (internal trigger input, filtered | |
4076 * timer input or external trigger input) and the ) and the Slave | |
4077 * mode (Disable, Reset, Gated, Trigger, External clock mode 1). | |
4078 * @retval HAL status | |
4079 */ | |
4080 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig) | |
4081 { | |
4082 /* Check the parameters */ | |
4083 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); | |
4084 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); | |
4085 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); | |
4086 | |
4087 __HAL_LOCK(htim); | |
4088 | |
4089 htim->State = HAL_TIM_STATE_BUSY; | |
4090 | |
4091 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig); | |
4092 | |
4093 /* Disable Trigger Interrupt */ | |
4094 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); | |
4095 | |
4096 /* Disable Trigger DMA request */ | |
4097 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); | |
4098 | |
4099 htim->State = HAL_TIM_STATE_READY; | |
4100 | |
4101 __HAL_UNLOCK(htim); | |
4102 | |
4103 return HAL_OK; | |
4104 } | |
4105 | |
4106 /** | |
4107 * @brief Configures the TIM in Slave mode in interrupt mode | |
4108 * @param htim: TIM handle. | |
4109 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that | |
4110 * contains the selected trigger (internal trigger input, filtered | |
4111 * timer input or external trigger input) and the ) and the Slave | |
4112 * mode (Disable, Reset, Gated, Trigger, External clock mode 1). | |
4113 * @retval HAL status | |
4114 */ | |
4115 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, | |
4116 TIM_SlaveConfigTypeDef * sSlaveConfig) | |
4117 { | |
4118 /* Check the parameters */ | |
4119 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); | |
4120 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); | |
4121 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); | |
4122 | |
4123 __HAL_LOCK(htim); | |
4124 | |
4125 htim->State = HAL_TIM_STATE_BUSY; | |
4126 | |
4127 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig); | |
4128 | |
4129 /* Enable Trigger Interrupt */ | |
4130 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); | |
4131 | |
4132 /* Disable Trigger DMA request */ | |
4133 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); | |
4134 | |
4135 htim->State = HAL_TIM_STATE_READY; | |
4136 | |
4137 __HAL_UNLOCK(htim); | |
4138 | |
4139 return HAL_OK; | |
4140 } | |
4141 | |
4142 /** | |
4143 * @brief Read the captured value from Capture Compare unit | |
4144 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
4145 * the configuration information for TIM module. | |
4146 * @param Channel: TIM Channels to be enabled. | |
4147 * This parameter can be one of the following values: | |
4148 * @arg TIM_CHANNEL_1: TIM Channel 1 selected | |
4149 * @arg TIM_CHANNEL_2: TIM Channel 2 selected | |
4150 * @arg TIM_CHANNEL_3: TIM Channel 3 selected | |
4151 * @arg TIM_CHANNEL_4: TIM Channel 4 selected | |
4152 * @retval Captured value | |
4153 */ | |
4154 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) | |
4155 { | |
4156 uint32_t tmpreg = 0; | |
4157 | |
4158 __HAL_LOCK(htim); | |
4159 | |
4160 switch (Channel) | |
4161 { | |
4162 case TIM_CHANNEL_1: | |
4163 { | |
4164 /* Check the parameters */ | |
4165 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); | |
4166 | |
4167 /* Return the capture 1 value */ | |
4168 tmpreg = htim->Instance->CCR1; | |
4169 | |
4170 break; | |
4171 } | |
4172 case TIM_CHANNEL_2: | |
4173 { | |
4174 /* Check the parameters */ | |
4175 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); | |
4176 | |
4177 /* Return the capture 2 value */ | |
4178 tmpreg = htim->Instance->CCR2; | |
4179 | |
4180 break; | |
4181 } | |
4182 | |
4183 case TIM_CHANNEL_3: | |
4184 { | |
4185 /* Check the parameters */ | |
4186 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); | |
4187 | |
4188 /* Return the capture 3 value */ | |
4189 tmpreg = htim->Instance->CCR3; | |
4190 | |
4191 break; | |
4192 } | |
4193 | |
4194 case TIM_CHANNEL_4: | |
4195 { | |
4196 /* Check the parameters */ | |
4197 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); | |
4198 | |
4199 /* Return the capture 4 value */ | |
4200 tmpreg = htim->Instance->CCR4; | |
4201 | |
4202 break; | |
4203 } | |
4204 | |
4205 default: | |
4206 break; | |
4207 } | |
4208 | |
4209 __HAL_UNLOCK(htim); | |
4210 return tmpreg; | |
4211 } | |
4212 /** | |
4213 * @} | |
4214 */ | |
4215 | |
4216 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions | |
4217 * @brief TIM Callbacks functions | |
4218 * | |
4219 @verbatim | |
4220 ============================================================================== | |
4221 ##### TIM Callbacks functions ##### | |
4222 ============================================================================== | |
4223 [..] | |
4224 This section provides TIM callback functions: | |
4225 (+) Timer Period elapsed callback | |
4226 (+) Timer Output Compare callback | |
4227 (+) Timer Input capture callback | |
4228 (+) Timer Trigger callback | |
4229 (+) Timer Error callback | |
4230 | |
4231 @endverbatim | |
4232 * @{ | |
4233 */ | |
4234 | |
4235 /** | |
4236 * @brief Period elapsed callback in non blocking mode | |
4237 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
4238 * the configuration information for TIM module. | |
4239 * @retval None | |
4240 */ | |
4241 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) | |
4242 { | |
4243 /* NOTE : This function Should not be modified, when the callback is needed, | |
4244 the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file | |
4245 */ | |
4246 | |
4247 } | |
4248 /** | |
4249 * @brief Output Compare callback in non blocking mode | |
4250 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
4251 * the configuration information for TIM module. | |
4252 * @retval None | |
4253 */ | |
4254 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) | |
4255 { | |
4256 /* NOTE : This function Should not be modified, when the callback is needed, | |
4257 the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file | |
4258 */ | |
4259 } | |
4260 /** | |
4261 * @brief Input Capture callback in non blocking mode | |
4262 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
4263 * the configuration information for TIM module. | |
4264 * @retval None | |
4265 */ | |
4266 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) | |
4267 { | |
4268 /* NOTE : This function Should not be modified, when the callback is needed, | |
4269 the __HAL_TIM_IC_CaptureCallback could be implemented in the user file | |
4270 */ | |
4271 } | |
4272 | |
4273 /** | |
4274 * @brief PWM Pulse finished callback in non blocking mode | |
4275 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
4276 * the configuration information for TIM module. | |
4277 * @retval None | |
4278 */ | |
4279 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) | |
4280 { | |
4281 /* NOTE : This function Should not be modified, when the callback is needed, | |
4282 the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file | |
4283 */ | |
4284 } | |
4285 | |
4286 /** | |
4287 * @brief Hall Trigger detection callback in non blocking mode | |
4288 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
4289 * the configuration information for TIM module. | |
4290 * @retval None | |
4291 */ | |
4292 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) | |
4293 { | |
4294 /* NOTE : This function Should not be modified, when the callback is needed, | |
4295 the HAL_TIM_TriggerCallback could be implemented in the user file | |
4296 */ | |
4297 } | |
4298 | |
4299 /** | |
4300 * @brief Timer error callback in non blocking mode | |
4301 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
4302 * the configuration information for TIM module. | |
4303 * @retval None | |
4304 */ | |
4305 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) | |
4306 { | |
4307 /* NOTE : This function Should not be modified, when the callback is needed, | |
4308 the HAL_TIM_ErrorCallback could be implemented in the user file | |
4309 */ | |
4310 } | |
4311 /** | |
4312 * @} | |
4313 */ | |
4314 | |
4315 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions | |
4316 * @brief Peripheral State functions | |
4317 * | |
4318 @verbatim | |
4319 ============================================================================== | |
4320 ##### Peripheral State functions ##### | |
4321 ============================================================================== | |
4322 [..] | |
4323 This subsection permits to get in run-time the status of the peripheral | |
4324 and the data flow. | |
4325 | |
4326 @endverbatim | |
4327 * @{ | |
4328 */ | |
4329 | |
4330 /** | |
4331 * @brief Return the TIM Base state | |
4332 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
4333 * the configuration information for TIM module. | |
4334 * @retval HAL state | |
4335 */ | |
4336 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) | |
4337 { | |
4338 return htim->State; | |
4339 } | |
4340 | |
4341 /** | |
4342 * @brief Return the TIM OC state | |
4343 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
4344 * the configuration information for TIM module. | |
4345 * @retval HAL state | |
4346 */ | |
4347 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) | |
4348 { | |
4349 return htim->State; | |
4350 } | |
4351 | |
4352 /** | |
4353 * @brief Return the TIM PWM state | |
4354 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
4355 * the configuration information for TIM module. | |
4356 * @retval HAL state | |
4357 */ | |
4358 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) | |
4359 { | |
4360 return htim->State; | |
4361 } | |
4362 | |
4363 /** | |
4364 * @brief Return the TIM Input Capture state | |
4365 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
4366 * the configuration information for TIM module. | |
4367 * @retval HAL state | |
4368 */ | |
4369 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) | |
4370 { | |
4371 return htim->State; | |
4372 } | |
4373 | |
4374 /** | |
4375 * @brief Return the TIM One Pulse Mode state | |
4376 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
4377 * the configuration information for TIM module. | |
4378 * @retval HAL state | |
4379 */ | |
4380 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) | |
4381 { | |
4382 return htim->State; | |
4383 } | |
4384 | |
4385 /** | |
4386 * @brief Return the TIM Encoder Mode state | |
4387 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
4388 * the configuration information for TIM module. | |
4389 * @retval HAL state | |
4390 */ | |
4391 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) | |
4392 { | |
4393 return htim->State; | |
4394 } | |
4395 /** | |
4396 * @} | |
4397 */ | |
4398 | |
4399 /** | |
4400 * @brief Time Base configuration | |
4401 * @param TIMx: TIM peripheral | |
4402 * @param Structure: pointer on TIM Time Base required parameters | |
4403 * @retval None | |
4404 */ | |
4405 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) | |
4406 { | |
4407 uint32_t tmpcr1 = 0; | |
4408 tmpcr1 = TIMx->CR1; | |
4409 | |
4410 /* Set TIM Time Base Unit parameters ---------------------------------------*/ | |
4411 if(IS_TIM_CC3_INSTANCE(TIMx) != RESET) | |
4412 { | |
4413 /* Select the Counter Mode */ | |
4414 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); | |
4415 tmpcr1 |= Structure->CounterMode; | |
4416 } | |
4417 | |
4418 if(IS_TIM_CC1_INSTANCE(TIMx) != RESET) | |
4419 { | |
4420 /* Set the clock division */ | |
4421 tmpcr1 &= ~TIM_CR1_CKD; | |
4422 tmpcr1 |= (uint32_t)Structure->ClockDivision; | |
4423 } | |
4424 | |
4425 TIMx->CR1 = tmpcr1; | |
4426 | |
4427 /* Set the Auto-reload value */ | |
4428 TIMx->ARR = (uint32_t)Structure->Period ; | |
4429 | |
4430 /* Set the Prescaler value */ | |
4431 TIMx->PSC = (uint32_t)Structure->Prescaler; | |
4432 | |
4433 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET) | |
4434 { | |
4435 /* Set the Repetition Counter value */ | |
4436 TIMx->RCR = Structure->RepetitionCounter; | |
4437 } | |
4438 | |
4439 /* Generate an update event to reload the Prescaler | |
4440 and the repetition counter(only for TIM1 and TIM8) value immediately */ | |
4441 TIMx->EGR = TIM_EGR_UG; | |
4442 } | |
4443 | |
4444 /** | |
4445 * @brief Configure the TI1 as Input. | |
4446 * @param TIMx to select the TIM peripheral. | |
4447 * @param TIM_ICPolarity : The Input Polarity. | |
4448 * This parameter can be one of the following values: | |
4449 * @arg TIM_ICPolarity_Rising | |
4450 * @arg TIM_ICPolarity_Falling | |
4451 * @arg TIM_ICPolarity_BothEdge | |
4452 * @param TIM_ICSelection: specifies the input to be used. | |
4453 * This parameter can be one of the following values: | |
4454 * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. | |
4455 * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. | |
4456 * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. | |
4457 * @param TIM_ICFilter: Specifies the Input Capture Filter. | |
4458 * This parameter must be a value between 0x00 and 0x0F. | |
4459 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 | |
4460 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be | |
4461 * protected against un-initialized filter and polarity values. | |
4462 * @retval None | |
4463 */ | |
4464 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, | |
4465 uint32_t TIM_ICFilter) | |
4466 { | |
4467 uint32_t tmpccmr1 = 0; | |
4468 uint32_t tmpccer = 0; | |
4469 | |
4470 /* Disable the Channel 1: Reset the CC1E Bit */ | |
4471 TIMx->CCER &= ~TIM_CCER_CC1E; | |
4472 tmpccmr1 = TIMx->CCMR1; | |
4473 tmpccer = TIMx->CCER; | |
4474 | |
4475 /* Select the Input */ | |
4476 if(IS_TIM_CC2_INSTANCE(TIMx) != RESET) | |
4477 { | |
4478 tmpccmr1 &= ~TIM_CCMR1_CC1S; | |
4479 tmpccmr1 |= TIM_ICSelection; | |
4480 } | |
4481 else | |
4482 { | |
4483 tmpccmr1 &= ~TIM_CCMR1_CC1S; | |
4484 tmpccmr1 |= TIM_CCMR1_CC1S_0; | |
4485 } | |
4486 | |
4487 /* Set the filter */ | |
4488 tmpccmr1 &= ~TIM_CCMR1_IC1F; | |
4489 tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F); | |
4490 | |
4491 /* Select the Polarity and set the CC1E Bit */ | |
4492 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); | |
4493 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); | |
4494 | |
4495 /* Write to TIMx CCMR1 and CCER registers */ | |
4496 TIMx->CCMR1 = tmpccmr1; | |
4497 TIMx->CCER = tmpccer; | |
4498 } | |
4499 | |
4500 /** | |
4501 * @brief Time Output Compare 2 configuration | |
4502 * @param TIMx to select the TIM peripheral | |
4503 * @param OC_Config: The output configuration structure | |
4504 * @retval None | |
4505 */ | |
4506 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) | |
4507 { | |
4508 uint32_t tmpccmrx = 0; | |
4509 uint32_t tmpccer = 0; | |
4510 uint32_t tmpcr2 = 0; | |
4511 | |
4512 /* Disable the Channel 2: Reset the CC2E Bit */ | |
4513 TIMx->CCER &= ~TIM_CCER_CC2E; | |
4514 | |
4515 /* Get the TIMx CCER register value */ | |
4516 tmpccer = TIMx->CCER; | |
4517 /* Get the TIMx CR2 register value */ | |
4518 tmpcr2 = TIMx->CR2; | |
4519 | |
4520 /* Get the TIMx CCMR1 register value */ | |
4521 tmpccmrx = TIMx->CCMR1; | |
4522 | |
4523 /* Reset the Output Compare mode and Capture/Compare selection Bits */ | |
4524 tmpccmrx &= ~TIM_CCMR1_OC2M; | |
4525 tmpccmrx &= ~TIM_CCMR1_CC2S; | |
4526 | |
4527 /* Select the Output Compare Mode */ | |
4528 tmpccmrx |= (OC_Config->OCMode << 8); | |
4529 | |
4530 /* Reset the Output Polarity level */ | |
4531 tmpccer &= ~TIM_CCER_CC2P; | |
4532 /* Set the Output Compare Polarity */ | |
4533 tmpccer |= (OC_Config->OCPolarity << 4); | |
4534 | |
4535 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET) | |
4536 { | |
4537 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); | |
4538 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); | |
4539 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); | |
4540 | |
4541 /* Reset the Output N Polarity level */ | |
4542 tmpccer &= ~TIM_CCER_CC2NP; | |
4543 /* Set the Output N Polarity */ | |
4544 tmpccer |= (OC_Config->OCNPolarity << 4); | |
4545 /* Reset the Output N State */ | |
4546 tmpccer &= ~TIM_CCER_CC2NE; | |
4547 | |
4548 /* Reset the Output Compare and Output Compare N IDLE State */ | |
4549 tmpcr2 &= ~TIM_CR2_OIS2; | |
4550 tmpcr2 &= ~TIM_CR2_OIS2N; | |
4551 /* Set the Output Idle state */ | |
4552 tmpcr2 |= (OC_Config->OCIdleState << 2); | |
4553 /* Set the Output N Idle state */ | |
4554 tmpcr2 |= (OC_Config->OCNIdleState << 2); | |
4555 } | |
4556 /* Write to TIMx CR2 */ | |
4557 TIMx->CR2 = tmpcr2; | |
4558 | |
4559 /* Write to TIMx CCMR1 */ | |
4560 TIMx->CCMR1 = tmpccmrx; | |
4561 | |
4562 /* Set the Capture Compare Register value */ | |
4563 TIMx->CCR2 = OC_Config->Pulse; | |
4564 | |
4565 /* Write to TIMx CCER */ | |
4566 TIMx->CCER = tmpccer; | |
4567 } | |
4568 | |
4569 /** | |
4570 * @brief TIM DMA Delay Pulse complete callback. | |
4571 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains | |
4572 * the configuration information for the specified DMA module. | |
4573 * @retval None | |
4574 */ | |
4575 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) | |
4576 { | |
4577 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; | |
4578 | |
4579 htim->State= HAL_TIM_STATE_READY; | |
4580 | |
4581 if(hdma == htim->hdma[TIM_DMA_ID_CC1]) | |
4582 { | |
4583 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; | |
4584 } | |
4585 else if(hdma == htim->hdma[TIM_DMA_ID_CC2]) | |
4586 { | |
4587 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; | |
4588 } | |
4589 else if(hdma == htim->hdma[TIM_DMA_ID_CC3]) | |
4590 { | |
4591 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; | |
4592 } | |
4593 else if(hdma == htim->hdma[TIM_DMA_ID_CC4]) | |
4594 { | |
4595 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; | |
4596 } | |
4597 | |
4598 HAL_TIM_PWM_PulseFinishedCallback(htim); | |
4599 | |
4600 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; | |
4601 } | |
4602 | |
4603 /** | |
4604 * @brief TIM DMA error callback | |
4605 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains | |
4606 * the configuration information for the specified DMA module. | |
4607 * @retval None | |
4608 */ | |
4609 void TIM_DMAError(DMA_HandleTypeDef *hdma) | |
4610 { | |
4611 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; | |
4612 | |
4613 htim->State= HAL_TIM_STATE_READY; | |
4614 | |
4615 HAL_TIM_ErrorCallback(htim); | |
4616 } | |
4617 | |
4618 /** | |
4619 * @brief TIM DMA Capture complete callback. | |
4620 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains | |
4621 * the configuration information for the specified DMA module. | |
4622 * @retval None | |
4623 */ | |
4624 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) | |
4625 { | |
4626 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; | |
4627 | |
4628 htim->State= HAL_TIM_STATE_READY; | |
4629 | |
4630 if(hdma == htim->hdma[TIM_DMA_ID_CC1]) | |
4631 { | |
4632 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; | |
4633 } | |
4634 else if(hdma == htim->hdma[TIM_DMA_ID_CC2]) | |
4635 { | |
4636 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; | |
4637 } | |
4638 else if(hdma == htim->hdma[TIM_DMA_ID_CC3]) | |
4639 { | |
4640 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; | |
4641 } | |
4642 else if(hdma == htim->hdma[TIM_DMA_ID_CC4]) | |
4643 { | |
4644 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; | |
4645 } | |
4646 | |
4647 HAL_TIM_IC_CaptureCallback(htim); | |
4648 | |
4649 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; | |
4650 } | |
4651 | |
4652 /** | |
4653 * @brief Enables or disables the TIM Capture Compare Channel x. | |
4654 * @param TIMx to select the TIM peripheral | |
4655 * @param Channel: specifies the TIM Channel | |
4656 * This parameter can be one of the following values: | |
4657 * @arg TIM_Channel_1: TIM Channel 1 | |
4658 * @arg TIM_Channel_2: TIM Channel 2 | |
4659 * @arg TIM_Channel_3: TIM Channel 3 | |
4660 * @arg TIM_Channel_4: TIM Channel 4 | |
4661 * @param ChannelState: specifies the TIM Channel CCxE bit new state. | |
4662 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable. | |
4663 * @retval None | |
4664 */ | |
4665 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState) | |
4666 { | |
4667 uint32_t tmp = 0; | |
4668 | |
4669 /* Check the parameters */ | |
4670 assert_param(IS_TIM_CC1_INSTANCE(TIMx)); | |
4671 assert_param(IS_TIM_CHANNELS(Channel)); | |
4672 | |
4673 tmp = TIM_CCER_CC1E << Channel; | |
4674 | |
4675 /* Reset the CCxE Bit */ | |
4676 TIMx->CCER &= ~tmp; | |
4677 | |
4678 /* Set or reset the CCxE Bit */ | |
4679 TIMx->CCER |= (uint32_t)(ChannelState << Channel); | |
4680 } | |
4681 | |
4682 /** | |
4683 * @brief TIM DMA Period Elapse complete callback. | |
4684 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains | |
4685 * the configuration information for the specified DMA module. | |
4686 * @retval None | |
4687 */ | |
4688 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) | |
4689 { | |
4690 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; | |
4691 | |
4692 htim->State= HAL_TIM_STATE_READY; | |
4693 | |
4694 HAL_TIM_PeriodElapsedCallback(htim); | |
4695 } | |
4696 | |
4697 /** | |
4698 * @brief TIM DMA Trigger callback. | |
4699 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains | |
4700 * the configuration information for the specified DMA module. | |
4701 * @retval None | |
4702 */ | |
4703 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) | |
4704 { | |
4705 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; | |
4706 | |
4707 htim->State= HAL_TIM_STATE_READY; | |
4708 | |
4709 HAL_TIM_TriggerCallback(htim); | |
4710 } | |
4711 | |
4712 /** | |
4713 * @brief Time Output Compare 1 configuration | |
4714 * @param TIMx to select the TIM peripheral | |
4715 * @param OC_Config: The output configuration structure | |
4716 * @retval None | |
4717 */ | |
4718 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) | |
4719 { | |
4720 uint32_t tmpccmrx = 0; | |
4721 uint32_t tmpccer = 0; | |
4722 uint32_t tmpcr2 = 0; | |
4723 | |
4724 /* Disable the Channel 1: Reset the CC1E Bit */ | |
4725 TIMx->CCER &= ~TIM_CCER_CC1E; | |
4726 | |
4727 /* Get the TIMx CCER register value */ | |
4728 tmpccer = TIMx->CCER; | |
4729 /* Get the TIMx CR2 register value */ | |
4730 tmpcr2 = TIMx->CR2; | |
4731 | |
4732 /* Get the TIMx CCMR1 register value */ | |
4733 tmpccmrx = TIMx->CCMR1; | |
4734 | |
4735 /* Reset the Output Compare Mode Bits */ | |
4736 tmpccmrx &= ~TIM_CCMR1_OC1M; | |
4737 tmpccmrx &= ~TIM_CCMR1_CC1S; | |
4738 /* Select the Output Compare Mode */ | |
4739 tmpccmrx |= OC_Config->OCMode; | |
4740 | |
4741 /* Reset the Output Polarity level */ | |
4742 tmpccer &= ~TIM_CCER_CC1P; | |
4743 /* Set the Output Compare Polarity */ | |
4744 tmpccer |= OC_Config->OCPolarity; | |
4745 | |
4746 | |
4747 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET) | |
4748 { | |
4749 /* Reset the Output N Polarity level */ | |
4750 tmpccer &= ~TIM_CCER_CC1NP; | |
4751 /* Set the Output N Polarity */ | |
4752 tmpccer |= OC_Config->OCNPolarity; | |
4753 /* Reset the Output N State */ | |
4754 tmpccer &= ~TIM_CCER_CC1NE; | |
4755 | |
4756 /* Reset the Output Compare and Output Compare N IDLE State */ | |
4757 tmpcr2 &= ~TIM_CR2_OIS1; | |
4758 tmpcr2 &= ~TIM_CR2_OIS1N; | |
4759 /* Set the Output Idle state */ | |
4760 tmpcr2 |= OC_Config->OCIdleState; | |
4761 /* Set the Output N Idle state */ | |
4762 tmpcr2 |= OC_Config->OCNIdleState; | |
4763 } | |
4764 /* Write to TIMx CR2 */ | |
4765 TIMx->CR2 = tmpcr2; | |
4766 | |
4767 /* Write to TIMx CCMR1 */ | |
4768 TIMx->CCMR1 = tmpccmrx; | |
4769 | |
4770 /* Set the Capture Compare Register value */ | |
4771 TIMx->CCR1 = OC_Config->Pulse; | |
4772 | |
4773 /* Write to TIMx CCER */ | |
4774 TIMx->CCER = tmpccer; | |
4775 } | |
4776 | |
4777 /** | |
4778 * @brief Time Output Compare 3 configuration | |
4779 * @param TIMx to select the TIM peripheral | |
4780 * @param OC_Config: The output configuration structure | |
4781 * @retval None | |
4782 */ | |
4783 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) | |
4784 { | |
4785 uint32_t tmpccmrx = 0; | |
4786 uint32_t tmpccer = 0; | |
4787 uint32_t tmpcr2 = 0; | |
4788 | |
4789 /* Disable the Channel 3: Reset the CC2E Bit */ | |
4790 TIMx->CCER &= ~TIM_CCER_CC3E; | |
4791 | |
4792 /* Get the TIMx CCER register value */ | |
4793 tmpccer = TIMx->CCER; | |
4794 /* Get the TIMx CR2 register value */ | |
4795 tmpcr2 = TIMx->CR2; | |
4796 | |
4797 /* Get the TIMx CCMR2 register value */ | |
4798 tmpccmrx = TIMx->CCMR2; | |
4799 | |
4800 /* Reset the Output Compare mode and Capture/Compare selection Bits */ | |
4801 tmpccmrx &= ~TIM_CCMR2_OC3M; | |
4802 tmpccmrx &= ~TIM_CCMR2_CC3S; | |
4803 /* Select the Output Compare Mode */ | |
4804 tmpccmrx |= OC_Config->OCMode; | |
4805 | |
4806 /* Reset the Output Polarity level */ | |
4807 tmpccer &= ~TIM_CCER_CC3P; | |
4808 /* Set the Output Compare Polarity */ | |
4809 tmpccer |= (OC_Config->OCPolarity << 8); | |
4810 | |
4811 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET) | |
4812 { | |
4813 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); | |
4814 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); | |
4815 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); | |
4816 | |
4817 /* Reset the Output N Polarity level */ | |
4818 tmpccer &= ~TIM_CCER_CC3NP; | |
4819 /* Set the Output N Polarity */ | |
4820 tmpccer |= (OC_Config->OCNPolarity << 8); | |
4821 /* Reset the Output N State */ | |
4822 tmpccer &= ~TIM_CCER_CC3NE; | |
4823 | |
4824 /* Reset the Output Compare and Output Compare N IDLE State */ | |
4825 tmpcr2 &= ~TIM_CR2_OIS3; | |
4826 tmpcr2 &= ~TIM_CR2_OIS3N; | |
4827 /* Set the Output Idle state */ | |
4828 tmpcr2 |= (OC_Config->OCIdleState << 4); | |
4829 /* Set the Output N Idle state */ | |
4830 tmpcr2 |= (OC_Config->OCNIdleState << 4); | |
4831 } | |
4832 /* Write to TIMx CR2 */ | |
4833 TIMx->CR2 = tmpcr2; | |
4834 | |
4835 /* Write to TIMx CCMR2 */ | |
4836 TIMx->CCMR2 = tmpccmrx; | |
4837 | |
4838 /* Set the Capture Compare Register value */ | |
4839 TIMx->CCR3 = OC_Config->Pulse; | |
4840 | |
4841 /* Write to TIMx CCER */ | |
4842 TIMx->CCER = tmpccer; | |
4843 } | |
4844 | |
4845 /** | |
4846 * @brief Time Output Compare 4 configuration | |
4847 * @param TIMx to select the TIM peripheral | |
4848 * @param OC_Config: The output configuration structure | |
4849 * @retval None | |
4850 */ | |
4851 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) | |
4852 { | |
4853 uint32_t tmpccmrx = 0; | |
4854 uint32_t tmpccer = 0; | |
4855 uint32_t tmpcr2 = 0; | |
4856 | |
4857 /* Disable the Channel 4: Reset the CC4E Bit */ | |
4858 TIMx->CCER &= ~TIM_CCER_CC4E; | |
4859 | |
4860 /* Get the TIMx CCER register value */ | |
4861 tmpccer = TIMx->CCER; | |
4862 /* Get the TIMx CR2 register value */ | |
4863 tmpcr2 = TIMx->CR2; | |
4864 | |
4865 /* Get the TIMx CCMR2 register value */ | |
4866 tmpccmrx = TIMx->CCMR2; | |
4867 | |
4868 /* Reset the Output Compare mode and Capture/Compare selection Bits */ | |
4869 tmpccmrx &= ~TIM_CCMR2_OC4M; | |
4870 tmpccmrx &= ~TIM_CCMR2_CC4S; | |
4871 | |
4872 /* Select the Output Compare Mode */ | |
4873 tmpccmrx |= (OC_Config->OCMode << 8); | |
4874 | |
4875 /* Reset the Output Polarity level */ | |
4876 tmpccer &= ~TIM_CCER_CC4P; | |
4877 /* Set the Output Compare Polarity */ | |
4878 tmpccer |= (OC_Config->OCPolarity << 12); | |
4879 | |
4880 /*if((TIMx == TIM1) || (TIMx == TIM8))*/ | |
4881 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET) | |
4882 { | |
4883 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); | |
4884 /* Reset the Output Compare IDLE State */ | |
4885 tmpcr2 &= ~TIM_CR2_OIS4; | |
4886 /* Set the Output Idle state */ | |
4887 tmpcr2 |= (OC_Config->OCIdleState << 6); | |
4888 } | |
4889 /* Write to TIMx CR2 */ | |
4890 TIMx->CR2 = tmpcr2; | |
4891 | |
4892 /* Write to TIMx CCMR2 */ | |
4893 TIMx->CCMR2 = tmpccmrx; | |
4894 | |
4895 /* Set the Capture Compare Register value */ | |
4896 TIMx->CCR4 = OC_Config->Pulse; | |
4897 | |
4898 /* Write to TIMx CCER */ | |
4899 TIMx->CCER = tmpccer; | |
4900 } | |
4901 | |
4902 /** | |
4903 * @brief Time Output Compare 4 configuration | |
4904 * @param htim: pointer to a TIM_HandleTypeDef structure that contains | |
4905 * the configuration information for TIM module. | |
4906 * @param sSlaveConfig: The slave configuration structure | |
4907 * @retval None | |
4908 */ | |
4909 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, | |
4910 TIM_SlaveConfigTypeDef * sSlaveConfig) | |
4911 { | |
4912 uint32_t tmpsmcr = 0; | |
4913 uint32_t tmpccmr1 = 0; | |
4914 uint32_t tmpccer = 0; | |
4915 | |
4916 /* Get the TIMx SMCR register value */ | |
4917 tmpsmcr = htim->Instance->SMCR; | |
4918 | |
4919 /* Reset the Trigger Selection Bits */ | |
4920 tmpsmcr &= ~TIM_SMCR_TS; | |
4921 /* Set the Input Trigger source */ | |
4922 tmpsmcr |= sSlaveConfig->InputTrigger; | |
4923 | |
4924 /* Reset the slave mode Bits */ | |
4925 tmpsmcr &= ~TIM_SMCR_SMS; | |
4926 /* Set the slave mode */ | |
4927 tmpsmcr |= sSlaveConfig->SlaveMode; | |
4928 | |
4929 /* Write to TIMx SMCR */ | |
4930 htim->Instance->SMCR = tmpsmcr; | |
4931 | |
4932 /* Configure the trigger prescaler, filter, and polarity */ | |
4933 switch (sSlaveConfig->InputTrigger) | |
4934 { | |
4935 case TIM_TS_ETRF: | |
4936 { | |
4937 /* Check the parameters */ | |
4938 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance)); | |
4939 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); | |
4940 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); | |
4941 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); | |
4942 /* Configure the ETR Trigger source */ | |
4943 TIM_ETR_SetConfig(htim->Instance, | |
4944 sSlaveConfig->TriggerPrescaler, | |
4945 sSlaveConfig->TriggerPolarity, | |
4946 sSlaveConfig->TriggerFilter); | |
4947 } | |
4948 break; | |
4949 | |
4950 case TIM_TS_TI1F_ED: | |
4951 { | |
4952 /* Check the parameters */ | |
4953 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); | |
4954 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); | |
4955 | |
4956 /* Disable the Channel 1: Reset the CC1E Bit */ | |
4957 tmpccer = htim->Instance->CCER; | |
4958 htim->Instance->CCER &= ~TIM_CCER_CC1E; | |
4959 tmpccmr1 = htim->Instance->CCMR1; | |
4960 | |
4961 /* Set the filter */ | |
4962 tmpccmr1 &= ~TIM_CCMR1_IC1F; | |
4963 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4); | |
4964 | |
4965 /* Write to TIMx CCMR1 and CCER registers */ | |
4966 htim->Instance->CCMR1 = tmpccmr1; | |
4967 htim->Instance->CCER = tmpccer; | |
4968 | |
4969 } | |
4970 break; | |
4971 | |
4972 case TIM_TS_TI1FP1: | |
4973 { | |
4974 /* Check the parameters */ | |
4975 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); | |
4976 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); | |
4977 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); | |
4978 | |
4979 /* Configure TI1 Filter and Polarity */ | |
4980 TIM_TI1_ConfigInputStage(htim->Instance, | |
4981 sSlaveConfig->TriggerPolarity, | |
4982 sSlaveConfig->TriggerFilter); | |
4983 } | |
4984 break; | |
4985 | |
4986 case TIM_TS_TI2FP2: | |
4987 { | |
4988 /* Check the parameters */ | |
4989 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); | |
4990 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); | |
4991 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); | |
4992 | |
4993 /* Configure TI2 Filter and Polarity */ | |
4994 TIM_TI2_ConfigInputStage(htim->Instance, | |
4995 sSlaveConfig->TriggerPolarity, | |
4996 sSlaveConfig->TriggerFilter); | |
4997 } | |
4998 break; | |
4999 | |
5000 case TIM_TS_ITR0: | |
5001 { | |
5002 /* Check the parameter */ | |
5003 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); | |
5004 } | |
5005 break; | |
5006 | |
5007 case TIM_TS_ITR1: | |
5008 { | |
5009 /* Check the parameter */ | |
5010 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); | |
5011 } | |
5012 break; | |
5013 | |
5014 case TIM_TS_ITR2: | |
5015 { | |
5016 /* Check the parameter */ | |
5017 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); | |
5018 } | |
5019 break; | |
5020 | |
5021 case TIM_TS_ITR3: | |
5022 { | |
5023 /* Check the parameter */ | |
5024 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); | |
5025 } | |
5026 break; | |
5027 | |
5028 default: | |
5029 break; | |
5030 } | |
5031 } | |
5032 | |
5033 | |
5034 /** | |
5035 * @brief Configure the Polarity and Filter for TI1. | |
5036 * @param TIMx to select the TIM peripheral. | |
5037 * @param TIM_ICPolarity : The Input Polarity. | |
5038 * This parameter can be one of the following values: | |
5039 * @arg TIM_ICPolarity_Rising | |
5040 * @arg TIM_ICPolarity_Falling | |
5041 * @arg TIM_ICPolarity_BothEdge | |
5042 * @param TIM_ICFilter: Specifies the Input Capture Filter. | |
5043 * This parameter must be a value between 0x00 and 0x0F. | |
5044 * @retval None | |
5045 */ | |
5046 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) | |
5047 { | |
5048 uint32_t tmpccmr1 = 0; | |
5049 uint32_t tmpccer = 0; | |
5050 | |
5051 /* Disable the Channel 1: Reset the CC1E Bit */ | |
5052 tmpccer = TIMx->CCER; | |
5053 TIMx->CCER &= ~TIM_CCER_CC1E; | |
5054 tmpccmr1 = TIMx->CCMR1; | |
5055 | |
5056 /* Set the filter */ | |
5057 tmpccmr1 &= ~TIM_CCMR1_IC1F; | |
5058 tmpccmr1 |= (TIM_ICFilter << 4); | |
5059 | |
5060 /* Select the Polarity and set the CC1E Bit */ | |
5061 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); | |
5062 tmpccer |= TIM_ICPolarity; | |
5063 | |
5064 /* Write to TIMx CCMR1 and CCER registers */ | |
5065 TIMx->CCMR1 = tmpccmr1; | |
5066 TIMx->CCER = tmpccer; | |
5067 } | |
5068 | |
5069 /** | |
5070 * @brief Configure the TI2 as Input. | |
5071 * @param TIMx to select the TIM peripheral | |
5072 * @param TIM_ICPolarity : The Input Polarity. | |
5073 * This parameter can be one of the following values: | |
5074 * @arg TIM_ICPolarity_Rising | |
5075 * @arg TIM_ICPolarity_Falling | |
5076 * @arg TIM_ICPolarity_BothEdge | |
5077 * @param TIM_ICSelection: specifies the input to be used. | |
5078 * This parameter can be one of the following values: | |
5079 * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. | |
5080 * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. | |
5081 * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. | |
5082 * @param TIM_ICFilter: Specifies the Input Capture Filter. | |
5083 * This parameter must be a value between 0x00 and 0x0F. | |
5084 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 | |
5085 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be | |
5086 * protected against un-initialized filter and polarity values. | |
5087 * @retval None | |
5088 */ | |
5089 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, | |
5090 uint32_t TIM_ICFilter) | |
5091 { | |
5092 uint32_t tmpccmr1 = 0; | |
5093 uint32_t tmpccer = 0; | |
5094 | |
5095 /* Disable the Channel 2: Reset the CC2E Bit */ | |
5096 TIMx->CCER &= ~TIM_CCER_CC2E; | |
5097 tmpccmr1 = TIMx->CCMR1; | |
5098 tmpccer = TIMx->CCER; | |
5099 | |
5100 /* Select the Input */ | |
5101 tmpccmr1 &= ~TIM_CCMR1_CC2S; | |
5102 tmpccmr1 |= (TIM_ICSelection << 8); | |
5103 | |
5104 /* Set the filter */ | |
5105 tmpccmr1 &= ~TIM_CCMR1_IC2F; | |
5106 tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F); | |
5107 | |
5108 /* Select the Polarity and set the CC2E Bit */ | |
5109 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); | |
5110 tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); | |
5111 | |
5112 /* Write to TIMx CCMR1 and CCER registers */ | |
5113 TIMx->CCMR1 = tmpccmr1 ; | |
5114 TIMx->CCER = tmpccer; | |
5115 } | |
5116 | |
5117 /** | |
5118 * @brief Configure the Polarity and Filter for TI2. | |
5119 * @param TIMx to select the TIM peripheral. | |
5120 * @param TIM_ICPolarity : The Input Polarity. | |
5121 * This parameter can be one of the following values: | |
5122 * @arg TIM_ICPolarity_Rising | |
5123 * @arg TIM_ICPolarity_Falling | |
5124 * @arg TIM_ICPolarity_BothEdge | |
5125 * @param TIM_ICFilter: Specifies the Input Capture Filter. | |
5126 * This parameter must be a value between 0x00 and 0x0F. | |
5127 * @retval None | |
5128 */ | |
5129 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) | |
5130 { | |
5131 uint32_t tmpccmr1 = 0; | |
5132 uint32_t tmpccer = 0; | |
5133 | |
5134 /* Disable the Channel 2: Reset the CC2E Bit */ | |
5135 TIMx->CCER &= ~TIM_CCER_CC2E; | |
5136 tmpccmr1 = TIMx->CCMR1; | |
5137 tmpccer = TIMx->CCER; | |
5138 | |
5139 /* Set the filter */ | |
5140 tmpccmr1 &= ~TIM_CCMR1_IC2F; | |
5141 tmpccmr1 |= (TIM_ICFilter << 12); | |
5142 | |
5143 /* Select the Polarity and set the CC2E Bit */ | |
5144 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); | |
5145 tmpccer |= (TIM_ICPolarity << 4); | |
5146 | |
5147 /* Write to TIMx CCMR1 and CCER registers */ | |
5148 TIMx->CCMR1 = tmpccmr1 ; | |
5149 TIMx->CCER = tmpccer; | |
5150 } | |
5151 | |
5152 /** | |
5153 * @brief Configure the TI3 as Input. | |
5154 * @param TIMx to select the TIM peripheral | |
5155 * @param TIM_ICPolarity : The Input Polarity. | |
5156 * This parameter can be one of the following values: | |
5157 * @arg TIM_ICPolarity_Rising | |
5158 * @arg TIM_ICPolarity_Falling | |
5159 * @arg TIM_ICPolarity_BothEdge | |
5160 * @param TIM_ICSelection: specifies the input to be used. | |
5161 * This parameter can be one of the following values: | |
5162 * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. | |
5163 * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. | |
5164 * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. | |
5165 * @param TIM_ICFilter: Specifies the Input Capture Filter. | |
5166 * This parameter must be a value between 0x00 and 0x0F. | |
5167 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 | |
5168 * (on channel4 path) is used as the input signal. Therefore CCMR2 must be | |
5169 * protected against un-initialized filter and polarity values. | |
5170 * @retval None | |
5171 */ | |
5172 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, | |
5173 uint32_t TIM_ICFilter) | |
5174 { | |
5175 uint32_t tmpccmr2 = 0; | |
5176 uint32_t tmpccer = 0; | |
5177 | |
5178 /* Disable the Channel 3: Reset the CC3E Bit */ | |
5179 TIMx->CCER &= ~TIM_CCER_CC3E; | |
5180 tmpccmr2 = TIMx->CCMR2; | |
5181 tmpccer = TIMx->CCER; | |
5182 | |
5183 /* Select the Input */ | |
5184 tmpccmr2 &= ~TIM_CCMR2_CC3S; | |
5185 tmpccmr2 |= TIM_ICSelection; | |
5186 | |
5187 /* Set the filter */ | |
5188 tmpccmr2 &= ~TIM_CCMR2_IC3F; | |
5189 tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F); | |
5190 | |
5191 /* Select the Polarity and set the CC3E Bit */ | |
5192 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); | |
5193 tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); | |
5194 | |
5195 /* Write to TIMx CCMR2 and CCER registers */ | |
5196 TIMx->CCMR2 = tmpccmr2; | |
5197 TIMx->CCER = tmpccer; | |
5198 } | |
5199 | |
5200 /** | |
5201 * @brief Configure the TI4 as Input. | |
5202 * @param TIMx to select the TIM peripheral | |
5203 * @param TIM_ICPolarity : The Input Polarity. | |
5204 * This parameter can be one of the following values: | |
5205 * @arg TIM_ICPolarity_Rising | |
5206 * @arg TIM_ICPolarity_Falling | |
5207 * @arg TIM_ICPolarity_BothEdge | |
5208 * @param TIM_ICSelection: specifies the input to be used. | |
5209 * This parameter can be one of the following values: | |
5210 * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. | |
5211 * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. | |
5212 * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. | |
5213 * @param TIM_ICFilter: Specifies the Input Capture Filter. | |
5214 * This parameter must be a value between 0x00 and 0x0F. | |
5215 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 | |
5216 * (on channel3 path) is used as the input signal. Therefore CCMR2 must be | |
5217 * protected against un-initialized filter and polarity values. | |
5218 * @retval None | |
5219 */ | |
5220 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, | |
5221 uint32_t TIM_ICFilter) | |
5222 { | |
5223 uint32_t tmpccmr2 = 0; | |
5224 uint32_t tmpccer = 0; | |
5225 | |
5226 /* Disable the Channel 4: Reset the CC4E Bit */ | |
5227 TIMx->CCER &= ~TIM_CCER_CC4E; | |
5228 tmpccmr2 = TIMx->CCMR2; | |
5229 tmpccer = TIMx->CCER; | |
5230 | |
5231 /* Select the Input */ | |
5232 tmpccmr2 &= ~TIM_CCMR2_CC4S; | |
5233 tmpccmr2 |= (TIM_ICSelection << 8); | |
5234 | |
5235 /* Set the filter */ | |
5236 tmpccmr2 &= ~TIM_CCMR2_IC4F; | |
5237 tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F); | |
5238 | |
5239 /* Select the Polarity and set the CC4E Bit */ | |
5240 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); | |
5241 tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); | |
5242 | |
5243 /* Write to TIMx CCMR2 and CCER registers */ | |
5244 TIMx->CCMR2 = tmpccmr2; | |
5245 TIMx->CCER = tmpccer ; | |
5246 } | |
5247 | |
5248 /** | |
5249 * @brief Selects the Input Trigger source | |
5250 * @param TIMx to select the TIM peripheral | |
5251 * @param TIM_ITRx: The Input Trigger source. | |
5252 * This parameter can be one of the following values: | |
5253 * @arg TIM_TS_ITR0: Internal Trigger 0 | |
5254 * @arg TIM_TS_ITR1: Internal Trigger 1 | |
5255 * @arg TIM_TS_ITR2: Internal Trigger 2 | |
5256 * @arg TIM_TS_ITR3: Internal Trigger 3 | |
5257 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector | |
5258 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 | |
5259 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 | |
5260 * @arg TIM_TS_ETRF: External Trigger input | |
5261 * @retval None | |
5262 */ | |
5263 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t TIM_ITRx) | |
5264 { | |
5265 uint32_t tmpsmcr = 0; | |
5266 | |
5267 /* Get the TIMx SMCR register value */ | |
5268 tmpsmcr = TIMx->SMCR; | |
5269 /* Reset the TS Bits */ | |
5270 tmpsmcr &= ~TIM_SMCR_TS; | |
5271 /* Set the Input Trigger source and the slave mode*/ | |
5272 tmpsmcr |= TIM_ITRx | TIM_SLAVEMODE_EXTERNAL1; | |
5273 /* Write to TIMx SMCR */ | |
5274 TIMx->SMCR = tmpsmcr; | |
5275 } | |
5276 | |
5277 /** | |
5278 * @brief Configures the TIMx External Trigger (ETR). | |
5279 * @param TIMx to select the TIM peripheral | |
5280 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. | |
5281 * This parameter can be one of the following values: | |
5282 * @arg TIM_ExtTRGPSC_DIV1: ETRP Prescaler OFF. | |
5283 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. | |
5284 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. | |
5285 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. | |
5286 * @param TIM_ExtTRGPolarity: The external Trigger Polarity. | |
5287 * This parameter can be one of the following values: | |
5288 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. | |
5289 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. | |
5290 * @param ExtTRGFilter: External Trigger Filter. | |
5291 * This parameter must be a value between 0x00 and 0x0F | |
5292 * @retval None | |
5293 */ | |
5294 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, | |
5295 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) | |
5296 { | |
5297 uint32_t tmpsmcr = 0; | |
5298 | |
5299 tmpsmcr = TIMx->SMCR; | |
5300 | |
5301 /* Reset the ETR Bits */ | |
5302 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); | |
5303 | |
5304 /* Set the Prescaler, the Filter value and the Polarity */ | |
5305 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8))); | |
5306 | |
5307 /* Write to TIMx SMCR */ | |
5308 TIMx->SMCR = tmpsmcr; | |
5309 } | |
5310 | |
5311 /** | |
5312 * @} | |
5313 */ | |
5314 | |
5315 #endif /* HAL_TIM_MODULE_ENABLED */ | |
5316 /** | |
5317 * @} | |
5318 */ | |
5319 | |
5320 /** | |
5321 * @} | |
5322 */ | |
5323 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |