Mercurial > public > ostc4
comparison Common/Drivers/STM32F4xx_HAL_DRIVER_v120/Src/stm32f4xx_hal_sram.c @ 38:5f11787b4f42
include in ostc4 repository
author | heinrichsweikamp |
---|---|
date | Sat, 28 Apr 2018 11:52:34 +0200 |
parents | |
children |
comparison
equal
deleted
inserted
replaced
37:ccc45c0e1ea2 | 38:5f11787b4f42 |
---|---|
1 /** | |
2 ****************************************************************************** | |
3 * @file stm32f4xx_hal_sram.c | |
4 * @author MCD Application Team | |
5 * @version V1.2.0 | |
6 * @date 26-December-2014 | |
7 * @brief SRAM HAL module driver. | |
8 * This file provides a generic firmware to drive SRAM memories | |
9 * mounted as external device. | |
10 * | |
11 @verbatim | |
12 ============================================================================== | |
13 ##### How to use this driver ##### | |
14 ============================================================================== | |
15 [..] | |
16 This driver is a generic layered driver which contains a set of APIs used to | |
17 control SRAM memories. It uses the FMC layer functions to interface | |
18 with SRAM devices. | |
19 The following sequence should be followed to configure the FMC/FSMC to interface | |
20 with SRAM/PSRAM memories: | |
21 | |
22 (#) Declare a SRAM_HandleTypeDef handle structure, for example: | |
23 SRAM_HandleTypeDef hsram; and: | |
24 | |
25 (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed | |
26 values of the structure member. | |
27 | |
28 (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined | |
29 base register instance for NOR or SRAM device | |
30 | |
31 (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined | |
32 base register instance for NOR or SRAM extended mode | |
33 | |
34 (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended | |
35 mode timings; for example: | |
36 FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming; | |
37 and fill its fields with the allowed values of the structure member. | |
38 | |
39 (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function | |
40 performs the following sequence: | |
41 | |
42 (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit() | |
43 (##) Control register configuration using the FMC NORSRAM interface function | |
44 FMC_NORSRAM_Init() | |
45 (##) Timing register configuration using the FMC NORSRAM interface function | |
46 FMC_NORSRAM_Timing_Init() | |
47 (##) Extended mode Timing register configuration using the FMC NORSRAM interface function | |
48 FMC_NORSRAM_Extended_Timing_Init() | |
49 (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE() | |
50 | |
51 (#) At this stage you can perform read/write accesses from/to the memory connected | |
52 to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the | |
53 following APIs: | |
54 (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access | |
55 (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer | |
56 | |
57 (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/ | |
58 HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation | |
59 | |
60 (#) You can continuously monitor the SRAM device HAL state by calling the function | |
61 HAL_SRAM_GetState() | |
62 | |
63 @endverbatim | |
64 ****************************************************************************** | |
65 * @attention | |
66 * | |
67 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> | |
68 * | |
69 * Redistribution and use in source and binary forms, with or without modification, | |
70 * are permitted provided that the following conditions are met: | |
71 * 1. Redistributions of source code must retain the above copyright notice, | |
72 * this list of conditions and the following disclaimer. | |
73 * 2. Redistributions in binary form must reproduce the above copyright notice, | |
74 * this list of conditions and the following disclaimer in the documentation | |
75 * and/or other materials provided with the distribution. | |
76 * 3. Neither the name of STMicroelectronics nor the names of its contributors | |
77 * may be used to endorse or promote products derived from this software | |
78 * without specific prior written permission. | |
79 * | |
80 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
81 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
82 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
83 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE | |
84 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
85 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
86 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER | |
87 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | |
88 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
89 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
90 * | |
91 ****************************************************************************** | |
92 */ | |
93 | |
94 /* Includes ------------------------------------------------------------------*/ | |
95 #include "stm32f4xx_hal.h" | |
96 | |
97 /** @addtogroup STM32F4xx_HAL_Driver | |
98 * @{ | |
99 */ | |
100 | |
101 /** @defgroup SRAM SRAM | |
102 * @brief SRAM driver modules | |
103 * @{ | |
104 */ | |
105 #ifdef HAL_SRAM_MODULE_ENABLED | |
106 | |
107 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) | |
108 | |
109 /* Private typedef -----------------------------------------------------------*/ | |
110 /* Private define ------------------------------------------------------------*/ | |
111 /* Private macro -------------------------------------------------------------*/ | |
112 /* Private variables ---------------------------------------------------------*/ | |
113 /* Private functions ---------------------------------------------------------*/ | |
114 | |
115 /* Exported functions --------------------------------------------------------*/ | |
116 /** @defgroup SRAM_Exported_Functions SRAM Exported Functions | |
117 * @{ | |
118 */ | |
119 /** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions | |
120 * @brief Initialization and Configuration functions | |
121 * | |
122 @verbatim | |
123 ============================================================================== | |
124 ##### SRAM Initialization and de_initialization functions ##### | |
125 ============================================================================== | |
126 [..] This section provides functions allowing to initialize/de-initialize | |
127 the SRAM memory | |
128 | |
129 @endverbatim | |
130 * @{ | |
131 */ | |
132 | |
133 /** | |
134 * @brief Performs the SRAM device initialization sequence | |
135 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains | |
136 * the configuration information for SRAM module. | |
137 * @param Timing: Pointer to SRAM control timing structure | |
138 * @param ExtTiming: Pointer to SRAM extended mode timing structure | |
139 * @retval HAL status | |
140 */ | |
141 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming) | |
142 { | |
143 /* Check the SRAM handle parameter */ | |
144 if(hsram == NULL) | |
145 { | |
146 return HAL_ERROR; | |
147 } | |
148 | |
149 if(hsram->State == HAL_SRAM_STATE_RESET) | |
150 { | |
151 /* Initialize the low level hardware (MSP) */ | |
152 HAL_SRAM_MspInit(hsram); | |
153 } | |
154 | |
155 /* Initialize SRAM control Interface */ | |
156 FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init)); | |
157 | |
158 /* Initialize SRAM timing Interface */ | |
159 FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank); | |
160 | |
161 /* Initialize SRAM extended mode timing Interface */ | |
162 FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode); | |
163 | |
164 /* Enable the NORSRAM device */ | |
165 __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank); | |
166 | |
167 return HAL_OK; | |
168 } | |
169 | |
170 /** | |
171 * @brief Performs the SRAM device De-initialization sequence. | |
172 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains | |
173 * the configuration information for SRAM module. | |
174 * @retval HAL status | |
175 */ | |
176 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram) | |
177 { | |
178 /* De-Initialize the low level hardware (MSP) */ | |
179 HAL_SRAM_MspDeInit(hsram); | |
180 | |
181 /* Configure the SRAM registers with their reset values */ | |
182 FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank); | |
183 | |
184 hsram->State = HAL_SRAM_STATE_RESET; | |
185 | |
186 /* Release Lock */ | |
187 __HAL_UNLOCK(hsram); | |
188 | |
189 return HAL_OK; | |
190 } | |
191 | |
192 /** | |
193 * @brief SRAM MSP Init. | |
194 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains | |
195 * the configuration information for SRAM module. | |
196 * @retval None | |
197 */ | |
198 __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram) | |
199 { | |
200 /* NOTE : This function Should not be modified, when the callback is needed, | |
201 the HAL_SRAM_MspInit could be implemented in the user file | |
202 */ | |
203 } | |
204 | |
205 /** | |
206 * @brief SRAM MSP DeInit. | |
207 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains | |
208 * the configuration information for SRAM module. | |
209 * @retval None | |
210 */ | |
211 __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram) | |
212 { | |
213 /* NOTE : This function Should not be modified, when the callback is needed, | |
214 the HAL_SRAM_MspDeInit could be implemented in the user file | |
215 */ | |
216 } | |
217 | |
218 /** | |
219 * @brief DMA transfer complete callback. | |
220 * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains | |
221 * the configuration information for SRAM module. | |
222 * @retval None | |
223 */ | |
224 __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma) | |
225 { | |
226 /* NOTE : This function Should not be modified, when the callback is needed, | |
227 the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file | |
228 */ | |
229 } | |
230 | |
231 /** | |
232 * @brief DMA transfer complete error callback. | |
233 * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains | |
234 * the configuration information for SRAM module. | |
235 * @retval None | |
236 */ | |
237 __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) | |
238 { | |
239 /* NOTE : This function Should not be modified, when the callback is needed, | |
240 the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file | |
241 */ | |
242 } | |
243 | |
244 /** | |
245 * @} | |
246 */ | |
247 | |
248 /** @defgroup SRAM_Exported_Functions_Group2 Input and Output functions | |
249 * @brief Input Output and memory control functions | |
250 * | |
251 @verbatim | |
252 ============================================================================== | |
253 ##### SRAM Input and Output functions ##### | |
254 ============================================================================== | |
255 [..] | |
256 This section provides functions allowing to use and control the SRAM memory | |
257 | |
258 @endverbatim | |
259 * @{ | |
260 */ | |
261 | |
262 /** | |
263 * @brief Reads 8-bit buffer from SRAM memory. | |
264 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains | |
265 * the configuration information for SRAM module. | |
266 * @param pAddress: Pointer to read start address | |
267 * @param pDstBuffer: Pointer to destination buffer | |
268 * @param BufferSize: Size of the buffer to read from memory | |
269 * @retval HAL status | |
270 */ | |
271 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize) | |
272 { | |
273 __IO uint8_t * pSramAddress = (uint8_t *)pAddress; | |
274 | |
275 /* Process Locked */ | |
276 __HAL_LOCK(hsram); | |
277 | |
278 /* Update the SRAM controller state */ | |
279 hsram->State = HAL_SRAM_STATE_BUSY; | |
280 | |
281 /* Read data from memory */ | |
282 for(; BufferSize != 0; BufferSize--) | |
283 { | |
284 *pDstBuffer = *(__IO uint8_t *)pSramAddress; | |
285 pDstBuffer++; | |
286 pSramAddress++; | |
287 } | |
288 | |
289 /* Update the SRAM controller state */ | |
290 hsram->State = HAL_SRAM_STATE_READY; | |
291 | |
292 /* Process unlocked */ | |
293 __HAL_UNLOCK(hsram); | |
294 | |
295 return HAL_OK; | |
296 } | |
297 | |
298 /** | |
299 * @brief Writes 8-bit buffer to SRAM memory. | |
300 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains | |
301 * the configuration information for SRAM module. | |
302 * @param pAddress: Pointer to write start address | |
303 * @param pSrcBuffer: Pointer to source buffer to write | |
304 * @param BufferSize: Size of the buffer to write to memory | |
305 * @retval HAL status | |
306 */ | |
307 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize) | |
308 { | |
309 __IO uint8_t * pSramAddress = (uint8_t *)pAddress; | |
310 | |
311 /* Check the SRAM controller state */ | |
312 if(hsram->State == HAL_SRAM_STATE_PROTECTED) | |
313 { | |
314 return HAL_ERROR; | |
315 } | |
316 | |
317 /* Process Locked */ | |
318 __HAL_LOCK(hsram); | |
319 | |
320 /* Update the SRAM controller state */ | |
321 hsram->State = HAL_SRAM_STATE_BUSY; | |
322 | |
323 /* Write data to memory */ | |
324 for(; BufferSize != 0; BufferSize--) | |
325 { | |
326 *(__IO uint8_t *)pSramAddress = *pSrcBuffer; | |
327 pSrcBuffer++; | |
328 pSramAddress++; | |
329 } | |
330 | |
331 /* Update the SRAM controller state */ | |
332 hsram->State = HAL_SRAM_STATE_READY; | |
333 | |
334 /* Process unlocked */ | |
335 __HAL_UNLOCK(hsram); | |
336 | |
337 return HAL_OK; | |
338 } | |
339 | |
340 /** | |
341 * @brief Reads 16-bit buffer from SRAM memory. | |
342 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains | |
343 * the configuration information for SRAM module. | |
344 * @param pAddress: Pointer to read start address | |
345 * @param pDstBuffer: Pointer to destination buffer | |
346 * @param BufferSize: Size of the buffer to read from memory | |
347 * @retval HAL status | |
348 */ | |
349 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize) | |
350 { | |
351 __IO uint16_t * pSramAddress = (uint16_t *)pAddress; | |
352 | |
353 /* Process Locked */ | |
354 __HAL_LOCK(hsram); | |
355 | |
356 /* Update the SRAM controller state */ | |
357 hsram->State = HAL_SRAM_STATE_BUSY; | |
358 | |
359 /* Read data from memory */ | |
360 for(; BufferSize != 0; BufferSize--) | |
361 { | |
362 *pDstBuffer = *(__IO uint16_t *)pSramAddress; | |
363 pDstBuffer++; | |
364 pSramAddress++; | |
365 } | |
366 | |
367 /* Update the SRAM controller state */ | |
368 hsram->State = HAL_SRAM_STATE_READY; | |
369 | |
370 /* Process unlocked */ | |
371 __HAL_UNLOCK(hsram); | |
372 | |
373 return HAL_OK; | |
374 } | |
375 | |
376 /** | |
377 * @brief Writes 16-bit buffer to SRAM memory. | |
378 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains | |
379 * the configuration information for SRAM module. | |
380 * @param pAddress: Pointer to write start address | |
381 * @param pSrcBuffer: Pointer to source buffer to write | |
382 * @param BufferSize: Size of the buffer to write to memory | |
383 * @retval HAL status | |
384 */ | |
385 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize) | |
386 { | |
387 __IO uint16_t * pSramAddress = (uint16_t *)pAddress; | |
388 | |
389 /* Check the SRAM controller state */ | |
390 if(hsram->State == HAL_SRAM_STATE_PROTECTED) | |
391 { | |
392 return HAL_ERROR; | |
393 } | |
394 | |
395 /* Process Locked */ | |
396 __HAL_LOCK(hsram); | |
397 | |
398 /* Update the SRAM controller state */ | |
399 hsram->State = HAL_SRAM_STATE_BUSY; | |
400 | |
401 /* Write data to memory */ | |
402 for(; BufferSize != 0; BufferSize--) | |
403 { | |
404 *(__IO uint16_t *)pSramAddress = *pSrcBuffer; | |
405 pSrcBuffer++; | |
406 pSramAddress++; | |
407 } | |
408 | |
409 /* Update the SRAM controller state */ | |
410 hsram->State = HAL_SRAM_STATE_READY; | |
411 | |
412 /* Process unlocked */ | |
413 __HAL_UNLOCK(hsram); | |
414 | |
415 return HAL_OK; | |
416 } | |
417 | |
418 /** | |
419 * @brief Reads 32-bit buffer from SRAM memory. | |
420 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains | |
421 * the configuration information for SRAM module. | |
422 * @param pAddress: Pointer to read start address | |
423 * @param pDstBuffer: Pointer to destination buffer | |
424 * @param BufferSize: Size of the buffer to read from memory | |
425 * @retval HAL status | |
426 */ | |
427 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) | |
428 { | |
429 /* Process Locked */ | |
430 __HAL_LOCK(hsram); | |
431 | |
432 /* Update the SRAM controller state */ | |
433 hsram->State = HAL_SRAM_STATE_BUSY; | |
434 | |
435 /* Read data from memory */ | |
436 for(; BufferSize != 0; BufferSize--) | |
437 { | |
438 *pDstBuffer = *(__IO uint32_t *)pAddress; | |
439 pDstBuffer++; | |
440 pAddress++; | |
441 } | |
442 | |
443 /* Update the SRAM controller state */ | |
444 hsram->State = HAL_SRAM_STATE_READY; | |
445 | |
446 /* Process unlocked */ | |
447 __HAL_UNLOCK(hsram); | |
448 | |
449 return HAL_OK; | |
450 } | |
451 | |
452 /** | |
453 * @brief Writes 32-bit buffer to SRAM memory. | |
454 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains | |
455 * the configuration information for SRAM module. | |
456 * @param pAddress: Pointer to write start address | |
457 * @param pSrcBuffer: Pointer to source buffer to write | |
458 * @param BufferSize: Size of the buffer to write to memory | |
459 * @retval HAL status | |
460 */ | |
461 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) | |
462 { | |
463 /* Check the SRAM controller state */ | |
464 if(hsram->State == HAL_SRAM_STATE_PROTECTED) | |
465 { | |
466 return HAL_ERROR; | |
467 } | |
468 | |
469 /* Process Locked */ | |
470 __HAL_LOCK(hsram); | |
471 | |
472 /* Update the SRAM controller state */ | |
473 hsram->State = HAL_SRAM_STATE_BUSY; | |
474 | |
475 /* Write data to memory */ | |
476 for(; BufferSize != 0; BufferSize--) | |
477 { | |
478 *(__IO uint32_t *)pAddress = *pSrcBuffer; | |
479 pSrcBuffer++; | |
480 pAddress++; | |
481 } | |
482 | |
483 /* Update the SRAM controller state */ | |
484 hsram->State = HAL_SRAM_STATE_READY; | |
485 | |
486 /* Process unlocked */ | |
487 __HAL_UNLOCK(hsram); | |
488 | |
489 return HAL_OK; | |
490 } | |
491 | |
492 /** | |
493 * @brief Reads a Words data from the SRAM memory using DMA transfer. | |
494 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains | |
495 * the configuration information for SRAM module. | |
496 * @param pAddress: Pointer to read start address | |
497 * @param pDstBuffer: Pointer to destination buffer | |
498 * @param BufferSize: Size of the buffer to read from memory | |
499 * @retval HAL status | |
500 */ | |
501 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) | |
502 { | |
503 /* Process Locked */ | |
504 __HAL_LOCK(hsram); | |
505 | |
506 /* Update the SRAM controller state */ | |
507 hsram->State = HAL_SRAM_STATE_BUSY; | |
508 | |
509 /* Configure DMA user callbacks */ | |
510 hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback; | |
511 hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback; | |
512 | |
513 /* Enable the DMA Stream */ | |
514 HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize); | |
515 | |
516 /* Update the SRAM controller state */ | |
517 hsram->State = HAL_SRAM_STATE_READY; | |
518 | |
519 /* Process unlocked */ | |
520 __HAL_UNLOCK(hsram); | |
521 | |
522 return HAL_OK; | |
523 } | |
524 | |
525 /** | |
526 * @brief Writes a Words data buffer to SRAM memory using DMA transfer. | |
527 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains | |
528 * the configuration information for SRAM module. | |
529 * @param pAddress: Pointer to write start address | |
530 * @param pSrcBuffer: Pointer to source buffer to write | |
531 * @param BufferSize: Size of the buffer to write to memory | |
532 * @retval HAL status | |
533 */ | |
534 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) | |
535 { | |
536 /* Check the SRAM controller state */ | |
537 if(hsram->State == HAL_SRAM_STATE_PROTECTED) | |
538 { | |
539 return HAL_ERROR; | |
540 } | |
541 | |
542 /* Process Locked */ | |
543 __HAL_LOCK(hsram); | |
544 | |
545 /* Update the SRAM controller state */ | |
546 hsram->State = HAL_SRAM_STATE_BUSY; | |
547 | |
548 /* Configure DMA user callbacks */ | |
549 hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback; | |
550 hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback; | |
551 | |
552 /* Enable the DMA Stream */ | |
553 HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize); | |
554 | |
555 /* Update the SRAM controller state */ | |
556 hsram->State = HAL_SRAM_STATE_READY; | |
557 | |
558 /* Process unlocked */ | |
559 __HAL_UNLOCK(hsram); | |
560 | |
561 return HAL_OK; | |
562 } | |
563 | |
564 /** | |
565 * @} | |
566 */ | |
567 | |
568 /** @defgroup SRAM_Exported_Functions_Group3 Control functions | |
569 * @brief management functions | |
570 * | |
571 @verbatim | |
572 ============================================================================== | |
573 ##### SRAM Control functions ##### | |
574 ============================================================================== | |
575 [..] | |
576 This subsection provides a set of functions allowing to control dynamically | |
577 the SRAM interface. | |
578 | |
579 @endverbatim | |
580 * @{ | |
581 */ | |
582 | |
583 /** | |
584 * @brief Enables dynamically SRAM write operation. | |
585 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains | |
586 * the configuration information for SRAM module. | |
587 * @retval HAL status | |
588 */ | |
589 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram) | |
590 { | |
591 /* Process Locked */ | |
592 __HAL_LOCK(hsram); | |
593 | |
594 /* Enable write operation */ | |
595 FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank); | |
596 | |
597 /* Update the SRAM controller state */ | |
598 hsram->State = HAL_SRAM_STATE_READY; | |
599 | |
600 /* Process unlocked */ | |
601 __HAL_UNLOCK(hsram); | |
602 | |
603 return HAL_OK; | |
604 } | |
605 | |
606 /** | |
607 * @brief Disables dynamically SRAM write operation. | |
608 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains | |
609 * the configuration information for SRAM module. | |
610 * @retval HAL status | |
611 */ | |
612 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram) | |
613 { | |
614 /* Process Locked */ | |
615 __HAL_LOCK(hsram); | |
616 | |
617 /* Update the SRAM controller state */ | |
618 hsram->State = HAL_SRAM_STATE_BUSY; | |
619 | |
620 /* Disable write operation */ | |
621 FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank); | |
622 | |
623 /* Update the SRAM controller state */ | |
624 hsram->State = HAL_SRAM_STATE_PROTECTED; | |
625 | |
626 /* Process unlocked */ | |
627 __HAL_UNLOCK(hsram); | |
628 | |
629 return HAL_OK; | |
630 } | |
631 | |
632 /** | |
633 * @} | |
634 */ | |
635 | |
636 /** @defgroup SRAM_Exported_Functions_Group4 State functions | |
637 * @brief Peripheral State functions | |
638 * | |
639 @verbatim | |
640 ============================================================================== | |
641 ##### SRAM State functions ##### | |
642 ============================================================================== | |
643 [..] | |
644 This subsection permits to get in run-time the status of the SRAM controller | |
645 and the data flow. | |
646 | |
647 @endverbatim | |
648 * @{ | |
649 */ | |
650 | |
651 /** | |
652 * @brief Returns the SRAM controller state | |
653 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains | |
654 * the configuration information for SRAM module. | |
655 * @retval HAL state | |
656 */ | |
657 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram) | |
658 { | |
659 return hsram->State; | |
660 } | |
661 /** | |
662 * @} | |
663 */ | |
664 | |
665 /** | |
666 * @} | |
667 */ | |
668 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ | |
669 #endif /* HAL_SRAM_MODULE_ENABLED */ | |
670 /** | |
671 * @} | |
672 */ | |
673 | |
674 /** | |
675 * @} | |
676 */ | |
677 | |
678 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |