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comparison Common/Drivers/STM32F4xx_HAL_DRIVER_v120/Src/stm32f4xx_hal_sdram.c @ 38:5f11787b4f42
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author | heinrichsweikamp |
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date | Sat, 28 Apr 2018 11:52:34 +0200 |
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1 /** | |
2 ****************************************************************************** | |
3 * @file stm32f4xx_hal_sdram.c | |
4 * @author MCD Application Team | |
5 * @version V1.2.0 | |
6 * @date 26-December-2014 | |
7 * @brief SDRAM HAL module driver. | |
8 * This file provides a generic firmware to drive SDRAM memories mounted | |
9 * as external device. | |
10 * | |
11 @verbatim | |
12 ============================================================================== | |
13 ##### How to use this driver ##### | |
14 ============================================================================== | |
15 [..] | |
16 This driver is a generic layered driver which contains a set of APIs used to | |
17 control SDRAM memories. It uses the FMC layer functions to interface | |
18 with SDRAM devices. | |
19 The following sequence should be followed to configure the FMC to interface | |
20 with SDRAM memories: | |
21 | |
22 (#) Declare a SDRAM_HandleTypeDef handle structure, for example: | |
23 SDRAM_HandleTypeDef hdsram | |
24 | |
25 (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed | |
26 values of the structure member. | |
27 | |
28 (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined | |
29 base register instance for NOR or SDRAM device | |
30 | |
31 (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example: | |
32 FMC_SDRAM_TimingTypeDef Timing; | |
33 and fill its fields with the allowed values of the structure member. | |
34 | |
35 (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function | |
36 performs the following sequence: | |
37 | |
38 (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit() | |
39 (##) Control register configuration using the FMC SDRAM interface function | |
40 FMC_SDRAM_Init() | |
41 (##) Timing register configuration using the FMC SDRAM interface function | |
42 FMC_SDRAM_Timing_Init() | |
43 (##) Program the SDRAM external device by applying its initialization sequence | |
44 according to the device plugged in your hardware. This step is mandatory | |
45 for accessing the SDRAM device. | |
46 | |
47 (#) At this stage you can perform read/write accesses from/to the memory connected | |
48 to the SDRAM Bank. You can perform either polling or DMA transfer using the | |
49 following APIs: | |
50 (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access | |
51 (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer | |
52 | |
53 (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/ | |
54 HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or | |
55 the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM | |
56 device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef | |
57 structure. | |
58 | |
59 (#) You can continuously monitor the SDRAM device HAL state by calling the function | |
60 HAL_SDRAM_GetState() | |
61 | |
62 @endverbatim | |
63 ****************************************************************************** | |
64 * @attention | |
65 * | |
66 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> | |
67 * | |
68 * Redistribution and use in source and binary forms, with or without modification, | |
69 * are permitted provided that the following conditions are met: | |
70 * 1. Redistributions of source code must retain the above copyright notice, | |
71 * this list of conditions and the following disclaimer. | |
72 * 2. Redistributions in binary form must reproduce the above copyright notice, | |
73 * this list of conditions and the following disclaimer in the documentation | |
74 * and/or other materials provided with the distribution. | |
75 * 3. Neither the name of STMicroelectronics nor the names of its contributors | |
76 * may be used to endorse or promote products derived from this software | |
77 * without specific prior written permission. | |
78 * | |
79 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
80 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
81 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
82 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE | |
83 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
84 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
85 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER | |
86 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | |
87 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
88 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
89 * | |
90 ****************************************************************************** | |
91 */ | |
92 | |
93 /* Includes ------------------------------------------------------------------*/ | |
94 #include "stm32f4xx_hal.h" | |
95 | |
96 /** @addtogroup STM32F4xx_HAL_Driver | |
97 * @{ | |
98 */ | |
99 | |
100 /** @defgroup SDRAM SDRAM | |
101 * @brief SDRAM driver modules | |
102 * @{ | |
103 */ | |
104 #ifdef HAL_SDRAM_MODULE_ENABLED | |
105 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) | |
106 | |
107 /* Private typedef -----------------------------------------------------------*/ | |
108 /* Private define ------------------------------------------------------------*/ | |
109 /* Private macro -------------------------------------------------------------*/ | |
110 /* Private variables ---------------------------------------------------------*/ | |
111 /* Private functions ---------------------------------------------------------*/ | |
112 /* Exported functions --------------------------------------------------------*/ | |
113 /** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions | |
114 * @{ | |
115 */ | |
116 | |
117 /** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions | |
118 * @brief Initialization and Configuration functions | |
119 * | |
120 @verbatim | |
121 ============================================================================== | |
122 ##### SDRAM Initialization and de_initialization functions ##### | |
123 ============================================================================== | |
124 [..] | |
125 This section provides functions allowing to initialize/de-initialize | |
126 the SDRAM memory | |
127 | |
128 @endverbatim | |
129 * @{ | |
130 */ | |
131 | |
132 /** | |
133 * @brief Performs the SDRAM device initialization sequence. | |
134 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains | |
135 * the configuration information for SDRAM module. | |
136 * @param Timing: Pointer to SDRAM control timing structure | |
137 * @retval HAL status | |
138 */ | |
139 HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing) | |
140 { | |
141 /* Check the SDRAM handle parameter */ | |
142 if(hsdram == NULL) | |
143 { | |
144 return HAL_ERROR; | |
145 } | |
146 | |
147 if(hsdram->State == HAL_SDRAM_STATE_RESET) | |
148 { | |
149 /* Initialize the low level hardware (MSP) */ | |
150 HAL_SDRAM_MspInit(hsdram); | |
151 } | |
152 | |
153 /* Initialize the SDRAM controller state */ | |
154 hsdram->State = HAL_SDRAM_STATE_BUSY; | |
155 | |
156 /* Initialize SDRAM control Interface */ | |
157 FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init)); | |
158 | |
159 /* Initialize SDRAM timing Interface */ | |
160 FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank); | |
161 | |
162 /* Update the SDRAM controller state */ | |
163 hsdram->State = HAL_SDRAM_STATE_READY; | |
164 | |
165 return HAL_OK; | |
166 } | |
167 | |
168 /** | |
169 * @brief Perform the SDRAM device initialization sequence. | |
170 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains | |
171 * the configuration information for SDRAM module. | |
172 * @retval HAL status | |
173 */ | |
174 HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram) | |
175 { | |
176 /* Initialize the low level hardware (MSP) */ | |
177 HAL_SDRAM_MspDeInit(hsdram); | |
178 | |
179 /* Configure the SDRAM registers with their reset values */ | |
180 FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank); | |
181 | |
182 /* Reset the SDRAM controller state */ | |
183 hsdram->State = HAL_SDRAM_STATE_RESET; | |
184 | |
185 /* Release Lock */ | |
186 __HAL_UNLOCK(hsdram); | |
187 | |
188 return HAL_OK; | |
189 } | |
190 | |
191 /** | |
192 * @brief SDRAM MSP Init. | |
193 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains | |
194 * the configuration information for SDRAM module. | |
195 * @retval None | |
196 */ | |
197 __weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram) | |
198 { | |
199 /* NOTE: This function Should not be modified, when the callback is needed, | |
200 the HAL_SDRAM_MspInit could be implemented in the user file | |
201 */ | |
202 } | |
203 | |
204 /** | |
205 * @brief SDRAM MSP DeInit. | |
206 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains | |
207 * the configuration information for SDRAM module. | |
208 * @retval None | |
209 */ | |
210 __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram) | |
211 { | |
212 /* NOTE: This function Should not be modified, when the callback is needed, | |
213 the HAL_SDRAM_MspDeInit could be implemented in the user file | |
214 */ | |
215 } | |
216 | |
217 /** | |
218 * @brief This function handles SDRAM refresh error interrupt request. | |
219 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains | |
220 * the configuration information for SDRAM module. | |
221 * @retval HAL status | |
222 */ | |
223 void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram) | |
224 { | |
225 /* Check SDRAM interrupt Rising edge flag */ | |
226 if(__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT)) | |
227 { | |
228 /* SDRAM refresh error interrupt callback */ | |
229 HAL_SDRAM_RefreshErrorCallback(hsdram); | |
230 | |
231 /* Clear SDRAM refresh error interrupt pending bit */ | |
232 __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR); | |
233 } | |
234 } | |
235 | |
236 /** | |
237 * @brief SDRAM Refresh error callback. | |
238 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains | |
239 * the configuration information for SDRAM module. | |
240 * @retval None | |
241 */ | |
242 __weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram) | |
243 { | |
244 /* NOTE: This function Should not be modified, when the callback is needed, | |
245 the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file | |
246 */ | |
247 } | |
248 | |
249 /** | |
250 * @brief DMA transfer complete callback. | |
251 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains | |
252 * the configuration information for the specified DMA module. | |
253 * @retval None | |
254 */ | |
255 __weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma) | |
256 { | |
257 /* NOTE: This function Should not be modified, when the callback is needed, | |
258 the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file | |
259 */ | |
260 } | |
261 | |
262 /** | |
263 * @brief DMA transfer complete error callback. | |
264 * @param hdma: DMA handle | |
265 * @retval None | |
266 */ | |
267 __weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) | |
268 { | |
269 /* NOTE: This function Should not be modified, when the callback is needed, | |
270 the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file | |
271 */ | |
272 } | |
273 /** | |
274 * @} | |
275 */ | |
276 | |
277 /** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions | |
278 * @brief Input Output and memory control functions | |
279 * | |
280 @verbatim | |
281 ============================================================================== | |
282 ##### SDRAM Input and Output functions ##### | |
283 ============================================================================== | |
284 [..] | |
285 This section provides functions allowing to use and control the SDRAM memory | |
286 | |
287 @endverbatim | |
288 * @{ | |
289 */ | |
290 | |
291 /** | |
292 * @brief Reads 8-bit data buffer from the SDRAM memory. | |
293 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains | |
294 * the configuration information for SDRAM module. | |
295 * @param pAddress: Pointer to read start address | |
296 * @param pDstBuffer: Pointer to destination buffer | |
297 * @param BufferSize: Size of the buffer to read from memory | |
298 * @retval HAL status | |
299 */ | |
300 HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize) | |
301 { | |
302 __IO uint8_t *pSdramAddress = (uint8_t *)pAddress; | |
303 | |
304 /* Process Locked */ | |
305 __HAL_LOCK(hsdram); | |
306 | |
307 /* Check the SDRAM controller state */ | |
308 if(hsdram->State == HAL_SDRAM_STATE_BUSY) | |
309 { | |
310 return HAL_BUSY; | |
311 } | |
312 else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED) | |
313 { | |
314 return HAL_ERROR; | |
315 } | |
316 | |
317 /* Read data from source */ | |
318 for(; BufferSize != 0; BufferSize--) | |
319 { | |
320 *pDstBuffer = *(__IO uint8_t *)pSdramAddress; | |
321 pDstBuffer++; | |
322 pSdramAddress++; | |
323 } | |
324 | |
325 /* Process Unlocked */ | |
326 __HAL_UNLOCK(hsdram); | |
327 | |
328 return HAL_OK; | |
329 } | |
330 | |
331 /** | |
332 * @brief Writes 8-bit data buffer to SDRAM memory. | |
333 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains | |
334 * the configuration information for SDRAM module. | |
335 * @param pAddress: Pointer to write start address | |
336 * @param pSrcBuffer: Pointer to source buffer to write | |
337 * @param BufferSize: Size of the buffer to write to memory | |
338 * @retval HAL status | |
339 */ | |
340 HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize) | |
341 { | |
342 __IO uint8_t *pSdramAddress = (uint8_t *)pAddress; | |
343 uint32_t tmp = 0; | |
344 | |
345 /* Process Locked */ | |
346 __HAL_LOCK(hsdram); | |
347 | |
348 /* Check the SDRAM controller state */ | |
349 tmp = hsdram->State; | |
350 | |
351 if(tmp == HAL_SDRAM_STATE_BUSY) | |
352 { | |
353 return HAL_BUSY; | |
354 } | |
355 else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) | |
356 { | |
357 return HAL_ERROR; | |
358 } | |
359 | |
360 /* Write data to memory */ | |
361 for(; BufferSize != 0; BufferSize--) | |
362 { | |
363 *(__IO uint8_t *)pSdramAddress = *pSrcBuffer; | |
364 pSrcBuffer++; | |
365 pSdramAddress++; | |
366 } | |
367 | |
368 /* Process Unlocked */ | |
369 __HAL_UNLOCK(hsdram); | |
370 | |
371 return HAL_OK; | |
372 } | |
373 | |
374 /** | |
375 * @brief Reads 16-bit data buffer from the SDRAM memory. | |
376 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains | |
377 * the configuration information for SDRAM module. | |
378 * @param pAddress: Pointer to read start address | |
379 * @param pDstBuffer: Pointer to destination buffer | |
380 * @param BufferSize: Size of the buffer to read from memory | |
381 * @retval HAL status | |
382 */ | |
383 HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize) | |
384 { | |
385 __IO uint16_t *pSdramAddress = (uint16_t *)pAddress; | |
386 | |
387 /* Process Locked */ | |
388 __HAL_LOCK(hsdram); | |
389 | |
390 /* Check the SDRAM controller state */ | |
391 if(hsdram->State == HAL_SDRAM_STATE_BUSY) | |
392 { | |
393 return HAL_BUSY; | |
394 } | |
395 else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED) | |
396 { | |
397 return HAL_ERROR; | |
398 } | |
399 | |
400 /* Read data from source */ | |
401 for(; BufferSize != 0; BufferSize--) | |
402 { | |
403 *pDstBuffer = *(__IO uint16_t *)pSdramAddress; | |
404 pDstBuffer++; | |
405 pSdramAddress++; | |
406 } | |
407 | |
408 /* Process Unlocked */ | |
409 __HAL_UNLOCK(hsdram); | |
410 | |
411 return HAL_OK; | |
412 } | |
413 | |
414 /** | |
415 * @brief Writes 16-bit data buffer to SDRAM memory. | |
416 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains | |
417 * the configuration information for SDRAM module. | |
418 * @param pAddress: Pointer to write start address | |
419 * @param pSrcBuffer: Pointer to source buffer to write | |
420 * @param BufferSize: Size of the buffer to write to memory | |
421 * @retval HAL status | |
422 */ | |
423 HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize) | |
424 { | |
425 __IO uint16_t *pSdramAddress = (uint16_t *)pAddress; | |
426 uint32_t tmp = 0; | |
427 | |
428 /* Process Locked */ | |
429 __HAL_LOCK(hsdram); | |
430 | |
431 /* Check the SDRAM controller state */ | |
432 tmp = hsdram->State; | |
433 | |
434 if(tmp == HAL_SDRAM_STATE_BUSY) | |
435 { | |
436 return HAL_BUSY; | |
437 } | |
438 else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) | |
439 { | |
440 return HAL_ERROR; | |
441 } | |
442 | |
443 /* Write data to memory */ | |
444 for(; BufferSize != 0; BufferSize--) | |
445 { | |
446 *(__IO uint16_t *)pSdramAddress = *pSrcBuffer; | |
447 pSrcBuffer++; | |
448 pSdramAddress++; | |
449 } | |
450 | |
451 /* Process Unlocked */ | |
452 __HAL_UNLOCK(hsdram); | |
453 | |
454 return HAL_OK; | |
455 } | |
456 | |
457 /** | |
458 * @brief Reads 32-bit data buffer from the SDRAM memory. | |
459 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains | |
460 * the configuration information for SDRAM module. | |
461 * @param pAddress: Pointer to read start address | |
462 * @param pDstBuffer: Pointer to destination buffer | |
463 * @param BufferSize: Size of the buffer to read from memory | |
464 * @retval HAL status | |
465 */ | |
466 HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) | |
467 { | |
468 __IO uint32_t *pSdramAddress = (uint32_t *)pAddress; | |
469 | |
470 /* Process Locked */ | |
471 __HAL_LOCK(hsdram); | |
472 | |
473 /* Check the SDRAM controller state */ | |
474 if(hsdram->State == HAL_SDRAM_STATE_BUSY) | |
475 { | |
476 return HAL_BUSY; | |
477 } | |
478 else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED) | |
479 { | |
480 return HAL_ERROR; | |
481 } | |
482 | |
483 /* Read data from source */ | |
484 for(; BufferSize != 0; BufferSize--) | |
485 { | |
486 *pDstBuffer = *(__IO uint32_t *)pSdramAddress; | |
487 pDstBuffer++; | |
488 pSdramAddress++; | |
489 } | |
490 | |
491 /* Process Unlocked */ | |
492 __HAL_UNLOCK(hsdram); | |
493 | |
494 return HAL_OK; | |
495 } | |
496 | |
497 /** | |
498 * @brief Writes 32-bit data buffer to SDRAM memory. | |
499 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains | |
500 * the configuration information for SDRAM module. | |
501 * @param pAddress: Pointer to write start address | |
502 * @param pSrcBuffer: Pointer to source buffer to write | |
503 * @param BufferSize: Size of the buffer to write to memory | |
504 * @retval HAL status | |
505 */ | |
506 HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) | |
507 { | |
508 __IO uint32_t *pSdramAddress = (uint32_t *)pAddress; | |
509 uint32_t tmp = 0; | |
510 | |
511 /* Process Locked */ | |
512 __HAL_LOCK(hsdram); | |
513 | |
514 /* Check the SDRAM controller state */ | |
515 tmp = hsdram->State; | |
516 | |
517 if(tmp == HAL_SDRAM_STATE_BUSY) | |
518 { | |
519 return HAL_BUSY; | |
520 } | |
521 else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) | |
522 { | |
523 return HAL_ERROR; | |
524 } | |
525 | |
526 /* Write data to memory */ | |
527 for(; BufferSize != 0; BufferSize--) | |
528 { | |
529 *(__IO uint32_t *)pSdramAddress = *pSrcBuffer; | |
530 pSrcBuffer++; | |
531 pSdramAddress++; | |
532 } | |
533 | |
534 /* Process Unlocked */ | |
535 __HAL_UNLOCK(hsdram); | |
536 | |
537 return HAL_OK; | |
538 } | |
539 | |
540 /** | |
541 * @brief Reads a Words data from the SDRAM memory using DMA transfer. | |
542 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains | |
543 * the configuration information for SDRAM module. | |
544 * @param pAddress: Pointer to read start address | |
545 * @param pDstBuffer: Pointer to destination buffer | |
546 * @param BufferSize: Size of the buffer to read from memory | |
547 * @retval HAL status | |
548 */ | |
549 HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) | |
550 { | |
551 uint32_t tmp = 0; | |
552 | |
553 /* Process Locked */ | |
554 __HAL_LOCK(hsdram); | |
555 | |
556 /* Check the SDRAM controller state */ | |
557 tmp = hsdram->State; | |
558 | |
559 if(tmp == HAL_SDRAM_STATE_BUSY) | |
560 { | |
561 return HAL_BUSY; | |
562 } | |
563 else if(tmp == HAL_SDRAM_STATE_PRECHARGED) | |
564 { | |
565 return HAL_ERROR; | |
566 } | |
567 | |
568 /* Configure DMA user callbacks */ | |
569 hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; | |
570 hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; | |
571 | |
572 /* Enable the DMA Stream */ | |
573 HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize); | |
574 | |
575 /* Process Unlocked */ | |
576 __HAL_UNLOCK(hsdram); | |
577 | |
578 return HAL_OK; | |
579 } | |
580 | |
581 /** | |
582 * @brief Writes a Words data buffer to SDRAM memory using DMA transfer. | |
583 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains | |
584 * the configuration information for SDRAM module. | |
585 * @param pAddress: Pointer to write start address | |
586 * @param pSrcBuffer: Pointer to source buffer to write | |
587 * @param BufferSize: Size of the buffer to write to memory | |
588 * @retval HAL status | |
589 */ | |
590 HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) | |
591 { | |
592 uint32_t tmp = 0; | |
593 | |
594 /* Process Locked */ | |
595 __HAL_LOCK(hsdram); | |
596 | |
597 /* Check the SDRAM controller state */ | |
598 tmp = hsdram->State; | |
599 | |
600 if(tmp == HAL_SDRAM_STATE_BUSY) | |
601 { | |
602 return HAL_BUSY; | |
603 } | |
604 else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) | |
605 { | |
606 return HAL_ERROR; | |
607 } | |
608 | |
609 /* Configure DMA user callbacks */ | |
610 hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; | |
611 hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; | |
612 | |
613 /* Enable the DMA Stream */ | |
614 HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize); | |
615 | |
616 /* Process Unlocked */ | |
617 __HAL_UNLOCK(hsdram); | |
618 | |
619 return HAL_OK; | |
620 } | |
621 /** | |
622 * @} | |
623 */ | |
624 | |
625 /** @defgroup SDRAM_Exported_Functions_Group3 Control functions | |
626 * @brief management functions | |
627 * | |
628 @verbatim | |
629 ============================================================================== | |
630 ##### SDRAM Control functions ##### | |
631 ============================================================================== | |
632 [..] | |
633 This subsection provides a set of functions allowing to control dynamically | |
634 the SDRAM interface. | |
635 | |
636 @endverbatim | |
637 * @{ | |
638 */ | |
639 | |
640 /** | |
641 * @brief Enables dynamically SDRAM write protection. | |
642 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains | |
643 * the configuration information for SDRAM module. | |
644 * @retval HAL status | |
645 */ | |
646 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram) | |
647 { | |
648 /* Check the SDRAM controller state */ | |
649 if(hsdram->State == HAL_SDRAM_STATE_BUSY) | |
650 { | |
651 return HAL_BUSY; | |
652 } | |
653 | |
654 /* Update the SDRAM state */ | |
655 hsdram->State = HAL_SDRAM_STATE_BUSY; | |
656 | |
657 /* Enable write protection */ | |
658 FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank); | |
659 | |
660 /* Update the SDRAM state */ | |
661 hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED; | |
662 | |
663 return HAL_OK; | |
664 } | |
665 | |
666 /** | |
667 * @brief Disables dynamically SDRAM write protection. | |
668 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains | |
669 * the configuration information for SDRAM module. | |
670 * @retval HAL status | |
671 */ | |
672 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram) | |
673 { | |
674 /* Check the SDRAM controller state */ | |
675 if(hsdram->State == HAL_SDRAM_STATE_BUSY) | |
676 { | |
677 return HAL_BUSY; | |
678 } | |
679 | |
680 /* Update the SDRAM state */ | |
681 hsdram->State = HAL_SDRAM_STATE_BUSY; | |
682 | |
683 /* Disable write protection */ | |
684 FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank); | |
685 | |
686 /* Update the SDRAM state */ | |
687 hsdram->State = HAL_SDRAM_STATE_READY; | |
688 | |
689 return HAL_OK; | |
690 } | |
691 | |
692 /** | |
693 * @brief Sends Command to the SDRAM bank. | |
694 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains | |
695 * the configuration information for SDRAM module. | |
696 * @param Command: SDRAM command structure | |
697 * @param Timeout: Timeout duration | |
698 * @retval HAL status | |
699 */ | |
700 HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) | |
701 { | |
702 /* Check the SDRAM controller state */ | |
703 if(hsdram->State == HAL_SDRAM_STATE_BUSY) | |
704 { | |
705 return HAL_BUSY; | |
706 } | |
707 | |
708 /* Update the SDRAM state */ | |
709 hsdram->State = HAL_SDRAM_STATE_BUSY; | |
710 | |
711 /* Send SDRAM command */ | |
712 FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout); | |
713 | |
714 /* Update the SDRAM controller state */ | |
715 if(Command->CommandMode == FMC_SDRAM_CMD_PALL) | |
716 { | |
717 hsdram->State = HAL_SDRAM_STATE_PRECHARGED; | |
718 } | |
719 else | |
720 { | |
721 hsdram->State = HAL_SDRAM_STATE_READY; | |
722 } | |
723 | |
724 return HAL_OK; | |
725 } | |
726 | |
727 /** | |
728 * @brief Programs the SDRAM Memory Refresh rate. | |
729 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains | |
730 * the configuration information for SDRAM module. | |
731 * @param RefreshRate: The SDRAM refresh rate value | |
732 * @retval HAL status | |
733 */ | |
734 HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate) | |
735 { | |
736 /* Check the SDRAM controller state */ | |
737 if(hsdram->State == HAL_SDRAM_STATE_BUSY) | |
738 { | |
739 return HAL_BUSY; | |
740 } | |
741 | |
742 /* Update the SDRAM state */ | |
743 hsdram->State = HAL_SDRAM_STATE_BUSY; | |
744 | |
745 /* Program the refresh rate */ | |
746 FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate); | |
747 | |
748 /* Update the SDRAM state */ | |
749 hsdram->State = HAL_SDRAM_STATE_READY; | |
750 | |
751 return HAL_OK; | |
752 } | |
753 | |
754 /** | |
755 * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands. | |
756 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains | |
757 * the configuration information for SDRAM module. | |
758 * @param AutoRefreshNumber: The SDRAM auto Refresh number | |
759 * @retval HAL status | |
760 */ | |
761 HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber) | |
762 { | |
763 /* Check the SDRAM controller state */ | |
764 if(hsdram->State == HAL_SDRAM_STATE_BUSY) | |
765 { | |
766 return HAL_BUSY; | |
767 } | |
768 | |
769 /* Update the SDRAM state */ | |
770 hsdram->State = HAL_SDRAM_STATE_BUSY; | |
771 | |
772 /* Set the Auto-Refresh number */ | |
773 FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance ,AutoRefreshNumber); | |
774 | |
775 /* Update the SDRAM state */ | |
776 hsdram->State = HAL_SDRAM_STATE_READY; | |
777 | |
778 return HAL_OK; | |
779 } | |
780 | |
781 /** | |
782 * @brief Returns the SDRAM memory current mode. | |
783 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains | |
784 * the configuration information for SDRAM module. | |
785 * @retval The SDRAM memory mode. | |
786 */ | |
787 uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram) | |
788 { | |
789 /* Return the SDRAM memory current mode */ | |
790 return(FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank)); | |
791 } | |
792 | |
793 /** | |
794 * @} | |
795 */ | |
796 | |
797 /** @defgroup SDRAM_Exported_Functions_Group4 State functions | |
798 * @brief Peripheral State functions | |
799 * | |
800 @verbatim | |
801 ============================================================================== | |
802 ##### SDRAM State functions ##### | |
803 ============================================================================== | |
804 [..] | |
805 This subsection permits to get in run-time the status of the SDRAM controller | |
806 and the data flow. | |
807 | |
808 @endverbatim | |
809 * @{ | |
810 */ | |
811 | |
812 /** | |
813 * @brief Returns the SDRAM state. | |
814 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains | |
815 * the configuration information for SDRAM module. | |
816 * @retval HAL state | |
817 */ | |
818 HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram) | |
819 { | |
820 return hsdram->State; | |
821 } | |
822 | |
823 /** | |
824 * @} | |
825 */ | |
826 | |
827 /** | |
828 * @} | |
829 */ | |
830 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ | |
831 #endif /* HAL_SDRAM_MODULE_ENABLED */ | |
832 /** | |
833 * @} | |
834 */ | |
835 | |
836 /** | |
837 * @} | |
838 */ | |
839 | |
840 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |