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1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_fmc.h
4 * @author MCD Application Team
5 * @version V1.2.0
6 * @date 26-December-2014
7 * @brief Header file of FMC HAL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F4xx_LL_FMC_H
40 #define __STM32F4xx_LL_FMC_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f4xx_hal_def.h"
48
49 /** @addtogroup STM32F4xx_HAL_Driver
50 * @{
51 */
52
53 /** @addtogroup FMC_LL
54 * @{
55 */
56 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
57 /* Private types -------------------------------------------------------------*/
58 /** @defgroup FMC_LL_Private_Types FMC Private Types
59 * @{
60 */
61
62 /**
63 * @brief FMC NORSRAM Configuration Structure definition
64 */
65 typedef struct
66 {
67 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
68 This parameter can be a value of @ref FMC_NORSRAM_Bank */
69
70 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
71 multiplexed on the data bus or not.
72 This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
73
74 uint32_t MemoryType; /*!< Specifies the type of external memory attached to
75 the corresponding memory device.
76 This parameter can be a value of @ref FMC_Memory_Type */
77
78 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
79 This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
80
81 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
82 valid only with synchronous burst Flash memories.
83 This parameter can be a value of @ref FMC_Burst_Access_Mode */
84
85 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
86 the Flash memory in burst mode.
87 This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
88
89 uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
90 memory, valid only when accessing Flash memories in burst mode.
91 This parameter can be a value of @ref FMC_Wrap_Mode */
92
93 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
94 clock cycle before the wait state or during the wait state,
95 valid only when accessing memories in burst mode.
96 This parameter can be a value of @ref FMC_Wait_Timing */
97
98 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
99 This parameter can be a value of @ref FMC_Write_Operation */
100
101 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
102 signal, valid for Flash memory access in burst mode.
103 This parameter can be a value of @ref FMC_Wait_Signal */
104
105 uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
106 This parameter can be a value of @ref FMC_Extended_Mode */
107
108 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
109 valid only with asynchronous Flash memories.
110 This parameter can be a value of @ref FMC_AsynchronousWait */
111
112 uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
113 This parameter can be a value of @ref FMC_Write_Burst */
114
115 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
116 This parameter is only enabled through the FMC_BCR1 register, and don't care
117 through FMC_BCR2..4 registers.
118 This parameter can be a value of @ref FMC_Continous_Clock */
119
120 }FMC_NORSRAM_InitTypeDef;
121
122 /**
123 * @brief FMC NORSRAM Timing parameters structure definition
124 */
125 typedef struct
126 {
127 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
128 the duration of the address setup time.
129 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
130 @note This parameter is not used with synchronous NOR Flash memories. */
131
132 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
133 the duration of the address hold time.
134 This parameter can be a value between Min_Data = 1 and Max_Data = 15.
135 @note This parameter is not used with synchronous NOR Flash memories. */
136
137 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
138 the duration of the data setup time.
139 This parameter can be a value between Min_Data = 1 and Max_Data = 255.
140 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
141 NOR Flash memories. */
142
143 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
144 the duration of the bus turnaround.
145 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
146 @note This parameter is only used for multiplexed NOR Flash memories. */
147
148 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
149 HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
150 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
151 accesses. */
152
153 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
154 to the memory before getting the first data.
155 The parameter value depends on the memory type as shown below:
156 - It must be set to 0 in case of a CRAM
157 - It is don't care in asynchronous NOR, SRAM or ROM accesses
158 - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
159 with synchronous burst mode enable */
160
161 uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
162 This parameter can be a value of @ref FMC_Access_Mode */
163 }FMC_NORSRAM_TimingTypeDef;
164
165 /**
166 * @brief FMC NAND Configuration Structure definition
167 */
168 typedef struct
169 {
170 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
171 This parameter can be a value of @ref FMC_NAND_Bank */
172
173 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
174 This parameter can be any value of @ref FMC_Wait_feature */
175
176 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
177 This parameter can be any value of @ref FMC_NAND_Data_Width */
178
179 uint32_t EccComputation; /*!< Enables or disables the ECC computation.
180 This parameter can be any value of @ref FMC_ECC */
181
182 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
183 This parameter can be any value of @ref FMC_ECC_Page_Size */
184
185 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
186 delay between CLE low and RE low.
187 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
188
189 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
190 delay between ALE low and RE low.
191 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
192 }FMC_NAND_InitTypeDef;
193
194 /**
195 * @brief FMC NAND/PCCARD Timing parameters structure definition
196 */
197 typedef struct
198 {
199 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
200 the command assertion for NAND-Flash read or write access
201 to common/Attribute or I/O memory space (depending on
202 the memory space timing to be configured).
203 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
204
205 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
206 command for NAND-Flash read or write access to
207 common/Attribute or I/O memory space (depending on the
208 memory space timing to be configured).
209 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
210
211 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
212 (and data for write access) after the command de-assertion
213 for NAND-Flash read or write access to common/Attribute
214 or I/O memory space (depending on the memory space timing
215 to be configured).
216 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
217
218 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
219 data bus is kept in HiZ after the start of a NAND-Flash
220 write access to common/Attribute or I/O memory space (depending
221 on the memory space timing to be configured).
222 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
223 }FMC_NAND_PCC_TimingTypeDef;
224
225 /**
226 * @brief FMC NAND Configuration Structure definition
227 */
228 typedef struct
229 {
230 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
231 This parameter can be any value of @ref FMC_Wait_feature */
232
233 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
234 delay between CLE low and RE low.
235 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
236
237 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
238 delay between ALE low and RE low.
239 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
240 }FMC_PCCARD_InitTypeDef;
241
242 /**
243 * @brief FMC SDRAM Configuration Structure definition
244 */
245 typedef struct
246 {
247 uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
248 This parameter can be a value of @ref FMC_SDRAM_Bank */
249
250 uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
251 This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
252
253 uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
254 This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
255
256 uint32_t MemoryDataWidth; /*!< Defines the memory device width.
257 This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
258
259 uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
260 This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
261
262 uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
263 This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
264
265 uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
266 This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
267
268 uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
269 to disable the clock before changing frequency.
270 This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
271
272 uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
273 commands during the CAS latency and stores data in the Read FIFO.
274 This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
275
276 uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
277 This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
278 }FMC_SDRAM_InitTypeDef;
279
280 /**
281 * @brief FMC SDRAM Timing parameters structure definition
282 */
283 typedef struct
284 {
285 uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
286 an active or Refresh command in number of memory clock cycles.
287 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
288
289 uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
290 issuing the Activate command in number of memory clock cycles.
291 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
292
293 uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
294 cycles.
295 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
296
297 uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
298 and the delay between two consecutive Refresh commands in number of
299 memory clock cycles.
300 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
301
302 uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
303 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
304
305 uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
306 in number of memory clock cycles.
307 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
308
309 uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
310 command in number of memory clock cycles.
311 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
312 }FMC_SDRAM_TimingTypeDef;
313
314 /**
315 * @brief SDRAM command parameters structure definition
316 */
317 typedef struct
318 {
319 uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
320 This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
321
322 uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
323 This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
324
325 uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
326 in auto refresh mode.
327 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
328 uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */
329 }FMC_SDRAM_CommandTypeDef;
330 /**
331 * @}
332 */
333
334 /* Private constants ---------------------------------------------------------*/
335 /** @defgroup FMC_LL_Private_Constants FMC Private Constants
336 * @{
337 */
338
339 /** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
340 * @{
341 */
342 /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
343 * @{
344 */
345 #define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
346 #define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
347 #define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
348 #define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
349 /**
350 * @}
351 */
352
353 /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
354 * @{
355 */
356 #define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
357 #define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
358 /**
359 * @}
360 */
361
362 /** @defgroup FMC_Memory_Type FMC Memory Type
363 * @{
364 */
365 #define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
366 #define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
367 #define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
368 /**
369 * @}
370 */
371
372 /** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
373 * @{
374 */
375 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
376 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
377 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
378 /**
379 * @}
380 */
381
382 /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
383 * @{
384 */
385 #define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
386 #define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
387 /**
388 * @}
389 */
390
391 /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
392 * @{
393 */
394 #define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
395 #define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
396 /**
397 * @}
398 */
399
400 /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
401 * @{
402 */
403 #define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
404 #define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
405 /**
406 * @}
407 */
408
409 /** @defgroup FMC_Wrap_Mode FMC Wrap Mode
410 * @{
411 */
412 #define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
413 #define FMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
414 /**
415 * @}
416 */
417
418 /** @defgroup FMC_Wait_Timing FMC Wait Timing
419 * @{
420 */
421 #define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
422 #define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
423 /**
424 * @}
425 */
426
427 /** @defgroup FMC_Write_Operation FMC Write Operation
428 * @{
429 */
430 #define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
431 #define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
432 /**
433 * @}
434 */
435
436 /** @defgroup FMC_Wait_Signal FMC Wait Signal
437 * @{
438 */
439 #define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
440 #define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
441 /**
442 * @}
443 */
444
445 /** @defgroup FMC_Extended_Mode FMC Extended Mode
446 * @{
447 */
448 #define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
449 #define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
450 /**
451 * @}
452 */
453
454 /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
455 * @{
456 */
457 #define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
458 #define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
459 /**
460 * @}
461 */
462
463 /** @defgroup FMC_Write_Burst FMC Write Burst
464 * @{
465 */
466 #define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
467 #define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
468 /**
469 * @}
470 */
471
472 /** @defgroup FMC_Continous_Clock FMC Continous Clock
473 * @{
474 */
475 #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
476 #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
477 /**
478 * @}
479 */
480
481 /** @defgroup FMC_Access_Mode FMC Access Mode
482 * @{
483 */
484 #define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
485 #define FMC_ACCESS_MODE_B ((uint32_t)0x10000000)
486 #define FMC_ACCESS_MODE_C ((uint32_t)0x20000000)
487 #define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)
488 /**
489 * @}
490 */
491
492 /**
493 * @}
494 */
495
496 /** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
497 * @{
498 */
499 /** @defgroup FMC_NAND_Bank FMC NAND Bank
500 * @{
501 */
502 #define FMC_NAND_BANK2 ((uint32_t)0x00000010)
503 #define FMC_NAND_BANK3 ((uint32_t)0x00000100)
504 /**
505 * @}
506 */
507
508 /** @defgroup FMC_Wait_feature FMC Wait feature
509 * @{
510 */
511 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
512 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
513 /**
514 * @}
515 */
516
517 /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
518 * @{
519 */
520 #define FMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
521 #define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
522 /**
523 * @}
524 */
525
526 /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
527 * @{
528 */
529 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
530 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
531 /**
532 * @}
533 */
534
535 /** @defgroup FMC_ECC FMC ECC
536 * @{
537 */
538 #define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
539 #define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
540 /**
541 * @}
542 */
543
544 /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
545 * @{
546 */
547 #define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
548 #define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
549 #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
550 #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
551 #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
552 #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
553 /**
554 * @}
555 */
556
557 /**
558 * @}
559 */
560
561 /** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller
562 * @{
563 */
564 /** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank
565 * @{
566 */
567 #define FMC_SDRAM_BANK1 ((uint32_t)0x00000000)
568 #define FMC_SDRAM_BANK2 ((uint32_t)0x00000001)
569 /**
570 * @}
571 */
572
573 /** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number
574 * @{
575 */
576 #define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000)
577 #define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001)
578 #define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002)
579 #define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003)
580 /**
581 * @}
582 */
583
584 /** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number
585 * @{
586 */
587 #define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000)
588 #define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004)
589 #define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008)
590 /**
591 * @}
592 */
593
594 /** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width
595 * @{
596 */
597 #define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
598 #define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
599 #define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
600 /**
601 * @}
602 */
603
604 /** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number
605 * @{
606 */
607 #define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000)
608 #define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040)
609 /**
610 * @}
611 */
612
613 /** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency
614 * @{
615 */
616 #define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080)
617 #define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100)
618 #define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180)
619 /**
620 * @}
621 */
622
623 /** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection
624 * @{
625 */
626 #define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000)
627 #define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200)
628
629 /**
630 * @}
631 */
632
633 /** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period
634 * @{
635 */
636 #define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000)
637 #define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800)
638 #define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00)
639 /**
640 * @}
641 */
642
643 /** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst
644 * @{
645 */
646 #define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000)
647 #define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000)
648 /**
649 * @}
650 */
651
652 /** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay
653 * @{
654 */
655 #define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000)
656 #define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000)
657 #define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000)
658 /**
659 * @}
660 */
661
662 /** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode
663 * @{
664 */
665 #define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000)
666 #define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001)
667 #define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002)
668 #define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003)
669 #define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004)
670 #define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005)
671 #define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006)
672 /**
673 * @}
674 */
675
676 /** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target
677 * @{
678 */
679 #define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
680 #define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
681 #define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018)
682 /**
683 * @}
684 */
685
686 /** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status
687 * @{
688 */
689 #define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000)
690 #define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
691 #define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
692 /**
693 * @}
694 */
695
696 /**
697 * @}
698 */
699
700 /** @defgroup FMC_LL_Interrupt_definition FMC Interrupt definition
701 * @{
702 */
703 #define FMC_IT_RISING_EDGE ((uint32_t)0x00000008)
704 #define FMC_IT_LEVEL ((uint32_t)0x00000010)
705 #define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
706 #define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
707 /**
708 * @}
709 */
710
711 /** @defgroup FMC_LL_Flag_definition FMC Flag definition
712 * @{
713 */
714 #define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
715 #define FMC_FLAG_LEVEL ((uint32_t)0x00000002)
716 #define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
717 #define FMC_FLAG_FEMPT ((uint32_t)0x00000040)
718 #define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
719 #define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
720 #define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
721 /**
722 * @}
723 */
724
725 /** @defgroup FMC_LL_Alias_definition FMC Alias definition
726 * @{
727 */
728 #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
729 #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
730 #define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
731 #define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
732 #define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
733
734 #define FMC_NORSRAM_DEVICE FMC_Bank1
735 #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
736 #define FMC_NAND_DEVICE FMC_Bank2_3
737 #define FMC_PCCARD_DEVICE FMC_Bank4
738 #define FMC_SDRAM_DEVICE FMC_Bank5_6
739 /**
740 * @}
741 */
742
743 /**
744 * @}
745 */
746
747 /* Private macro -------------------------------------------------------------*/
748 /** @defgroup FMC_LL_Private_Macros FMC Private Macros
749 * @{
750 */
751
752 /** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
753 * @brief macros to handle NOR device enable/disable and read/write operations
754 * @{
755 */
756 /**
757 * @brief Enable the NORSRAM device access.
758 * @param __INSTANCE__: FMC_NORSRAM Instance
759 * @param __BANK__: FMC_NORSRAM Bank
760 * @retval None
761 */
762 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1_MBKEN)
763
764 /**
765 * @brief Disable the NORSRAM device access.
766 * @param __INSTANCE__: FMC_NORSRAM Instance
767 * @param __BANK__: FMC_NORSRAM Bank
768 * @retval None
769 */
770 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
771 /**
772 * @}
773 */
774
775 /** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
776 * @brief macros to handle NAND device enable/disable
777 * @{
778 */
779 /**
780 * @brief Enable the NAND device access.
781 * @param __INSTANCE__: FMC_NAND Instance
782 * @param __BANK__: FMC_NAND Bank
783 * @retval None
784 */
785 #define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FMC_PCR2_PBKEN): \
786 ((__INSTANCE__)->PCR3 |= FMC_PCR3_PBKEN))
787
788 /**
789 * @brief Disable the NAND device access.
790 * @param __INSTANCE__: FMC_NAND Instance
791 * @param __BANK__: FMC_NAND Bank
792 * @retval None
793 */
794 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
795 ((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
796 /**
797 * @}
798 */
799
800 /** @defgroup FMC_LL_PCCARD_Macros FMC PCCARD Macros
801 * @brief macros to handle SRAM read/write operations
802 * @{
803 */
804 /**
805 * @brief Enable the PCCARD device access.
806 * @param __INSTANCE__: FMC_PCCARD Instance
807 * @retval None
808 */
809 #define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FMC_PCR4_PBKEN)
810
811 /**
812 * @brief Disable the PCCARD device access.
813 * @param __INSTANCE__: FMC_PCCARD Instance
814 * @retval None
815 */
816 #define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
817 /**
818 * @}
819 */
820
821 /** @defgroup FMC_LL_Flag_Interrupt_Macros FMC Flag&Interrupt Macros
822 * @brief macros to handle FMC flags and interrupts
823 * @{
824 */
825 /**
826 * @brief Enable the NAND device interrupt.
827 * @param __INSTANCE__: FMC_NAND instance
828 * @param __BANK__: FMC_NAND Bank
829 * @param __INTERRUPT__: FMC_NAND interrupt
830 * This parameter can be any combination of the following values:
831 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
832 * @arg FMC_IT_LEVEL: Interrupt level.
833 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
834 * @retval None
835 */
836 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
837 ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
838
839 /**
840 * @brief Disable the NAND device interrupt.
841 * @param __INSTANCE__: FMC_NAND Instance
842 * @param __BANK__: FMC_NAND Bank
843 * @param __INTERRUPT__: FMC_NAND interrupt
844 * This parameter can be any combination of the following values:
845 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
846 * @arg FMC_IT_LEVEL: Interrupt level.
847 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
848 * @retval None
849 */
850 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
851 ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
852
853 /**
854 * @brief Get flag status of the NAND device.
855 * @param __INSTANCE__: FMC_NAND Instance
856 * @param __BANK__: FMC_NAND Bank
857 * @param __FLAG__: FMC_NAND flag
858 * This parameter can be any combination of the following values:
859 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
860 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
861 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
862 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
863 * @retval The state of FLAG (SET or RESET).
864 */
865 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
866 (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
867 /**
868 * @brief Clear flag status of the NAND device.
869 * @param __INSTANCE__: FMC_NAND Instance
870 * @param __BANK__: FMC_NAND Bank
871 * @param __FLAG__: FMC_NAND flag
872 * This parameter can be any combination of the following values:
873 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
874 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
875 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
876 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
877 * @retval None
878 */
879 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
880 ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
881 /**
882 * @brief Enable the PCCARD device interrupt.
883 * @param __INSTANCE__: FMC_PCCARD instance
884 * @param __INTERRUPT__: FMC_PCCARD interrupt
885 * This parameter can be any combination of the following values:
886 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
887 * @arg FMC_IT_LEVEL: Interrupt level.
888 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
889 * @retval None
890 */
891 #define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
892
893 /**
894 * @brief Disable the PCCARD device interrupt.
895 * @param __INSTANCE__: FMC_PCCARD instance
896 * @param __INTERRUPT__: FMC_PCCARD interrupt
897 * This parameter can be any combination of the following values:
898 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
899 * @arg FMC_IT_LEVEL: Interrupt level.
900 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
901 * @retval None
902 */
903 #define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
904
905 /**
906 * @brief Get flag status of the PCCARD device.
907 * @param __INSTANCE__: FMC_PCCARD instance
908 * @param __FLAG__: FMC_PCCARD flag
909 * This parameter can be any combination of the following values:
910 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
911 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
912 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
913 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
914 * @retval The state of FLAG (SET or RESET).
915 */
916 #define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
917
918 /**
919 * @brief Clear flag status of the PCCARD device.
920 * @param __INSTANCE__: FMC_PCCARD instance
921 * @param __FLAG__: FMC_PCCARD flag
922 * This parameter can be any combination of the following values:
923 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
924 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
925 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
926 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
927 * @retval None
928 */
929 #define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
930
931 /**
932 * @brief Enable the SDRAM device interrupt.
933 * @param __INSTANCE__: FMC_SDRAM instance
934 * @param __INTERRUPT__: FMC_SDRAM interrupt
935 * This parameter can be any combination of the following values:
936 * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
937 * @retval None
938 */
939 #define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR |= (__INTERRUPT__))
940
941 /**
942 * @brief Disable the SDRAM device interrupt.
943 * @param __INSTANCE__: FMC_SDRAM instance
944 * @param __INTERRUPT__: FMC_SDRAM interrupt
945 * This parameter can be any combination of the following values:
946 * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
947 * @retval None
948 */
949 #define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
950
951 /**
952 * @brief Get flag status of the SDRAM device.
953 * @param __INSTANCE__: FMC_SDRAM instance
954 * @param __FLAG__: FMC_SDRAM flag
955 * This parameter can be any combination of the following values:
956 * @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
957 * @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
958 * @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
959 * @retval The state of FLAG (SET or RESET).
960 */
961 #define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
962
963 /**
964 * @brief Clear flag status of the SDRAM device.
965 * @param __INSTANCE__: FMC_SDRAM instance
966 * @param __FLAG__: FMC_SDRAM flag
967 * This parameter can be any combination of the following values:
968 * @arg FMC_SDRAM_FLAG_REFRESH_ERROR
969 * @retval None
970 */
971 #define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR |= (__FLAG__))
972 /**
973 * @}
974 */
975
976 /** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
977 * @{
978 */
979 #define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) || \
980 ((BANK) == FMC_NORSRAM_BANK2) || \
981 ((BANK) == FMC_NORSRAM_BANK3) || \
982 ((BANK) == FMC_NORSRAM_BANK4))
983
984 #define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
985 ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
986
987 #define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \
988 ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \
989 ((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
990
991 #define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
992 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
993 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
994
995 #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \
996 ((__MODE__) == FMC_ACCESS_MODE_B) || \
997 ((__MODE__) == FMC_ACCESS_MODE_C) || \
998 ((__MODE__) == FMC_ACCESS_MODE_D))
999
1000 #define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) || \
1001 ((BANK) == FMC_NAND_BANK3))
1002
1003 #define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
1004 ((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
1005
1006 #define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
1007 ((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
1008
1009 #define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) || \
1010 ((STATE) == FMC_NAND_ECC_ENABLE))
1011
1012 #define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
1013 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
1014 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
1015 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
1016 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
1017 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
1018
1019 #define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255)
1020
1021 #define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
1022
1023 #define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255)
1024
1025 #define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255)
1026
1027 #define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255)
1028
1029 #define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255)
1030
1031 #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
1032
1033 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
1034
1035 #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
1036
1037 #define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE)
1038
1039 #define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
1040 ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
1041
1042 #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
1043 ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
1044
1045 #define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) || \
1046 ((__MODE__) == FMC_WRAP_MODE_ENABLE))
1047
1048 #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
1049 ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
1050
1051 #define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
1052 ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
1053
1054 #define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
1055 ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
1056
1057 #define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
1058 ((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
1059
1060 #define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
1061 ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
1062
1063 #define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
1064
1065 #define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
1066 ((__BURST__) == FMC_WRITE_BURST_ENABLE))
1067
1068 #define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
1069 ((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
1070
1071 #define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
1072
1073 #define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
1074
1075 #define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
1076
1077 #define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
1078
1079 #define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
1080
1081 #define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) || \
1082 ((BANK) == FMC_SDRAM_BANK2))
1083
1084 #define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \
1085 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \
1086 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \
1087 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
1088
1089 #define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) || \
1090 ((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) || \
1091 ((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
1092
1093 #define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \
1094 ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \
1095 ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
1096
1097 #define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \
1098 ((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
1099
1100
1101 #define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) || \
1102 ((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) || \
1103 ((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
1104
1105 #define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDRAM_CLOCK_DISABLE) || \
1106 ((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_2) || \
1107 ((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_3))
1108
1109 #define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_SDRAM_RBURST_DISABLE) || \
1110 ((RBURST) == FMC_SDRAM_RBURST_ENABLE))
1111
1112
1113 #define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_SDRAM_RPIPE_DELAY_0) || \
1114 ((DELAY) == FMC_SDRAM_RPIPE_DELAY_1) || \
1115 ((DELAY) == FMC_SDRAM_RPIPE_DELAY_2))
1116
1117 #define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
1118
1119 #define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
1120
1121 #define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
1122
1123 #define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
1124
1125 #define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
1126
1127 #define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
1128
1129 #define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
1130
1131 #define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_SDRAM_CMD_NORMAL_MODE) || \
1132 ((COMMAND) == FMC_SDRAM_CMD_CLK_ENABLE) || \
1133 ((COMMAND) == FMC_SDRAM_CMD_PALL) || \
1134 ((COMMAND) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \
1135 ((COMMAND) == FMC_SDRAM_CMD_LOAD_MODE) || \
1136 ((COMMAND) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \
1137 ((COMMAND) == FMC_SDRAM_CMD_POWERDOWN_MODE))
1138
1139 #define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1) || \
1140 ((TARGET) == FMC_SDRAM_CMD_TARGET_BANK2) || \
1141 ((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1_2))
1142
1143 #define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0) && ((NUMBER) <= 16))
1144
1145 #define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191)
1146
1147 #define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191)
1148
1149 #define IS_FMC_SDRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_SDRAM_DEVICE)
1150
1151 #define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \
1152 ((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
1153
1154 /**
1155 * @}
1156 */
1157
1158 /**
1159 * @}
1160 */
1161
1162 /* Private functions ---------------------------------------------------------*/
1163 /** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
1164 * @{
1165 */
1166
1167 /** @defgroup FMC_LL_NORSRAM NOR SRAM
1168 * @{
1169 */
1170 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
1171 * @{
1172 */
1173 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);
1174 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
1175 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
1176 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
1177 /**
1178 * @}
1179 */
1180
1181 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
1182 * @{
1183 */
1184 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1185 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1186 /**
1187 * @}
1188 */
1189 /**
1190 * @}
1191 */
1192
1193 /** @defgroup FMC_LL_NAND NAND
1194 * @{
1195 */
1196 /** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
1197 * @{
1198 */
1199 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
1200 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1201 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1202 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
1203 /**
1204 * @}
1205 */
1206
1207 /** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
1208 * @{
1209 */
1210 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
1211 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
1212 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
1213
1214 /**
1215 * @}
1216 */
1217 /**
1218 * @}
1219 */
1220
1221 /** @defgroup FMC_LL_PCCARD PCCARD
1222 * @{
1223 */
1224 /** @defgroup FMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
1225 * @{
1226 */
1227 HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init);
1228 HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
1229 HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
1230 HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
1231 HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
1232 /**
1233 * @}
1234 */
1235 /**
1236 * @}
1237 */
1238
1239 /** @defgroup FMC_LL_SDRAM SDRAM
1240 * @{
1241 */
1242 /** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions
1243 * @{
1244 */
1245 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init);
1246 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank);
1247 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1248 /**
1249 * @}
1250 */
1251
1252 /** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions
1253 * @{
1254 */
1255 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1256 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1257 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
1258 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
1259 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
1260 uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1261 /**
1262 * @}
1263 */
1264 /**
1265 * @}
1266 */
1267
1268 /**
1269 * @}
1270 */
1271
1272 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
1273 /**
1274 * @}
1275 */
1276
1277 /**
1278 * @}
1279 */
1280 #ifdef __cplusplus
1281 }
1282 #endif
1283
1284 #endif /* __STM32F4xx_LL_FMC_H */
1285
1286 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/