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comparison Common/Drivers/STM32F4xx_HAL_DRIVER_v120/Inc/stm32f4xx_hal_rcc_ex.h @ 38:5f11787b4f42

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author heinrichsweikamp
date Sat, 28 Apr 2018 11:52:34 +0200
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1 /**
2 ******************************************************************************
3 * @file stm32f4xx_hal_rcc_ex.h
4 * @author MCD Application Team
5 * @version V1.2.0
6 * @date 26-December-2014
7 * @brief Header file of RCC HAL Extension module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F4xx_HAL_RCC_EX_H
40 #define __STM32F4xx_HAL_RCC_EX_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f4xx_hal_def.h"
48
49 /** @addtogroup STM32F4xx_HAL_Driver
50 * @{
51 */
52
53 /** @addtogroup RCCEx
54 * @{
55 */
56
57 /* Exported types ------------------------------------------------------------*/
58 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
59 * @{
60 */
61
62 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
63 /**
64 * @brief PLLI2S Clock structure definition
65 */
66 typedef struct
67 {
68 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
69 This parameter must be a number between Min_Data = 192 and Max_Data = 432.
70 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
71
72 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
73 This parameter must be a number between Min_Data = 2 and Max_Data = 7.
74 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
75
76 uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
77 This parameter must be a number between Min_Data = 2 and Max_Data = 15.
78 This parameter will be used only when PLLI2S is selected as Clock Source SAI */
79 }RCC_PLLI2SInitTypeDef;
80
81 /**
82 * @brief PLLSAI Clock structure definition
83 */
84 typedef struct
85 {
86 uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
87 This parameter must be a number between Min_Data = 192 and Max_Data = 432.
88 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
89
90 uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
91 This parameter must be a number between Min_Data = 2 and Max_Data = 15.
92 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
93
94 uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
95 This parameter must be a number between Min_Data = 2 and Max_Data = 7.
96 This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
97
98 }RCC_PLLSAIInitTypeDef;
99 /**
100 * @brief RCC extended clocks structure definition
101 */
102 typedef struct
103 {
104 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
105 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
106
107 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
108 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
109
110 RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
111 This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
112
113 uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
114 This parameter must be a number between Min_Data = 1 and Max_Data = 32
115 This parameter will be used only when PLLI2S is selected as Clock Source SAI */
116
117 uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
118 This parameter must be a number between Min_Data = 1 and Max_Data = 32
119 This parameter will be used only when PLLSAI is selected as Clock Source SAI */
120
121 uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
122 This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
123
124 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
125 This parameter can be a value of @ref RCC_RTC_Clock_Source */
126
127 uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
128 This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
129
130 }RCC_PeriphCLKInitTypeDef;
131 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
132
133 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
134 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
135 /**
136 * @brief PLLI2S Clock structure definition
137 */
138 typedef struct
139 {
140 #if defined(STM32F411xE)
141 uint32_t PLLI2SM; /*!< PLLM: Division factor for PLLI2S VCO input clock.
142 This parameter must be a number between Min_Data = 2 and Max_Data = 62 */
143 #endif /* STM32F411xE */
144
145 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
146 This parameter must be a number between Min_Data = 192 and Max_Data = 432
147 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
148
149 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
150 This parameter must be a number between Min_Data = 2 and Max_Data = 7.
151 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
152
153 }RCC_PLLI2SInitTypeDef;
154
155
156 /**
157 * @brief RCC extended clocks structure definition
158 */
159 typedef struct
160 {
161 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
162 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
163
164 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
165 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
166
167 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
168 This parameter can be a value of @ref RCC_RTC_Clock_Source */
169
170 }RCC_PeriphCLKInitTypeDef;
171 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
172 /**
173 * @}
174 */
175
176 /* Exported constants --------------------------------------------------------*/
177 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
178 * @{
179 */
180
181 /** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
182 * @{
183 */
184 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
185 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
186 #define RCC_PERIPHCLK_SAI_PLLI2S ((uint32_t)0x00000002)
187 #define RCC_PERIPHCLK_SAI_PLLSAI ((uint32_t)0x00000004)
188 #define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008)
189 #define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)
190 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
191 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
192
193 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
194 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
195 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
196 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000002)
197 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
198 /**
199 * @}
200 */
201
202 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
203 /** @defgroup RCCEx_PLLSAI_DIVR RCC PLLSAI DIVR
204 * @{
205 */
206 #define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000)
207 #define RCC_PLLSAIDIVR_4 ((uint32_t)0x00010000)
208 #define RCC_PLLSAIDIVR_8 ((uint32_t)0x00020000)
209 #define RCC_PLLSAIDIVR_16 ((uint32_t)0x00030000)
210 /**
211 * @}
212 */
213
214 /** @defgroup RCCEx_SAI_BlockA_Clock_Source RCC SAI BlockA Clock Source
215 * @{
216 */
217 #define RCC_SAIACLKSOURCE_PLLSAI ((uint32_t)0x00000000)
218 #define RCC_SAIACLKSOURCE_PLLI2S ((uint32_t)0x00100000)
219 #define RCC_SAIACLKSOURCE_EXT ((uint32_t)0x00200000)
220 /**
221 * @}
222 */
223
224 /** @defgroup RCCEx_SAI_BlockB_Clock_Source RCC SAI BlockB Clock Source
225 * @{
226 */
227 #define RCC_SAIBCLKSOURCE_PLLSAI ((uint32_t)0x00000000)
228 #define RCC_SAIBCLKSOURCE_PLLI2S ((uint32_t)0x00400000)
229 #define RCC_SAIBCLKSOURCE_EXT ((uint32_t)0x00800000)
230 /**
231 * @}
232 */
233
234 /** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection
235 * @{
236 */
237 #define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
238 #define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
239 /**
240 * @}
241 */
242 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
243
244 #if defined(STM32F411xE)
245 /** @defgroup RCCEx_LSE_Dual_Mode_Selection RCC LSE Dual Mode Selection
246 * @{
247 */
248 #define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00)
249 #define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01)
250 /**
251 * @}
252 */
253 #endif /* STM32F411xE */
254
255 /**
256 * @}
257 */
258
259 /* Exported macro ------------------------------------------------------------*/
260 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
261 * @{
262 */
263 /*----------------------------------- STM32F42xxx/STM32F43xxx----------------------------------*/
264 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
265 /** @brief Enables or disables the AHB1 peripheral clock.
266 * @note After reset, the peripheral clock (used for registers read/write access)
267 * is disabled and the application software has to enable this clock before
268 * using it.
269 */
270 #define __HAL_RCC_GPIOI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOIEN))
271 #define __HAL_RCC_GPIOF_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOFEN))
272 #define __HAL_RCC_GPIOG_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOGEN))
273 #define __HAL_RCC_GPIOJ_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOJEN))
274 #define __HAL_RCC_GPIOK_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOKEN))
275 #define __HAL_RCC_DMA2D_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_DMA2DEN))
276 #define __HAL_RCC_ETHMAC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACEN))
277 #define __HAL_RCC_ETHMACTX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACTXEN))
278 #define __HAL_RCC_ETHMACRX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACRXEN))
279 #define __HAL_RCC_ETHMACPTP_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACPTPEN))
280 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSEN))
281 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSULPIEN))
282
283 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
284 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
285 #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
286 #define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
287 #define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
288 #define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
289 #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
290 #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
291 #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
292 #define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
293 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
294 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
295
296 /**
297 * @brief Enable ETHERNET clock.
298 */
299 #define __HAL_RCC_ETH_CLK_ENABLE() do { \
300 __HAL_RCC_ETHMAC_CLK_ENABLE(); \
301 __HAL_RCC_ETHMACTX_CLK_ENABLE(); \
302 __HAL_RCC_ETHMACRX_CLK_ENABLE(); \
303 } while(0)
304 /**
305 * @brief Disable ETHERNET clock.
306 */
307 #define __HAL_RCC_ETH_CLK_DISABLE() do { \
308 __HAL_RCC_ETHMACTX_CLK_DISABLE(); \
309 __HAL_RCC_ETHMACRX_CLK_DISABLE(); \
310 __HAL_RCC_ETHMAC_CLK_DISABLE(); \
311 } while(0)
312
313 /** @brief Enable or disable the AHB2 peripheral clock.
314 * @note After reset, the peripheral clock (used for registers read/write access)
315 * is disabled and the application software has to enable this clock before
316 * using it.
317 */
318
319 #define __HAL_RCC_DCMI_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_DCMIEN))
320 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
321
322 #if defined(STM32F437xx)|| defined(STM32F439xx)
323 #define __HAL_RCC_CRYP_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_CRYPEN))
324 #define __HAL_RCC_HASH_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_HASHEN))
325
326 #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
327 #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
328 #endif /* STM32F437xx || STM32F439xx */
329
330 /** @brief Enables or disables the AHB3 peripheral clock.
331 * @note After reset, the peripheral clock (used for registers read/write access)
332 * is disabled and the application software has to enable this clock before
333 * using it.
334 */
335 #define __HAL_RCC_FMC_CLK_ENABLE() (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN))
336 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
337
338 /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
339 * @note After reset, the peripheral clock (used for registers read/write access)
340 * is disabled and the application software has to enable this clock before
341 * using it.
342 */
343 #define __HAL_RCC_TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
344 #define __HAL_RCC_TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
345 #define __HAL_RCC_TIM12_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM12EN))
346 #define __HAL_RCC_TIM13_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM13EN))
347 #define __HAL_RCC_TIM14_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM14EN))
348 #define __HAL_RCC_WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
349 #define __HAL_RCC_USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN))
350 #define __HAL_RCC_UART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART4EN))
351 #define __HAL_RCC_UART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART5EN))
352 #define __HAL_RCC_CAN1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN1EN))
353 #define __HAL_RCC_CAN2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN2EN))
354 #define __HAL_RCC_DAC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
355 #define __HAL_RCC_UART7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART7EN))
356 #define __HAL_RCC_UART8_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART8EN))
357
358 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
359 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
360 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
361 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
362 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
363 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
364 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
365 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
366 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
367 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
368 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
369 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
370 #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
371 #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
372
373 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
374 * @note After reset, the peripheral clock (used for registers read/write access)
375 * is disabled and the application software has to enable this clock before
376 * using it.
377 */
378 #define __HAL_RCC_TIM8_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM8EN))
379 #define __HAL_RCC_ADC2_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC2EN))
380 #define __HAL_RCC_ADC3_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC3EN))
381 #define __HAL_RCC_SPI5_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI5EN))
382 #define __HAL_RCC_SPI6_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI6EN))
383 #define __HAL_RCC_SAI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SAI1EN))
384
385 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
386 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
387 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
388 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
389 #define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
390 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
391
392 #if defined(STM32F429xx)|| defined(STM32F439xx)
393 #define __HAL_RCC_LTDC_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_LTDCEN))
394
395 #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
396 #endif /* STM32F429xx || STM32F439xx */
397
398 /** @brief Force or release AHB1 peripheral reset.
399 */
400 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
401 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
402 #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
403 #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
404 #define __HAL_RCC_OTGHS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
405 #define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))
406 #define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))
407 #define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))
408
409 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
410 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
411 #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
412 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
413 #define __HAL_RCC_OTGHS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
414 #define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
415 #define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
416 #define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
417
418 /** @brief Force or release AHB2 peripheral reset.
419 */
420 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
421 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
422
423 #if defined(STM32F437xx)|| defined(STM32F439xx)
424 #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
425 #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
426
427 #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
428 #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
429 #endif /* STM32F437xx || STM32F439xx */
430
431 /** @brief Force or release AHB3 peripheral reset
432 */
433 #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
434 #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
435
436 /** @brief Force or release APB1 peripheral reset.
437 */
438 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
439 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
440 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
441 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
442 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
443 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
444 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
445 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
446 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
447 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
448 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
449 #define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
450 #define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
451
452 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
453 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
454 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
455 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
456 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
457 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
458 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
459 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
460 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
461 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
462 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
463 #define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
464 #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
465
466 /** @brief Force or release APB2 peripheral reset.
467 */
468 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
469 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
470 #define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
471 #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
472
473 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
474 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
475 #define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
476 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
477
478 #if defined(STM32F429xx)|| defined(STM32F439xx)
479 #define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))
480 #define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
481 #endif /* STM32F429xx|| STM32F439xx */
482
483 /** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
484 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
485 * power consumption.
486 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
487 * @note By default, all peripheral clocks are enabled during SLEEP mode.
488 */
489 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
490 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
491 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
492 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
493 #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
494 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
495 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
496 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
497 #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
498 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
499 #define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))
500 #define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))
501 #define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM3LPEN))
502 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))
503
504 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
505 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
506 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
507 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
508 #define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
509 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
510 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
511 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
512 #define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
513 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
514 #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
515 #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
516 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
517
518 /** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
519 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
520 * power consumption.
521 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
522 * @note By default, all peripheral clocks are enabled during SLEEP mode.
523 */
524 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
525 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
526
527 #if defined(STM32F437xx)|| defined(STM32F439xx)
528 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
529 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
530
531 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
532 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
533 #endif /* STM32F437xx || STM32F439xx */
534
535 /** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
536 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
537 * power consumption.
538 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
539 * @note By default, all peripheral clocks are enabled during SLEEP mode.
540 */
541 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
542 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
543
544 /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
545 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
546 * power consumption.
547 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
548 * @note By default, all peripheral clocks are enabled during SLEEP mode.
549 */
550 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
551 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
552 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
553 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
554 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
555 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
556 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
557 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
558 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
559 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
560 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
561 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
562 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))
563
564 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
565 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
566 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
567 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
568 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
569 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
570 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
571 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
572 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
573 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
574 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
575 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
576 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
577
578 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
579 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
580 * power consumption.
581 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
582 * @note By default, all peripheral clocks are enabled during SLEEP mode.
583 */
584 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
585 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
586 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
587 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
588 #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))
589 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
590
591 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
592 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
593 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
594 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
595 #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
596 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
597
598 #if defined(STM32F429xx)|| defined(STM32F439xx)
599 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))
600
601 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
602 #endif /* STM32F429xx || STM32F439xx */
603 #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
604 /*---------------------------------------------------------------------------------------------*/
605
606 /*----------------------------------- STM32F40xxx/STM32F41xxx----------------------------------*/
607 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
608 /** @brief Enables or disables the AHB1 peripheral clock.
609 * @note After reset, the peripheral clock (used for registers read/write access)
610 * is disabled and the application software has to enable this clock before
611 * using it.
612 */
613 #define __HAL_RCC_GPIOI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOIEN))
614 #define __HAL_RCC_GPIOF_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOFEN))
615 #define __HAL_RCC_GPIOG_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOGEN))
616 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSEN))
617 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSULPIEN))
618
619 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
620 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
621 #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
622 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
623 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
624
625 #if defined(STM32F407xx)|| defined(STM32F417xx)
626 /**
627 * @brief Enable ETHERNET clock.
628 */
629 #define __HAL_RCC_ETHMAC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACEN))
630 #define __HAL_RCC_ETHMACTX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACTXEN))
631 #define __HAL_RCC_ETHMACRX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACRXEN))
632 #define __HAL_RCC_ETHMACPTP_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACPTPEN))
633 #define __HAL_RCC_ETH_CLK_ENABLE() do { \
634 __HAL_RCC_ETHMAC_CLK_ENABLE(); \
635 __HAL_RCC_ETHMACTX_CLK_ENABLE(); \
636 __HAL_RCC_ETHMACRX_CLK_ENABLE(); \
637 } while(0)
638
639 /**
640 * @brief Disable ETHERNET clock.
641 */
642 #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
643 #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
644 #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
645 #define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
646 #define __HAL_RCC_ETH_CLK_DISABLE() do { \
647 __HAL_RCC_ETHMACTX_CLK_DISABLE(); \
648 __HAL_RCC_ETHMACRX_CLK_DISABLE(); \
649 __HAL_RCC_ETHMAC_CLK_DISABLE(); \
650 } while(0)
651 #endif /* STM32F407xx || STM32F417xx */
652
653 /** @brief Enable or disable the AHB2 peripheral clock.
654 * @note After reset, the peripheral clock (used for registers read/write access)
655 * is disabled and the application software has to enable this clock before
656 * using it.
657 */
658 #if defined(STM32F407xx)|| defined(STM32F417xx)
659 #define __HAL_RCC_DCMI_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_DCMIEN))
660 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
661 #endif /* STM32F407xx || STM32F417xx */
662
663 #if defined(STM32F415xx) || defined(STM32F417xx)
664 #define __HAL_RCC_CRYP_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_CRYPEN))
665 #define __HAL_RCC_HASH_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_HASHEN))
666
667 #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
668 #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
669 #endif /* STM32F415xx || STM32F417xx */
670
671 /** @brief Enables or disables the AHB3 peripheral clock.
672 * @note After reset, the peripheral clock (used for registers read/write access)
673 * is disabled and the application software has to enable this clock before
674 * using it.
675 */
676 #define __HAL_RCC_FSMC_CLK_ENABLE() (RCC->AHB3ENR |= (RCC_AHB3ENR_FSMCEN))
677 #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
678
679 /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
680 * @note After reset, the peripheral clock (used for registers read/write access)
681 * is disabled and the application software has to enable this clock before
682 * using it.
683 */
684 #define __HAL_RCC_TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
685 #define __HAL_RCC_TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
686 #define __HAL_RCC_TIM12_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM12EN))
687 #define __HAL_RCC_TIM13_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM13EN))
688 #define __HAL_RCC_TIM14_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM14EN))
689 #define __HAL_RCC_WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
690 #define __HAL_RCC_USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN))
691 #define __HAL_RCC_UART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART4EN))
692 #define __HAL_RCC_UART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART5EN))
693 #define __HAL_RCC_CAN1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN1EN))
694 #define __HAL_RCC_CAN2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN2EN))
695 #define __HAL_RCC_DAC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
696
697 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
698 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
699 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
700 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
701 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
702 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
703 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
704 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
705 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
706 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
707 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
708 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
709
710 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
711 * @note After reset, the peripheral clock (used for registers read/write access)
712 * is disabled and the application software has to enable this clock before
713 * using it.
714 */
715 #define __HAL_RCC_TIM8_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM8EN))
716 #define __HAL_RCC_ADC2_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC2EN))
717 #define __HAL_RCC_ADC3_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC3EN))
718
719 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
720 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
721 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
722
723 /** @brief Force or release AHB1 peripheral reset.
724 */
725 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
726 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
727 #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
728 #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
729 #define __HAL_RCC_OTGHS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
730
731 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
732 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
733 #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
734 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
735 #define __HAL_RCC_OTGHS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
736
737 /** @brief Force or release AHB2 peripheral reset.
738 */
739 #if defined(STM32F407xx)|| defined(STM32F417xx)
740 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
741 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
742 #endif /* STM32F407xx || STM32F417xx */
743
744 #if defined(STM32F415xx) || defined(STM32F417xx)
745 #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
746 #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
747
748 #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
749 #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
750
751 #endif /* STM32F415xx || STM32F417xx */
752
753 /** @brief Force or release AHB3 peripheral reset
754 */
755 #define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST))
756 #define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
757
758 /** @brief Force or release APB1 peripheral reset.
759 */
760 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
761 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
762 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
763 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
764 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
765 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
766 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
767 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
768 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
769 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
770 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
771
772 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
773 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
774 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
775 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
776 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
777 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
778 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
779 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
780 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
781 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
782 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
783
784 /** @brief Force or release APB2 peripheral reset.
785 */
786 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
787 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
788
789 /** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
790 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
791 * power consumption.
792 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
793 * @note By default, all peripheral clocks are enabled during SLEEP mode.
794 */
795 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
796 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
797 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
798 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
799 #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
800 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
801 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
802 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
803 #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
804 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
805
806 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
807 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
808 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
809 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
810 #define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
811 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
812 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
813 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
814 #define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
815 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
816
817 /** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
818 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
819 * power consumption.
820 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
821 * @note By default, all peripheral clocks are enabled during SLEEP mode.
822 */
823 #if defined(STM32F407xx)|| defined(STM32F417xx)
824 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
825 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
826 #endif /* STM32F407xx || STM32F417xx */
827
828 #if defined(STM32F415xx) || defined(STM32F417xx)
829 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
830 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
831
832 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
833 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
834 #endif /* STM32F415xx || STM32F417xx */
835
836 /** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
837 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
838 * power consumption.
839 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
840 * @note By default, all peripheral clocks are enabled during SLEEP mode.
841 */
842 #define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN))
843 #define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
844
845 /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
846 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
847 * power consumption.
848 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
849 * @note By default, all peripheral clocks are enabled during SLEEP mode.
850 */
851 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
852 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
853 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
854 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
855 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
856 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
857 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
858 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
859 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
860 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
861 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
862
863 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
864 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
865 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
866 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
867 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
868 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
869 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
870 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
871 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
872 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
873 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
874
875 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
876 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
877 * power consumption.
878 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
879 * @note By default, all peripheral clocks are enabled during SLEEP mode.
880 */
881 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
882 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
883 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
884
885 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
886 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
887 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
888 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
889 /*---------------------------------------------------------------------------------------------*/
890
891 /*------------------------------------------ STM32F411xx --------------------------------------*/
892 #if defined(STM32F411xE)
893 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
894 */
895 #define __HAL_RCC_SPI5_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI5EN))
896 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
897
898 /** @brief Force or release APB2 peripheral reset.
899 */
900 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
901 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
902
903 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
904 */
905 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
906 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
907
908 #endif /* STM32F411xE */
909 /*---------------------------------------------------------------------------------------------*/
910
911 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
912 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
913
914 /** @brief Macro to configure the Timers clocks prescalers
915 * @note This feature is only available with STM32F429x/439x Devices.
916 * @param __PRESC__ : specifies the Timers clocks prescalers selection
917 * This parameter can be one of the following values:
918 * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
919 * equal to HPRE if PPREx is corresponding to division by 1 or 2,
920 * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
921 * division by 4 or more.
922 * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
923 * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
924 * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
925 * to division by 8 or more.
926 */
927 #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__))
928
929 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx) || STM32F401xC || STM32F401xE || STM32F411xE */
930
931 #if defined(STM32F411xE)
932
933 /** @brief Macro to configure the PLLI2S clock multiplication and division factors .
934 * @note This macro must be used only when the PLLI2S is disabled.
935 * @note This macro must be used only when the PLLI2S is disabled.
936 * @note PLLI2S clock source is common with the main PLL (configured in
937 * HAL_RCC_ClockConfig() API).
938 * @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
939 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
940 * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
941 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
942 * of 2 MHz to limit PLLI2S jitter.
943 * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
944 * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
945 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
946 * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
947 * @param __PLLI2SR__: specifies the division factor for I2S clock
948 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
949 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
950 * on the I2S clock frequency.
951 */
952 #define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\
953 ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)) | (__PLLI2SM__))
954 #endif /* STM32F411xE */
955
956
957 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
958
959 /** @brief Macros to Enable or Disable the PLLISAI.
960 * @note The PLLSAI is only available with STM32F429x/439x Devices.
961 * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
962 */
963 #define __HAL_RCC_PLLSAI_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = ENABLE)
964 #define __HAL_RCC_PLLSAI_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = DISABLE)
965
966 /** @brief Macro to configure the PLLSAI clock multiplication and division factors.
967 * @note The PLLSAI is only available with STM32F429x/439x Devices.
968 * @note This function must be used only when the PLLSAI is disabled.
969 * @note PLLSAI clock source is common with the main PLL (configured in
970 * RCC_PLLConfig function )
971 * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
972 * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
973 * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
974 * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
975 * @param __PLLSAIQ__: specifies the division factor for SAI1 clock
976 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
977 * @param __PLLSAIR__: specifies the division factor for LTDC clock
978 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
979 */
980 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) (RCC->PLLSAICFGR = ((__PLLSAIN__) << 6) | ((__PLLSAIQ__) << 24) | ((__PLLSAIR__) << 28))
981
982 /** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
983 * @note This macro must be used only when the PLLI2S is disabled.
984 * @note PLLI2S clock source is common with the main PLL (configured in
985 * HAL_RCC_ClockConfig() API)
986 * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
987 * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
988 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
989 * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
990 * @param __PLLI2SQ__: specifies the division factor for SAI1 clock.
991 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
992 * @note the PLLI2SQ parameter is only available with STM32F429x/439x Devices
993 * and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro
994 * @param __PLLI2SR__: specifies the division factor for I2S clock
995 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
996 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
997 * on the I2S clock frequency.
998 */
999 #define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) | ((__PLLI2SQ__) << 24) | ((__PLLI2SR__) << 28))
1000
1001 /** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
1002 * @note The SAI peripheral is only available with STM32F429x/439x Devices.
1003 * @note This function must be called before enabling the PLLI2S.
1004 * @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock .
1005 * This parameter must be a number between 1 and 32.
1006 * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
1007 */
1008 #define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
1009
1010 /** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
1011 * @note The SAI peripheral is only available with STM32F429x/439x Devices.
1012 * @note This function must be called before enabling the PLLSAI.
1013 * @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
1014 * This parameter must be a number between Min_Data = 1 and Max_Data = 32.
1015 * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
1016 */
1017 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
1018
1019 /** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
1020 *
1021 * @note The LTDC peripheral is only available with STM32F429x/439x Devices.
1022 * @note This function must be called before enabling the PLLSAI.
1023 * @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
1024 * This parameter must be a number between Min_Data = 2 and Max_Data = 16.
1025 * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
1026 */
1027 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
1028
1029 /** @brief Macro to configure SAI1BlockA clock source selection.
1030 * @note The SAI peripheral is only available with STM32F429x/439x Devices.
1031 * @note This function must be called before enabling PLLSAI, PLLI2S and
1032 * the SAI clock.
1033 * @param __SOURCE__: specifies the SAI Block A clock source.
1034 * This parameter can be one of the following values:
1035 * @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
1036 * as SAI1 Block A clock.
1037 * @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
1038 * as SAI1 Block A clock.
1039 * @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
1040 * used as SAI1 Block A clock.
1041 */
1042 #define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
1043
1044 /** @brief Macro to configure SAI1BlockB clock source selection.
1045 * @note The SAI peripheral is only available with STM32F429x/439x Devices.
1046 * @note This function must be called before enabling PLLSAI, PLLI2S and
1047 * the SAI clock.
1048 * @param __SOURCE__: specifies the SAI Block B clock source.
1049 * This parameter can be one of the following values:
1050 * @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
1051 * as SAI1 Block B clock.
1052 * @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
1053 * as SAI1 Block B clock.
1054 * @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
1055 * used as SAI1 Block B clock.
1056 */
1057 #define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
1058
1059 /** @brief Enable PLLSAI_RDY interrupt.
1060 */
1061 #define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))
1062
1063 /** @brief Disable PLLSAI_RDY interrupt.
1064 */
1065 #define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
1066
1067 /** @brief Clear the PLLSAI RDY interrupt pending bits.
1068 */
1069 #define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))
1070
1071 /** @brief Check the PLLSAI RDY interrupt has occurred or not.
1072 * @retval The new state (TRUE or FALSE).
1073 */
1074 #define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
1075
1076 /** @brief Check PLLSAI RDY flag is set or not.
1077 * @retval The new state (TRUE or FALSE).
1078 */
1079 #define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
1080
1081 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
1082 /**
1083 * @}
1084 */
1085
1086 /* Exported functions --------------------------------------------------------*/
1087 /** @addtogroup RCCEx_Exported_Functions
1088 * @{
1089 */
1090
1091 /** @addtogroup RCCEx_Exported_Functions_Group1
1092 * @{
1093 */
1094 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
1095 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
1096
1097 #if defined(STM32F411xE)
1098 void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
1099 #endif /* STM32F411xE */
1100 /**
1101 * @}
1102 */
1103
1104 /**
1105 * @}
1106 */
1107 /* Private types -------------------------------------------------------------*/
1108 /* Private variables ---------------------------------------------------------*/
1109 /* Private constants ---------------------------------------------------------*/
1110 /** @defgroup RCCEx_Private_Constants RCCEx Private Constants
1111 * @{
1112 */
1113 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
1114 /** @defgroup RCCEx_BitAddress_AliasRegion RCC BitAddress AliasRegion
1115 * @brief RCC registers bit address in the alias region
1116 * @{
1117 */
1118 /* --- CR Register ---*/
1119 /* Alias word address of PLLSAION bit */
1120 #define RCC_PLLSAION_BIT_NUMBER 0x1C
1121 #define RCC_CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLSAION_BIT_NUMBER * 4))
1122
1123 /* --- DCKCFGR Register ---*/
1124 /* Alias word address of TIMPRE bit */
1125 #define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8C)
1126 #define RCC_TIMPRE_BIT_NUMBER 0x18
1127 #define RCC_DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32) + (RCC_TIMPRE_BIT_NUMBER * 4))
1128 /**
1129 * @}
1130 */
1131 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
1132
1133 /**
1134 * @}
1135 */
1136
1137 /* Private macros ------------------------------------------------------------*/
1138 /** @addtogroup RCCEx_Private_Macros RCCEx Private Macros
1139 * @{
1140 */
1141 /** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
1142 * @{
1143 */
1144 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
1145 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000002F))
1146 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
1147
1148 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
1149 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
1150 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000003))
1151 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
1152
1153 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
1154 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
1155 #define IS_RCC_PLLSAIN_VALUE(VALUE) ((49 <= (VALUE)) && ((VALUE) <= 432))
1156 #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
1157 #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
1158 #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
1159 #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
1160 #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\
1161 ((VALUE) == RCC_PLLSAIDIVR_4) ||\
1162 ((VALUE) == RCC_PLLSAIDIVR_8) ||\
1163 ((VALUE) == RCC_PLLSAIDIVR_16))
1164 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
1165
1166 #if defined(STM32F411xE)
1167
1168 #define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63)
1169 #define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\
1170 ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
1171 #endif /* STM32F411xE */
1172
1173 /**
1174 * @}
1175 */
1176
1177 /**
1178 * @}
1179 */
1180
1181 /**
1182 * @}
1183 */
1184
1185 /**
1186 * @}
1187 */
1188 #ifdef __cplusplus
1189 }
1190 #endif
1191
1192 #endif /* __STM32F4xx_HAL_RCC_EX_H */
1193
1194 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/