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comparison Common/Drivers/STM32F4xx_HAL_DRIVER_v120/Inc/stm32f4xx_hal_rcc.h @ 38:5f11787b4f42
include in ostc4 repository
author | heinrichsweikamp |
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date | Sat, 28 Apr 2018 11:52:34 +0200 |
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1 /** | |
2 ****************************************************************************** | |
3 * @file stm32f4xx_hal_rcc.h | |
4 * @author MCD Application Team | |
5 * @version V1.2.0 | |
6 * @date 26-December-2014 | |
7 * @brief Header file of RCC HAL module. | |
8 ****************************************************************************** | |
9 * @attention | |
10 * | |
11 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> | |
12 * | |
13 * Redistribution and use in source and binary forms, with or without modification, | |
14 * are permitted provided that the following conditions are met: | |
15 * 1. Redistributions of source code must retain the above copyright notice, | |
16 * this list of conditions and the following disclaimer. | |
17 * 2. Redistributions in binary form must reproduce the above copyright notice, | |
18 * this list of conditions and the following disclaimer in the documentation | |
19 * and/or other materials provided with the distribution. | |
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors | |
21 * may be used to endorse or promote products derived from this software | |
22 * without specific prior written permission. | |
23 * | |
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE | |
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER | |
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | |
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
34 * | |
35 ****************************************************************************** | |
36 */ | |
37 | |
38 /* Define to prevent recursive inclusion -------------------------------------*/ | |
39 #ifndef __STM32F4xx_HAL_RCC_H | |
40 #define __STM32F4xx_HAL_RCC_H | |
41 | |
42 #ifdef __cplusplus | |
43 extern "C" { | |
44 #endif | |
45 | |
46 /* Includes ------------------------------------------------------------------*/ | |
47 #include "stm32f4xx_hal_def.h" | |
48 | |
49 /** @addtogroup STM32F4xx_HAL_Driver | |
50 * @{ | |
51 */ | |
52 | |
53 /** @addtogroup RCC | |
54 * @{ | |
55 */ | |
56 | |
57 /* Exported types ------------------------------------------------------------*/ | |
58 /** @defgroup RCC_Exported_Types RCC Exported Types | |
59 * @{ | |
60 */ | |
61 | |
62 /** | |
63 * @brief RCC PLL configuration structure definition | |
64 */ | |
65 typedef struct | |
66 { | |
67 uint32_t PLLState; /*!< The new state of the PLL. | |
68 This parameter can be a value of @ref RCC_PLL_Config */ | |
69 | |
70 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. | |
71 This parameter must be a value of @ref RCC_PLL_Clock_Source */ | |
72 | |
73 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. | |
74 This parameter must be a number between Min_Data = 0 and Max_Data = 63 */ | |
75 | |
76 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. | |
77 This parameter must be a number between Min_Data = 192 and Max_Data = 432 */ | |
78 | |
79 uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK). | |
80 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ | |
81 | |
82 uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks. | |
83 This parameter must be a number between Min_Data = 4 and Max_Data = 15 */ | |
84 | |
85 }RCC_PLLInitTypeDef; | |
86 | |
87 /** | |
88 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition | |
89 */ | |
90 typedef struct | |
91 { | |
92 uint32_t OscillatorType; /*!< The oscillators to be configured. | |
93 This parameter can be a value of @ref RCC_Oscillator_Type */ | |
94 | |
95 uint32_t HSEState; /*!< The new state of the HSE. | |
96 This parameter can be a value of @ref RCC_HSE_Config */ | |
97 | |
98 uint32_t LSEState; /*!< The new state of the LSE. | |
99 This parameter can be a value of @ref RCC_LSE_Config */ | |
100 | |
101 uint32_t HSIState; /*!< The new state of the HSI. | |
102 This parameter can be a value of @ref RCC_HSI_Config */ | |
103 | |
104 uint32_t HSICalibrationValue; /*!< The calibration trimming value. | |
105 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ | |
106 | |
107 uint32_t LSIState; /*!< The new state of the LSI. | |
108 This parameter can be a value of @ref RCC_LSI_Config */ | |
109 | |
110 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ | |
111 | |
112 }RCC_OscInitTypeDef; | |
113 | |
114 /** | |
115 * @brief RCC System, AHB and APB busses clock configuration structure definition | |
116 */ | |
117 typedef struct | |
118 { | |
119 uint32_t ClockType; /*!< The clock to be configured. | |
120 This parameter can be a value of @ref RCC_System_Clock_Type */ | |
121 | |
122 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. | |
123 This parameter can be a value of @ref RCC_System_Clock_Source */ | |
124 | |
125 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). | |
126 This parameter can be a value of @ref RCC_AHB_Clock_Source */ | |
127 | |
128 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). | |
129 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ | |
130 | |
131 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). | |
132 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ | |
133 | |
134 }RCC_ClkInitTypeDef; | |
135 | |
136 /** | |
137 * @} | |
138 */ | |
139 | |
140 /* Exported constants --------------------------------------------------------*/ | |
141 /** @defgroup RCC_Exported_Constants RCC Exported Constants | |
142 * @{ | |
143 */ | |
144 | |
145 /** @defgroup RCC_Oscillator_Type Oscillator Type | |
146 * @{ | |
147 */ | |
148 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000) | |
149 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001) | |
150 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002) | |
151 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004) | |
152 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008) | |
153 /** | |
154 * @} | |
155 */ | |
156 | |
157 /** @defgroup RCC_HSE_Config HSE Config | |
158 * @{ | |
159 */ | |
160 #define RCC_HSE_OFF ((uint8_t)0x00) | |
161 #define RCC_HSE_ON ((uint8_t)0x01) | |
162 #define RCC_HSE_BYPASS ((uint8_t)0x05) | |
163 /** | |
164 * @} | |
165 */ | |
166 | |
167 /** @defgroup RCC_LSE_Config LSE Config | |
168 * @{ | |
169 */ | |
170 #define RCC_LSE_OFF ((uint8_t)0x00) | |
171 #define RCC_LSE_ON ((uint8_t)0x01) | |
172 #define RCC_LSE_BYPASS ((uint8_t)0x05) | |
173 /** | |
174 * @} | |
175 */ | |
176 | |
177 /** @defgroup RCC_HSI_Config HSI Config | |
178 * @{ | |
179 */ | |
180 #define RCC_HSI_OFF ((uint8_t)0x00) | |
181 #define RCC_HSI_ON ((uint8_t)0x01) | |
182 /** | |
183 * @} | |
184 */ | |
185 | |
186 /** @defgroup RCC_LSI_Config LSI Config | |
187 * @{ | |
188 */ | |
189 #define RCC_LSI_OFF ((uint8_t)0x00) | |
190 #define RCC_LSI_ON ((uint8_t)0x01) | |
191 /** | |
192 * @} | |
193 */ | |
194 | |
195 /** @defgroup RCC_PLL_Config PLL Config | |
196 * @{ | |
197 */ | |
198 #define RCC_PLL_NONE ((uint8_t)0x00) | |
199 #define RCC_PLL_OFF ((uint8_t)0x01) | |
200 #define RCC_PLL_ON ((uint8_t)0x02) | |
201 /** | |
202 * @} | |
203 */ | |
204 | |
205 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider | |
206 * @{ | |
207 */ | |
208 #define RCC_PLLP_DIV2 ((uint32_t)0x00000002) | |
209 #define RCC_PLLP_DIV4 ((uint32_t)0x00000004) | |
210 #define RCC_PLLP_DIV6 ((uint32_t)0x00000006) | |
211 #define RCC_PLLP_DIV8 ((uint32_t)0x00000008) | |
212 /** | |
213 * @} | |
214 */ | |
215 | |
216 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source | |
217 * @{ | |
218 */ | |
219 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI | |
220 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE | |
221 /** | |
222 * @} | |
223 */ | |
224 | |
225 /** @defgroup RCC_System_Clock_Type System Clock Type | |
226 * @{ | |
227 */ | |
228 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) | |
229 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) | |
230 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) | |
231 #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008) | |
232 /** | |
233 * @} | |
234 */ | |
235 | |
236 /** @defgroup RCC_System_Clock_Source System Clock Source | |
237 * @{ | |
238 */ | |
239 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI | |
240 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE | |
241 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL | |
242 /** | |
243 * @} | |
244 */ | |
245 | |
246 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source | |
247 * @{ | |
248 */ | |
249 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 | |
250 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 | |
251 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 | |
252 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 | |
253 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 | |
254 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 | |
255 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 | |
256 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 | |
257 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 | |
258 /** | |
259 * @} | |
260 */ | |
261 | |
262 /** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source | |
263 * @{ | |
264 */ | |
265 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 | |
266 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 | |
267 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 | |
268 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 | |
269 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 | |
270 /** | |
271 * @} | |
272 */ | |
273 | |
274 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source | |
275 * @{ | |
276 */ | |
277 #define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100) | |
278 #define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200) | |
279 #define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300) | |
280 #define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300) | |
281 #define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300) | |
282 #define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300) | |
283 #define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300) | |
284 #define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300) | |
285 #define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300) | |
286 #define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300) | |
287 #define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300) | |
288 #define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300) | |
289 #define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300) | |
290 #define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300) | |
291 #define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300) | |
292 #define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300) | |
293 #define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300) | |
294 #define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300) | |
295 #define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300) | |
296 #define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300) | |
297 #define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300) | |
298 #define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300) | |
299 #define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300) | |
300 #define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300) | |
301 #define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300) | |
302 #define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300) | |
303 #define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300) | |
304 #define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300) | |
305 #define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300) | |
306 #define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300) | |
307 #define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300) | |
308 #define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300) | |
309 /** | |
310 * @} | |
311 */ | |
312 | |
313 /** @defgroup RCC_I2S_Clock_Source I2S Clock Source | |
314 * @{ | |
315 */ | |
316 #define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000) | |
317 #define RCC_I2SCLKSOURCE_EXT ((uint32_t)0x00000001) | |
318 /** | |
319 * @} | |
320 */ | |
321 | |
322 /** @defgroup RCC_MCO_Index MCO Index | |
323 * @{ | |
324 */ | |
325 #define RCC_MCO1 ((uint32_t)0x00000000) | |
326 #define RCC_MCO2 ((uint32_t)0x00000001) | |
327 /** | |
328 * @} | |
329 */ | |
330 | |
331 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source | |
332 * @{ | |
333 */ | |
334 #define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000) | |
335 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0 | |
336 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1 | |
337 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1 | |
338 /** | |
339 * @} | |
340 */ | |
341 | |
342 /** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source | |
343 * @{ | |
344 */ | |
345 #define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000) | |
346 #define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0 | |
347 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1 | |
348 #define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2 | |
349 /** | |
350 * @} | |
351 */ | |
352 | |
353 /** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler | |
354 * @{ | |
355 */ | |
356 #define RCC_MCODIV_1 ((uint32_t)0x00000000) | |
357 #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2 | |
358 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2) | |
359 #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2) | |
360 #define RCC_MCODIV_5 RCC_CFGR_MCO1PRE | |
361 /** | |
362 * @} | |
363 */ | |
364 | |
365 /** @defgroup RCC_Interrupt Interrupts | |
366 * @{ | |
367 */ | |
368 #define RCC_IT_LSIRDY ((uint8_t)0x01) | |
369 #define RCC_IT_LSERDY ((uint8_t)0x02) | |
370 #define RCC_IT_HSIRDY ((uint8_t)0x04) | |
371 #define RCC_IT_HSERDY ((uint8_t)0x08) | |
372 #define RCC_IT_PLLRDY ((uint8_t)0x10) | |
373 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20) | |
374 #define RCC_IT_CSS ((uint8_t)0x80) | |
375 /** | |
376 * @} | |
377 */ | |
378 | |
379 /** @defgroup RCC_Flag Flags | |
380 * Elements values convention: 0XXYYYYYb | |
381 * - YYYYY : Flag position in the register | |
382 * - 0XX : Register index | |
383 * - 01: CR register | |
384 * - 10: BDCR register | |
385 * - 11: CSR register | |
386 * @{ | |
387 */ | |
388 /* Flags in the CR register */ | |
389 #define RCC_FLAG_HSIRDY ((uint8_t)0x21) | |
390 #define RCC_FLAG_HSERDY ((uint8_t)0x31) | |
391 #define RCC_FLAG_PLLRDY ((uint8_t)0x39) | |
392 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B) | |
393 | |
394 /* Flags in the BDCR register */ | |
395 #define RCC_FLAG_LSERDY ((uint8_t)0x41) | |
396 | |
397 /* Flags in the CSR register */ | |
398 #define RCC_FLAG_LSIRDY ((uint8_t)0x61) | |
399 #define RCC_FLAG_BORRST ((uint8_t)0x79) | |
400 #define RCC_FLAG_PINRST ((uint8_t)0x7A) | |
401 #define RCC_FLAG_PORRST ((uint8_t)0x7B) | |
402 #define RCC_FLAG_SFTRST ((uint8_t)0x7C) | |
403 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D) | |
404 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E) | |
405 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F) | |
406 /** | |
407 * @} | |
408 */ | |
409 | |
410 /** | |
411 * @} | |
412 */ | |
413 | |
414 /* Exported macro ------------------------------------------------------------*/ | |
415 /** @defgroup RCC_Exported_Macros RCC Exported Macros | |
416 * @{ | |
417 */ | |
418 | |
419 /** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable | |
420 * @brief Enable or disable the AHB1 peripheral clock. | |
421 * @note After reset, the peripheral clock (used for registers read/write access) | |
422 * is disabled and the application software has to enable this clock before | |
423 * using it. | |
424 * @{ | |
425 */ | |
426 #define __HAL_RCC_GPIOA_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOAEN)) | |
427 #define __HAL_RCC_GPIOB_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOBEN)) | |
428 #define __HAL_RCC_GPIOC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOCEN)) | |
429 #define __HAL_RCC_GPIOD_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIODEN)) | |
430 #define __HAL_RCC_GPIOE_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOEEN)) | |
431 #define __HAL_RCC_GPIOH_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOHEN)) | |
432 #define __HAL_RCC_CRC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_CRCEN)) | |
433 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_BKPSRAMEN)) | |
434 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_CCMDATARAMEN)) | |
435 #define __HAL_RCC_DMA1_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_DMA1EN)) | |
436 #define __HAL_RCC_DMA2_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_DMA2EN)) | |
437 | |
438 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN)) | |
439 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN)) | |
440 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN)) | |
441 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) | |
442 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) | |
443 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN)) | |
444 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) | |
445 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) | |
446 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) | |
447 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN)) | |
448 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN)) | |
449 | |
450 /** | |
451 * @} | |
452 */ | |
453 | |
454 /** @defgroup RCC_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable | |
455 * @brief Enable or disable the AHB2 peripheral clock. | |
456 * @note After reset, the peripheral clock (used for registers read/write access) | |
457 * is disabled and the application software has to enable this clock before | |
458 * using it. | |
459 * @{ | |
460 */ | |
461 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ | |
462 __HAL_RCC_SYSCFG_CLK_ENABLE();\ | |
463 }while(0) | |
464 | |
465 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\ | |
466 __HAL_RCC_SYSCFG_CLK_DISABLE();\ | |
467 }while(0) | |
468 | |
469 #define __HAL_RCC_RNG_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_RNGEN)) | |
470 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) | |
471 | |
472 /** | |
473 * @} | |
474 */ | |
475 | |
476 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable | |
477 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. | |
478 * @note After reset, the peripheral clock (used for registers read/write access) | |
479 * is disabled and the application software has to enable this clock before | |
480 * using it. | |
481 * @{ | |
482 */ | |
483 #define __HAL_RCC_TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN)) | |
484 #define __HAL_RCC_TIM3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN)) | |
485 #define __HAL_RCC_TIM4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM4EN)) | |
486 #define __HAL_RCC_TIM5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM5EN)) | |
487 #define __HAL_RCC_WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN)) | |
488 #define __HAL_RCC_SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN)) | |
489 #define __HAL_RCC_SPI3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI3EN)) | |
490 #define __HAL_RCC_USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN)) | |
491 #define __HAL_RCC_I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN)) | |
492 #define __HAL_RCC_I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN)) | |
493 #define __HAL_RCC_I2C3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C3EN)) | |
494 #define __HAL_RCC_PWR_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_PWREN)) | |
495 | |
496 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) | |
497 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) | |
498 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) | |
499 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) | |
500 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) | |
501 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) | |
502 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) | |
503 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) | |
504 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) | |
505 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) | |
506 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) | |
507 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) | |
508 /** | |
509 * @} | |
510 */ | |
511 | |
512 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable | |
513 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. | |
514 * @note After reset, the peripheral clock (used for registers read/write access) | |
515 * is disabled and the application software has to enable this clock before | |
516 * using it. | |
517 * @{ | |
518 */ | |
519 #define __HAL_RCC_TIM1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM1EN)) | |
520 #define __HAL_RCC_USART1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART1EN)) | |
521 #define __HAL_RCC_USART6_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART6EN)) | |
522 #define __HAL_RCC_ADC1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN)) | |
523 #define __HAL_RCC_SDIO_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SDIOEN)) | |
524 #define __HAL_RCC_SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN)) | |
525 #define __HAL_RCC_SPI4_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI4EN)) | |
526 #define __HAL_RCC_SYSCFG_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SYSCFGEN)) | |
527 #define __HAL_RCC_TIM9_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM9EN)) | |
528 #define __HAL_RCC_TIM10_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM10EN)) | |
529 #define __HAL_RCC_TIM11_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM11EN)) | |
530 | |
531 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) | |
532 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) | |
533 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) | |
534 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) | |
535 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) | |
536 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) | |
537 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) | |
538 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) | |
539 #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) | |
540 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) | |
541 #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN)) | |
542 /** | |
543 * @} | |
544 */ | |
545 | |
546 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset | |
547 * @brief Force or release AHB1 peripheral reset. | |
548 * @{ | |
549 */ | |
550 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFF) | |
551 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST)) | |
552 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST)) | |
553 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST)) | |
554 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) | |
555 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) | |
556 #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST)) | |
557 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) | |
558 #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST)) | |
559 #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST)) | |
560 | |
561 #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00) | |
562 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST)) | |
563 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST)) | |
564 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST)) | |
565 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) | |
566 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) | |
567 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) | |
568 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) | |
569 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST)) | |
570 #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) | |
571 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) | |
572 #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST)) | |
573 #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST)) | |
574 /** | |
575 * @} | |
576 */ | |
577 | |
578 /** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Force Release Reset | |
579 * @brief Force or release AHB2 peripheral reset. | |
580 * @{ | |
581 */ | |
582 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF) | |
583 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) | |
584 | |
585 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00) | |
586 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) | |
587 | |
588 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) | |
589 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) | |
590 /** | |
591 * @} | |
592 */ | |
593 | |
594 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset | |
595 * @brief Force or release APB1 peripheral reset. | |
596 * @{ | |
597 */ | |
598 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF) | |
599 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) | |
600 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) | |
601 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) | |
602 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) | |
603 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) | |
604 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) | |
605 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) | |
606 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) | |
607 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) | |
608 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) | |
609 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) | |
610 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) | |
611 | |
612 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00) | |
613 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) | |
614 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) | |
615 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) | |
616 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) | |
617 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) | |
618 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) | |
619 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) | |
620 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) | |
621 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) | |
622 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) | |
623 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) | |
624 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) | |
625 /** | |
626 * @} | |
627 */ | |
628 | |
629 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset | |
630 * @brief Force or release APB2 peripheral reset. | |
631 * @{ | |
632 */ | |
633 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF) | |
634 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) | |
635 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) | |
636 #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST)) | |
637 #define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST)) | |
638 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) | |
639 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) | |
640 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) | |
641 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) | |
642 #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST)) | |
643 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) | |
644 #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST)) | |
645 | |
646 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00) | |
647 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) | |
648 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) | |
649 #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST)) | |
650 #define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST)) | |
651 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) | |
652 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) | |
653 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) | |
654 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) | |
655 #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST)) | |
656 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) | |
657 #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST)) | |
658 /** | |
659 * @} | |
660 */ | |
661 | |
662 /** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Force Release Reset | |
663 * @brief Force or release AHB3 peripheral reset. | |
664 * @{ | |
665 */ | |
666 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF) | |
667 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00) | |
668 /** | |
669 * @} | |
670 */ | |
671 | |
672 /** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable | |
673 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. | |
674 * @note Peripheral clock gating in SLEEP mode can be used to further reduce | |
675 * power consumption. | |
676 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. | |
677 * @note By default, all peripheral clocks are enabled during SLEEP mode. | |
678 * @{ | |
679 */ | |
680 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN)) | |
681 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN)) | |
682 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN)) | |
683 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) | |
684 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) | |
685 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN)) | |
686 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) | |
687 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) | |
688 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) | |
689 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) | |
690 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN)) | |
691 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN)) | |
692 | |
693 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN)) | |
694 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN)) | |
695 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN)) | |
696 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) | |
697 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) | |
698 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN)) | |
699 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) | |
700 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) | |
701 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) | |
702 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) | |
703 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN)) | |
704 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN)) | |
705 /** | |
706 * @} | |
707 */ | |
708 | |
709 /** @defgroup RCC_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable | |
710 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. | |
711 * @note Peripheral clock gating in SLEEP mode can be used to further reduce | |
712 * power consumption. | |
713 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. | |
714 * @note By default, all peripheral clocks are enabled during SLEEP mode. | |
715 * @{ | |
716 */ | |
717 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) | |
718 | |
719 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) | |
720 | |
721 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) | |
722 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) | |
723 /** | |
724 * @} | |
725 */ | |
726 | |
727 /** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable | |
728 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. | |
729 * @note Peripheral clock gating in SLEEP mode can be used to further reduce | |
730 * power consumption. | |
731 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. | |
732 * @note By default, all peripheral clocks are enabled during SLEEP mode. | |
733 * @{ | |
734 */ | |
735 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) | |
736 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) | |
737 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) | |
738 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN)) | |
739 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN)) | |
740 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN)) | |
741 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) | |
742 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN)) | |
743 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN)) | |
744 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN)) | |
745 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) | |
746 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN)) | |
747 | |
748 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) | |
749 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) | |
750 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) | |
751 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN)) | |
752 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN)) | |
753 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN)) | |
754 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) | |
755 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN)) | |
756 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN)) | |
757 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN)) | |
758 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) | |
759 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN)) | |
760 /** | |
761 * @} | |
762 */ | |
763 | |
764 /** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable | |
765 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. | |
766 * @note Peripheral clock gating in SLEEP mode can be used to further reduce | |
767 * power consumption. | |
768 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. | |
769 * @note By default, all peripheral clocks are enabled during SLEEP mode. | |
770 * @{ | |
771 */ | |
772 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN)) | |
773 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN)) | |
774 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN)) | |
775 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN)) | |
776 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) | |
777 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN)) | |
778 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) | |
779 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN)) | |
780 #define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN)) | |
781 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) | |
782 #define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN)) | |
783 | |
784 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN)) | |
785 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN)) | |
786 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN)) | |
787 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN)) | |
788 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) | |
789 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN)) | |
790 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) | |
791 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN)) | |
792 #define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN)) | |
793 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) | |
794 #define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN)) | |
795 /** | |
796 * @} | |
797 */ | |
798 | |
799 /** @defgroup RCC_HSI_Configuration HSI Configuration | |
800 * @{ | |
801 */ | |
802 | |
803 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). | |
804 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. | |
805 * It is used (enabled by hardware) as system clock source after startup | |
806 * from Reset, wake-up from STOP and STANDBY mode, or in case of failure | |
807 * of the HSE used directly or indirectly as system clock (if the Clock | |
808 * Security System CSS is enabled). | |
809 * @note HSI can not be stopped if it is used as system clock source. In this case, | |
810 * you have to select another source of the system clock then stop the HSI. | |
811 * @note After enabling the HSI, the application software should wait on HSIRDY | |
812 * flag to be set indicating that HSI clock is stable and can be used as | |
813 * system clock source. | |
814 * This parameter can be: ENABLE or DISABLE. | |
815 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator | |
816 * clock cycles. | |
817 */ | |
818 #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE) | |
819 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE) | |
820 | |
821 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. | |
822 * @note The calibration is used to compensate for the variations in voltage | |
823 * and temperature that influence the frequency of the internal HSI RC. | |
824 * @param __HSICalibrationValue__: specifies the calibration trimming value. | |
825 * This parameter must be a number between 0 and 0x1F. | |
826 */ | |
827 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\ | |
828 RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM))) | |
829 /** | |
830 * @} | |
831 */ | |
832 | |
833 /** @defgroup RCC_LSI_Configuration LSI Configuration | |
834 * @{ | |
835 */ | |
836 | |
837 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). | |
838 * @note After enabling the LSI, the application software should wait on | |
839 * LSIRDY flag to be set indicating that LSI clock is stable and can | |
840 * be used to clock the IWDG and/or the RTC. | |
841 * @note LSI can not be disabled if the IWDG is running. | |
842 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator | |
843 * clock cycles. | |
844 */ | |
845 #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE) | |
846 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE) | |
847 /** | |
848 * @} | |
849 */ | |
850 | |
851 /** @defgroup RCC_HSE_Configuration HSE Configuration | |
852 * @{ | |
853 */ | |
854 | |
855 /** | |
856 * @brief Macro to configure the External High Speed oscillator (HSE). | |
857 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application | |
858 * software should wait on HSERDY flag to be set indicating that HSE clock | |
859 * is stable and can be used to clock the PLL and/or system clock. | |
860 * @note HSE state can not be changed if it is used directly or through the | |
861 * PLL as system clock. In this case, you have to select another source | |
862 * of the system clock then change the HSE state (ex. disable it). | |
863 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. | |
864 * @note This function reset the CSSON bit, so if the clock security system(CSS) | |
865 * was previously enabled you have to enable it again after calling this | |
866 * function. | |
867 * @param __STATE__: specifies the new state of the HSE. | |
868 * This parameter can be one of the following values: | |
869 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after | |
870 * 6 HSE oscillator clock cycles. | |
871 * @arg RCC_HSE_ON: turn ON the HSE oscillator. | |
872 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock. | |
873 */ | |
874 #define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *) RCC_CR_BYTE2_ADDRESS = (__STATE__)) | |
875 /** | |
876 * @} | |
877 */ | |
878 | |
879 /** @defgroup RCC_LSE_Configuration LSE Configuration | |
880 * @{ | |
881 */ | |
882 | |
883 /** | |
884 * @brief Macro to configure the External Low Speed oscillator (LSE). | |
885 * @note As the LSE is in the Backup domain and write access is denied to | |
886 * this domain after reset, you have to enable write access using | |
887 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE | |
888 * (to be done once after reset). | |
889 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application | |
890 * software should wait on LSERDY flag to be set indicating that LSE clock | |
891 * is stable and can be used to clock the RTC. | |
892 * @param __STATE__: specifies the new state of the LSE. | |
893 * This parameter can be one of the following values: | |
894 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after | |
895 * 6 LSE oscillator clock cycles. | |
896 * @arg RCC_LSE_ON: turn ON the LSE oscillator. | |
897 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock. | |
898 */ | |
899 #define __HAL_RCC_LSE_CONFIG(__STATE__) (*(__IO uint8_t *) RCC_BDCR_BYTE0_ADDRESS = (__STATE__)) | |
900 | |
901 /** | |
902 * @} | |
903 */ | |
904 | |
905 /** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration | |
906 * @{ | |
907 */ | |
908 | |
909 /** @brief Macros to enable or disable the RTC clock. | |
910 * @note These macros must be used only after the RTC clock source was selected. | |
911 */ | |
912 #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE) | |
913 #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE) | |
914 | |
915 /** @brief Macros to configure the RTC clock (RTCCLK). | |
916 * @note As the RTC clock configuration bits are in the Backup domain and write | |
917 * access is denied to this domain after reset, you have to enable write | |
918 * access using the Power Backup Access macro before to configure | |
919 * the RTC clock source (to be done once after reset). | |
920 * @note Once the RTC clock is configured it can't be changed unless the | |
921 * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by | |
922 * a Power On Reset (POR). | |
923 * @param __RTCCLKSource__: specifies the RTC clock source. | |
924 * This parameter can be one of the following values: | |
925 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock. | |
926 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock. | |
927 * @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected | |
928 * as RTC clock, where x:[2,31] | |
929 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to | |
930 * work in STOP and STANDBY modes, and can be used as wake-up source. | |
931 * However, when the HSE clock is used as RTC clock source, the RTC | |
932 * cannot be used in STOP and STANDBY modes. | |
933 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as | |
934 * RTC clock source). | |
935 */ | |
936 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \ | |
937 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | |
938 | |
939 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \ | |
940 RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF); \ | |
941 } while (0) | |
942 | |
943 /** @brief Macros to force or release the Backup domain reset. | |
944 * @note This function resets the RTC peripheral (including the backup registers) | |
945 * and the RTC clock source selection in RCC_CSR register. | |
946 * @note The BKPSRAM is not affected by this reset. | |
947 */ | |
948 #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE) | |
949 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE) | |
950 /** | |
951 * @} | |
952 */ | |
953 | |
954 /** @defgroup RCC_PLL_Configuration PLL Configuration | |
955 * @{ | |
956 */ | |
957 | |
958 /** @brief Macros to enable or disable the main PLL. | |
959 * @note After enabling the main PLL, the application software should wait on | |
960 * PLLRDY flag to be set indicating that PLL clock is stable and can | |
961 * be used as system clock source. | |
962 * @note The main PLL can not be disabled if it is used as system clock source | |
963 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. | |
964 */ | |
965 #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE) | |
966 #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE) | |
967 | |
968 /** @brief Macro to configure the main PLL clock source, multiplication and division factors. | |
969 * @note This function must be used only when the main PLL is disabled. | |
970 * @param __RCC_PLLSource__: specifies the PLL entry clock source. | |
971 * This parameter can be one of the following values: | |
972 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry | |
973 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry | |
974 * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. | |
975 * @param __PLLM__: specifies the division factor for PLL VCO input clock | |
976 * This parameter must be a number between Min_Data = 2 and Max_Data = 63. | |
977 * @note You have to set the PLLM parameter correctly to ensure that the VCO input | |
978 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency | |
979 * of 2 MHz to limit PLL jitter. | |
980 * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock | |
981 * This parameter must be a number between Min_Data = 192 and Max_Data = 432. | |
982 * @note You have to set the PLLN parameter correctly to ensure that the VCO | |
983 * output frequency is between 192 and 432 MHz. | |
984 * @param __PLLP__: specifies the division factor for main system clock (SYSCLK) | |
985 * This parameter must be a number in the range {2, 4, 6, or 8}. | |
986 * @note You have to set the PLLP parameter correctly to not exceed 168 MHz on | |
987 * the System clock frequency. | |
988 * @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks | |
989 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. | |
990 * @note If the USB OTG FS is used in your application, you have to set the | |
991 * PLLQ parameter correctly to have 48 MHz clock for the USB. However, | |
992 * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work | |
993 * correctly. | |
994 */ | |
995 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__)\ | |
996 (RCC->PLLCFGR = (0x20000000 | (__PLLM__) | ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \ | |
997 ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | (__RCC_PLLSource__) | \ | |
998 ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)))) | |
999 /** | |
1000 * @} | |
1001 */ | |
1002 | |
1003 /** @defgroup RCC_PLL_I2S_Configuration PLL I2S Configuration | |
1004 * @{ | |
1005 */ | |
1006 | |
1007 /** @brief Macro to configure the I2S clock source (I2SCLK). | |
1008 * @note This function must be called before enabling the I2S APB clock. | |
1009 * @param __SOURCE__: specifies the I2S clock source. | |
1010 * This parameter can be one of the following values: | |
1011 * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source. | |
1012 * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin | |
1013 * used as I2S clock source. | |
1014 */ | |
1015 #define __HAL_RCC_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_CFGR_I2SSRC_BB = (__SOURCE__)) | |
1016 | |
1017 /** @brief Macros to enable or disable the PLLI2S. | |
1018 * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. | |
1019 */ | |
1020 #define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE) | |
1021 #define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE) | |
1022 | |
1023 /** @brief Macro to configure the PLLI2S clock multiplication and division factors . | |
1024 * @note This macro must be used only when the PLLI2S is disabled. | |
1025 * @note PLLI2S clock source is common with the main PLL (configured in | |
1026 * HAL_RCC_ClockConfig() API). | |
1027 * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock | |
1028 * This parameter must be a number between Min_Data = 192 and Max_Data = 432. | |
1029 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO | |
1030 * output frequency is between Min_Data = 192 and Max_Data = 432 MHz. | |
1031 * @param __PLLI2SR__: specifies the division factor for I2S clock | |
1032 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. | |
1033 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz | |
1034 * on the I2S clock frequency. | |
1035 */ | |
1036 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) | ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))) | |
1037 /** | |
1038 * @} | |
1039 */ | |
1040 | |
1041 /** @defgroup RCC_Get_Clock_source Get Clock source | |
1042 * @{ | |
1043 */ | |
1044 | |
1045 /** @brief Macro to get the clock source used as system clock. | |
1046 * @retval The clock source used as system clock. The returned value can be one | |
1047 * of the following: | |
1048 * - RCC_CFGR_SWS_HSI: HSI used as system clock. | |
1049 * - RCC_CFGR_SWS_HSE: HSE used as system clock. | |
1050 * - RCC_CFGR_SWS_PLL: PLL used as system clock. | |
1051 */ | |
1052 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS)) | |
1053 | |
1054 /** @brief Macro to get the oscillator used as PLL clock source. | |
1055 * @retval The oscillator used as PLL clock source. The returned value can be one | |
1056 * of the following: | |
1057 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. | |
1058 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. | |
1059 */ | |
1060 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC)) | |
1061 /** | |
1062 * @} | |
1063 */ | |
1064 | |
1065 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management | |
1066 * @brief macros to manage the specified RCC Flags and interrupts. | |
1067 * @{ | |
1068 */ | |
1069 | |
1070 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable | |
1071 * the selected interrupts). | |
1072 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. | |
1073 * This parameter can be any combination of the following values: | |
1074 * @arg RCC_IT_LSIRDY: LSI ready interrupt. | |
1075 * @arg RCC_IT_LSERDY: LSE ready interrupt. | |
1076 * @arg RCC_IT_HSIRDY: HSI ready interrupt. | |
1077 * @arg RCC_IT_HSERDY: HSE ready interrupt. | |
1078 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. | |
1079 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. | |
1080 */ | |
1081 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) | |
1082 | |
1083 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable | |
1084 * the selected interrupts). | |
1085 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled. | |
1086 * This parameter can be any combination of the following values: | |
1087 * @arg RCC_IT_LSIRDY: LSI ready interrupt. | |
1088 * @arg RCC_IT_LSERDY: LSE ready interrupt. | |
1089 * @arg RCC_IT_HSIRDY: HSI ready interrupt. | |
1090 * @arg RCC_IT_HSERDY: HSE ready interrupt. | |
1091 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. | |
1092 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. | |
1093 */ | |
1094 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__)) | |
1095 | |
1096 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] | |
1097 * bits to clear the selected interrupt pending bits. | |
1098 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. | |
1099 * This parameter can be any combination of the following values: | |
1100 * @arg RCC_IT_LSIRDY: LSI ready interrupt. | |
1101 * @arg RCC_IT_LSERDY: LSE ready interrupt. | |
1102 * @arg RCC_IT_HSIRDY: HSI ready interrupt. | |
1103 * @arg RCC_IT_HSERDY: HSE ready interrupt. | |
1104 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. | |
1105 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. | |
1106 * @arg RCC_IT_CSS: Clock Security System interrupt | |
1107 */ | |
1108 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) | |
1109 | |
1110 /** @brief Check the RCC's interrupt has occurred or not. | |
1111 * @param __INTERRUPT__: specifies the RCC interrupt source to check. | |
1112 * This parameter can be one of the following values: | |
1113 * @arg RCC_IT_LSIRDY: LSI ready interrupt. | |
1114 * @arg RCC_IT_LSERDY: LSE ready interrupt. | |
1115 * @arg RCC_IT_HSIRDY: HSI ready interrupt. | |
1116 * @arg RCC_IT_HSERDY: HSE ready interrupt. | |
1117 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. | |
1118 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. | |
1119 * @arg RCC_IT_CSS: Clock Security System interrupt | |
1120 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). | |
1121 */ | |
1122 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) | |
1123 | |
1124 /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, | |
1125 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. | |
1126 */ | |
1127 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) | |
1128 | |
1129 /** @brief Check RCC flag is set or not. | |
1130 * @param __FLAG__: specifies the flag to check. | |
1131 * This parameter can be one of the following values: | |
1132 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready. | |
1133 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready. | |
1134 * @arg RCC_FLAG_PLLRDY: Main PLL clock ready. | |
1135 * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready. | |
1136 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready. | |
1137 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready. | |
1138 * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset. | |
1139 * @arg RCC_FLAG_PINRST: Pin reset. | |
1140 * @arg RCC_FLAG_PORRST: POR/PDR reset. | |
1141 * @arg RCC_FLAG_SFTRST: Software reset. | |
1142 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset. | |
1143 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset. | |
1144 * @arg RCC_FLAG_LPWRRST: Low Power reset. | |
1145 * @retval The new state of __FLAG__ (TRUE or FALSE). | |
1146 */ | |
1147 #define RCC_FLAG_MASK ((uint8_t)0x1F) | |
1148 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0) | |
1149 | |
1150 /** | |
1151 * @} | |
1152 */ | |
1153 | |
1154 /** | |
1155 * @} | |
1156 */ | |
1157 | |
1158 /* Include RCC HAL Extension module */ | |
1159 #include "stm32f4xx_hal_rcc_ex.h" | |
1160 | |
1161 /* Exported functions --------------------------------------------------------*/ | |
1162 /** @addtogroup RCC_Exported_Functions | |
1163 * @{ | |
1164 */ | |
1165 | |
1166 /** @addtogroup RCC_Exported_Functions_Group1 | |
1167 * @{ | |
1168 */ | |
1169 /* Initialization and de-initialization functions ******************************/ | |
1170 void HAL_RCC_DeInit(void); | |
1171 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); | |
1172 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); | |
1173 /** | |
1174 * @} | |
1175 */ | |
1176 | |
1177 /** @addtogroup RCC_Exported_Functions_Group2 | |
1178 * @{ | |
1179 */ | |
1180 /* Peripheral Control functions ************************************************/ | |
1181 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); | |
1182 void HAL_RCC_EnableCSS(void); | |
1183 void HAL_RCC_DisableCSS(void); | |
1184 uint32_t HAL_RCC_GetSysClockFreq(void); | |
1185 uint32_t HAL_RCC_GetHCLKFreq(void); | |
1186 uint32_t HAL_RCC_GetPCLK1Freq(void); | |
1187 uint32_t HAL_RCC_GetPCLK2Freq(void); | |
1188 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); | |
1189 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); | |
1190 | |
1191 /* CSS NMI IRQ handler */ | |
1192 void HAL_RCC_NMI_IRQHandler(void); | |
1193 | |
1194 /* User Callbacks in non blocking mode (IT mode) */ | |
1195 void HAL_RCC_CSSCallback(void); | |
1196 | |
1197 /** | |
1198 * @} | |
1199 */ | |
1200 | |
1201 /** | |
1202 * @} | |
1203 */ | |
1204 | |
1205 /* Private types -------------------------------------------------------------*/ | |
1206 /* Private variables ---------------------------------------------------------*/ | |
1207 /* Private constants ---------------------------------------------------------*/ | |
1208 /** @defgroup RCC_Private_Constants RCC Private Constants | |
1209 * @{ | |
1210 */ | |
1211 | |
1212 /** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion | |
1213 * @brief RCC registers bit address in the alias region | |
1214 * @{ | |
1215 */ | |
1216 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE) | |
1217 /* --- CR Register ---*/ | |
1218 /* Alias word address of HSION bit */ | |
1219 #define RCC_CR_OFFSET (RCC_OFFSET + 0x00) | |
1220 #define RCC_HSION_BIT_NUMBER 0x00 | |
1221 #define RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_HSION_BIT_NUMBER * 4)) | |
1222 /* Alias word address of CSSON bit */ | |
1223 #define RCC_CSSON_BIT_NUMBER 0x13 | |
1224 #define RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_CSSON_BIT_NUMBER * 4)) | |
1225 /* Alias word address of PLLON bit */ | |
1226 #define RCC_PLLON_BIT_NUMBER 0x18 | |
1227 #define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLON_BIT_NUMBER * 4)) | |
1228 /* Alias word address of PLLI2SON bit */ | |
1229 #define RCC_PLLI2SON_BIT_NUMBER 0x1A | |
1230 #define RCC_CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLI2SON_BIT_NUMBER * 4)) | |
1231 | |
1232 /* --- CFGR Register ---*/ | |
1233 /* Alias word address of I2SSRC bit */ | |
1234 #define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08) | |
1235 #define RCC_I2SSRC_BIT_NUMBER 0x17 | |
1236 #define RCC_CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_I2SSRC_BIT_NUMBER * 4)) | |
1237 | |
1238 /* --- BDCR Register ---*/ | |
1239 /* Alias word address of RTCEN bit */ | |
1240 #define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70) | |
1241 #define RCC_RTCEN_BIT_NUMBER 0x0F | |
1242 #define RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RCC_RTCEN_BIT_NUMBER * 4)) | |
1243 /* Alias word address of BDRST bit */ | |
1244 #define RCC_BDRST_BIT_NUMBER 0x10 | |
1245 #define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RCC_BDRST_BIT_NUMBER * 4)) | |
1246 | |
1247 /* --- CSR Register ---*/ | |
1248 /* Alias word address of LSION bit */ | |
1249 #define RCC_CSR_OFFSET (RCC_OFFSET + 0x74) | |
1250 #define RCC_LSION_BIT_NUMBER 0x00 | |
1251 #define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32) + (RCC_LSION_BIT_NUMBER * 4)) | |
1252 | |
1253 /* CR register byte 3 (Bits[23:16]) base address */ | |
1254 #define RCC_CR_BYTE2_ADDRESS ((uint32_t)0x40023802) | |
1255 | |
1256 /* CIR register byte 2 (Bits[15:8]) base address */ | |
1257 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01)) | |
1258 | |
1259 /* CIR register byte 3 (Bits[23:16]) base address */ | |
1260 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02)) | |
1261 | |
1262 /* BDCR register base address */ | |
1263 #define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET) | |
1264 | |
1265 #define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) | |
1266 #define RCC_LSE_TIMEOUT_VALUE ((uint32_t)5000) | |
1267 /** | |
1268 * @} | |
1269 */ | |
1270 | |
1271 /** | |
1272 * @} | |
1273 */ | |
1274 | |
1275 /* Private macros ------------------------------------------------------------*/ | |
1276 /** @addtogroup RCC_Private_Macros RCC Private Macros | |
1277 * @{ | |
1278 */ | |
1279 | |
1280 /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters | |
1281 * @{ | |
1282 */ | |
1283 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15) | |
1284 | |
1285 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ | |
1286 ((HSE) == RCC_HSE_BYPASS)) | |
1287 | |
1288 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ | |
1289 ((LSE) == RCC_LSE_BYPASS)) | |
1290 | |
1291 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON)) | |
1292 | |
1293 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON)) | |
1294 | |
1295 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON)) | |
1296 | |
1297 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ | |
1298 ((SOURCE) == RCC_PLLSOURCE_HSE)) | |
1299 | |
1300 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ | |
1301 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ | |
1302 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK)) | |
1303 #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63) | |
1304 | |
1305 #define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) | |
1306 | |
1307 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8)) | |
1308 | |
1309 #define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15)) | |
1310 | |
1311 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) | |
1312 | |
1313 #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) | |
1314 | |
1315 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \ | |
1316 ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \ | |
1317 ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \ | |
1318 ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \ | |
1319 ((HCLK) == RCC_SYSCLK_DIV512)) | |
1320 | |
1321 #define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15)) | |
1322 | |
1323 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \ | |
1324 ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \ | |
1325 ((PCLK) == RCC_HCLK_DIV16)) | |
1326 | |
1327 #define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2)) | |
1328 | |
1329 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ | |
1330 ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK)) | |
1331 | |
1332 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \ | |
1333 ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)) | |
1334 | |
1335 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ | |
1336 ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \ | |
1337 ((DIV) == RCC_MCODIV_5)) | |
1338 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) | |
1339 | |
1340 /** | |
1341 * @} | |
1342 */ | |
1343 | |
1344 /** | |
1345 * @} | |
1346 */ | |
1347 | |
1348 /** | |
1349 * @} | |
1350 */ | |
1351 | |
1352 /** | |
1353 * @} | |
1354 */ | |
1355 | |
1356 #ifdef __cplusplus | |
1357 } | |
1358 #endif | |
1359 | |
1360 #endif /* __STM32F4xx_HAL_RCC_H */ | |
1361 | |
1362 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |