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comparison Common/Drivers/STM32F4xx_HAL_DRIVER_v120/Inc/stm32f4xx_hal_eth.h @ 38:5f11787b4f42

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author heinrichsweikamp
date Sat, 28 Apr 2018 11:52:34 +0200
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37:ccc45c0e1ea2 38:5f11787b4f42
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_hal_eth.h
4 * @author MCD Application Team
5 * @version V1.2.0
6 * @date 26-December-2014
7 * @brief Header file of ETH HAL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F4xx_HAL_ETH_H
40 #define __STM32F4xx_HAL_ETH_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 #if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
47 /* Includes ------------------------------------------------------------------*/
48 #include "stm32f4xx_hal_def.h"
49
50 /** @addtogroup STM32F4xx_HAL_Driver
51 * @{
52 */
53
54 /** @addtogroup ETH
55 * @{
56 */
57
58 /** @addtogroup ETH_Private_Macros
59 * @{
60 */
61 #define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
62 #define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \
63 ((CMD) == ETH_AUTONEGOTIATION_DISABLE))
64 #define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
65 ((SPEED) == ETH_SPEED_100M))
66 #define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
67 ((MODE) == ETH_MODE_HALFDUPLEX))
68 #define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
69 ((MODE) == ETH_MODE_HALFDUPLEX))
70 #define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
71 ((MODE) == ETH_RXINTERRUPT_MODE))
72 #define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
73 ((MODE) == ETH_RXINTERRUPT_MODE))
74 #define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
75 ((MODE) == ETH_RXINTERRUPT_MODE))
76 #define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \
77 ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
78 #define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \
79 ((MODE) == ETH_MEDIA_INTERFACE_RMII))
80 #define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \
81 ((CMD) == ETH_WATCHDOG_DISABLE))
82 #define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \
83 ((CMD) == ETH_JABBER_DISABLE))
84 #define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \
85 ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \
86 ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \
87 ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \
88 ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \
89 ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \
90 ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \
91 ((GAP) == ETH_INTERFRAMEGAP_40BIT))
92 #define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \
93 ((CMD) == ETH_CARRIERSENCE_DISABLE))
94 #define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \
95 ((CMD) == ETH_RECEIVEOWN_DISABLE))
96 #define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \
97 ((CMD) == ETH_LOOPBACKMODE_DISABLE))
98 #define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \
99 ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
100 #define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \
101 ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
102 #define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \
103 ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
104 #define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \
105 ((LIMIT) == ETH_BACKOFFLIMIT_8) || \
106 ((LIMIT) == ETH_BACKOFFLIMIT_4) || \
107 ((LIMIT) == ETH_BACKOFFLIMIT_1))
108 #define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \
109 ((CMD) == ETH_DEFFERRALCHECK_DISABLE))
110 #define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \
111 ((CMD) == ETH_RECEIVEAll_DISABLE))
112 #define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \
113 ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \
114 ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
115 #define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \
116 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \
117 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
118 #define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \
119 ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
120 #define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \
121 ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
122 #define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \
123 ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))
124 #define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \
125 ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \
126 ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \
127 ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
128 #define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \
129 ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \
130 ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
131 #define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
132 #define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \
133 ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
134 #define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \
135 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \
136 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \
137 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
138 #define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \
139 ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
140 #define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \
141 ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
142 #define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \
143 ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
144 #define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \
145 ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
146 #define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
147 #define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \
148 ((ADDRESS) == ETH_MAC_ADDRESS1) || \
149 ((ADDRESS) == ETH_MAC_ADDRESS2) || \
150 ((ADDRESS) == ETH_MAC_ADDRESS3))
151 #define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \
152 ((ADDRESS) == ETH_MAC_ADDRESS2) || \
153 ((ADDRESS) == ETH_MAC_ADDRESS3))
154 #define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \
155 ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
156 #define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \
157 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \
158 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \
159 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \
160 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \
161 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
162 #define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \
163 ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
164 #define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \
165 ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
166 #define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \
167 ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
168 #define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \
169 ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
170 #define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \
171 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \
172 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \
173 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \
174 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \
175 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \
176 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \
177 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
178 #define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \
179 ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
180 #define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \
181 ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
182 #define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \
183 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \
184 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \
185 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
186 #define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \
187 ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
188 #define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \
189 ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
190 #define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \
191 ((CMD) == ETH_FIXEDBURST_DISABLE))
192 #define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \
193 ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \
194 ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \
195 ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \
196 ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \
197 ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \
198 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \
199 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \
200 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \
201 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \
202 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \
203 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
204 #define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \
205 ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \
206 ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \
207 ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \
208 ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \
209 ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \
210 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \
211 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \
212 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \
213 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \
214 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
215 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
216 #define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
217 #define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \
218 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \
219 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \
220 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \
221 ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
222 #define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \
223 ((FLAG) == ETH_DMATXDESC_IC) || \
224 ((FLAG) == ETH_DMATXDESC_LS) || \
225 ((FLAG) == ETH_DMATXDESC_FS) || \
226 ((FLAG) == ETH_DMATXDESC_DC) || \
227 ((FLAG) == ETH_DMATXDESC_DP) || \
228 ((FLAG) == ETH_DMATXDESC_TTSE) || \
229 ((FLAG) == ETH_DMATXDESC_TER) || \
230 ((FLAG) == ETH_DMATXDESC_TCH) || \
231 ((FLAG) == ETH_DMATXDESC_TTSS) || \
232 ((FLAG) == ETH_DMATXDESC_IHE) || \
233 ((FLAG) == ETH_DMATXDESC_ES) || \
234 ((FLAG) == ETH_DMATXDESC_JT) || \
235 ((FLAG) == ETH_DMATXDESC_FF) || \
236 ((FLAG) == ETH_DMATXDESC_PCE) || \
237 ((FLAG) == ETH_DMATXDESC_LCA) || \
238 ((FLAG) == ETH_DMATXDESC_NC) || \
239 ((FLAG) == ETH_DMATXDESC_LCO) || \
240 ((FLAG) == ETH_DMATXDESC_EC) || \
241 ((FLAG) == ETH_DMATXDESC_VF) || \
242 ((FLAG) == ETH_DMATXDESC_CC) || \
243 ((FLAG) == ETH_DMATXDESC_ED) || \
244 ((FLAG) == ETH_DMATXDESC_UF) || \
245 ((FLAG) == ETH_DMATXDESC_DB))
246 #define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \
247 ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
248 #define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \
249 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \
250 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \
251 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
252 #define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
253 #define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \
254 ((FLAG) == ETH_DMARXDESC_AFM) || \
255 ((FLAG) == ETH_DMARXDESC_ES) || \
256 ((FLAG) == ETH_DMARXDESC_DE) || \
257 ((FLAG) == ETH_DMARXDESC_SAF) || \
258 ((FLAG) == ETH_DMARXDESC_LE) || \
259 ((FLAG) == ETH_DMARXDESC_OE) || \
260 ((FLAG) == ETH_DMARXDESC_VLAN) || \
261 ((FLAG) == ETH_DMARXDESC_FS) || \
262 ((FLAG) == ETH_DMARXDESC_LS) || \
263 ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \
264 ((FLAG) == ETH_DMARXDESC_LC) || \
265 ((FLAG) == ETH_DMARXDESC_FT) || \
266 ((FLAG) == ETH_DMARXDESC_RWT) || \
267 ((FLAG) == ETH_DMARXDESC_RE) || \
268 ((FLAG) == ETH_DMARXDESC_DBE) || \
269 ((FLAG) == ETH_DMARXDESC_CE) || \
270 ((FLAG) == ETH_DMARXDESC_MAMPCE))
271 #define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \
272 ((BUFFER) == ETH_DMARXDESC_BUFFER2))
273 #define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
274 ((FLAG) == ETH_PMT_FLAG_MPR))
275 #define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00))
276 #define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
277 ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \
278 ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \
279 ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
280 ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
281 ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
282 ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
283 ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
284 ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
285 ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
286 ((FLAG) == ETH_DMA_FLAG_T))
287 #define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF1) == 0x00) && ((IT) != 0x00))
288 #define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
289 ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
290 ((IT) == ETH_MAC_IT_PMT))
291 #define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
292 ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
293 ((FLAG) == ETH_MAC_FLAG_PMT))
294 #define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00))
295 #define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
296 ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
297 ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
298 ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
299 ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
300 ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
301 ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
302 ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
303 ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
304 #define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \
305 ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
306 #define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \
307 ((IT) != 0x00))
308 #define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
309 ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
310 ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
311 #define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \
312 ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
313
314
315 /**
316 * @}
317 */
318
319 /** @addtogroup ETH_Private_Defines
320 * @{
321 */
322 /* Delay to wait when writing to some Ethernet registers */
323 #define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)
324
325 /* ETHERNET Errors */
326 #define ETH_SUCCESS ((uint32_t)0)
327 #define ETH_ERROR ((uint32_t)1)
328
329 /* ETHERNET DMA Tx descriptors Collision Count Shift */
330 #define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3)
331
332 /* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
333 #define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
334
335 /* ETHERNET DMA Rx descriptors Frame Length Shift */
336 #define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16)
337
338 /* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
339 #define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
340
341 /* ETHERNET DMA Rx descriptors Frame length Shift */
342 #define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16)
343
344 /* ETHERNET MAC address offsets */
345 #define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40) /* ETHERNET MAC address high offset */
346 #define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44) /* ETHERNET MAC address low offset */
347
348 /* ETHERNET MACMIIAR register Mask */
349 #define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3)
350
351 /* ETHERNET MACCR register Mask */
352 #define ETH_MACCR_CLEAR_MASK ((uint32_t)0xFF20810F)
353
354 /* ETHERNET MACFCR register Mask */
355 #define ETH_MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41)
356
357 /* ETHERNET DMAOMR register Mask */
358 #define ETH_DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23)
359
360 /* ETHERNET Remote Wake-up frame register length */
361 #define ETH_WAKEUP_REGISTER_LENGTH 8
362
363 /* ETHERNET Missed frames counter Shift */
364 #define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17
365 /**
366 * @}
367 */
368
369 /* Exported types ------------------------------------------------------------*/
370 /** @defgroup ETH_Exported_Types ETH Exported Types
371 * @{
372 */
373
374 /**
375 * @brief HAL State structures definition
376 */
377 typedef enum
378 {
379 HAL_ETH_STATE_RESET = 0x00, /*!< Peripheral not yet Initialized or disabled */
380 HAL_ETH_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
381 HAL_ETH_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
382 HAL_ETH_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
383 HAL_ETH_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
384 HAL_ETH_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
385 HAL_ETH_STATE_BUSY_WR = 0x42, /*!< Write process is ongoing */
386 HAL_ETH_STATE_BUSY_RD = 0x82, /*!< Read process is ongoing */
387 HAL_ETH_STATE_TIMEOUT = 0x03, /*!< Timeout state */
388 HAL_ETH_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
389 }HAL_ETH_StateTypeDef;
390
391 /**
392 * @brief ETH Init Structure definition
393 */
394
395 typedef struct
396 {
397 uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
398 The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
399 and the mode (half/full-duplex).
400 This parameter can be a value of @ref ETH_AutoNegotiation */
401
402 uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
403 This parameter can be a value of @ref ETH_Speed */
404
405 uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
406 This parameter can be a value of @ref ETH_Duplex_Mode */
407
408 uint16_t PhyAddress; /*!< Ethernet PHY address.
409 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
410
411 uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
412
413 uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
414 This parameter can be a value of @ref ETH_Rx_Mode */
415
416 uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
417 This parameter can be a value of @ref ETH_Checksum_Mode */
418
419 uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface.
420 This parameter can be a value of @ref ETH_Media_Interface */
421
422 } ETH_InitTypeDef;
423
424
425 /**
426 * @brief ETH MAC Configuration Structure definition
427 */
428
429 typedef struct
430 {
431 uint32_t Watchdog; /*!< Selects or not the Watchdog timer
432 When enabled, the MAC allows no more then 2048 bytes to be received.
433 When disabled, the MAC can receive up to 16384 bytes.
434 This parameter can be a value of @ref ETH_Watchdog */
435
436 uint32_t Jabber; /*!< Selects or not Jabber timer
437 When enabled, the MAC allows no more then 2048 bytes to be sent.
438 When disabled, the MAC can send up to 16384 bytes.
439 This parameter can be a value of @ref ETH_Jabber */
440
441 uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.
442 This parameter can be a value of @ref ETH_Inter_Frame_Gap */
443
444 uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.
445 This parameter can be a value of @ref ETH_Carrier_Sense */
446
447 uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,
448 ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
449 in Half-Duplex mode.
450 This parameter can be a value of @ref ETH_Receive_Own */
451
452 uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.
453 This parameter can be a value of @ref ETH_Loop_Back_Mode */
454
455 uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
456 This parameter can be a value of @ref ETH_Checksum_Offload */
457
458 uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
459 when a collision occurs (Half-Duplex mode).
460 This parameter can be a value of @ref ETH_Retry_Transmission */
461
462 uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
463 This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
464
465 uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
466 This parameter can be a value of @ref ETH_Back_Off_Limit */
467
468 uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).
469 This parameter can be a value of @ref ETH_Deferral_Check */
470
471 uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
472 This parameter can be a value of @ref ETH_Receive_All */
473
474 uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
475 This parameter can be a value of @ref ETH_Source_Addr_Filter */
476
477 uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
478 This parameter can be a value of @ref ETH_Pass_Control_Frames */
479
480 uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
481 This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
482
483 uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.
484 This parameter can be a value of @ref ETH_Destination_Addr_Filter */
485
486 uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
487 This parameter can be a value of @ref ETH_Promiscuous_Mode */
488
489 uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
490 This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
491
492 uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
493 This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
494
495 uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
496 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
497
498 uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
499 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
500
501 uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
502 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
503
504 uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
505 This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
506
507 uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
508 automatic retransmission of PAUSE Frame.
509 This parameter can be a value of @ref ETH_Pause_Low_Threshold */
510
511 uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
512 unicast address and unique multicast address).
513 This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
514
515 uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
516 disable its transmitter for a specified time (Pause Time)
517 This parameter can be a value of @ref ETH_Receive_Flow_Control */
518
519 uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
520 or the MAC back-pressure operation (Half-Duplex mode)
521 This parameter can be a value of @ref ETH_Transmit_Flow_Control */
522
523 uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
524 comparison and filtering.
525 This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
526
527 uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */
528
529 } ETH_MACInitTypeDef;
530
531
532 /**
533 * @brief ETH DMA Configuration Structure definition
534 */
535
536 typedef struct
537 {
538 uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
539 This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
540
541 uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.
542 This parameter can be a value of @ref ETH_Receive_Store_Forward */
543
544 uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.
545 This parameter can be a value of @ref ETH_Flush_Received_Frame */
546
547 uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.
548 This parameter can be a value of @ref ETH_Transmit_Store_Forward */
549
550 uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.
551 This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
552
553 uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.
554 This parameter can be a value of @ref ETH_Forward_Error_Frames */
555
556 uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
557 and length less than 64 bytes) including pad-bytes and CRC)
558 This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
559
560 uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.
561 This parameter can be a value of @ref ETH_Receive_Threshold_Control */
562
563 uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
564 frame of Transmit data even before obtaining the status for the first frame.
565 This parameter can be a value of @ref ETH_Second_Frame_Operate */
566
567 uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.
568 This parameter can be a value of @ref ETH_Address_Aligned_Beats */
569
570 uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
571 This parameter can be a value of @ref ETH_Fixed_Burst */
572
573 uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
574 This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
575
576 uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
577 This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
578
579 uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format.
580 This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */
581
582 uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
583 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
584
585 uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
586 This parameter can be a value of @ref ETH_DMA_Arbitration */
587 } ETH_DMAInitTypeDef;
588
589
590 /**
591 * @brief ETH DMA Descriptors data structure definition
592 */
593
594 typedef struct
595 {
596 __IO uint32_t Status; /*!< Status */
597
598 uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */
599
600 uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
601
602 uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
603
604 /*!< Enhanced ETHERNET DMA PTP Descriptors */
605 uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */
606
607 uint32_t Reserved1; /*!< Reserved */
608
609 uint32_t TimeStampLow; /*!< Time Stamp Low value for transmit and receive */
610
611 uint32_t TimeStampHigh; /*!< Time Stamp High value for transmit and receive */
612
613 } ETH_DMADescTypeDef;
614
615
616 /**
617 * @brief Received Frame Informations structure definition
618 */
619 typedef struct
620 {
621 ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */
622
623 ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */
624
625 uint32_t SegCount; /*!< Segment count */
626
627 uint32_t length; /*!< Frame length */
628
629 uint32_t buffer; /*!< Frame buffer */
630
631 } ETH_DMARxFrameInfos;
632
633
634 /**
635 * @brief ETH Handle Structure definition
636 */
637
638 typedef struct
639 {
640 ETH_TypeDef *Instance; /*!< Register base address */
641
642 ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */
643
644 uint32_t LinkStatus; /*!< Ethernet link status */
645
646 ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */
647
648 ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */
649
650 ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */
651
652 __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */
653
654 HAL_LockTypeDef Lock; /*!< ETH Lock */
655
656 } ETH_HandleTypeDef;
657
658 /**
659 * @}
660 */
661
662 /* Exported constants --------------------------------------------------------*/
663 /** @defgroup ETH_Exported_Constants ETH Exported Constants
664 * @{
665 */
666
667 /** @defgroup ETH_Buffers_setting ETH Buffers setting
668 * @{
669 */
670 #define ETH_MAX_PACKET_SIZE ((uint32_t)1524) /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */
671 #define ETH_HEADER ((uint32_t)14) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
672 #define ETH_CRC ((uint32_t)4) /*!< Ethernet CRC */
673 #define ETH_EXTRA ((uint32_t)2) /*!< Extra bytes in some cases */
674 #define ETH_VLAN_TAG ((uint32_t)4) /*!< optional 802.1q VLAN Tag */
675 #define ETH_MIN_ETH_PAYLOAD ((uint32_t)46) /*!< Minimum Ethernet payload size */
676 #define ETH_MAX_ETH_PAYLOAD ((uint32_t)1500) /*!< Maximum Ethernet payload size */
677 #define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000) /*!< Jumbo frame payload size */
678
679 /* Ethernet driver receive buffers are organized in a chained linked-list, when
680 an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
681 to the driver receive buffers memory.
682
683 Depending on the size of the received ethernet packet and the size of
684 each ethernet driver receive buffer, the received packet can take one or more
685 ethernet driver receive buffer.
686
687 In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
688 and the total count of the driver receive buffers ETH_RXBUFNB.
689
690 The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
691 example, they can be reconfigured in the application layer to fit the application
692 needs */
693
694 /* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
695 packet */
696 #ifndef ETH_RX_BUF_SIZE
697 #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
698 #endif
699
700 /* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
701 #ifndef ETH_RXBUFNB
702 #define ETH_RXBUFNB ((uint32_t)5 /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
703 #endif
704
705
706 /* Ethernet driver transmit buffers are organized in a chained linked-list, when
707 an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
708 driver transmit buffers memory to the TxFIFO.
709
710 Depending on the size of the Ethernet packet to be transmitted and the size of
711 each ethernet driver transmit buffer, the packet to be transmitted can take
712 one or more ethernet driver transmit buffer.
713
714 In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
715 and the total count of the driver transmit buffers ETH_TXBUFNB.
716
717 The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
718 example, they can be reconfigured in the application layer to fit the application
719 needs */
720
721 /* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
722 packet */
723 #ifndef ETH_TX_BUF_SIZE
724 #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
725 #endif
726
727 /* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
728 #ifndef ETH_TXBUFNB
729 #define ETH_TXBUFNB ((uint32_t)5 /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
730 #endif
731
732 /**
733 * @}
734 */
735
736 /** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor
737 * @{
738 */
739
740 /*
741 DMA Tx Descriptor
742 -----------------------------------------------------------------------------------------------
743 TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
744 -----------------------------------------------------------------------------------------------
745 TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
746 -----------------------------------------------------------------------------------------------
747 TDES2 | Buffer1 Address [31:0] |
748 -----------------------------------------------------------------------------------------------
749 TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
750 -----------------------------------------------------------------------------------------------
751 */
752
753 /**
754 * @brief Bit definition of TDES0 register: DMA Tx descriptor status register
755 */
756 #define ETH_DMATXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */
757 #define ETH_DMATXDESC_IC ((uint32_t)0x40000000) /*!< Interrupt on Completion */
758 #define ETH_DMATXDESC_LS ((uint32_t)0x20000000) /*!< Last Segment */
759 #define ETH_DMATXDESC_FS ((uint32_t)0x10000000) /*!< First Segment */
760 #define ETH_DMATXDESC_DC ((uint32_t)0x08000000) /*!< Disable CRC */
761 #define ETH_DMATXDESC_DP ((uint32_t)0x04000000) /*!< Disable Padding */
762 #define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000) /*!< Transmit Time Stamp Enable */
763 #define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000) /*!< Checksum Insertion Control: 4 cases */
764 #define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000) /*!< Do Nothing: Checksum Engine is bypassed */
765 #define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000) /*!< IPV4 header Checksum Insertion */
766 #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
767 #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
768 #define ETH_DMATXDESC_TER ((uint32_t)0x00200000) /*!< Transmit End of Ring */
769 #define ETH_DMATXDESC_TCH ((uint32_t)0x00100000) /*!< Second Address Chained */
770 #define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000) /*!< Tx Time Stamp Status */
771 #define ETH_DMATXDESC_IHE ((uint32_t)0x00010000) /*!< IP Header Error */
772 #define ETH_DMATXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
773 #define ETH_DMATXDESC_JT ((uint32_t)0x00004000) /*!< Jabber Timeout */
774 #define ETH_DMATXDESC_FF ((uint32_t)0x00002000) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
775 #define ETH_DMATXDESC_PCE ((uint32_t)0x00001000) /*!< Payload Checksum Error */
776 #define ETH_DMATXDESC_LCA ((uint32_t)0x00000800) /*!< Loss of Carrier: carrier lost during transmission */
777 #define ETH_DMATXDESC_NC ((uint32_t)0x00000400) /*!< No Carrier: no carrier signal from the transceiver */
778 #define ETH_DMATXDESC_LCO ((uint32_t)0x00000200) /*!< Late Collision: transmission aborted due to collision */
779 #define ETH_DMATXDESC_EC ((uint32_t)0x00000100) /*!< Excessive Collision: transmission aborted after 16 collisions */
780 #define ETH_DMATXDESC_VF ((uint32_t)0x00000080) /*!< VLAN Frame */
781 #define ETH_DMATXDESC_CC ((uint32_t)0x00000078) /*!< Collision Count */
782 #define ETH_DMATXDESC_ED ((uint32_t)0x00000004) /*!< Excessive Deferral */
783 #define ETH_DMATXDESC_UF ((uint32_t)0x00000002) /*!< Underflow Error: late data arrival from the memory */
784 #define ETH_DMATXDESC_DB ((uint32_t)0x00000001) /*!< Deferred Bit */
785
786 /**
787 * @brief Bit definition of TDES1 register
788 */
789 #define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000) /*!< Transmit Buffer2 Size */
790 #define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFF) /*!< Transmit Buffer1 Size */
791
792 /**
793 * @brief Bit definition of TDES2 register
794 */
795 #define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
796
797 /**
798 * @brief Bit definition of TDES3 register
799 */
800 #define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
801
802 /*---------------------------------------------------------------------------------------------
803 TDES6 | Transmit Time Stamp Low [31:0] |
804 -----------------------------------------------------------------------------------------------
805 TDES7 | Transmit Time Stamp High [31:0] |
806 ----------------------------------------------------------------------------------------------*/
807
808 /* Bit definition of TDES6 register */
809 #define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp Low */
810
811 /* Bit definition of TDES7 register */
812 #define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp High */
813
814 /**
815 * @}
816 */
817 /** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
818 * @{
819 */
820
821 /*
822 DMA Rx Descriptor
823 --------------------------------------------------------------------------------------------------------------------
824 RDES0 | OWN(31) | Status [30:0] |
825 ---------------------------------------------------------------------------------------------------------------------
826 RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
827 ---------------------------------------------------------------------------------------------------------------------
828 RDES2 | Buffer1 Address [31:0] |
829 ---------------------------------------------------------------------------------------------------------------------
830 RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
831 ---------------------------------------------------------------------------------------------------------------------
832 */
833
834 /**
835 * @brief Bit definition of RDES0 register: DMA Rx descriptor status register
836 */
837 #define ETH_DMARXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */
838 #define ETH_DMARXDESC_AFM ((uint32_t)0x40000000) /*!< DA Filter Fail for the rx frame */
839 #define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000) /*!< Receive descriptor frame length */
840 #define ETH_DMARXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
841 #define ETH_DMARXDESC_DE ((uint32_t)0x00004000) /*!< Descriptor error: no more descriptors for receive frame */
842 #define ETH_DMARXDESC_SAF ((uint32_t)0x00002000) /*!< SA Filter Fail for the received frame */
843 #define ETH_DMARXDESC_LE ((uint32_t)0x00001000) /*!< Frame size not matching with length field */
844 #define ETH_DMARXDESC_OE ((uint32_t)0x00000800) /*!< Overflow Error: Frame was damaged due to buffer overflow */
845 #define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400) /*!< VLAN Tag: received frame is a VLAN frame */
846 #define ETH_DMARXDESC_FS ((uint32_t)0x00000200) /*!< First descriptor of the frame */
847 #define ETH_DMARXDESC_LS ((uint32_t)0x00000100) /*!< Last descriptor of the frame */
848 #define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */
849 #define ETH_DMARXDESC_LC ((uint32_t)0x00000040) /*!< Late collision occurred during reception */
850 #define ETH_DMARXDESC_FT ((uint32_t)0x00000020) /*!< Frame type - Ethernet, otherwise 802.3 */
851 #define ETH_DMARXDESC_RWT ((uint32_t)0x00000010) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */
852 #define ETH_DMARXDESC_RE ((uint32_t)0x00000008) /*!< Receive error: error reported by MII interface */
853 #define ETH_DMARXDESC_DBE ((uint32_t)0x00000004) /*!< Dribble bit error: frame contains non int multiple of 8 bits */
854 #define ETH_DMARXDESC_CE ((uint32_t)0x00000002) /*!< CRC error */
855 #define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
856
857 /**
858 * @brief Bit definition of RDES1 register
859 */
860 #define ETH_DMARXDESC_DIC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */
861 #define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000) /*!< Receive Buffer2 Size */
862 #define ETH_DMARXDESC_RER ((uint32_t)0x00008000) /*!< Receive End of Ring */
863 #define ETH_DMARXDESC_RCH ((uint32_t)0x00004000) /*!< Second Address Chained */
864 #define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFF) /*!< Receive Buffer1 Size */
865
866 /**
867 * @brief Bit definition of RDES2 register
868 */
869 #define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
870
871 /**
872 * @brief Bit definition of RDES3 register
873 */
874 #define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
875
876 /*---------------------------------------------------------------------------------------------------------------------
877 RDES4 | Reserved[31:15] | Extended Status [14:0] |
878 ---------------------------------------------------------------------------------------------------------------------
879 RDES5 | Reserved[31:0] |
880 ---------------------------------------------------------------------------------------------------------------------
881 RDES6 | Receive Time Stamp Low [31:0] |
882 ---------------------------------------------------------------------------------------------------------------------
883 RDES7 | Receive Time Stamp High [31:0] |
884 --------------------------------------------------------------------------------------------------------------------*/
885
886 /* Bit definition of RDES4 register */
887 #define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000) /* PTP Version */
888 #define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000) /* PTP Frame Type */
889 #define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00) /* PTP Message Type */
890 #define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100) /* SYNC message (all clock types) */
891 #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200) /* FollowUp message (all clock types) */
892 #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300) /* DelayReq message (all clock types) */
893 #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400) /* DelayResp message (all clock types) */
894 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
895 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
896 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
897 #define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080) /* IPv6 Packet Received */
898 #define ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040) /* IPv4 Packet Received */
899 #define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020) /* IP Checksum Bypassed */
900 #define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010) /* IP Payload Error */
901 #define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008) /* IP Header Error */
902 #define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007) /* IP Payload Type */
903 #define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001) /* UDP payload encapsulated in the IP datagram */
904 #define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002) /* TCP payload encapsulated in the IP datagram */
905 #define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003) /* ICMP payload encapsulated in the IP datagram */
906
907 /* Bit definition of RDES6 register */
908 #define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp Low */
909
910 /* Bit definition of RDES7 register */
911 #define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp High */
912 /**
913 * @}
914 */
915 /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
916 * @{
917 */
918 #define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001)
919 #define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000)
920
921 /**
922 * @}
923 */
924 /** @defgroup ETH_Speed ETH Speed
925 * @{
926 */
927 #define ETH_SPEED_10M ((uint32_t)0x00000000)
928 #define ETH_SPEED_100M ((uint32_t)0x00004000)
929
930 /**
931 * @}
932 */
933 /** @defgroup ETH_Duplex_Mode ETH Duplex Mode
934 * @{
935 */
936 #define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800)
937 #define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000)
938 /**
939 * @}
940 */
941 /** @defgroup ETH_Rx_Mode ETH Rx Mode
942 * @{
943 */
944 #define ETH_RXPOLLING_MODE ((uint32_t)0x00000000)
945 #define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001)
946 /**
947 * @}
948 */
949
950 /** @defgroup ETH_Checksum_Mode ETH Checksum Mode
951 * @{
952 */
953 #define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000)
954 #define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001)
955 /**
956 * @}
957 */
958
959 /** @defgroup ETH_Media_Interface ETH Media Interface
960 * @{
961 */
962 #define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000)
963 #define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
964 /**
965 * @}
966 */
967
968 /** @defgroup ETH_Watchdog ETH Watchdog
969 * @{
970 */
971 #define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000)
972 #define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000)
973 /**
974 * @}
975 */
976
977 /** @defgroup ETH_Jabber ETH Jabber
978 * @{
979 */
980 #define ETH_JABBER_ENABLE ((uint32_t)0x00000000)
981 #define ETH_JABBER_DISABLE ((uint32_t)0x00400000)
982 /**
983 * @}
984 */
985
986 /** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
987 * @{
988 */
989 #define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000) /*!< minimum IFG between frames during transmission is 96Bit */
990 #define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000) /*!< minimum IFG between frames during transmission is 88Bit */
991 #define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000) /*!< minimum IFG between frames during transmission is 80Bit */
992 #define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000) /*!< minimum IFG between frames during transmission is 72Bit */
993 #define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000) /*!< minimum IFG between frames during transmission is 64Bit */
994 #define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000) /*!< minimum IFG between frames during transmission is 56Bit */
995 #define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000) /*!< minimum IFG between frames during transmission is 48Bit */
996 #define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000) /*!< minimum IFG between frames during transmission is 40Bit */
997 /**
998 * @}
999 */
1000
1001 /** @defgroup ETH_Carrier_Sense ETH Carrier Sense
1002 * @{
1003 */
1004 #define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000)
1005 #define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000)
1006 /**
1007 * @}
1008 */
1009
1010 /** @defgroup ETH_Receive_Own ETH Receive Own
1011 * @{
1012 */
1013 #define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000)
1014 #define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000)
1015 /**
1016 * @}
1017 */
1018
1019 /** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
1020 * @{
1021 */
1022 #define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000)
1023 #define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000)
1024 /**
1025 * @}
1026 */
1027
1028 /** @defgroup ETH_Checksum_Offload ETH Checksum Offload
1029 * @{
1030 */
1031 #define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400)
1032 #define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000)
1033 /**
1034 * @}
1035 */
1036
1037 /** @defgroup ETH_Retry_Transmission ETH Retry Transmission
1038 * @{
1039 */
1040 #define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000)
1041 #define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200)
1042 /**
1043 * @}
1044 */
1045
1046 /** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
1047 * @{
1048 */
1049 #define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080)
1050 #define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000)
1051 /**
1052 * @}
1053 */
1054
1055 /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
1056 * @{
1057 */
1058 #define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000)
1059 #define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020)
1060 #define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040)
1061 #define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060)
1062 /**
1063 * @}
1064 */
1065
1066 /** @defgroup ETH_Deferral_Check ETH Deferral Check
1067 * @{
1068 */
1069 #define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010)
1070 #define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000)
1071 /**
1072 * @}
1073 */
1074
1075 /** @defgroup ETH_Receive_All ETH Receive All
1076 * @{
1077 */
1078 #define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000)
1079 #define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000)
1080 /**
1081 * @}
1082 */
1083
1084 /** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
1085 * @{
1086 */
1087 #define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200)
1088 #define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300)
1089 #define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000)
1090 /**
1091 * @}
1092 */
1093
1094 /** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
1095 * @{
1096 */
1097 #define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040) /*!< MAC filters all control frames from reaching the application */
1098 #define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080) /*!< MAC forwards all control frames to application even if they fail the Address Filter */
1099 #define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0) /*!< MAC forwards control frames that pass the Address Filter. */
1100 /**
1101 * @}
1102 */
1103
1104 /** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
1105 * @{
1106 */
1107 #define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000)
1108 #define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020)
1109 /**
1110 * @}
1111 */
1112
1113 /** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
1114 * @{
1115 */
1116 #define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000)
1117 #define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008)
1118 /**
1119 * @}
1120 */
1121
1122 /** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
1123 * @{
1124 */
1125 #define ETH_PROMISCUOUS_MODE_ENABLE ((uint32_t)0x00000001)
1126 #define ETH_PROMISCUOUS_MODE_DISABLE ((uint32_t)0x00000000)
1127 /**
1128 * @}
1129 */
1130
1131 /** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
1132 * @{
1133 */
1134 #define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404)
1135 #define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004)
1136 #define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
1137 #define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010)
1138 /**
1139 * @}
1140 */
1141
1142 /** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
1143 * @{
1144 */
1145 #define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402)
1146 #define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002)
1147 #define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
1148 /**
1149 * @}
1150 */
1151
1152 /** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
1153 * @{
1154 */
1155 #define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000)
1156 #define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080)
1157 /**
1158 * @}
1159 */
1160
1161 /** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
1162 * @{
1163 */
1164 #define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000) /*!< Pause time minus 4 slot times */
1165 #define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010) /*!< Pause time minus 28 slot times */
1166 #define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020) /*!< Pause time minus 144 slot times */
1167 #define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030) /*!< Pause time minus 256 slot times */
1168 /**
1169 * @}
1170 */
1171
1172 /** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
1173 * @{
1174 */
1175 #define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008)
1176 #define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000)
1177 /**
1178 * @}
1179 */
1180
1181 /** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
1182 * @{
1183 */
1184 #define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004)
1185 #define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
1186 /**
1187 * @}
1188 */
1189
1190 /** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
1191 * @{
1192 */
1193 #define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002)
1194 #define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
1195 /**
1196 * @}
1197 */
1198
1199 /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
1200 * @{
1201 */
1202 #define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000)
1203 #define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000)
1204 /**
1205 * @}
1206 */
1207
1208 /** @defgroup ETH_MAC_addresses ETH MAC addresses
1209 * @{
1210 */
1211 #define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000)
1212 #define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008)
1213 #define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010)
1214 #define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018)
1215 /**
1216 * @}
1217 */
1218
1219 /** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA
1220 * @{
1221 */
1222 #define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000)
1223 #define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008)
1224 /**
1225 * @}
1226 */
1227
1228 /** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes
1229 * @{
1230 */
1231 #define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000) /*!< Mask MAC Address high reg bits [15:8] */
1232 #define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000) /*!< Mask MAC Address high reg bits [7:0] */
1233 #define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000) /*!< Mask MAC Address low reg bits [31:24] */
1234 #define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000) /*!< Mask MAC Address low reg bits [23:16] */
1235 #define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000) /*!< Mask MAC Address low reg bits [15:8] */
1236 #define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000) /*!< Mask MAC Address low reg bits [70] */
1237 /**
1238 * @}
1239 */
1240
1241 /** @defgroup ETH_MAC_Debug_flags ETH MAC Debug flags
1242 * @{
1243 */
1244 #define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
1245 #define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
1246 #define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
1247 #define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
1248 #define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
1249 #define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
1250 #define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
1251 #define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
1252 #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
1253 #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
1254 #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
1255 #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
1256 #define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
1257 #define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
1258 #define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
1259 #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
1260 #define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
1261 #define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000060) /* Rx FIFO read controller IDLE state */
1262 #define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame data */
1263 #define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame status (or time-stamp) */
1264 #define ETH_MAC_READCONTROLLER_ FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
1265 #define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
1266 #define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
1267 #define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
1268 #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
1269 #define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
1270 #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
1271 /**
1272 * @}
1273 */
1274
1275 /** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame
1276 * @{
1277 */
1278 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000)
1279 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000)
1280 /**
1281 * @}
1282 */
1283
1284 /** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward
1285 * @{
1286 */
1287 #define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000)
1288 #define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000)
1289 /**
1290 * @}
1291 */
1292
1293 /** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame
1294 * @{
1295 */
1296 #define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000)
1297 #define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000)
1298 /**
1299 * @}
1300 */
1301
1302 /** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward
1303 * @{
1304 */
1305 #define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000)
1306 #define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000)
1307 /**
1308 * @}
1309 */
1310
1311 /** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
1312 * @{
1313 */
1314 #define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
1315 #define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
1316 #define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
1317 #define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
1318 #define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
1319 #define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
1320 #define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
1321 #define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
1322 /**
1323 * @}
1324 */
1325
1326 /** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames
1327 * @{
1328 */
1329 #define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080)
1330 #define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000)
1331 /**
1332 * @}
1333 */
1334
1335 /** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames
1336 * @{
1337 */
1338 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040)
1339 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000)
1340 /**
1341 * @}
1342 */
1343
1344 /** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
1345 * @{
1346 */
1347 #define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
1348 #define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
1349 #define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
1350 #define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
1351 /**
1352 * @}
1353 */
1354
1355 /** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate
1356 * @{
1357 */
1358 #define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004)
1359 #define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000)
1360 /**
1361 * @}
1362 */
1363
1364 /** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
1365 * @{
1366 */
1367 #define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000)
1368 #define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000)
1369 /**
1370 * @}
1371 */
1372
1373 /** @defgroup ETH_Fixed_Burst ETH Fixed Burst
1374 * @{
1375 */
1376 #define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000)
1377 #define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000)
1378 /**
1379 * @}
1380 */
1381
1382 /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
1383 * @{
1384 */
1385 #define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
1386 #define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
1387 #define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
1388 #define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
1389 #define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
1390 #define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
1391 #define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
1392 #define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
1393 #define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
1394 #define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
1395 #define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
1396 #define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
1397 /**
1398 * @}
1399 */
1400
1401 /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
1402 * @{
1403 */
1404 #define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
1405 #define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
1406 #define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
1407 #define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
1408 #define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
1409 #define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
1410 #define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
1411 #define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
1412 #define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
1413 #define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
1414 #define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
1415 #define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
1416 /**
1417 * @}
1418 */
1419
1420 /** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format
1421 * @{
1422 */
1423 #define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080)
1424 #define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000)
1425 /**
1426 * @}
1427 */
1428
1429 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
1430 * @{
1431 */
1432 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000)
1433 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000)
1434 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000)
1435 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000)
1436 #define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002)
1437 /**
1438 * @}
1439 */
1440
1441 /** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment
1442 * @{
1443 */
1444 #define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000) /*!< Last Segment */
1445 #define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000) /*!< First Segment */
1446 /**
1447 * @}
1448 */
1449
1450 /** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control
1451 * @{
1452 */
1453 #define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000) /*!< Checksum engine bypass */
1454 #define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000) /*!< IPv4 header checksum insertion */
1455 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
1456 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
1457 /**
1458 * @}
1459 */
1460
1461 /** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers
1462 * @{
1463 */
1464 #define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000) /*!< DMA Rx Desc Buffer1 */
1465 #define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001) /*!< DMA Rx Desc Buffer2 */
1466 /**
1467 * @}
1468 */
1469
1470 /** @defgroup ETH_PMT_Flags ETH PMT Flags
1471 * @{
1472 */
1473 #define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /*!< Wake-Up Frame Filter Register Pointer Reset */
1474 #define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /*!< Wake-Up Frame Received */
1475 #define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /*!< Magic Packet Received */
1476 /**
1477 * @}
1478 */
1479
1480 /** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts
1481 * @{
1482 */
1483 #define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /*!< When Tx good frame counter reaches half the maximum value */
1484 #define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /*!< When Tx good multi col counter reaches half the maximum value */
1485 #define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /*!< When Tx good single col counter reaches half the maximum value */
1486 /**
1487 * @}
1488 */
1489
1490 /** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts
1491 * @{
1492 */
1493 #define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /*!< When Rx good unicast frames counter reaches half the maximum value */
1494 #define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /*!< When Rx alignment error counter reaches half the maximum value */
1495 #define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /*!< When Rx crc error counter reaches half the maximum value */
1496 /**
1497 * @}
1498 */
1499
1500 /** @defgroup ETH_MAC_Flags ETH MAC Flags
1501 * @{
1502 */
1503 #define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /*!< Time stamp trigger flag (on MAC) */
1504 #define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /*!< MMC transmit flag */
1505 #define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /*!< MMC receive flag */
1506 #define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /*!< MMC flag (on MAC) */
1507 #define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /*!< PMT flag (on MAC) */
1508 /**
1509 * @}
1510 */
1511
1512 /** @defgroup ETH_DMA_Flags ETH DMA Flags
1513 * @{
1514 */
1515 #define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
1516 #define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */
1517 #define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */
1518 #define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000) /*!< Error bits 0-Rx DMA, 1-Tx DMA */
1519 #define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000) /*!< Error bits 0-write transfer, 1-read transfer */
1520 #define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000) /*!< Error bits 0-data buffer, 1-desc. access */
1521 #define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary flag */
1522 #define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary flag */
1523 #define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /*!< Early receive flag */
1524 #define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /*!< Fatal bus error flag */
1525 #define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /*!< Early transmit flag */
1526 #define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout flag */
1527 #define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /*!< Receive process stopped flag */
1528 #define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable flag */
1529 #define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /*!< Receive flag */
1530 #define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /*!< Underflow flag */
1531 #define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /*!< Overflow flag */
1532 #define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout flag */
1533 #define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable flag */
1534 #define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped flag */
1535 #define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /*!< Transmit flag */
1536 /**
1537 * @}
1538 */
1539
1540 /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
1541 * @{
1542 */
1543 #define ETH_MAC_IT_TST ((uint32_t)0x00000200) /*!< Time stamp trigger interrupt (on MAC) */
1544 #define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /*!< MMC transmit interrupt */
1545 #define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /*!< MMC receive interrupt */
1546 #define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /*!< MMC interrupt (on MAC) */
1547 #define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /*!< PMT interrupt (on MAC) */
1548 /**
1549 * @}
1550 */
1551
1552 /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
1553 * @{
1554 */
1555 #define ETH_DMA_IT_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
1556 #define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */
1557 #define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */
1558 #define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary */
1559 #define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary */
1560 #define ETH_DMA_IT_ER ((uint32_t)0x00004000) /*!< Early receive interrupt */
1561 #define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /*!< Fatal bus error interrupt */
1562 #define ETH_DMA_IT_ET ((uint32_t)0x00000400) /*!< Early transmit interrupt */
1563 #define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout interrupt */
1564 #define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /*!< Receive process stopped interrupt */
1565 #define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable interrupt */
1566 #define ETH_DMA_IT_R ((uint32_t)0x00000040) /*!< Receive interrupt */
1567 #define ETH_DMA_IT_TU ((uint32_t)0x00000020) /*!< Underflow interrupt */
1568 #define ETH_DMA_IT_RO ((uint32_t)0x00000010) /*!< Overflow interrupt */
1569 #define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout interrupt */
1570 #define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable interrupt */
1571 #define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped interrupt */
1572 #define ETH_DMA_IT_T ((uint32_t)0x00000001) /*!< Transmit interrupt */
1573 /**
1574 * @}
1575 */
1576
1577 /** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
1578 * @{
1579 */
1580 #define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Tx Command issued */
1581 #define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000) /*!< Running - fetching the Tx descriptor */
1582 #define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000) /*!< Running - waiting for status */
1583 #define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000) /*!< Running - reading the data from host memory */
1584 #define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000) /*!< Suspended - Tx Descriptor unavailable */
1585 #define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000) /*!< Running - closing Rx descriptor */
1586
1587 /**
1588 * @}
1589 */
1590
1591
1592 /** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
1593 * @{
1594 */
1595 #define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Rx Command issued */
1596 #define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000) /*!< Running - fetching the Rx descriptor */
1597 #define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000) /*!< Running - waiting for packet */
1598 #define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000) /*!< Suspended - Rx Descriptor unavailable */
1599 #define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000) /*!< Running - closing descriptor */
1600 #define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000) /*!< Running - queuing the receive frame into host memory */
1601
1602 /**
1603 * @}
1604 */
1605
1606 /** @defgroup ETH_DMA_overflow ETH DMA overflow
1607 * @{
1608 */
1609 #define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000) /*!< Overflow bit for FIFO overflow counter */
1610 #define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000) /*!< Overflow bit for missed frame counter */
1611 /**
1612 * @}
1613 */
1614
1615 /** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
1616 * @{
1617 */
1618 #define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000) /*!< External interrupt line 19 Connected to the ETH EXTI Line */
1619
1620 /**
1621 * @}
1622 */
1623
1624 /**
1625 * @}
1626 */
1627
1628 /* Exported macro ------------------------------------------------------------*/
1629 /** @defgroup ETH_Exported_Macros ETH Exported Macros
1630 * @brief macros to handle interrupts and specific clock configurations
1631 * @{
1632 */
1633
1634 /** @brief Reset ETH handle state
1635 * @param __HANDLE__: specifies the ETH handle.
1636 * @retval None
1637 */
1638 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
1639
1640 /**
1641 * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
1642 * @param __HANDLE__: ETH Handle
1643 * @param __FLAG__: specifies the flag of TDES0 to check.
1644 * @retval the ETH_DMATxDescFlag (SET or RESET).
1645 */
1646 #define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
1647
1648 /**
1649 * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
1650 * @param __HANDLE__: ETH Handle
1651 * @param __FLAG__: specifies the flag of RDES0 to check.
1652 * @retval the ETH_DMATxDescFlag (SET or RESET).
1653 */
1654 #define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
1655
1656 /**
1657 * @brief Enables the specified DMA Rx Desc receive interrupt.
1658 * @param __HANDLE__: ETH Handle
1659 * @retval None
1660 */
1661 #define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
1662
1663 /**
1664 * @brief Disables the specified DMA Rx Desc receive interrupt.
1665 * @param __HANDLE__: ETH Handle
1666 * @retval None
1667 */
1668 #define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)
1669
1670 /**
1671 * @brief Set the specified DMA Rx Desc Own bit.
1672 * @param __HANDLE__: ETH Handle
1673 * @retval None
1674 */
1675 #define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)
1676
1677 /**
1678 * @brief Returns the specified ETHERNET DMA Tx Desc collision count.
1679 * @param __HANDLE__: ETH Handle
1680 * @retval The Transmit descriptor collision counter value.
1681 */
1682 #define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
1683
1684 /**
1685 * @brief Set the specified DMA Tx Desc Own bit.
1686 * @param __HANDLE__: ETH Handle
1687 * @retval None
1688 */
1689 #define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)
1690
1691 /**
1692 * @brief Enables the specified DMA Tx Desc Transmit interrupt.
1693 * @param __HANDLE__: ETH Handle
1694 * @retval None
1695 */
1696 #define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)
1697
1698 /**
1699 * @brief Disables the specified DMA Tx Desc Transmit interrupt.
1700 * @param __HANDLE__: ETH Handle
1701 * @retval None
1702 */
1703 #define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
1704
1705 /**
1706 * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
1707 * @param __HANDLE__: ETH Handle
1708 * @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
1709 * This parameter can be one of the following values:
1710 * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
1711 * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
1712 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
1713 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
1714 * @retval None
1715 */
1716 #define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))
1717
1718 /**
1719 * @brief Enables the DMA Tx Desc CRC.
1720 * @param __HANDLE__: ETH Handle
1721 * @retval None
1722 */
1723 #define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
1724
1725 /**
1726 * @brief Disables the DMA Tx Desc CRC.
1727 * @param __HANDLE__: ETH Handle
1728 * @retval None
1729 */
1730 #define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)
1731
1732 /**
1733 * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
1734 * @param __HANDLE__: ETH Handle
1735 * @retval None
1736 */
1737 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
1738
1739 /**
1740 * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
1741 * @param __HANDLE__: ETH Handle
1742 * @retval None
1743 */
1744 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)
1745
1746 /**
1747 * @brief Enables the specified ETHERNET MAC interrupts.
1748 * @param __HANDLE__ : ETH Handle
1749 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
1750 * enabled or disabled.
1751 * This parameter can be any combination of the following values:
1752 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
1753 * @arg ETH_MAC_IT_PMT : PMT interrupt
1754 * @retval None
1755 */
1756 #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))
1757
1758 /**
1759 * @brief Disables the specified ETHERNET MAC interrupts.
1760 * @param __HANDLE__ : ETH Handle
1761 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
1762 * enabled or disabled.
1763 * This parameter can be any combination of the following values:
1764 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
1765 * @arg ETH_MAC_IT_PMT : PMT interrupt
1766 * @retval None
1767 */
1768 #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
1769
1770 /**
1771 * @brief Initiate a Pause Control Frame (Full-duplex only).
1772 * @param __HANDLE__: ETH Handle
1773 * @retval None
1774 */
1775 #define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
1776
1777 /**
1778 * @brief Checks whether the ETHERNET flow control busy bit is set or not.
1779 * @param __HANDLE__: ETH Handle
1780 * @retval The new state of flow control busy status bit (SET or RESET).
1781 */
1782 #define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
1783
1784 /**
1785 * @brief Enables the MAC Back Pressure operation activation (Half-duplex only).
1786 * @param __HANDLE__: ETH Handle
1787 * @retval None
1788 */
1789 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
1790
1791 /**
1792 * @brief Disables the MAC BackPressure operation activation (Half-duplex only).
1793 * @param __HANDLE__: ETH Handle
1794 * @retval None
1795 */
1796 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
1797
1798 /**
1799 * @brief Checks whether the specified ETHERNET MAC flag is set or not.
1800 * @param __HANDLE__: ETH Handle
1801 * @param __FLAG__: specifies the flag to check.
1802 * This parameter can be one of the following values:
1803 * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
1804 * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
1805 * @arg ETH_MAC_FLAG_MMCR : MMC receive flag
1806 * @arg ETH_MAC_FLAG_MMC : MMC flag
1807 * @arg ETH_MAC_FLAG_PMT : PMT flag
1808 * @retval The state of ETHERNET MAC flag.
1809 */
1810 #define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
1811
1812 /**
1813 * @brief Enables the specified ETHERNET DMA interrupts.
1814 * @param __HANDLE__ : ETH Handle
1815 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
1816 * enabled @ref ETH_DMA_Interrupts
1817 * @retval None
1818 */
1819 #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))
1820
1821 /**
1822 * @brief Disables the specified ETHERNET DMA interrupts.
1823 * @param __HANDLE__ : ETH Handle
1824 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
1825 * disabled. @ref ETH_DMA_Interrupts
1826 * @retval None
1827 */
1828 #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
1829
1830 /**
1831 * @brief Clears the ETHERNET DMA IT pending bit.
1832 * @param __HANDLE__ : ETH Handle
1833 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
1834 * @retval None
1835 */
1836 #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
1837
1838 /**
1839 * @brief Checks whether the specified ETHERNET DMA flag is set or not.
1840 * @param __HANDLE__: ETH Handle
1841 * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags
1842 * @retval The new state of ETH_DMA_FLAG (SET or RESET).
1843 */
1844 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
1845
1846 /**
1847 * @brief Checks whether the specified ETHERNET DMA flag is set or not.
1848 * @param __HANDLE__: ETH Handle
1849 * @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags
1850 * @retval The new state of ETH_DMA_FLAG (SET or RESET).
1851 */
1852 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
1853
1854 /**
1855 * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
1856 * @param __HANDLE__: ETH Handle
1857 * @param __OVERFLOW__: specifies the DMA overflow flag to check.
1858 * This parameter can be one of the following values:
1859 * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
1860 * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
1861 * @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
1862 */
1863 #define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
1864
1865 /**
1866 * @brief Set the DMA Receive status watchdog timer register value
1867 * @param __HANDLE__: ETH Handle
1868 * @param __VALUE__: DMA Receive status watchdog timer register value
1869 * @retval None
1870 */
1871 #define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
1872
1873 /**
1874 * @brief Enables any unicast packet filtered by the MAC address
1875 * recognition to be a wake-up frame.
1876 * @param __HANDLE__: ETH Handle.
1877 * @retval None
1878 */
1879 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)
1880
1881 /**
1882 * @brief Disables any unicast packet filtered by the MAC address
1883 * recognition to be a wake-up frame.
1884 * @param __HANDLE__: ETH Handle.
1885 * @retval None
1886 */
1887 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
1888
1889 /**
1890 * @brief Enables the MAC Wake-Up Frame Detection.
1891 * @param __HANDLE__: ETH Handle.
1892 * @retval None
1893 */
1894 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)
1895
1896 /**
1897 * @brief Disables the MAC Wake-Up Frame Detection.
1898 * @param __HANDLE__: ETH Handle.
1899 * @retval None
1900 */
1901 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
1902
1903 /**
1904 * @brief Enables the MAC Magic Packet Detection.
1905 * @param __HANDLE__: ETH Handle.
1906 * @retval None
1907 */
1908 #define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)
1909
1910 /**
1911 * @brief Disables the MAC Magic Packet Detection.
1912 * @param __HANDLE__: ETH Handle.
1913 * @retval None
1914 */
1915 #define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
1916
1917 /**
1918 * @brief Enables the MAC Power Down.
1919 * @param __HANDLE__: ETH Handle
1920 * @retval None
1921 */
1922 #define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)
1923
1924 /**
1925 * @brief Disables the MAC Power Down.
1926 * @param __HANDLE__: ETH Handle
1927 * @retval None
1928 */
1929 #define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
1930
1931 /**
1932 * @brief Checks whether the specified ETHERNET PMT flag is set or not.
1933 * @param __HANDLE__: ETH Handle.
1934 * @param __FLAG__: specifies the flag to check.
1935 * This parameter can be one of the following values:
1936 * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
1937 * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
1938 * @arg ETH_PMT_FLAG_MPR : Magic Packet Received
1939 * @retval The new state of ETHERNET PMT Flag (SET or RESET).
1940 */
1941 #define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
1942
1943 /**
1944 * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
1945 * @param __HANDLE__: ETH Handle.
1946 * @retval None
1947 */
1948 #define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))
1949
1950 /**
1951 * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
1952 * @param __HANDLE__: ETH Handle.
1953 * @retval None
1954 */
1955 #define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
1956 (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0)
1957
1958 /**
1959 * @brief Enables the MMC Counter Freeze.
1960 * @param __HANDLE__: ETH Handle.
1961 * @retval None
1962 */
1963 #define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)
1964
1965 /**
1966 * @brief Disables the MMC Counter Freeze.
1967 * @param __HANDLE__: ETH Handle.
1968 * @retval None
1969 */
1970 #define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
1971
1972 /**
1973 * @brief Enables the MMC Reset On Read.
1974 * @param __HANDLE__: ETH Handle.
1975 * @retval None
1976 */
1977 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)
1978
1979 /**
1980 * @brief Disables the MMC Reset On Read.
1981 * @param __HANDLE__: ETH Handle.
1982 * @retval None
1983 */
1984 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
1985
1986 /**
1987 * @brief Enables the MMC Counter Stop Rollover.
1988 * @param __HANDLE__: ETH Handle.
1989 * @retval None
1990 */
1991 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
1992
1993 /**
1994 * @brief Disables the MMC Counter Stop Rollover.
1995 * @param __HANDLE__: ETH Handle.
1996 * @retval None
1997 */
1998 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)
1999
2000 /**
2001 * @brief Resets the MMC Counters.
2002 * @param __HANDLE__: ETH Handle.
2003 * @retval None
2004 */
2005 #define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)
2006
2007 /**
2008 * @brief Enables the specified ETHERNET MMC Rx interrupts.
2009 * @param __HANDLE__: ETH Handle.
2010 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
2011 * This parameter can be one of the following values:
2012 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
2013 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
2014 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
2015 * @retval None
2016 */
2017 #define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)
2018 /**
2019 * @brief Disables the specified ETHERNET MMC Rx interrupts.
2020 * @param __HANDLE__: ETH Handle.
2021 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
2022 * This parameter can be one of the following values:
2023 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
2024 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
2025 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
2026 * @retval None
2027 */
2028 #define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF)
2029 /**
2030 * @brief Enables the specified ETHERNET MMC Tx interrupts.
2031 * @param __HANDLE__: ETH Handle.
2032 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
2033 * This parameter can be one of the following values:
2034 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
2035 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
2036 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
2037 * @retval None
2038 */
2039 #define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
2040
2041 /**
2042 * @brief Disables the specified ETHERNET MMC Tx interrupts.
2043 * @param __HANDLE__: ETH Handle.
2044 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
2045 * This parameter can be one of the following values:
2046 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
2047 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
2048 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
2049 * @retval None
2050 */
2051 #define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))
2052
2053 /**
2054 * @brief Enables the ETH External interrupt line.
2055 * @retval None
2056 */
2057 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)
2058
2059 /**
2060 * @brief Disables the ETH External interrupt line.
2061 * @retval None
2062 */
2063 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
2064
2065 /**
2066 * @brief Enable event on ETH External event line.
2067 * @retval None.
2068 */
2069 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP)
2070
2071 /**
2072 * @brief Disable event on ETH External event line
2073 * @retval None.
2074 */
2075 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
2076
2077 /**
2078 * @brief Get flag of the ETH External interrupt line.
2079 * @retval None
2080 */
2081 #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
2082
2083 /**
2084 * @brief Clear flag of the ETH External interrupt line.
2085 * @retval None
2086 */
2087 #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
2088
2089 /**
2090 * @brief Enables rising edge trigger to the ETH External interrupt line.
2091 * @retval None
2092 */
2093 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP
2094
2095 /**
2096 * @brief Disables the rising edge trigger to the ETH External interrupt line.
2097 * @retval None
2098 */
2099 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
2100
2101 /**
2102 * @brief Enables falling edge trigger to the ETH External interrupt line.
2103 * @retval None
2104 */
2105 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)
2106
2107 /**
2108 * @brief Disables falling edge trigger to the ETH External interrupt line.
2109 * @retval None
2110 */
2111 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
2112
2113 /**
2114 * @brief Enables rising/falling edge trigger to the ETH External interrupt line.
2115 * @retval None
2116 */
2117 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
2118 EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP
2119
2120 /**
2121 * @brief Disables rising/falling edge trigger to the ETH External interrupt line.
2122 * @retval None
2123 */
2124 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
2125 EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
2126
2127 /**
2128 * @brief Generate a Software interrupt on selected EXTI line.
2129 * @retval None.
2130 */
2131 #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP
2132
2133 /**
2134 * @}
2135 */
2136 /* Exported functions --------------------------------------------------------*/
2137
2138 /** @addtogroup ETH_Exported_Functions
2139 * @{
2140 */
2141
2142 /* Initialization and de-initialization functions ****************************/
2143
2144 /** @addtogroup ETH_Exported_Functions_Group1
2145 * @{
2146 */
2147 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
2148 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
2149 void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
2150 void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
2151 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
2152 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
2153
2154 /**
2155 * @}
2156 */
2157 /* IO operation functions ****************************************************/
2158
2159 /** @addtogroup ETH_Exported_Functions_Group2
2160 * @{
2161 */
2162 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
2163 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
2164 /* Communication with PHY functions*/
2165 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);
2166 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
2167 /* Non-Blocking mode: Interrupt */
2168 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
2169 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
2170 /* Callback in non blocking modes (Interrupt) */
2171 void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
2172 void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
2173 void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
2174 /**
2175 * @}
2176 */
2177
2178 /* Peripheral Control functions **********************************************/
2179
2180 /** @addtogroup ETH_Exported_Functions_Group3
2181 * @{
2182 */
2183
2184 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
2185 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
2186 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);
2187 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);
2188 /**
2189 * @}
2190 */
2191
2192 /* Peripheral State functions ************************************************/
2193
2194 /** @addtogroup ETH_Exported_Functions_Group4
2195 * @{
2196 */
2197 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
2198 /**
2199 * @}
2200 */
2201
2202 /**
2203 * @}
2204 */
2205
2206 /**
2207 * @}
2208 */
2209
2210 /**
2211 * @}
2212 */
2213
2214 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
2215
2216 #ifdef __cplusplus
2217 }
2218 #endif
2219
2220 #endif /* __STM32F4xx_HAL_ETH_H */
2221
2222
2223 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/