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comparison Common/Drivers/STM32F4xx_HAL_DRIVER_v120/Inc/stm32f4xx_hal_dma.h @ 38:5f11787b4f42

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author heinrichsweikamp
date Sat, 28 Apr 2018 11:52:34 +0200
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1 /**
2 ******************************************************************************
3 * @file stm32f4xx_hal_dma.h
4 * @author MCD Application Team
5 * @version V1.2.0
6 * @date 26-December-2014
7 * @brief Header file of DMA HAL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F4xx_HAL_DMA_H
40 #define __STM32F4xx_HAL_DMA_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f4xx_hal_def.h"
48
49 /** @addtogroup STM32F4xx_HAL_Driver
50 * @{
51 */
52
53 /** @addtogroup DMA
54 * @{
55 */
56
57 /* Exported types ------------------------------------------------------------*/
58
59 /** @defgroup DMA_Exported_Types DMA Exported Types
60 * @brief DMA Exported Types
61 * @{
62 */
63
64 /**
65 * @brief DMA Configuration Structure definition
66 */
67 typedef struct
68 {
69 uint32_t Channel; /*!< Specifies the channel used for the specified stream.
70 This parameter can be a value of @ref DMA_Channel_selection */
71
72 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
73 from memory to memory or from peripheral to memory.
74 This parameter can be a value of @ref DMA_Data_transfer_direction */
75
76 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
77 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
78
79 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
80 This parameter can be a value of @ref DMA_Memory_incremented_mode */
81
82 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
83 This parameter can be a value of @ref DMA_Peripheral_data_size */
84
85 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
86 This parameter can be a value of @ref DMA_Memory_data_size */
87
88 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx.
89 This parameter can be a value of @ref DMA_mode
90 @note The circular buffer mode cannot be used if the memory-to-memory
91 data transfer is configured on the selected Stream */
92
93 uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx.
94 This parameter can be a value of @ref DMA_Priority_level */
95
96 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
97 This parameter can be a value of @ref DMA_FIFO_direct_mode
98 @note The Direct mode (FIFO mode disabled) cannot be used if the
99 memory-to-memory data transfer is configured on the selected stream */
100
101 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
102 This parameter can be a value of @ref DMA_FIFO_threshold_level */
103
104 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
105 It specifies the amount of data to be transferred in a single non interruptible
106 transaction.
107 This parameter can be a value of @ref DMA_Memory_burst
108 @note The burst mode is possible only if the address Increment mode is enabled. */
109
110 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
111 It specifies the amount of data to be transferred in a single non interruptable
112 transaction.
113 This parameter can be a value of @ref DMA_Peripheral_burst
114 @note The burst mode is possible only if the address Increment mode is enabled. */
115 }DMA_InitTypeDef;
116
117
118 /**
119 * @brief HAL DMA State structures definition
120 */
121 typedef enum
122 {
123 HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
124 HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */
125 HAL_DMA_STATE_READY_MEM0 = 0x11, /*!< DMA Mem0 process success */
126 HAL_DMA_STATE_READY_MEM1 = 0x21, /*!< DMA Mem1 process success */
127 HAL_DMA_STATE_READY_HALF_MEM0 = 0x31, /*!< DMA Mem0 Half process success */
128 HAL_DMA_STATE_READY_HALF_MEM1 = 0x41, /*!< DMA Mem1 Half process success */
129 HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
130 HAL_DMA_STATE_BUSY_MEM0 = 0x12, /*!< DMA Mem0 process is ongoing */
131 HAL_DMA_STATE_BUSY_MEM1 = 0x22, /*!< DMA Mem1 process is ongoing */
132 HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
133 HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
134 }HAL_DMA_StateTypeDef;
135
136 /**
137 * @brief HAL DMA Error Code structure definition
138 */
139 typedef enum
140 {
141 HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
142 HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
143 }HAL_DMA_LevelCompleteTypeDef;
144
145 /**
146 * @brief DMA handle Structure definition
147 */
148 typedef struct __DMA_HandleTypeDef
149 {
150 DMA_Stream_TypeDef *Instance; /*!< Register base address */
151
152 DMA_InitTypeDef Init; /*!< DMA communication parameters */
153
154 HAL_LockTypeDef Lock; /*!< DMA locking object */
155
156 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
157
158 void *Parent; /*!< Parent object state */
159
160 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
161
162 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
163
164 void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */
165
166 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
167
168 __IO uint32_t ErrorCode; /*!< DMA Error code */
169 }DMA_HandleTypeDef;
170
171 /**
172 * @}
173 */
174
175 /* Exported constants --------------------------------------------------------*/
176
177 /** @defgroup DMA_Exported_Constants DMA Exported Constants
178 * @brief DMA Exported constants
179 * @{
180 */
181
182 /** @defgroup DMA_Error_Code DMA Error Code
183 * @brief DMA Error Code
184 * @{
185 */
186 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
187 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
188 #define HAL_DMA_ERROR_FE ((uint32_t)0x00000002) /*!< FIFO error */
189 #define HAL_DMA_ERROR_DME ((uint32_t)0x00000004) /*!< Direct Mode error */
190 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
191 /**
192 * @}
193 */
194
195 /** @defgroup DMA_Channel_selection DMA Channel selection
196 * @brief DMA channel selection
197 * @{
198 */
199 #define DMA_CHANNEL_0 ((uint32_t)0x00000000) /*!< DMA Channel 0 */
200 #define DMA_CHANNEL_1 ((uint32_t)0x02000000) /*!< DMA Channel 1 */
201 #define DMA_CHANNEL_2 ((uint32_t)0x04000000) /*!< DMA Channel 2 */
202 #define DMA_CHANNEL_3 ((uint32_t)0x06000000) /*!< DMA Channel 3 */
203 #define DMA_CHANNEL_4 ((uint32_t)0x08000000) /*!< DMA Channel 4 */
204 #define DMA_CHANNEL_5 ((uint32_t)0x0A000000) /*!< DMA Channel 5 */
205 #define DMA_CHANNEL_6 ((uint32_t)0x0C000000) /*!< DMA Channel 6 */
206 #define DMA_CHANNEL_7 ((uint32_t)0x0E000000) /*!< DMA Channel 7 */
207 /**
208 * @}
209 */
210
211 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
212 * @brief DMA data transfer direction
213 * @{
214 */
215 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
216 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */
217 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */
218 /**
219 * @}
220 */
221
222 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
223 * @brief DMA peripheral incremented mode
224 * @{
225 */
226 #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */
227 #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode disable */
228 /**
229 * @}
230 */
231
232 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
233 * @brief DMA memory incremented mode
234 * @{
235 */
236 #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */
237 #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode disable */
238 /**
239 * @}
240 */
241
242 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
243 * @brief DMA peripheral data size
244 * @{
245 */
246 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment: Byte */
247 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
248 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */
249 /**
250 * @}
251 */
252
253 /** @defgroup DMA_Memory_data_size DMA Memory data size
254 * @brief DMA memory data size
255 * @{
256 */
257 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment: Byte */
258 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
259 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */
260 /**
261 * @}
262 */
263
264 /** @defgroup DMA_mode DMA mode
265 * @brief DMA mode
266 * @{
267 */
268 #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
269 #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */
270 #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */
271 /**
272 * @}
273 */
274
275 /** @defgroup DMA_Priority_level DMA Priority level
276 * @brief DMA priority levels
277 * @{
278 */
279 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level: Low */
280 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */
281 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */
282 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */
283 /**
284 * @}
285 */
286
287 /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
288 * @brief DMA FIFO direct mode
289 * @{
290 */
291 #define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000) /*!< FIFO mode disable */
292 #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */
293 /**
294 * @}
295 */
296
297 /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
298 * @brief DMA FIFO level
299 * @{
300 */
301 #define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000) /*!< FIFO threshold 1 quart full configuration */
302 #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */
303 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */
304 #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */
305 /**
306 * @}
307 */
308
309 /** @defgroup DMA_Memory_burst DMA Memory burst
310 * @brief DMA memory burst
311 * @{
312 */
313 #define DMA_MBURST_SINGLE ((uint32_t)0x00000000)
314 #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
315 #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
316 #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
317 /**
318 * @}
319 */
320
321 /** @defgroup DMA_Peripheral_burst DMA Peripheral burst
322 * @brief DMA peripheral burst
323 * @{
324 */
325 #define DMA_PBURST_SINGLE ((uint32_t)0x00000000)
326 #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
327 #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
328 #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
329 /**
330 * @}
331 */
332
333 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
334 * @brief DMA interrupts definition
335 * @{
336 */
337 #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
338 #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
339 #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
340 #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
341 #define DMA_IT_FE ((uint32_t)0x00000080)
342 /**
343 * @}
344 */
345
346 /** @defgroup DMA_flag_definitions DMA flag definitions
347 * @brief DMA flag definitions
348 * @{
349 */
350 #define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001)
351 #define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004)
352 #define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008)
353 #define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010)
354 #define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020)
355 #define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040)
356 #define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100)
357 #define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200)
358 #define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400)
359 #define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800)
360 #define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000)
361 #define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000)
362 #define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000)
363 #define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000)
364 #define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000)
365 #define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000)
366 #define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000)
367 #define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000)
368 #define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000)
369 #define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000)
370 /**
371 * @}
372 */
373
374 /**
375 * @}
376 */
377
378 /* Exported macro ------------------------------------------------------------*/
379
380 /** @brief Reset DMA handle state
381 * @param __HANDLE__: specifies the DMA handle.
382 * @retval None
383 */
384 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
385
386 /**
387 * @brief Return the current DMA Stream FIFO filled level.
388 * @param __HANDLE__: DMA handle
389 * @retval The FIFO filling state.
390 * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
391 * and not empty.
392 * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
393 * - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
394 * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
395 * - DMA_FIFOStatus_Empty: when FIFO is empty
396 * - DMA_FIFOStatus_Full: when FIFO is full
397 */
398 #define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
399
400 /**
401 * @brief Enable the specified DMA Stream.
402 * @param __HANDLE__: DMA handle
403 * @retval None
404 */
405 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
406
407 /**
408 * @brief Disable the specified DMA Stream.
409 * @param __HANDLE__: DMA handle
410 * @retval None
411 */
412 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
413
414 /* Interrupt & Flag management */
415
416 /**
417 * @brief Return the current DMA Stream transfer complete flag.
418 * @param __HANDLE__: DMA handle
419 * @retval The specified transfer complete flag index.
420 */
421 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
422 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
423 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
424 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
425 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
426 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
427 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
428 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
429 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
430 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
431 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
432 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
433 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
434 DMA_FLAG_TCIF3_7)
435
436 /**
437 * @brief Return the current DMA Stream half transfer complete flag.
438 * @param __HANDLE__: DMA handle
439 * @retval The specified half transfer complete flag index.
440 */
441 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
442 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
443 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
444 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
445 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
446 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
447 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
448 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
449 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
450 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
451 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
452 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
453 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
454 DMA_FLAG_HTIF3_7)
455
456 /**
457 * @brief Return the current DMA Stream transfer error flag.
458 * @param __HANDLE__: DMA handle
459 * @retval The specified transfer error flag index.
460 */
461 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
462 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
463 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
464 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
465 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
466 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
467 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
468 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
469 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
470 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
471 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
472 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
473 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
474 DMA_FLAG_TEIF3_7)
475
476 /**
477 * @brief Return the current DMA Stream FIFO error flag.
478 * @param __HANDLE__: DMA handle
479 * @retval The specified FIFO error flag index.
480 */
481 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
482 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
483 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
484 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
485 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
486 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
487 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
488 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
489 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
490 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
491 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
492 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
493 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
494 DMA_FLAG_FEIF3_7)
495
496 /**
497 * @brief Return the current DMA Stream direct mode error flag.
498 * @param __HANDLE__: DMA handle
499 * @retval The specified direct mode error flag index.
500 */
501 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
502 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
503 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
504 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
505 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
506 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
507 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
508 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
509 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
510 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
511 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
512 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
513 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
514 DMA_FLAG_DMEIF3_7)
515
516 /**
517 * @brief Get the DMA Stream pending flags.
518 * @param __HANDLE__: DMA handle
519 * @param __FLAG__: Get the specified flag.
520 * This parameter can be any combination of the following values:
521 * @arg DMA_FLAG_TCIFx: Transfer complete flag.
522 * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
523 * @arg DMA_FLAG_TEIFx: Transfer error flag.
524 * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
525 * @arg DMA_FLAG_FEIFx: FIFO error flag.
526 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
527 * @retval The state of FLAG (SET or RESET).
528 */
529 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
530 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
531 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
532 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
533
534 /**
535 * @brief Clear the DMA Stream pending flags.
536 * @param __HANDLE__: DMA handle
537 * @param __FLAG__: specifies the flag to clear.
538 * This parameter can be any combination of the following values:
539 * @arg DMA_FLAG_TCIFx: Transfer complete flag.
540 * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
541 * @arg DMA_FLAG_TEIFx: Transfer error flag.
542 * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
543 * @arg DMA_FLAG_FEIFx: FIFO error flag.
544 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
545 * @retval None
546 */
547 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
548 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
549 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
550 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
551
552 /**
553 * @brief Enable the specified DMA Stream interrupts.
554 * @param __HANDLE__: DMA handle
555 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
556 * This parameter can be any combination of the following values:
557 * @arg DMA_IT_TC: Transfer complete interrupt mask.
558 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
559 * @arg DMA_IT_TE: Transfer error interrupt mask.
560 * @arg DMA_IT_FE: FIFO error interrupt mask.
561 * @arg DMA_IT_DME: Direct mode error interrupt.
562 * @retval None
563 */
564 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
565 ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
566
567 /**
568 * @brief Disable the specified DMA Stream interrupts.
569 * @param __HANDLE__: DMA handle
570 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
571 * This parameter can be any combination of the following values:
572 * @arg DMA_IT_TC: Transfer complete interrupt mask.
573 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
574 * @arg DMA_IT_TE: Transfer error interrupt mask.
575 * @arg DMA_IT_FE: FIFO error interrupt mask.
576 * @arg DMA_IT_DME: Direct mode error interrupt.
577 * @retval None
578 */
579 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
580 ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
581
582 /**
583 * @brief Check whether the specified DMA Stream interrupt has occurred or not.
584 * @param __HANDLE__: DMA handle
585 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
586 * This parameter can be one of the following values:
587 * @arg DMA_IT_TC: Transfer complete interrupt mask.
588 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
589 * @arg DMA_IT_TE: Transfer error interrupt mask.
590 * @arg DMA_IT_FE: FIFO error interrupt mask.
591 * @arg DMA_IT_DME: Direct mode error interrupt.
592 * @retval The state of DMA_IT.
593 */
594 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
595 ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
596 ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
597
598 /**
599 * @brief Writes the number of data units to be transferred on the DMA Stream.
600 * @param __HANDLE__: DMA handle
601 * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535)
602 * Number of data items depends only on the Peripheral data format.
603 *
604 * @note If Peripheral data format is Bytes: number of data units is equal
605 * to total number of bytes to be transferred.
606 *
607 * @note If Peripheral data format is Half-Word: number of data units is
608 * equal to total number of bytes to be transferred / 2.
609 *
610 * @note If Peripheral data format is Word: number of data units is equal
611 * to total number of bytes to be transferred / 4.
612 *
613 * @retval The number of remaining data units in the current DMAy Streamx transfer.
614 */
615 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
616
617 /**
618 * @brief Returns the number of remaining data units in the current DMAy Streamx transfer.
619 * @param __HANDLE__: DMA handle
620 *
621 * @retval The number of remaining data units in the current DMA Stream transfer.
622 */
623 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
624
625
626 /* Include DMA HAL Extension module */
627 #include "stm32f4xx_hal_dma_ex.h"
628
629 /* Exported functions --------------------------------------------------------*/
630
631 /** @defgroup DMA_Exported_Functions DMA Exported Functions
632 * @brief DMA Exported functions
633 * @{
634 */
635
636 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
637 * @brief Initialization and de-initialization functions
638 * @{
639 */
640 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
641 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
642 /**
643 * @}
644 */
645
646 /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
647 * @brief I/O operation functions
648 * @{
649 */
650 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
651 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
652 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
653 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
654 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
655 /**
656 * @}
657 */
658
659 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
660 * @brief Peripheral State functions
661 * @{
662 */
663 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
664 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
665 /**
666 * @}
667 */
668 /**
669 * @}
670 */
671 /* Private Constants -------------------------------------------------------------*/
672 /** @defgroup DMA_Private_Constants DMA Private Constants
673 * @brief DMA private defines and constants
674 * @{
675 */
676 /**
677 * @}
678 */
679
680 /* Private macros ------------------------------------------------------------*/
681 /** @defgroup DMA_Private_Macros DMA Private Macros
682 * @brief DMA private macros
683 * @{
684 */
685 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
686 ((CHANNEL) == DMA_CHANNEL_1) || \
687 ((CHANNEL) == DMA_CHANNEL_2) || \
688 ((CHANNEL) == DMA_CHANNEL_3) || \
689 ((CHANNEL) == DMA_CHANNEL_4) || \
690 ((CHANNEL) == DMA_CHANNEL_5) || \
691 ((CHANNEL) == DMA_CHANNEL_6) || \
692 ((CHANNEL) == DMA_CHANNEL_7))
693
694 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
695 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
696 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
697
698 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
699
700 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
701 ((STATE) == DMA_PINC_DISABLE))
702
703 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
704 ((STATE) == DMA_MINC_DISABLE))
705
706 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
707 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
708 ((SIZE) == DMA_PDATAALIGN_WORD))
709
710 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
711 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
712 ((SIZE) == DMA_MDATAALIGN_WORD ))
713
714 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
715 ((MODE) == DMA_CIRCULAR) || \
716 ((MODE) == DMA_PFCTRL))
717
718 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
719 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
720 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
721 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
722
723 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
724 ((STATE) == DMA_FIFOMODE_ENABLE))
725
726 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
727 ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
728 ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
729 ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
730
731 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
732 ((BURST) == DMA_MBURST_INC4) || \
733 ((BURST) == DMA_MBURST_INC8) || \
734 ((BURST) == DMA_MBURST_INC16))
735
736 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
737 ((BURST) == DMA_PBURST_INC4) || \
738 ((BURST) == DMA_PBURST_INC8) || \
739 ((BURST) == DMA_PBURST_INC16))
740 /**
741 * @}
742 */
743
744 /* Private functions ---------------------------------------------------------*/
745 /** @defgroup DMA_Private_Functions DMA Private Functions
746 * @brief DMA private functions
747 * @{
748 */
749 /**
750 * @}
751 */
752
753 /**
754 * @}
755 */
756
757 /**
758 * @}
759 */
760
761 #ifdef __cplusplus
762 }
763 #endif
764
765 #endif /* __STM32F4xx_HAL_DMA_H */
766
767 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/