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comparison Common/Drivers/STM32F4xx_HAL_DRIVER_v120/Inc/stm32f4xx_hal_adc.h @ 38:5f11787b4f42
include in ostc4 repository
author | heinrichsweikamp |
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date | Sat, 28 Apr 2018 11:52:34 +0200 |
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1 /** | |
2 ****************************************************************************** | |
3 * @file stm32f4xx_hal_adc.h | |
4 * @author MCD Application Team | |
5 * @version V1.2.0 | |
6 * @date 26-December-2014 | |
7 * @brief Header file of ADC HAL extension module. | |
8 ****************************************************************************** | |
9 * @attention | |
10 * | |
11 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> | |
12 * | |
13 * Redistribution and use in source and binary forms, with or without modification, | |
14 * are permitted provided that the following conditions are met: | |
15 * 1. Redistributions of source code must retain the above copyright notice, | |
16 * this list of conditions and the following disclaimer. | |
17 * 2. Redistributions in binary form must reproduce the above copyright notice, | |
18 * this list of conditions and the following disclaimer in the documentation | |
19 * and/or other materials provided with the distribution. | |
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors | |
21 * may be used to endorse or promote products derived from this software | |
22 * without specific prior written permission. | |
23 * | |
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE | |
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER | |
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | |
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
34 * | |
35 ****************************************************************************** | |
36 */ | |
37 | |
38 /* Define to prevent recursive inclusion -------------------------------------*/ | |
39 #ifndef __STM32F4xx_ADC_H | |
40 #define __STM32F4xx_ADC_H | |
41 | |
42 #ifdef __cplusplus | |
43 extern "C" { | |
44 #endif | |
45 | |
46 /* Includes ------------------------------------------------------------------*/ | |
47 #include "stm32f4xx_hal_def.h" | |
48 | |
49 /** @addtogroup STM32F4xx_HAL_Driver | |
50 * @{ | |
51 */ | |
52 | |
53 /** @addtogroup ADC | |
54 * @{ | |
55 */ | |
56 | |
57 /* Exported types ------------------------------------------------------------*/ | |
58 /** @defgroup ADC_Exported_Types ADC Exported Types | |
59 * @{ | |
60 */ | |
61 | |
62 /** | |
63 * @brief HAL State structures definition | |
64 */ | |
65 typedef enum | |
66 { | |
67 HAL_ADC_STATE_RESET = 0x00, /*!< ADC not yet initialized or disabled */ | |
68 HAL_ADC_STATE_READY = 0x01, /*!< ADC peripheral ready for use */ | |
69 HAL_ADC_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ | |
70 HAL_ADC_STATE_BUSY_REG = 0x12, /*!< Regular conversion is ongoing */ | |
71 HAL_ADC_STATE_BUSY_INJ = 0x22, /*!< Injected conversion is ongoing */ | |
72 HAL_ADC_STATE_BUSY_INJ_REG = 0x32, /*!< Injected and regular conversion are ongoing */ | |
73 HAL_ADC_STATE_TIMEOUT = 0x03, /*!< Timeout state */ | |
74 HAL_ADC_STATE_ERROR = 0x04, /*!< ADC state error */ | |
75 HAL_ADC_STATE_EOC = 0x05, /*!< Conversion is completed */ | |
76 HAL_ADC_STATE_EOC_REG = 0x15, /*!< Regular conversion is completed */ | |
77 HAL_ADC_STATE_EOC_INJ = 0x25, /*!< Injected conversion is completed */ | |
78 HAL_ADC_STATE_EOC_INJ_REG = 0x35, /*!< Injected and regular conversion are completed */ | |
79 HAL_ADC_STATE_AWD = 0x06 /*!< ADC state analog watchdog */ | |
80 | |
81 }HAL_ADC_StateTypeDef; | |
82 | |
83 /** | |
84 * @brief ADC Init structure definition | |
85 */ | |
86 typedef struct | |
87 { | |
88 uint32_t ClockPrescaler; /*!< Select the frequency of the clock to the ADC. The clock is common for | |
89 all the ADCs. | |
90 This parameter can be a value of @ref ADC_ClockPrescaler */ | |
91 uint32_t Resolution; /*!< Configures the ADC resolution dual mode. | |
92 This parameter can be a value of @ref ADC_Resolution */ | |
93 uint32_t DataAlign; /*!< Specifies whether the ADC data alignment is left or right. | |
94 This parameter can be a value of @ref ADC_data_align */ | |
95 uint32_t ScanConvMode; /*!< Specifies whether the conversion is performed in Scan (multi channels) or | |
96 Single (one channel) mode. | |
97 This parameter can be set to ENABLE or DISABLE */ | |
98 uint32_t EOCSelection; /*!< Specifies whether the EOC flag is set | |
99 at the end of single channel conversion or at the end of all conversions. | |
100 This parameter can be a value of @ref ADC_EOCSelection */ | |
101 uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in Continuous or Single mode. | |
102 This parameter can be set to ENABLE or DISABLE. */ | |
103 uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests is performed in Continuous or in Single mode. | |
104 This parameter can be set to ENABLE or DISABLE. */ | |
105 uint32_t NbrOfConversion; /*!< Specifies the number of ADC conversions that will be done using the sequencer for | |
106 regular channel group. | |
107 This parameter must be a number between Min_Data = 1 and Max_Data = 16. */ | |
108 uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversion is performed in Discontinuous or not | |
109 for regular channels. | |
110 This parameter can be set to ENABLE or DISABLE. */ | |
111 uint32_t NbrOfDiscConversion; /*!< Specifies the number of ADC discontinuous conversions that will be done | |
112 using the sequencer for regular channel group. | |
113 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ | |
114 uint32_t ExternalTrigConvEdge; /*!< Select the external trigger edge and enable the trigger of a regular group. | |
115 This parameter can be a value of @ref ADC_External_trigger_edge_Regular */ | |
116 uint32_t ExternalTrigConv; /*!< Select the external event used to trigger the start of conversion of a regular group. | |
117 This parameter can be a value of @ref ADC_External_trigger_Source_Regular */ | |
118 }ADC_InitTypeDef; | |
119 | |
120 /** | |
121 * @brief ADC handle Structure definition | |
122 */ | |
123 typedef struct | |
124 { | |
125 ADC_TypeDef *Instance; /*!< Register base address */ | |
126 | |
127 ADC_InitTypeDef Init; /*!< ADC required parameters */ | |
128 | |
129 __IO uint32_t NbrOfCurrentConversionRank; /*!< ADC number of current conversion rank */ | |
130 | |
131 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ | |
132 | |
133 HAL_LockTypeDef Lock; /*!< ADC locking object */ | |
134 | |
135 __IO HAL_ADC_StateTypeDef State; /*!< ADC communication state */ | |
136 | |
137 __IO uint32_t ErrorCode; /*!< ADC Error code */ | |
138 }ADC_HandleTypeDef; | |
139 | |
140 /** | |
141 * @brief ADC Configuration regular Channel structure definition | |
142 */ | |
143 typedef struct | |
144 { | |
145 uint32_t Channel; /*!< The ADC channel to configure. | |
146 This parameter can be a value of @ref ADC_channels */ | |
147 uint32_t Rank; /*!< The rank in the regular group sequencer. | |
148 This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ | |
149 uint32_t SamplingTime; /*!< The sample time value to be set for the selected channel. | |
150 This parameter can be a value of @ref ADC_sampling_times */ | |
151 uint32_t Offset; /*!< Reserved for future use, can be set to 0 */ | |
152 }ADC_ChannelConfTypeDef; | |
153 | |
154 /** | |
155 * @brief ADC Configuration multi-mode structure definition | |
156 */ | |
157 typedef struct | |
158 { | |
159 uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode. | |
160 This parameter can be a value of @ref ADC_analog_watchdog_selection */ | |
161 uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. | |
162 This parameter must be a 12-bit value. */ | |
163 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. | |
164 This parameter must be a 12-bit value. */ | |
165 uint32_t Channel; /*!< Configures ADC channel for the analog watchdog. | |
166 This parameter has an effect only if watchdog mode is configured on single channel | |
167 This parameter can be a value of @ref ADC_channels */ | |
168 uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured | |
169 is interrupt mode or in polling mode. | |
170 This parameter can be set to ENABLE or DISABLE */ | |
171 uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */ | |
172 }ADC_AnalogWDGConfTypeDef; | |
173 /** | |
174 * @} | |
175 */ | |
176 | |
177 /* Exported constants --------------------------------------------------------*/ | |
178 /** @defgroup ADC_Exported_Constants ADC Exported Constants | |
179 * @{ | |
180 */ | |
181 | |
182 /** @defgroup ADC_Error_Code ADC Error Code | |
183 * @{ | |
184 */ | |
185 #define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */ | |
186 #define HAL_ADC_ERROR_OVR ((uint32_t)0x01) /*!< OVR error */ | |
187 #define HAL_ADC_ERROR_DMA ((uint32_t)0x02) /*!< DMA transfer error */ | |
188 /** | |
189 * @} | |
190 */ | |
191 | |
192 | |
193 /** @defgroup ADC_ClockPrescaler ADC Clock Prescaler | |
194 * @{ | |
195 */ | |
196 #define ADC_CLOCKPRESCALER_PCLK_DIV2 ((uint32_t)0x00000000) | |
197 #define ADC_CLOCKPRESCALER_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0) | |
198 #define ADC_CLOCKPRESCALER_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1) | |
199 #define ADC_CLOCKPRESCALER_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE) | |
200 /** | |
201 * @} | |
202 */ | |
203 | |
204 /** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases | |
205 * @{ | |
206 */ | |
207 #define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000) | |
208 #define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0) | |
209 #define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1) | |
210 #define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) | |
211 #define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2) | |
212 #define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)) | |
213 #define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1)) | |
214 #define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) | |
215 #define ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3) | |
216 #define ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0)) | |
217 #define ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1)) | |
218 #define ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) | |
219 #define ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2)) | |
220 #define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)) | |
221 #define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1)) | |
222 #define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY) | |
223 /** | |
224 * @} | |
225 */ | |
226 | |
227 /** @defgroup ADC_Resolution ADC Resolution | |
228 * @{ | |
229 */ | |
230 #define ADC_RESOLUTION_12B ((uint32_t)0x00000000) | |
231 #define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0) | |
232 #define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1) | |
233 #define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES) | |
234 /** | |
235 * @} | |
236 */ | |
237 | |
238 /** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular | |
239 * @{ | |
240 */ | |
241 #define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000) | |
242 #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0) | |
243 #define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1) | |
244 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN) | |
245 /** | |
246 * @} | |
247 */ | |
248 | |
249 /** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular | |
250 * @{ | |
251 */ | |
252 #define ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000) | |
253 #define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0) | |
254 #define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1) | |
255 #define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) | |
256 #define ADC_EXTERNALTRIGCONV_T2_CC3 ((uint32_t)ADC_CR2_EXTSEL_2) | |
257 #define ADC_EXTERNALTRIGCONV_T2_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) | |
258 #define ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1)) | |
259 #define ADC_EXTERNALTRIGCONV_T3_CC1 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) | |
260 #define ADC_EXTERNALTRIGCONV_T3_TRGO ((uint32_t)ADC_CR2_EXTSEL_3) | |
261 #define ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0)) | |
262 #define ADC_EXTERNALTRIGCONV_T5_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1)) | |
263 #define ADC_EXTERNALTRIGCONV_T5_CC2 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) | |
264 #define ADC_EXTERNALTRIGCONV_T5_CC3 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2)) | |
265 #define ADC_EXTERNALTRIGCONV_T8_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) | |
266 #define ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1)) | |
267 #define ADC_EXTERNALTRIGCONV_Ext_IT11 ((uint32_t)ADC_CR2_EXTSEL) | |
268 /** | |
269 * @} | |
270 */ | |
271 | |
272 /** @defgroup ADC_data_align ADC Data Align | |
273 * @{ | |
274 */ | |
275 #define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000) | |
276 #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN) | |
277 /** | |
278 * @} | |
279 */ | |
280 | |
281 /** @defgroup ADC_channels ADC Common Channels | |
282 * @{ | |
283 */ | |
284 #define ADC_CHANNEL_0 ((uint32_t)0x00000000) | |
285 #define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0) | |
286 #define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1) | |
287 #define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) | |
288 #define ADC_CHANNEL_4 ((uint32_t)ADC_CR1_AWDCH_2) | |
289 #define ADC_CHANNEL_5 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)) | |
290 #define ADC_CHANNEL_6 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1)) | |
291 #define ADC_CHANNEL_7 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) | |
292 #define ADC_CHANNEL_8 ((uint32_t)ADC_CR1_AWDCH_3) | |
293 #define ADC_CHANNEL_9 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0)) | |
294 #define ADC_CHANNEL_10 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1)) | |
295 #define ADC_CHANNEL_11 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) | |
296 #define ADC_CHANNEL_12 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2)) | |
297 #define ADC_CHANNEL_13 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)) | |
298 #define ADC_CHANNEL_14 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1)) | |
299 #define ADC_CHANNEL_15 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) | |
300 #define ADC_CHANNEL_16 ((uint32_t)ADC_CR1_AWDCH_4) | |
301 #define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0)) | |
302 #define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1)) | |
303 | |
304 #define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17) | |
305 #define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18) | |
306 /** | |
307 * @} | |
308 */ | |
309 | |
310 /** @defgroup ADC_sampling_times ADC Sampling Times | |
311 * @{ | |
312 */ | |
313 #define ADC_SAMPLETIME_3CYCLES ((uint32_t)0x00000000) | |
314 #define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0) | |
315 #define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1) | |
316 #define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0)) | |
317 #define ADC_SAMPLETIME_84CYCLES ((uint32_t)ADC_SMPR1_SMP10_2) | |
318 #define ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0)) | |
319 #define ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1)) | |
320 #define ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10) | |
321 /** | |
322 * @} | |
323 */ | |
324 | |
325 /** @defgroup ADC_EOCSelection ADC EOC Selection | |
326 * @{ | |
327 */ | |
328 #define ADC_EOC_SEQ_CONV ((uint32_t)0x00000000) | |
329 #define ADC_EOC_SINGLE_CONV ((uint32_t)0x00000001) | |
330 #define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)0x00000002) /*!< reserved for future use */ | |
331 /** | |
332 * @} | |
333 */ | |
334 | |
335 /** @defgroup ADC_Event_type ADC Event Type | |
336 * @{ | |
337 */ | |
338 #define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) | |
339 #define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) | |
340 /** | |
341 * @} | |
342 */ | |
343 | |
344 /** @defgroup ADC_analog_watchdog_selection ADC Analog Watchdog Selection | |
345 * @{ | |
346 */ | |
347 #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN)) | |
348 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN)) | |
349 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) | |
350 #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN) | |
351 #define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN) | |
352 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) | |
353 #define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000) | |
354 /** | |
355 * @} | |
356 */ | |
357 | |
358 /** @defgroup ADC_interrupts_definition ADC Interrupts Definition | |
359 * @{ | |
360 */ | |
361 #define ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE) | |
362 #define ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE) | |
363 #define ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE) | |
364 #define ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE) | |
365 /** | |
366 * @} | |
367 */ | |
368 | |
369 /** @defgroup ADC_flags_definition ADC Flags Definition | |
370 * @{ | |
371 */ | |
372 #define ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD) | |
373 #define ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC) | |
374 #define ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC) | |
375 #define ADC_FLAG_JSTRT ((uint32_t)ADC_SR_JSTRT) | |
376 #define ADC_FLAG_STRT ((uint32_t)ADC_SR_STRT) | |
377 #define ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR) | |
378 /** | |
379 * @} | |
380 */ | |
381 | |
382 /** @defgroup ADC_channels_type ADC Channels Type | |
383 * @{ | |
384 */ | |
385 #define ADC_ALL_CHANNELS ((uint32_t)0x00000001) | |
386 #define ADC_REGULAR_CHANNELS ((uint32_t)0x00000002) /*!< reserved for future use */ | |
387 #define ADC_INJECTED_CHANNELS ((uint32_t)0x00000003) /*!< reserved for future use */ | |
388 /** | |
389 * @} | |
390 */ | |
391 | |
392 /** | |
393 * @} | |
394 */ | |
395 | |
396 /* Exported macro ------------------------------------------------------------*/ | |
397 /** @defgroup ADC_Exported_Macros ADC Exported Macros | |
398 * @{ | |
399 */ | |
400 | |
401 /** @brief Reset ADC handle state | |
402 * @param __HANDLE__: ADC handle | |
403 * @retval None | |
404 */ | |
405 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET) | |
406 | |
407 /** | |
408 * @brief Enable the ADC peripheral. | |
409 * @param __HANDLE__: ADC handle | |
410 * @retval None | |
411 */ | |
412 #define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON) | |
413 | |
414 /** | |
415 * @brief Disable the ADC peripheral. | |
416 * @param __HANDLE__: ADC handle | |
417 * @retval None | |
418 */ | |
419 #define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON) | |
420 | |
421 /** | |
422 * @brief Enable the ADC end of conversion interrupt. | |
423 * @param __HANDLE__: specifies the ADC Handle. | |
424 * @param __INTERRUPT__: ADC Interrupt. | |
425 * @retval None | |
426 */ | |
427 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__)) | |
428 | |
429 /** | |
430 * @brief Disable the ADC end of conversion interrupt. | |
431 * @param __HANDLE__: specifies the ADC Handle. | |
432 * @param __INTERRUPT__: ADC interrupt. | |
433 * @retval None | |
434 */ | |
435 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__)) | |
436 | |
437 /** @brief Check if the specified ADC interrupt source is enabled or disabled. | |
438 * @param __HANDLE__: specifies the ADC Handle. | |
439 * @param __INTERRUPT__: specifies the ADC interrupt source to check. | |
440 * @retval The new state of __IT__ (TRUE or FALSE). | |
441 */ | |
442 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) | |
443 | |
444 /** | |
445 * @brief Clear the ADC's pending flags. | |
446 * @param __HANDLE__: specifies the ADC Handle. | |
447 * @param __FLAG__: ADC flag. | |
448 * @retval None | |
449 */ | |
450 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__)) | |
451 | |
452 /** | |
453 * @brief Get the selected ADC's flag status. | |
454 * @param __HANDLE__: specifies the ADC Handle. | |
455 * @param __FLAG__: ADC flag. | |
456 * @retval None | |
457 */ | |
458 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) | |
459 | |
460 /** | |
461 * @} | |
462 */ | |
463 | |
464 /* Include ADC HAL Extension module */ | |
465 #include "stm32f4xx_hal_adc_ex.h" | |
466 | |
467 /* Exported functions --------------------------------------------------------*/ | |
468 /** @addtogroup ADC_Exported_Functions | |
469 * @{ | |
470 */ | |
471 | |
472 /** @addtogroup ADC_Exported_Functions_Group1 | |
473 * @{ | |
474 */ | |
475 /* Initialization/de-initialization functions ***********************************/ | |
476 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); | |
477 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); | |
478 void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); | |
479 void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); | |
480 /** | |
481 * @} | |
482 */ | |
483 | |
484 /** @addtogroup ADC_Exported_Functions_Group2 | |
485 * @{ | |
486 */ | |
487 /* I/O operation functions ******************************************************/ | |
488 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); | |
489 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); | |
490 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); | |
491 | |
492 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); | |
493 | |
494 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); | |
495 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); | |
496 | |
497 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); | |
498 | |
499 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); | |
500 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); | |
501 | |
502 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); | |
503 | |
504 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); | |
505 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); | |
506 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); | |
507 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); | |
508 /** | |
509 * @} | |
510 */ | |
511 | |
512 /** @addtogroup ADC_Exported_Functions_Group3 | |
513 * @{ | |
514 */ | |
515 /* Peripheral Control functions *************************************************/ | |
516 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); | |
517 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); | |
518 /** | |
519 * @} | |
520 */ | |
521 | |
522 /** @addtogroup ADC_Exported_Functions_Group4 | |
523 * @{ | |
524 */ | |
525 /* Peripheral State functions ***************************************************/ | |
526 HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc); | |
527 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); | |
528 /** | |
529 * @} | |
530 */ | |
531 | |
532 /** | |
533 * @} | |
534 */ | |
535 /* Private types -------------------------------------------------------------*/ | |
536 /* Private variables ---------------------------------------------------------*/ | |
537 /* Private constants ---------------------------------------------------------*/ | |
538 /** @defgroup ADC_Private_Constants ADC Private Constants | |
539 * @{ | |
540 */ | |
541 | |
542 /** | |
543 * @} | |
544 */ | |
545 | |
546 /* Private macros ------------------------------------------------------------*/ | |
547 /** @defgroup ADC_Private_Macros ADC Private Macros | |
548 * @{ | |
549 */ | |
550 #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV2) || \ | |
551 ((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV4) || \ | |
552 ((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV6) || \ | |
553 ((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV8)) | |
554 #define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \ | |
555 ((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \ | |
556 ((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \ | |
557 ((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \ | |
558 ((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \ | |
559 ((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \ | |
560 ((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \ | |
561 ((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \ | |
562 ((DELAY) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \ | |
563 ((DELAY) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \ | |
564 ((DELAY) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \ | |
565 ((DELAY) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \ | |
566 ((DELAY) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \ | |
567 ((DELAY) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \ | |
568 ((DELAY) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \ | |
569 ((DELAY) == ADC_TWOSAMPLINGDELAY_20CYCLES)) | |
570 #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \ | |
571 ((RESOLUTION) == ADC_RESOLUTION_10B) || \ | |
572 ((RESOLUTION) == ADC_RESOLUTION_8B) || \ | |
573 ((RESOLUTION) == ADC_RESOLUTION_6B)) | |
574 #define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ | |
575 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ | |
576 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ | |
577 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)) | |
578 #define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ | |
579 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ | |
580 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \ | |
581 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ | |
582 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \ | |
583 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC4) || \ | |
584 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ | |
585 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \ | |
586 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ | |
587 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ | |
588 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || \ | |
589 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC2) || \ | |
590 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || \ | |
591 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \ | |
592 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \ | |
593 ((REGTRIG) == ADC_EXTERNALTRIGCONV_Ext_IT11)) | |
594 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ | |
595 ((ALIGN) == ADC_DATAALIGN_LEFT)) | |
596 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ | |
597 ((CHANNEL) == ADC_CHANNEL_1) || \ | |
598 ((CHANNEL) == ADC_CHANNEL_2) || \ | |
599 ((CHANNEL) == ADC_CHANNEL_3) || \ | |
600 ((CHANNEL) == ADC_CHANNEL_4) || \ | |
601 ((CHANNEL) == ADC_CHANNEL_5) || \ | |
602 ((CHANNEL) == ADC_CHANNEL_6) || \ | |
603 ((CHANNEL) == ADC_CHANNEL_7) || \ | |
604 ((CHANNEL) == ADC_CHANNEL_8) || \ | |
605 ((CHANNEL) == ADC_CHANNEL_9) || \ | |
606 ((CHANNEL) == ADC_CHANNEL_10) || \ | |
607 ((CHANNEL) == ADC_CHANNEL_11) || \ | |
608 ((CHANNEL) == ADC_CHANNEL_12) || \ | |
609 ((CHANNEL) == ADC_CHANNEL_13) || \ | |
610 ((CHANNEL) == ADC_CHANNEL_14) || \ | |
611 ((CHANNEL) == ADC_CHANNEL_15) || \ | |
612 ((CHANNEL) == ADC_CHANNEL_16) || \ | |
613 ((CHANNEL) == ADC_CHANNEL_17) || \ | |
614 ((CHANNEL) == ADC_CHANNEL_18)) | |
615 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_3CYCLES) || \ | |
616 ((TIME) == ADC_SAMPLETIME_15CYCLES) || \ | |
617 ((TIME) == ADC_SAMPLETIME_28CYCLES) || \ | |
618 ((TIME) == ADC_SAMPLETIME_56CYCLES) || \ | |
619 ((TIME) == ADC_SAMPLETIME_84CYCLES) || \ | |
620 ((TIME) == ADC_SAMPLETIME_112CYCLES) || \ | |
621 ((TIME) == ADC_SAMPLETIME_144CYCLES) || \ | |
622 ((TIME) == ADC_SAMPLETIME_480CYCLES)) | |
623 #define IS_ADC_EOCSelection(EOCSelection) (((EOCSelection) == ADC_EOC_SINGLE_CONV) || \ | |
624 ((EOCSelection) == ADC_EOC_SEQ_CONV) || \ | |
625 ((EOCSelection) == ADC_EOC_SINGLE_SEQ_CONV)) | |
626 #define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \ | |
627 ((EVENT) == ADC_OVR_EVENT)) | |
628 #define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ | |
629 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ | |
630 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ | |
631 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \ | |
632 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ | |
633 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) || \ | |
634 ((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE)) | |
635 #define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \ | |
636 ((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \ | |
637 ((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS)) | |
638 #define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= ((uint32_t)0xFFF)) | |
639 | |
640 #define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16))) | |
641 #define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= ((uint32_t)1)) && ((RANK) <= ((uint32_t)16))) | |
642 #define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8))) | |
643 #define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \ | |
644 ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \ | |
645 (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \ | |
646 (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= ((uint32_t)0x00FF))) || \ | |
647 (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= ((uint32_t)0x003F)))) | |
648 | |
649 /** | |
650 * @brief Set ADC Regular channel sequence length. | |
651 * @param _NbrOfConversion_: Regular channel sequence length. | |
652 * @retval None | |
653 */ | |
654 #define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20) | |
655 | |
656 /** | |
657 * @brief Set the ADC's sample time for channel numbers between 10 and 18. | |
658 * @param _SAMPLETIME_: Sample time parameter. | |
659 * @param _CHANNELNB_: Channel number. | |
660 * @retval None | |
661 */ | |
662 #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10))) | |
663 | |
664 /** | |
665 * @brief Set the ADC's sample time for channel numbers between 0 and 9. | |
666 * @param _SAMPLETIME_: Sample time parameter. | |
667 * @param _CHANNELNB_: Channel number. | |
668 * @retval None | |
669 */ | |
670 #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((uint32_t)((uint16_t)(_CHANNELNB_))))) | |
671 | |
672 /** | |
673 * @brief Set the selected regular channel rank for rank between 1 and 6. | |
674 * @param _CHANNELNB_: Channel number. | |
675 * @param _RANKNB_: Rank number. | |
676 * @retval None | |
677 */ | |
678 #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 1))) | |
679 | |
680 /** | |
681 * @brief Set the selected regular channel rank for rank between 7 and 12. | |
682 * @param _CHANNELNB_: Channel number. | |
683 * @param _RANKNB_: Rank number. | |
684 * @retval None | |
685 */ | |
686 #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 7))) | |
687 | |
688 /** | |
689 * @brief Set the selected regular channel rank for rank between 13 and 16. | |
690 * @param _CHANNELNB_: Channel number. | |
691 * @param _RANKNB_: Rank number. | |
692 * @retval None | |
693 */ | |
694 #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 13))) | |
695 | |
696 /** | |
697 * @brief Enable ADC continuous conversion mode. | |
698 * @param _CONTINUOUS_MODE_: Continuous mode. | |
699 * @retval None | |
700 */ | |
701 #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1) | |
702 | |
703 /** | |
704 * @brief Configures the number of discontinuous conversions for the regular group channels. | |
705 * @param _NBR_DISCONTINUOUSCONV_: Number of discontinuous conversions. | |
706 * @retval None | |
707 */ | |
708 #define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << 13) | |
709 | |
710 /** | |
711 * @brief Enable ADC scan mode. | |
712 * @param _SCANCONV_MODE_: Scan conversion mode. | |
713 * @retval None | |
714 */ | |
715 #define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8) | |
716 | |
717 /** | |
718 * @brief Enable the ADC end of conversion selection. | |
719 * @param _EOCSelection_MODE_: End of conversion selection mode. | |
720 * @retval None | |
721 */ | |
722 #define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10) | |
723 | |
724 /** | |
725 * @brief Enable the ADC DMA continuous request. | |
726 * @param _DMAContReq_MODE_: DMA continuous request mode. | |
727 * @retval None | |
728 */ | |
729 #define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9) | |
730 | |
731 /** | |
732 * @brief Return resolution bits in CR1 register. | |
733 * @param __HANDLE__: ADC handle | |
734 * @retval None | |
735 */ | |
736 #define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES) | |
737 | |
738 /** | |
739 * @} | |
740 */ | |
741 | |
742 /* Private functions ---------------------------------------------------------*/ | |
743 /** @defgroup ADC_Private_Functions ADC Private Functions | |
744 * @{ | |
745 */ | |
746 | |
747 /** | |
748 * @} | |
749 */ | |
750 | |
751 /** | |
752 * @} | |
753 */ | |
754 | |
755 /** | |
756 * @} | |
757 */ | |
758 | |
759 #ifdef __cplusplus | |
760 } | |
761 #endif | |
762 | |
763 #endif /*__STM32F4xx_ADC_H */ | |
764 | |
765 | |
766 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |