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1 /**************************************************************************//**
2 * @file core_cm4.h
3 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
4 * @version V2.10
5 * @date 19. July 2011
6 *
7 * @note
8 * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
9 *
10 * @par
11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
12 * processor based microcontrollers. This file can be freely distributed
13 * within development tools that are supporting such ARM based processors.
14 *
15 * @par
16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
21 *
22 ******************************************************************************/
23 #if defined ( __ICCARM__ )
24 #pragma system_include /* treat file as system include file for MISRA check */
25 #endif
26
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30
31 #ifndef __CORE_CM4_H_GENERIC
32 #define __CORE_CM4_H_GENERIC
33
34
35 /** \mainpage CMSIS Cortex-M4
36
37 This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
38 It consists of:
39
40 - Cortex-M Core Register Definitions
41 - Cortex-M functions
42 - Cortex-M instructions
43 - Cortex-M SIMD instructions
44
45 The CMSIS Cortex-M4 Core Peripheral Access Layer contains C and assembly functions that ease
46 access to the Cortex-M Core
47 */
48
49 /** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions
50 CMSIS violates following MISRA-C2004 Rules:
51
52 - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.<br>
53 Function definitions in header files are used to allow 'inlining'.
54
55 - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
56 Unions are used for effective representation of core registers.
57
58 - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.<br>
59 Function-like macros are used to allow more efficient code.
60
61 */
62
63
64 /*******************************************************************************
65 * CMSIS definitions
66 ******************************************************************************/
67 /** \defgroup CMSIS_core_definitions CMSIS Core Definitions
68 This file defines all structures and symbols for CMSIS core:
69 - CMSIS version number
70 - Cortex-M core
71 - Cortex-M core Revision Number
72 @{
73 */
74
75 /* CMSIS CM4 definitions */
76 #define __CM4_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */
77 #define __CM4_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */
78 #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | __CM4_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
79
80 #define __CORTEX_M (0x04) /*!< Cortex core */
81
82
83 #if defined ( __CC_ARM )
84 #define __ASM __asm /*!< asm keyword for ARM Compiler */
85 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
86
87 #elif defined ( __ICCARM__ )
88 #define __ASM __asm /*!< asm keyword for IAR Compiler */
89 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
90
91 #elif defined ( __GNUC__ )
92 #define __ASM __asm /*!< asm keyword for GNU Compiler */
93 #define __INLINE inline /*!< inline keyword for GNU Compiler */
94
95 #elif defined ( __TASKING__ )
96 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
97 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
98
99 #endif
100
101 /*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */
102 #if defined ( __CC_ARM )
103 #if defined __TARGET_FPU_VFP
104 #if (__FPU_PRESENT == 1)
105 #define __FPU_USED 1
106 #else
107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
108 #define __FPU_USED 0
109 #endif
110 #else
111 #define __FPU_USED 0
112 #endif
113
114 #elif defined ( __ICCARM__ )
115 #if defined __ARMVFP__
116 #if (__FPU_PRESENT == 1)
117 #define __FPU_USED 1
118 #else
119 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
120 #define __FPU_USED 0
121 #endif
122 #else
123 #define __FPU_USED 0
124 #endif
125
126 #elif defined ( __GNUC__ )
127 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
128 #if (__FPU_PRESENT == 1)
129 #define __FPU_USED 1
130 #else
131 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
132 #define __FPU_USED 0
133 #endif
134 #else
135 #define __FPU_USED 0
136 #endif
137
138 #elif defined ( __TASKING__ )
139 /* add preprocessor checks to define __FPU_USED */
140 #define __FPU_USED 0
141 #endif
142
143 #include <stdint.h> /*!< standard types definitions */
144 #include <core_cmInstr.h> /*!< Core Instruction Access */
145 #include <core_cmFunc.h> /*!< Core Function Access */
146 #include <core_cm4_simd.h> /*!< Compiler specific SIMD Intrinsics */
147
148 #endif /* __CORE_CM4_H_GENERIC */
149
150 #ifndef __CMSIS_GENERIC
151
152 #ifndef __CORE_CM4_H_DEPENDANT
153 #define __CORE_CM4_H_DEPENDANT
154
155 /* check device defines and use defaults */
156 #if defined __CHECK_DEVICE_DEFINES
157 #ifndef __CM4_REV
158 #define __CM4_REV 0x0000
159 #warning "__CM4_REV not defined in device header file; using default!"
160 #endif
161
162 #ifndef __FPU_PRESENT
163 #define __FPU_PRESENT 0
164 #warning "__FPU_PRESENT not defined in device header file; using default!"
165 #endif
166
167 #ifndef __MPU_PRESENT
168 #define __MPU_PRESENT 0
169 #warning "__MPU_PRESENT not defined in device header file; using default!"
170 #endif
171
172 #ifndef __NVIC_PRIO_BITS
173 #define __NVIC_PRIO_BITS 4
174 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
175 #endif
176
177 #ifndef __Vendor_SysTickConfig
178 #define __Vendor_SysTickConfig 0
179 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
180 #endif
181 #endif
182
183 /* IO definitions (access restrictions to peripheral registers) */
184 #ifdef __cplusplus
185 #define __I volatile /*!< defines 'read only' permissions */
186 #else
187 #define __I volatile const /*!< defines 'read only' permissions */
188 #endif
189 #define __O volatile /*!< defines 'write only' permissions */
190 #define __IO volatile /*!< defines 'read / write' permissions */
191
192 /*@} end of group CMSIS_core_definitions */
193
194
195
196 /*******************************************************************************
197 * Register Abstraction
198 ******************************************************************************/
199 /** \defgroup CMSIS_core_register CMSIS Core Register
200 Core Register contain:
201 - Core Register
202 - Core NVIC Register
203 - Core SCB Register
204 - Core SysTick Register
205 - Core Debug Register
206 - Core MPU Register
207 - Core FPU Register
208 */
209
210 /** \ingroup CMSIS_core_register
211 \defgroup CMSIS_CORE CMSIS Core
212 Type definitions for the Cortex-M Core Registers
213 @{
214 */
215
216 /** \brief Union type to access the Application Program Status Register (APSR).
217 */
218 typedef union
219 {
220 struct
221 {
222 #if (__CORTEX_M != 0x04)
223 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
224 #else
225 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
226 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
227 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
228 #endif
229 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
230 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
231 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
232 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
233 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
234 } b; /*!< Structure used for bit access */
235 uint32_t w; /*!< Type used for word access */
236 } APSR_Type;
237
238
239 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
240 */
241 typedef union
242 {
243 struct
244 {
245 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
246 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
247 } b; /*!< Structure used for bit access */
248 uint32_t w; /*!< Type used for word access */
249 } IPSR_Type;
250
251
252 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
253 */
254 typedef union
255 {
256 struct
257 {
258 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
259 #if (__CORTEX_M != 0x04)
260 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
261 #else
262 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
263 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
264 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
265 #endif
266 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
267 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
268 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
269 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
270 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
271 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
272 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
273 } b; /*!< Structure used for bit access */
274 uint32_t w; /*!< Type used for word access */
275 } xPSR_Type;
276
277
278 /** \brief Union type to access the Control Registers (CONTROL).
279 */
280 typedef union
281 {
282 struct
283 {
284 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
285 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
286 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
287 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
288 } b; /*!< Structure used for bit access */
289 uint32_t w; /*!< Type used for word access */
290 } CONTROL_Type;
291
292 /*@} end of group CMSIS_CORE */
293
294
295 /** \ingroup CMSIS_core_register
296 \defgroup CMSIS_NVIC CMSIS NVIC
297 Type definitions for the Cortex-M NVIC Registers
298 @{
299 */
300
301 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
302 */
303 typedef struct
304 {
305 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
306 uint32_t RESERVED0[24];
307 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
308 uint32_t RSERVED1[24];
309 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
310 uint32_t RESERVED2[24];
311 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
312 uint32_t RESERVED3[24];
313 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
314 uint32_t RESERVED4[56];
315 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
316 uint32_t RESERVED5[644];
317 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
318 } NVIC_Type;
319
320 /* Software Triggered Interrupt Register Definitions */
321 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
322 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
323
324 /*@} end of group CMSIS_NVIC */
325
326
327 /** \ingroup CMSIS_core_register
328 \defgroup CMSIS_SCB CMSIS SCB
329 Type definitions for the Cortex-M System Control Block Registers
330 @{
331 */
332
333 /** \brief Structure type to access the System Control Block (SCB).
334 */
335 typedef struct
336 {
337 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
338 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
339 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
340 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
341 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
342 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
343 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
344 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
345 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
346 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
347 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
348 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
349 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
350 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
351 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
352 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
353 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
354 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
355 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
356 uint32_t RESERVED0[5];
357 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
358 } SCB_Type;
359
360 /* SCB CPUID Register Definitions */
361 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
362 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
363
364 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
365 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
366
367 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
368 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
369
370 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
371 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
372
373 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
374 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
375
376 /* SCB Interrupt Control State Register Definitions */
377 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
378 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
379
380 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
381 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
382
383 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
384 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
385
386 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
387 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
388
389 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
390 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
391
392 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
393 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
394
395 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
396 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
397
398 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
399 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
400
401 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
402 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
403
404 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
405 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
406
407 /* SCB Vector Table Offset Register Definitions */
408 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
409 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
410
411 /* SCB Application Interrupt and Reset Control Register Definitions */
412 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
413 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
414
415 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
416 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
417
418 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
419 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
420
421 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
422 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
423
424 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
425 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
426
427 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
428 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
429
430 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
431 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
432
433 /* SCB System Control Register Definitions */
434 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
435 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
436
437 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
438 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
439
440 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
441 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
442
443 /* SCB Configuration Control Register Definitions */
444 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
445 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
446
447 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
448 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
449
450 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
451 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
452
453 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
454 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
455
456 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
457 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
458
459 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
460 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
461
462 /* SCB System Handler Control and State Register Definitions */
463 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
464 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
465
466 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
467 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
468
469 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
470 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
471
472 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
473 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
474
475 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
476 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
477
478 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
479 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
480
481 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
482 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
483
484 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
485 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
486
487 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
488 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
489
490 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
491 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
492
493 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
494 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
495
496 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
497 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
498
499 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
500 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
501
502 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
503 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
504
505 /* SCB Configurable Fault Status Registers Definitions */
506 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
507 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
508
509 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
510 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
511
512 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
513 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
514
515 /* SCB Hard Fault Status Registers Definitions */
516 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
517 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
518
519 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
520 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
521
522 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
523 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
524
525 /* SCB Debug Fault Status Register Definitions */
526 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
527 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
528
529 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
530 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
531
532 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
533 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
534
535 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
536 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
537
538 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
539 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
540
541 /*@} end of group CMSIS_SCB */
542
543
544 /** \ingroup CMSIS_core_register
545 \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB
546 Type definitions for the Cortex-M System Control and ID Register not in the SCB
547 @{
548 */
549
550 /** \brief Structure type to access the System Control and ID Register not in the SCB.
551 */
552 typedef struct
553 {
554 uint32_t RESERVED0[1];
555 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
556 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
557 } SCnSCB_Type;
558
559 /* Interrupt Controller Type Register Definitions */
560 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
561 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
562
563 /* Auxiliary Control Register Definitions */
564 #define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
565 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
566
567 #define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
568 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
569
570 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
571 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
572
573 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
574 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
575
576 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
577 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
578
579 /*@} end of group CMSIS_SCnotSCB */
580
581
582 /** \ingroup CMSIS_core_register
583 \defgroup CMSIS_SysTick CMSIS SysTick
584 Type definitions for the Cortex-M System Timer Registers
585 @{
586 */
587
588 /** \brief Structure type to access the System Timer (SysTick).
589 */
590 typedef struct
591 {
592 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
593 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
594 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
595 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
596 } SysTick_Type;
597
598 /* SysTick Control / Status Register Definitions */
599 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
600 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
601
602 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
603 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
604
605 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
606 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
607
608 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
609 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
610
611 /* SysTick Reload Register Definitions */
612 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
613 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
614
615 /* SysTick Current Register Definitions */
616 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
617 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
618
619 /* SysTick Calibration Register Definitions */
620 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
621 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
622
623 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
624 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
625
626 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
627 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
628
629 /*@} end of group CMSIS_SysTick */
630
631
632 /** \ingroup CMSIS_core_register
633 \defgroup CMSIS_ITM CMSIS ITM
634 Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)
635 @{
636 */
637
638 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
639 */
640 typedef struct
641 {
642 __O union
643 {
644 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
645 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
646 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
647 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
648 uint32_t RESERVED0[864];
649 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
650 uint32_t RESERVED1[15];
651 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
652 uint32_t RESERVED2[15];
653 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
654 } ITM_Type;
655
656 /* ITM Trace Privilege Register Definitions */
657 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
658 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
659
660 /* ITM Trace Control Register Definitions */
661 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
662 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
663
664 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
665 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
666
667 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
668 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
669
670 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
671 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
672
673 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
674 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
675
676 #define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */
677 #define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */
678
679 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
680 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
681
682 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
683 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
684
685 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
686 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
687
688 /*@}*/ /* end of group CMSIS_ITM */
689
690
691 #if (__MPU_PRESENT == 1)
692 /** \ingroup CMSIS_core_register
693 \defgroup CMSIS_MPU CMSIS MPU
694 Type definitions for the Cortex-M Memory Protection Unit (MPU)
695 @{
696 */
697
698 /** \brief Structure type to access the Memory Protection Unit (MPU).
699 */
700 typedef struct
701 {
702 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
703 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
704 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
705 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
706 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
707 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
708 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
709 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
710 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
711 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
712 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
713 } MPU_Type;
714
715 /* MPU Type Register */
716 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
717 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
718
719 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
720 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
721
722 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
723 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
724
725 /* MPU Control Register */
726 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
727 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
728
729 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
730 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
731
732 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
733 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
734
735 /* MPU Region Number Register */
736 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
737 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
738
739 /* MPU Region Base Address Register */
740 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
741 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
742
743 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
744 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
745
746 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
747 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
748
749 /* MPU Region Attribute and Size Register */
750 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
751 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
752
753 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
754 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
755
756 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
757 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
758
759 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
760 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
761
762 /*@} end of group CMSIS_MPU */
763 #endif
764
765
766 #if (__FPU_PRESENT == 1)
767 /** \ingroup CMSIS_core_register
768 \defgroup CMSIS_FPU CMSIS FPU
769 Type definitions for the Cortex-M Floating Point Unit (FPU)
770 @{
771 */
772
773 /** \brief Structure type to access the Floating Point Unit (FPU).
774 */
775 typedef struct
776 {
777 uint32_t RESERVED0[1];
778 __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
779 __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
780 __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
781 __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
782 __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
783 } FPU_Type;
784
785 /* Floating-Point Context Control Register */
786 #define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
787 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
788
789 #define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
790 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
791
792 #define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
793 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
794
795 #define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
796 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
797
798 #define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
799 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
800
801 #define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
802 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
803
804 #define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
805 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
806
807 #define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
808 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
809
810 #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
811 #define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */
812
813 /* Floating-Point Context Address Register */
814 #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
815 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
816
817 /* Floating-Point Default Status Control Register */
818 #define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
819 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
820
821 #define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
822 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
823
824 #define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
825 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
826
827 #define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
828 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
829
830 /* Media and FP Feature Register 0 */
831 #define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
832 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
833
834 #define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
835 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
836
837 #define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
838 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
839
840 #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
841 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
842
843 #define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
844 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
845
846 #define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
847 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
848
849 #define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
850 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
851
852 #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
853 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */
854
855 /* Media and FP Feature Register 1 */
856 #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
857 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
858
859 #define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
860 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
861
862 #define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
863 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
864
865 #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
866 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */
867
868 /*@} end of group CMSIS_FPU */
869 #endif
870
871
872 /** \ingroup CMSIS_core_register
873 \defgroup CMSIS_CoreDebug CMSIS Core Debug
874 Type definitions for the Cortex-M Core Debug Registers
875 @{
876 */
877
878 /** \brief Structure type to access the Core Debug Register (CoreDebug).
879 */
880 typedef struct
881 {
882 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
883 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
884 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
885 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
886 } CoreDebug_Type;
887
888 /* Debug Halting Control and Status Register */
889 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
890 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
891
892 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
893 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
894
895 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
896 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
897
898 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
899 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
900
901 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
902 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
903
904 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
905 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
906
907 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
908 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
909
910 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
911 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
912
913 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
914 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
915
916 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
917 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
918
919 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
920 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
921
922 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
923 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
924
925 /* Debug Core Register Selector Register */
926 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
927 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
928
929 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
930 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
931
932 /* Debug Exception and Monitor Control Register */
933 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
934 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
935
936 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
937 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
938
939 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
940 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
941
942 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
943 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
944
945 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
946 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
947
948 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
949 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
950
951 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
952 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
953
954 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
955 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
956
957 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
958 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
959
960 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
961 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
962
963 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
964 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
965
966 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
967 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
968
969 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
970 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
971
972 /*@} end of group CMSIS_CoreDebug */
973
974
975 /** \ingroup CMSIS_core_register
976 @{
977 */
978
979 /* Memory mapping of Cortex-M4 Hardware */
980 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
981 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
982 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
983 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
984 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
985 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
986
987 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
988 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
989 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
990 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
991 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
992 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
993
994 #if (__MPU_PRESENT == 1)
995 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
996 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
997 #endif
998
999 #if (__FPU_PRESENT == 1)
1000 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
1001 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
1002 #endif
1003
1004 /*@} */
1005
1006
1007
1008 /*******************************************************************************
1009 * Hardware Abstraction Layer
1010 ******************************************************************************/
1011 /** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
1012 Core Function Interface contains:
1013 - Core NVIC Functions
1014 - Core SysTick Functions
1015 - Core Debug Functions
1016 - Core Register Access Functions
1017 */
1018
1019
1020
1021 /* ########################## NVIC functions #################################### */
1022 /** \ingroup CMSIS_Core_FunctionInterface
1023 \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
1024 @{
1025 */
1026
1027 /** \brief Set Priority Grouping
1028
1029 This function sets the priority grouping field using the required unlock sequence.
1030 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
1031 Only values from 0..7 are used.
1032 In case of a conflict between priority grouping and available
1033 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
1034
1035 \param [in] PriorityGroup Priority grouping field
1036 */
1037 static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1038 {
1039 uint32_t reg_value;
1040 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
1041
1042 reg_value = SCB->AIRCR; /* read old register configuration */
1043 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
1044 reg_value = (reg_value |
1045 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1046 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
1047 SCB->AIRCR = reg_value;
1048 }
1049
1050
1051 /** \brief Get Priority Grouping
1052
1053 This function gets the priority grouping from NVIC Interrupt Controller.
1054 Priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
1055
1056 \return Priority grouping field
1057 */
1058 static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
1059 {
1060 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
1061 }
1062
1063
1064 /** \brief Enable External Interrupt
1065
1066 This function enables a device specific interrupt in the NVIC interrupt controller.
1067 The interrupt number cannot be a negative value.
1068
1069 \param [in] IRQn Number of the external interrupt to enable
1070 */
1071 static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
1072 {
1073 /* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
1074 NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
1075 }
1076
1077
1078 /** \brief Disable External Interrupt
1079
1080 This function disables a device specific interrupt in the NVIC interrupt controller.
1081 The interrupt number cannot be a negative value.
1082
1083 \param [in] IRQn Number of the external interrupt to disable
1084 */
1085 static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
1086 {
1087 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
1088 }
1089
1090
1091 /** \brief Get Pending Interrupt
1092
1093 This function reads the pending register in the NVIC and returns the pending bit
1094 for the specified interrupt.
1095
1096 \param [in] IRQn Number of the interrupt for get pending
1097 \return 0 Interrupt status is not pending
1098 \return 1 Interrupt status is pending
1099 */
1100 static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
1101 {
1102 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
1103 }
1104
1105
1106 /** \brief Set Pending Interrupt
1107
1108 This function sets the pending bit for the specified interrupt.
1109 The interrupt number cannot be a negative value.
1110
1111 \param [in] IRQn Number of the interrupt for set pending
1112 */
1113 static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
1114 {
1115 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
1116 }
1117
1118
1119 /** \brief Clear Pending Interrupt
1120
1121 This function clears the pending bit for the specified interrupt.
1122 The interrupt number cannot be a negative value.
1123
1124 \param [in] IRQn Number of the interrupt for clear pending
1125 */
1126 static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1127 {
1128 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
1129 }
1130
1131
1132 /** \brief Get Active Interrupt
1133
1134 This function reads the active register in NVIC and returns the active bit.
1135 \param [in] IRQn Number of the interrupt for get active
1136 \return 0 Interrupt status is not active
1137 \return 1 Interrupt status is active
1138 */
1139 static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
1140 {
1141 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
1142 }
1143
1144
1145 /** \brief Set Interrupt Priority
1146
1147 This function sets the priority for the specified interrupt. The interrupt
1148 number can be positive to specify an external (device specific)
1149 interrupt, or negative to specify an internal (core) interrupt.
1150
1151 Note: The priority cannot be set for every core interrupt.
1152
1153 \param [in] IRQn Number of the interrupt for set priority
1154 \param [in] priority Priority to set
1155 */
1156 static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1157 {
1158 if(IRQn < 0) {
1159 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
1160 else {
1161 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
1162 }
1163
1164
1165 /** \brief Get Interrupt Priority
1166
1167 This function reads the priority for the specified interrupt. The interrupt
1168 number can be positive to specify an external (device specific)
1169 interrupt, or negative to specify an internal (core) interrupt.
1170
1171 The returned priority value is automatically aligned to the implemented
1172 priority bits of the microcontroller.
1173
1174 \param [in] IRQn Number of the interrupt for get priority
1175 \return Interrupt Priority
1176 */
1177 static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
1178 {
1179
1180 if(IRQn < 0) {
1181 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
1182 else {
1183 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
1184 }
1185
1186
1187 /** \brief Encode Priority
1188
1189 This function encodes the priority for an interrupt with the given priority group,
1190 preemptive priority value and sub priority value.
1191 In case of a conflict between priority grouping and available
1192 priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
1193
1194 The returned priority value can be used for NVIC_SetPriority(...) function
1195
1196 \param [in] PriorityGroup Used priority group
1197 \param [in] PreemptPriority Preemptive priority value (starting from 0)
1198 \param [in] SubPriority Sub priority value (starting from 0)
1199 \return Encoded priority for the interrupt
1200 */
1201 static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1202 {
1203 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1204 uint32_t PreemptPriorityBits;
1205 uint32_t SubPriorityBits;
1206
1207 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1208 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1209
1210 return (
1211 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
1212 ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
1213 );
1214 }
1215
1216
1217 /** \brief Decode Priority
1218
1219 This function decodes an interrupt priority value with the given priority group to
1220 preemptive priority value and sub priority value.
1221 In case of a conflict between priority grouping and available
1222 priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
1223
1224 The priority value can be retrieved with NVIC_GetPriority(...) function
1225
1226 \param [in] Priority Priority value
1227 \param [in] PriorityGroup Used priority group
1228 \param [out] pPreemptPriority Preemptive priority value (starting from 0)
1229 \param [out] pSubPriority Sub priority value (starting from 0)
1230 */
1231 static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
1232 {
1233 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1234 uint32_t PreemptPriorityBits;
1235 uint32_t SubPriorityBits;
1236
1237 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1238 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1239
1240 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
1241 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
1242 }
1243
1244
1245 /** \brief System Reset
1246
1247 This function initiate a system reset request to reset the MCU.
1248 */
1249 static __INLINE void NVIC_SystemReset(void)
1250 {
1251 __DSB(); /* Ensure all outstanding memory accesses included
1252 buffered write are completed before reset */
1253 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1254 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1255 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
1256 __DSB(); /* Ensure completion of memory access */
1257 while(1); /* wait until reset */
1258 }
1259
1260 /*@} end of CMSIS_Core_NVICFunctions */
1261
1262
1263
1264 /* ################################## SysTick function ############################################ */
1265 /** \ingroup CMSIS_Core_FunctionInterface
1266 \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
1267 @{
1268 */
1269
1270 #if (__Vendor_SysTickConfig == 0)
1271
1272 /** \brief System Tick Configuration
1273
1274 This function initialises the system tick timer and its interrupt and start the system tick timer.
1275 Counter is in free running mode to generate periodical interrupts.
1276
1277 \param [in] ticks Number of ticks between two interrupts
1278 \return 0 Function succeeded
1279 \return 1 Function failed
1280 */
1281 static __INLINE uint32_t SysTick_Config(uint32_t ticks)
1282 {
1283 if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
1284
1285 SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
1286 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
1287 SysTick->VAL = 0; /* Load the SysTick Counter Value */
1288 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1289 SysTick_CTRL_TICKINT_Msk |
1290 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1291 return (0); /* Function successful */
1292 }
1293
1294 #endif
1295
1296 /*@} end of CMSIS_Core_SysTickFunctions */
1297
1298
1299
1300 /* ##################################### Debug In/Output function ########################################### */
1301 /** \ingroup CMSIS_Core_FunctionInterface
1302 \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions
1303 @{
1304 */
1305
1306 extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */
1307 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
1308
1309
1310 /** \brief ITM Send Character
1311
1312 This function transmits a character via the ITM channel 0.
1313 It just returns when no debugger is connected that has booked the output.
1314 It is blocking when a debugger is connected, but the previous character send is not transmitted.
1315
1316 \param [in] ch Character to transmit
1317 \return Character to transmit
1318 */
1319 static __INLINE uint32_t ITM_SendChar (uint32_t ch)
1320 {
1321 if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */
1322 (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
1323 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
1324 {
1325 while (ITM->PORT[0].u32 == 0);
1326 ITM->PORT[0].u8 = (uint8_t) ch;
1327 }
1328 return (ch);
1329 }
1330
1331
1332 /** \brief ITM Receive Character
1333
1334 This function inputs a character via external variable ITM_RxBuffer.
1335 It just returns when no debugger is connected that has booked the output.
1336 It is blocking when a debugger is connected, but the previous character send is not transmitted.
1337
1338 \return Received character
1339 \return -1 No character received
1340 */
1341 static __INLINE int32_t ITM_ReceiveChar (void) {
1342 int32_t ch = -1; /* no character available */
1343
1344 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
1345 ch = ITM_RxBuffer;
1346 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
1347 }
1348
1349 return (ch);
1350 }
1351
1352
1353 /** \brief ITM Check Character
1354
1355 This function checks external variable ITM_RxBuffer whether a character is available or not.
1356 It returns '1' if a character is available and '0' if no character is available.
1357
1358 \return 0 No character available
1359 \return 1 Character available
1360 */
1361 static __INLINE int32_t ITM_CheckChar (void) {
1362
1363 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
1364 return (0); /* no character available */
1365 } else {
1366 return (1); /* character available */
1367 }
1368 }
1369
1370 /*@} end of CMSIS_core_DebugFunctions */
1371
1372 #endif /* __CORE_CM4_H_DEPENDANT */
1373
1374 #endif /* __CMSIS_GENERIC */
1375
1376 #ifdef __cplusplus
1377 }
1378 #endif