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CLEAN retrieve original startup code. reset linker script.
author jDG
date Mon, 18 Dec 2017 14:03:55 +0100
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children 4e10a3e087a1
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6:b355f462c952 7:2de06b1abed3
1 /**
2 ******************************************************************************
3 * @file system_stm32f4xx.c
4 * @author MCD Application Team
5 * @version V2.1.0
6 * @date 19-June-2014
7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
8 *
9 * This file provides two functions and one global variable to be called from
10 * user application:
11 * - SystemInit(): This function is called at startup just after reset and
12 * before branch to main program. This call is made inside
13 * the "startup_stm32f4xx.s" file.
14 *
15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
16 * by the user application to setup the SysTick
17 * timer or configure other parameters.
18 *
19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
20 * be called whenever the core clock is changed
21 * during program execution.
22 *
23 *
24 ******************************************************************************
25 * @attention
26 *
27 * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
28 *
29 * Redistribution and use in source and binary forms, with or without modification,
30 * are permitted provided that the following conditions are met:
31 * 1. Redistributions of source code must retain the above copyright notice,
32 * this list of conditions and the following disclaimer.
33 * 2. Redistributions in binary form must reproduce the above copyright notice,
34 * this list of conditions and the following disclaimer in the documentation
35 * and/or other materials provided with the distribution.
36 * 3. Neither the name of STMicroelectronics nor the names of its contributors
37 * may be used to endorse or promote products derived from this software
38 * without specific prior written permission.
39 *
40 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
41 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
43 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
46 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
47 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
48 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
49 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
50 *
51 ******************************************************************************
52 */
53
54 /** @addtogroup CMSIS
55 * @{
56 */
57
58 /** @addtogroup stm32f4xx_system
59 * @{
60 */
61
62 /** @addtogroup STM32F4xx_System_Private_Includes
63 * @{
64 */
65
66
67 #include "stm32f4xx.h"
68
69 #if !defined (HSE_VALUE)
70 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
71 #endif /* HSE_VALUE */
72
73 #if !defined (HSI_VALUE)
74 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
75 #endif /* HSI_VALUE */
76
77 /**
78 * @}
79 */
80
81 /** @addtogroup STM32F4xx_System_Private_TypesDefinitions
82 * @{
83 */
84
85 /**
86 * @}
87 */
88
89 /** @addtogroup STM32F4xx_System_Private_Defines
90 * @{
91 */
92
93 /************************* Miscellaneous Configuration ************************/
94 /*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
95 on STM324xG_EVAL/STM324x9I_EVAL boards as data memory */
96 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
97 /* #define DATA_IN_ExtSRAM */
98 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
99
100 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
101 /* #define DATA_IN_ExtSDRAM */
102 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
103
104 #if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
105 #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM "
106 #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
107
108 /*!< Uncomment the following line if you need to relocate your vector Table in
109 Internal SRAM. */
110 /* #define VECT_TAB_SRAM */
111 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
112 This value must be a multiple of 0x200. */
113 /******************************************************************************/
114
115 /**
116 * @}
117 */
118
119 /** @addtogroup STM32F4xx_System_Private_Macros
120 * @{
121 */
122
123 /**
124 * @}
125 */
126
127 /** @addtogroup STM32F4xx_System_Private_Variables
128 * @{
129 */
130 /* This variable is updated in three ways:
131 1) by calling CMSIS function SystemCoreClockUpdate()
132 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
133 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
134 Note: If you use this function to configure the system clock; then there
135 is no need to call the 2 first functions listed above, since SystemCoreClock
136 variable is updated automatically.
137 */
138 uint32_t SystemCoreClock = 16000000;
139 __IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
140
141 /**
142 * @}
143 */
144
145 /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
146 * @{
147 */
148
149 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
150 static void SystemInit_ExtMemCtl(void);
151 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
152
153 /**
154 * @}
155 */
156
157 /** @addtogroup STM32F4xx_System_Private_Functions
158 * @{
159 */
160
161 /**
162 * @brief Setup the microcontroller system
163 * Initialize the FPU setting, vector table location and External memory
164 * configuration.
165 * @param None
166 * @retval None
167 */
168 void SystemInit(void)
169 {
170 /* FPU settings ------------------------------------------------------------*/
171 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
172 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
173 #endif
174 /* Reset the RCC clock configuration to the default reset state ------------*/
175 /* Set HSION bit */
176 RCC->CR |= (uint32_t)0x00000001;
177
178 /* Reset CFGR register */
179 RCC->CFGR = 0x00000000;
180
181 /* Reset HSEON, CSSON and PLLON bits */
182 RCC->CR &= (uint32_t)0xFEF6FFFF;
183
184 /* Reset PLLCFGR register */
185 RCC->PLLCFGR = 0x24003010;
186
187 /* Reset HSEBYP bit */
188 RCC->CR &= (uint32_t)0xFFFBFFFF;
189
190 /* Disable all interrupts */
191 RCC->CIR = 0x00000000;
192
193 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
194 SystemInit_ExtMemCtl();
195 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
196
197 /* Configure the Vector Table location add offset address ------------------*/
198 #ifdef VECT_TAB_SRAM
199 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
200 #else
201 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
202 #endif
203 }
204
205 /**
206 * @brief Update SystemCoreClock variable according to Clock Register Values.
207 * The SystemCoreClock variable contains the core clock (HCLK), it can
208 * be used by the user application to setup the SysTick timer or configure
209 * other parameters.
210 *
211 * @note Each time the core clock (HCLK) changes, this function must be called
212 * to update SystemCoreClock variable value. Otherwise, any configuration
213 * based on this variable will be incorrect.
214 *
215 * @note - The system frequency computed by this function is not the real
216 * frequency in the chip. It is calculated based on the predefined
217 * constant and the selected clock source:
218 *
219 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
220 *
221 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
222 *
223 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
224 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
225 *
226 * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
227 * 16 MHz) but the real value may vary depending on the variations
228 * in voltage and temperature.
229 *
230 * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
231 * depends on the application requirements), user has to ensure that HSE_VALUE
232 * is same as the real frequency of the crystal used. Otherwise, this function
233 * may have wrong result.
234 *
235 * - The result of this function could be not correct when using fractional
236 * value for HSE crystal.
237 *
238 * @param None
239 * @retval None
240 */
241 void SystemCoreClockUpdate(void)
242 {
243 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
244
245 /* Get SYSCLK source -------------------------------------------------------*/
246 tmp = RCC->CFGR & RCC_CFGR_SWS;
247
248 switch (tmp)
249 {
250 case 0x00: /* HSI used as system clock source */
251 SystemCoreClock = HSI_VALUE;
252 break;
253 case 0x04: /* HSE used as system clock source */
254 SystemCoreClock = HSE_VALUE;
255 break;
256 case 0x08: /* PLL used as system clock source */
257
258 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
259 SYSCLK = PLL_VCO / PLL_P
260 */
261 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
262 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
263
264 if (pllsource != 0)
265 {
266 /* HSE used as PLL clock source */
267 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
268 }
269 else
270 {
271 /* HSI used as PLL clock source */
272 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
273 }
274
275 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
276 SystemCoreClock = pllvco/pllp;
277 break;
278 default:
279 SystemCoreClock = HSI_VALUE;
280 break;
281 }
282 /* Compute HCLK frequency --------------------------------------------------*/
283 /* Get HCLK prescaler */
284 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
285 /* HCLK frequency */
286 SystemCoreClock >>= tmp;
287 }
288
289 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
290 /**
291 * @brief Setup the external memory controller.
292 * Called in startup_stm32f4xx.s before jump to main.
293 * This function configures the external memories (SRAM/SDRAM)
294 * This SRAM/SDRAM will be used as program data memory (including heap and stack).
295 * @param None
296 * @retval None
297 */
298 void SystemInit_ExtMemCtl(void)
299 {
300 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
301 #if defined (DATA_IN_ExtSDRAM)
302 register uint32_t tmpreg = 0, timeout = 0xFFFF;
303 register uint32_t index;
304
305 /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
306 clock */
307 RCC->AHB1ENR |= 0x000001F8;
308
309 /* Connect PDx pins to FMC Alternate function */
310 GPIOD->AFR[0] = 0x000000CC;
311 GPIOD->AFR[1] = 0xCC000CCC;
312 /* Configure PDx pins in Alternate function mode */
313 GPIOD->MODER = 0xA02A000A;
314 /* Configure PDx pins speed to 50 MHz */
315 GPIOD->OSPEEDR = 0xA02A000A;
316 /* Configure PDx pins Output type to push-pull */
317 GPIOD->OTYPER = 0x00000000;
318 /* No pull-up, pull-down for PDx pins */
319 GPIOD->PUPDR = 0x00000000;
320
321 /* Connect PEx pins to FMC Alternate function */
322 GPIOE->AFR[0] = 0xC00000CC;
323 GPIOE->AFR[1] = 0xCCCCCCCC;
324 /* Configure PEx pins in Alternate function mode */
325 GPIOE->MODER = 0xAAAA800A;
326 /* Configure PEx pins speed to 50 MHz */
327 GPIOE->OSPEEDR = 0xAAAA800A;
328 /* Configure PEx pins Output type to push-pull */
329 GPIOE->OTYPER = 0x00000000;
330 /* No pull-up, pull-down for PEx pins */
331 GPIOE->PUPDR = 0x00000000;
332
333 /* Connect PFx pins to FMC Alternate function */
334 GPIOF->AFR[0] = 0xCCCCCCCC;
335 GPIOF->AFR[1] = 0xCCCCCCCC;
336 /* Configure PFx pins in Alternate function mode */
337 GPIOF->MODER = 0xAA800AAA;
338 /* Configure PFx pins speed to 50 MHz */
339 GPIOF->OSPEEDR = 0xAA800AAA;
340 /* Configure PFx pins Output type to push-pull */
341 GPIOF->OTYPER = 0x00000000;
342 /* No pull-up, pull-down for PFx pins */
343 GPIOF->PUPDR = 0x00000000;
344
345 /* Connect PGx pins to FMC Alternate function */
346 GPIOG->AFR[0] = 0xCCCCCCCC;
347 GPIOG->AFR[1] = 0xCCCCCCCC;
348 /* Configure PGx pins in Alternate function mode */
349 GPIOG->MODER = 0xAAAAAAAA;
350 /* Configure PGx pins speed to 50 MHz */
351 GPIOG->OSPEEDR = 0xAAAAAAAA;
352 /* Configure PGx pins Output type to push-pull */
353 GPIOG->OTYPER = 0x00000000;
354 /* No pull-up, pull-down for PGx pins */
355 GPIOG->PUPDR = 0x00000000;
356
357 /* Connect PHx pins to FMC Alternate function */
358 GPIOH->AFR[0] = 0x00C0CC00;
359 GPIOH->AFR[1] = 0xCCCCCCCC;
360 /* Configure PHx pins in Alternate function mode */
361 GPIOH->MODER = 0xAAAA08A0;
362 /* Configure PHx pins speed to 50 MHz */
363 GPIOH->OSPEEDR = 0xAAAA08A0;
364 /* Configure PHx pins Output type to push-pull */
365 GPIOH->OTYPER = 0x00000000;
366 /* No pull-up, pull-down for PHx pins */
367 GPIOH->PUPDR = 0x00000000;
368
369 /* Connect PIx pins to FMC Alternate function */
370 GPIOI->AFR[0] = 0xCCCCCCCC;
371 GPIOI->AFR[1] = 0x00000CC0;
372 /* Configure PIx pins in Alternate function mode */
373 GPIOI->MODER = 0x0028AAAA;
374 /* Configure PIx pins speed to 50 MHz */
375 GPIOI->OSPEEDR = 0x0028AAAA;
376 /* Configure PIx pins Output type to push-pull */
377 GPIOI->OTYPER = 0x00000000;
378 /* No pull-up, pull-down for PIx pins */
379 GPIOI->PUPDR = 0x00000000;
380
381 /*-- FMC Configuration ------------------------------------------------------*/
382 /* Enable the FMC interface clock */
383 RCC->AHB3ENR |= 0x00000001;
384
385 /* Configure and enable SDRAM bank1 */
386 FMC_Bank5_6->SDCR[0] = 0x000019E0;
387 FMC_Bank5_6->SDTR[0] = 0x01115351;
388
389 /* SDRAM initialization sequence */
390 /* Clock enable command */
391 FMC_Bank5_6->SDCMR = 0x00000011;
392 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
393 while((tmpreg != 0) && (timeout-- > 0))
394 {
395 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
396 }
397
398 /* Delay */
399 for (index = 0; index<1000; index++);
400
401 /* PALL command */
402 FMC_Bank5_6->SDCMR = 0x00000012;
403 timeout = 0xFFFF;
404 while((tmpreg != 0) && (timeout-- > 0))
405 {
406 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
407 }
408
409 /* Auto refresh command */
410 FMC_Bank5_6->SDCMR = 0x00000073;
411 timeout = 0xFFFF;
412 while((tmpreg != 0) && (timeout-- > 0))
413 {
414 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
415 }
416
417 /* MRD register program */
418 FMC_Bank5_6->SDCMR = 0x00046014;
419 timeout = 0xFFFF;
420 while((tmpreg != 0) && (timeout-- > 0))
421 {
422 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
423 }
424
425 /* Set refresh count */
426 tmpreg = FMC_Bank5_6->SDRTR;
427 FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
428
429 /* Disable write protection */
430 tmpreg = FMC_Bank5_6->SDCR[0];
431 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
432 #endif /* DATA_IN_ExtSDRAM */
433 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
434
435 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
436 #if defined(DATA_IN_ExtSRAM)
437 /*-- GPIOs Configuration -----------------------------------------------------*/
438 /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
439 RCC->AHB1ENR |= 0x00000078;
440
441 /* Connect PDx pins to FMC Alternate function */
442 GPIOD->AFR[0] = 0x00CCC0CC;
443 GPIOD->AFR[1] = 0xCCCCCCCC;
444 /* Configure PDx pins in Alternate function mode */
445 GPIOD->MODER = 0xAAAA0A8A;
446 /* Configure PDx pins speed to 100 MHz */
447 GPIOD->OSPEEDR = 0xFFFF0FCF;
448 /* Configure PDx pins Output type to push-pull */
449 GPIOD->OTYPER = 0x00000000;
450 /* No pull-up, pull-down for PDx pins */
451 GPIOD->PUPDR = 0x00000000;
452
453 /* Connect PEx pins to FMC Alternate function */
454 GPIOE->AFR[0] = 0xC00CC0CC;
455 GPIOE->AFR[1] = 0xCCCCCCCC;
456 /* Configure PEx pins in Alternate function mode */
457 GPIOE->MODER = 0xAAAA828A;
458 /* Configure PEx pins speed to 100 MHz */
459 GPIOE->OSPEEDR = 0xFFFFC3CF;
460 /* Configure PEx pins Output type to push-pull */
461 GPIOE->OTYPER = 0x00000000;
462 /* No pull-up, pull-down for PEx pins */
463 GPIOE->PUPDR = 0x00000000;
464
465 /* Connect PFx pins to FMC Alternate function */
466 GPIOF->AFR[0] = 0x00CCCCCC;
467 GPIOF->AFR[1] = 0xCCCC0000;
468 /* Configure PFx pins in Alternate function mode */
469 GPIOF->MODER = 0xAA000AAA;
470 /* Configure PFx pins speed to 100 MHz */
471 GPIOF->OSPEEDR = 0xFF000FFF;
472 /* Configure PFx pins Output type to push-pull */
473 GPIOF->OTYPER = 0x00000000;
474 /* No pull-up, pull-down for PFx pins */
475 GPIOF->PUPDR = 0x00000000;
476
477 /* Connect PGx pins to FMC Alternate function */
478 GPIOG->AFR[0] = 0x00CCCCCC;
479 GPIOG->AFR[1] = 0x000000C0;
480 /* Configure PGx pins in Alternate function mode */
481 GPIOG->MODER = 0x00085AAA;
482 /* Configure PGx pins speed to 100 MHz */
483 GPIOG->OSPEEDR = 0x000CAFFF;
484 /* Configure PGx pins Output type to push-pull */
485 GPIOG->OTYPER = 0x00000000;
486 /* No pull-up, pull-down for PGx pins */
487 GPIOG->PUPDR = 0x00000000;
488
489 /*-- FMC/FSMC Configuration --------------------------------------------------*/
490 /* Enable the FMC/FSMC interface clock */
491 RCC->AHB3ENR |= 0x00000001;
492
493 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
494 /* Configure and enable Bank1_SRAM2 */
495 FMC_Bank1->BTCR[2] = 0x00001011;
496 FMC_Bank1->BTCR[3] = 0x00000201;
497 FMC_Bank1E->BWTR[2] = 0x0fffffff;
498 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
499
500 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
501 /* Configure and enable Bank1_SRAM2 */
502 FSMC_Bank1->BTCR[2] = 0x00001011;
503 FSMC_Bank1->BTCR[3] = 0x00000201;
504 FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
505 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
506
507 #endif /* DATA_IN_ExtSRAM */
508 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
509 }
510 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
511 /**
512 * @}
513 */
514
515 /**
516 * @}
517 */
518
519 /**
520 * @}
521 */
522 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/