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38
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1 /**
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2 ******************************************************************************
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3 * @file stm32f4xx_ll_sdmmc.h
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4 * @author MCD Application Team
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5 * @version V1.2.0
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6 * @date 26-December-2014
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7 * @brief Header file of SDMMC HAL module.
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8 ******************************************************************************
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9 * @attention
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10 *
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11 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
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12 *
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13 * Redistribution and use in source and binary forms, with or without modification,
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14 * are permitted provided that the following conditions are met:
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15 * 1. Redistributions of source code must retain the above copyright notice,
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16 * this list of conditions and the following disclaimer.
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17 * 2. Redistributions in binary form must reproduce the above copyright notice,
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18 * this list of conditions and the following disclaimer in the documentation
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19 * and/or other materials provided with the distribution.
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20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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21 * may be used to endorse or promote products derived from this software
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22 * without specific prior written permission.
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23 *
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24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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34 *
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35 ******************************************************************************
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36 */
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37
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38 /* Define to prevent recursive inclusion -------------------------------------*/
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39 #ifndef __STM32F4xx_LL_SDMMC_H
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40 #define __STM32F4xx_LL_SDMMC_H
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41
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42 #ifdef __cplusplus
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43 extern "C" {
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44 #endif
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45
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46 /* Includes ------------------------------------------------------------------*/
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47 #include "stm32f4xx_hal_def.h"
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48
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49 /** @addtogroup STM32F4xx_Driver
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50 * @{
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51 */
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52
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53 /** @addtogroup SDMMC_LL
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54 * @{
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55 */
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56
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57 /* Exported types ------------------------------------------------------------*/
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58 /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
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59 * @{
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60 */
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61
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62 /**
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63 * @brief SDMMC Configuration Structure definition
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64 */
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65 typedef struct
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66 {
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67 uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
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68 This parameter can be a value of @ref SDIO_Clock_Edge */
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69
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70 uint32_t ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is
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71 enabled or disabled.
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72 This parameter can be a value of @ref SDIO_Clock_Bypass */
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73
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74 uint32_t ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or
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75 disabled when the bus is idle.
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76 This parameter can be a value of @ref SDIO_Clock_Power_Save */
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77
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78 uint32_t BusWide; /*!< Specifies the SDIO bus width.
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79 This parameter can be a value of @ref SDIO_Bus_Wide */
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80
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81 uint32_t HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
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82 This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
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83
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84 uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.
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85 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
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86
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87 }SDIO_InitTypeDef;
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88
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89
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90 /**
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91 * @brief SDIO Command Control structure
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92 */
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93 typedef struct
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94 {
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95 uint32_t Argument; /*!< Specifies the SDIO command argument which is sent
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96 to a card as part of a command message. If a command
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97 contains an argument, it must be loaded into this register
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98 before writing the command to the command register. */
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99
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100 uint32_t CmdIndex; /*!< Specifies the SDIO command index. It must be Min_Data = 0 and
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101 Max_Data = 64 */
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102
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103 uint32_t Response; /*!< Specifies the SDIO response type.
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104 This parameter can be a value of @ref SDIO_Response_Type */
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105
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106 uint32_t WaitForInterrupt; /*!< Specifies whether SDIO wait for interrupt request is
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107 enabled or disabled.
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108 This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
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109
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110 uint32_t CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)
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111 is enabled or disabled.
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112 This parameter can be a value of @ref SDIO_CPSM_State */
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113 }SDIO_CmdInitTypeDef;
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114
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115
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116 /**
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117 * @brief SDIO Data Control structure
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118 */
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119 typedef struct
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120 {
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121 uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
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122
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123 uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */
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124
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125 uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
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126 This parameter can be a value of @ref SDIO_Data_Block_Size */
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127
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128 uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
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129 is a read or write.
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130 This parameter can be a value of @ref SDIO_Transfer_Direction */
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131
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132 uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
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133 This parameter can be a value of @ref SDIO_Transfer_Type */
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134
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135 uint32_t DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)
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136 is enabled or disabled.
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137 This parameter can be a value of @ref SDIO_DPSM_State */
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138 }SDIO_DataInitTypeDef;
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139
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140 /**
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141 * @}
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142 */
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143
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144 /* Exported constants --------------------------------------------------------*/
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145 /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
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146 * @{
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147 */
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148
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149 /** @defgroup SDIO_Clock_Edge Clock Edge
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150 * @{
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151 */
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152 #define SDIO_CLOCK_EDGE_RISING ((uint32_t)0x00000000)
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153 #define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE
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154
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155 #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \
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156 ((EDGE) == SDIO_CLOCK_EDGE_FALLING))
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157 /**
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158 * @}
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159 */
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160
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161 /** @defgroup SDIO_Clock_Bypass Clock Bypass
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162 * @{
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163 */
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164 #define SDIO_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000)
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165 #define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS
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166
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167 #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \
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168 ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
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169 /**
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170 * @}
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171 */
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172
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173 /** @defgroup SDIO_Clock_Power_Save Clock Power Saving
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174 * @{
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175 */
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176 #define SDIO_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000)
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177 #define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV
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178
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179 #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \
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180 ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
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181 /**
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182 * @}
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183 */
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184
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185 /** @defgroup SDIO_Bus_Wide Bus Width
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186 * @{
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187 */
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188 #define SDIO_BUS_WIDE_1B ((uint32_t)0x00000000)
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189 #define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0
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190 #define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1
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191
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192 #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \
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193 ((WIDE) == SDIO_BUS_WIDE_4B) || \
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194 ((WIDE) == SDIO_BUS_WIDE_8B))
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195 /**
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196 * @}
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197 */
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198
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199 /** @defgroup SDIO_Hardware_Flow_Control Hardware Flow Control
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200 * @{
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201 */
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202 #define SDIO_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000)
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203 #define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN
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204
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205 #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \
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206 ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
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207 /**
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208 * @}
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209 */
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210
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211 /** @defgroup SDIO_Clock_Division Clock Division
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212 * @{
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213 */
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214 #define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFF)
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215 /**
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216 * @}
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217 */
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218
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219 /** @defgroup SDIO_Command_Index Command Index
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220 * @{
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221 */
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222 #define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
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223 /**
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224 * @}
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225 */
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226
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227 /** @defgroup SDIO_Response_Type Response Type
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228 * @{
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229 */
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230 #define SDIO_RESPONSE_NO ((uint32_t)0x00000000)
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231 #define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0
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232 #define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP
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233
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234 #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \
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235 ((RESPONSE) == SDIO_RESPONSE_SHORT) || \
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236 ((RESPONSE) == SDIO_RESPONSE_LONG))
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237 /**
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238 * @}
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239 */
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240
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241 /** @defgroup SDIO_Wait_Interrupt_State Wait Interrupt
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242 * @{
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243 */
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244 #define SDIO_WAIT_NO ((uint32_t)0x00000000)
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245 #define SDIO_WAIT_IT SDIO_CMD_WAITINT
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246 #define SDIO_WAIT_PEND SDIO_CMD_WAITPEND
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247
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248 #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \
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249 ((WAIT) == SDIO_WAIT_IT) || \
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250 ((WAIT) == SDIO_WAIT_PEND))
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251 /**
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252 * @}
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253 */
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254
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255 /** @defgroup SDIO_CPSM_State CPSM State
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256 * @{
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257 */
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258 #define SDIO_CPSM_DISABLE ((uint32_t)0x00000000)
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259 #define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN
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260
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261 #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \
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262 ((CPSM) == SDIO_CPSM_ENABLE))
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263 /**
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264 * @}
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265 */
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266
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267 /** @defgroup SDIO_Response_Registers Response Register
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268 * @{
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269 */
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270 #define SDIO_RESP1 ((uint32_t)0x00000000)
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271 #define SDIO_RESP2 ((uint32_t)0x00000004)
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272 #define SDIO_RESP3 ((uint32_t)0x00000008)
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273 #define SDIO_RESP4 ((uint32_t)0x0000000C)
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274
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275 #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \
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276 ((RESP) == SDIO_RESP2) || \
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277 ((RESP) == SDIO_RESP3) || \
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278 ((RESP) == SDIO_RESP4))
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279 /**
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280 * @}
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281 */
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282
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283 /** @defgroup SDIO_Data_Length Data Lenght
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284 * @{
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285 */
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286 #define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
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287 /**
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288 * @}
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289 */
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290
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291 /** @defgroup SDIO_Data_Block_Size Data Block Size
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292 * @{
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293 */
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294 #define SDIO_DATABLOCK_SIZE_1B ((uint32_t)0x00000000)
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295 #define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0
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296 #define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1
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297 #define SDIO_DATABLOCK_SIZE_8B ((uint32_t)0x00000030)
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298 #define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2
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299 #define SDIO_DATABLOCK_SIZE_32B ((uint32_t)0x00000050)
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300 #define SDIO_DATABLOCK_SIZE_64B ((uint32_t)0x00000060)
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301 #define SDIO_DATABLOCK_SIZE_128B ((uint32_t)0x00000070)
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302 #define SDIO_DATABLOCK_SIZE_256B SDIO_DCTRL_DBLOCKSIZE_3
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303 #define SDIO_DATABLOCK_SIZE_512B ((uint32_t)0x00000090)
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304 #define SDIO_DATABLOCK_SIZE_1024B ((uint32_t)0x000000A0)
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305 #define SDIO_DATABLOCK_SIZE_2048B ((uint32_t)0x000000B0)
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306 #define SDIO_DATABLOCK_SIZE_4096B ((uint32_t)0x000000C0)
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307 #define SDIO_DATABLOCK_SIZE_8192B ((uint32_t)0x000000D0)
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308 #define SDIO_DATABLOCK_SIZE_16384B ((uint32_t)0x000000E0)
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309
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310 #define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) || \
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311 ((SIZE) == SDIO_DATABLOCK_SIZE_2B) || \
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312 ((SIZE) == SDIO_DATABLOCK_SIZE_4B) || \
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313 ((SIZE) == SDIO_DATABLOCK_SIZE_8B) || \
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314 ((SIZE) == SDIO_DATABLOCK_SIZE_16B) || \
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315 ((SIZE) == SDIO_DATABLOCK_SIZE_32B) || \
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316 ((SIZE) == SDIO_DATABLOCK_SIZE_64B) || \
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317 ((SIZE) == SDIO_DATABLOCK_SIZE_128B) || \
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318 ((SIZE) == SDIO_DATABLOCK_SIZE_256B) || \
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319 ((SIZE) == SDIO_DATABLOCK_SIZE_512B) || \
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320 ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \
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321 ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \
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322 ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \
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323 ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \
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324 ((SIZE) == SDIO_DATABLOCK_SIZE_16384B))
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325 /**
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326 * @}
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327 */
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328
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329 /** @defgroup SDIO_Transfer_Direction Transfer Direction
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330 * @{
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331 */
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332 #define SDIO_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000)
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333 #define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR
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334
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335 #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \
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336 ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
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337 /**
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338 * @}
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339 */
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340
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341 /** @defgroup SDIO_Transfer_Type Transfer Type
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342 * @{
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343 */
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344 #define SDIO_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000)
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345 #define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE
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346
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347 #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \
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348 ((MODE) == SDIO_TRANSFER_MODE_STREAM))
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349 /**
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350 * @}
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351 */
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352
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353 /** @defgroup SDIO_DPSM_State DPSM State
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354 * @{
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355 */
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356 #define SDIO_DPSM_DISABLE ((uint32_t)0x00000000)
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357 #define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN
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358
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359 #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\
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360 ((DPSM) == SDIO_DPSM_ENABLE))
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361 /**
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362 * @}
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363 */
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364
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365 /** @defgroup SDIO_Read_Wait_Mode Read Wait Mode
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366 * @{
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367 */
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368 #define SDIO_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000)
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369 #define SDIO_READ_WAIT_MODE_CLK ((uint32_t)0x00000001)
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370
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371 #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \
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372 ((MODE) == SDIO_READ_WAIT_MODE_DATA2))
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373 /**
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374 * @}
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375 */
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376
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377 /** @defgroup SDIO_Interrupt_sources Interrupt Sources
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378 * @{
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379 */
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380 #define SDIO_IT_CCRCFAIL SDIO_STA_CCRCFAIL
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381 #define SDIO_IT_DCRCFAIL SDIO_STA_DCRCFAIL
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382 #define SDIO_IT_CTIMEOUT SDIO_STA_CTIMEOUT
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383 #define SDIO_IT_DTIMEOUT SDIO_STA_DTIMEOUT
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384 #define SDIO_IT_TXUNDERR SDIO_STA_TXUNDERR
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385 #define SDIO_IT_RXOVERR SDIO_STA_RXOVERR
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386 #define SDIO_IT_CMDREND SDIO_STA_CMDREND
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387 #define SDIO_IT_CMDSENT SDIO_STA_CMDSENT
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388 #define SDIO_IT_DATAEND SDIO_STA_DATAEND
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389 #define SDIO_IT_STBITERR SDIO_STA_STBITERR
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390 #define SDIO_IT_DBCKEND SDIO_STA_DBCKEND
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391 #define SDIO_IT_CMDACT SDIO_STA_CMDACT
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392 #define SDIO_IT_TXACT SDIO_STA_TXACT
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393 #define SDIO_IT_RXACT SDIO_STA_RXACT
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394 #define SDIO_IT_TXFIFOHE SDIO_STA_TXFIFOHE
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395 #define SDIO_IT_RXFIFOHF SDIO_STA_RXFIFOHF
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396 #define SDIO_IT_TXFIFOF SDIO_STA_TXFIFOF
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397 #define SDIO_IT_RXFIFOF SDIO_STA_RXFIFOF
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398 #define SDIO_IT_TXFIFOE SDIO_STA_TXFIFOE
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399 #define SDIO_IT_RXFIFOE SDIO_STA_RXFIFOE
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400 #define SDIO_IT_TXDAVL SDIO_STA_TXDAVL
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401 #define SDIO_IT_RXDAVL SDIO_STA_RXDAVL
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402 #define SDIO_IT_SDIOIT SDIO_STA_SDIOIT
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403 #define SDIO_IT_CEATAEND SDIO_STA_CEATAEND
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404 /**
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405 * @}
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406 */
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407
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408 /** @defgroup SDIO_Flags Flags
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409 * @{
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410 */
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411 #define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL
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412 #define SDIO_FLAG_DCRCFAIL SDIO_STA_DCRCFAIL
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413 #define SDIO_FLAG_CTIMEOUT SDIO_STA_CTIMEOUT
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414 #define SDIO_FLAG_DTIMEOUT SDIO_STA_DTIMEOUT
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415 #define SDIO_FLAG_TXUNDERR SDIO_STA_TXUNDERR
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416 #define SDIO_FLAG_RXOVERR SDIO_STA_RXOVERR
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417 #define SDIO_FLAG_CMDREND SDIO_STA_CMDREND
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418 #define SDIO_FLAG_CMDSENT SDIO_STA_CMDSENT
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419 #define SDIO_FLAG_DATAEND SDIO_STA_DATAEND
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420 #define SDIO_FLAG_STBITERR SDIO_STA_STBITERR
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421 #define SDIO_FLAG_DBCKEND SDIO_STA_DBCKEND
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422 #define SDIO_FLAG_CMDACT SDIO_STA_CMDACT
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423 #define SDIO_FLAG_TXACT SDIO_STA_TXACT
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424 #define SDIO_FLAG_RXACT SDIO_STA_RXACT
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425 #define SDIO_FLAG_TXFIFOHE SDIO_STA_TXFIFOHE
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426 #define SDIO_FLAG_RXFIFOHF SDIO_STA_RXFIFOHF
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427 #define SDIO_FLAG_TXFIFOF SDIO_STA_TXFIFOF
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428 #define SDIO_FLAG_RXFIFOF SDIO_STA_RXFIFOF
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429 #define SDIO_FLAG_TXFIFOE SDIO_STA_TXFIFOE
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430 #define SDIO_FLAG_RXFIFOE SDIO_STA_RXFIFOE
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431 #define SDIO_FLAG_TXDAVL SDIO_STA_TXDAVL
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432 #define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL
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433 #define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT
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434 #define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND
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435 /**
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436 * @}
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437 */
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438
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439 /**
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440 * @}
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441 */
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442 /* Exported macro ------------------------------------------------------------*/
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443 /** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
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444 * @{
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445 */
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446
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447 /** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region
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448 * @{
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449 */
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450 /* ------------ SDIO registers bit address in the alias region -------------- */
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451 #define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
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452
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453 /* --- CLKCR Register ---*/
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454 /* Alias word address of CLKEN bit */
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455 #define CLKCR_OFFSET (SDIO_OFFSET + 0x04)
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456 #define CLKEN_BITNUMBER 0x08
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457 #define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BITNUMBER * 4))
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458
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459 /* --- CMD Register ---*/
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460 /* Alias word address of SDIOSUSPEND bit */
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461 #define CMD_OFFSET (SDIO_OFFSET + 0x0C)
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462 #define SDIOSUSPEND_BITNUMBER 0x0B
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463 #define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BITNUMBER * 4))
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464
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465 /* Alias word address of ENCMDCOMPL bit */
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466 #define ENCMDCOMPL_BITNUMBER 0x0C
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467 #define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BITNUMBER * 4))
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468
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469 /* Alias word address of NIEN bit */
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470 #define NIEN_BITNUMBER 0x0D
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471 #define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BITNUMBER * 4))
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472
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473 /* Alias word address of ATACMD bit */
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474 #define ATACMD_BITNUMBER 0x0E
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475 #define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BITNUMBER * 4))
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476
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477 /* --- DCTRL Register ---*/
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478 /* Alias word address of DMAEN bit */
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479 #define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
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480 #define DMAEN_BITNUMBER 0x03
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481 #define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BITNUMBER * 4))
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482
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483 /* Alias word address of RWSTART bit */
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484 #define RWSTART_BITNUMBER 0x08
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485 #define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BITNUMBER * 4))
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486
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487 /* Alias word address of RWSTOP bit */
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|
488 #define RWSTOP_BITNUMBER 0x09
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|
489 #define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BITNUMBER * 4))
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490
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491 /* Alias word address of RWMOD bit */
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492 #define RWMOD_BITNUMBER 0x0A
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493 #define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BITNUMBER * 4))
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494
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495 /* Alias word address of SDIOEN bit */
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496 #define SDIOEN_BITNUMBER 0x0B
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497 #define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BITNUMBER * 4))
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498 /**
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499 * @}
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500 */
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501
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502 /** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
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|
503 * @brief SDMMC_LL registers bit address in the alias region
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|
504 * @{
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505 */
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506
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507 /* ---------------------- SDIO registers bit mask --------------------------- */
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508 /* --- CLKCR Register ---*/
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509 /* CLKCR register clear mask */
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|
510 #define CLKCR_CLEAR_MASK ((uint32_t)(SDIO_CLKCR_CLKDIV | SDIO_CLKCR_PWRSAV |\
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|
511 SDIO_CLKCR_BYPASS | SDIO_CLKCR_WIDBUS |\
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|
512 SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN))
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513
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514 /* --- PWRCTRL Register ---*/
|
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|
515 /* --- DCTRL Register ---*/
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516 /* SDIO DCTRL Clear Mask */
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|
517 #define DCTRL_CLEAR_MASK ((uint32_t)(SDIO_DCTRL_DTEN | SDIO_DCTRL_DTDIR |\
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|
518 SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE))
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|
|
519
|
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|
520 /* --- CMD Register ---*/
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|
521 /* CMD Register clear mask */
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|
|
522 #define CMD_CLEAR_MASK ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\
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|
|
523 SDIO_CMD_WAITINT | SDIO_CMD_WAITPEND |\
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|
|
524 SDIO_CMD_CPSMEN | SDIO_CMD_SDIOSUSPEND))
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525
|
|
|
526 /* SDIO RESP Registers Address */
|
|
|
527 #define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
|
|
|
528
|
|
|
529 /* SDIO Initialization Frequency (400KHz max) */
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|
|
530 #define SDIO_INIT_CLK_DIV ((uint8_t)0x76)
|
|
|
531
|
|
|
532 /* SDIO Data Transfer Frequency (25MHz max) */
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|
|
533 #define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0)
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|
|
534 /**
|
|
|
535 * @}
|
|
|
536 */
|
|
|
537
|
|
|
538 /** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
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|
539 * @brief macros to handle interrupts and specific clock configurations
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|
|
540 * @{
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|
|
541 */
|
|
|
542
|
|
|
543 /**
|
|
|
544 * @brief Enable the SDIO device.
|
|
|
545 * @retval None
|
|
|
546 */
|
|
|
547 #define __SDIO_ENABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE)
|
|
|
548
|
|
|
549 /**
|
|
|
550 * @brief Disable the SDIO device.
|
|
|
551 * @retval None
|
|
|
552 */
|
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|
553 #define __SDIO_DISABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE)
|
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|
554
|
|
|
555 /**
|
|
|
556 * @brief Enable the SDIO DMA transfer.
|
|
|
557 * @retval None
|
|
|
558 */
|
|
|
559 #define __SDIO_DMA_ENABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE)
|
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|
560
|
|
|
561 /**
|
|
|
562 * @brief Disable the SDIO DMA transfer.
|
|
|
563 * @retval None
|
|
|
564 */
|
|
|
565 #define __SDIO_DMA_DISABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE)
|
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|
566
|
|
|
567 /**
|
|
|
568 * @brief Enable the SDIO device interrupt.
|
|
|
569 * @param __INSTANCE__ : Pointer to SDIO register base
|
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|
570 * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled.
|
|
|
571 * This parameter can be one or a combination of the following values:
|
|
|
572 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
|
|
573 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
|
|
574 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
|
|
|
575 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
|
|
|
576 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
|
|
577 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
|
|
|
578 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
|
|
|
579 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
|
|
|
580 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
|
|
|
581 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
|
|
|
582 * bus mode interrupt
|
|
|
583 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
|
|
584 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
|
|
|
585 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
|
|
|
586 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
|
|
|
587 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
|
|
588 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
|
|
589 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
|
|
|
590 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
|
|
|
591 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
|
|
|
592 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
|
|
|
593 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
|
|
|
594 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
|
|
|
595 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
|
|
|
596 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
|
|
|
597 * @retval None
|
|
|
598 */
|
|
|
599 #define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__))
|
|
|
600
|
|
|
601 /**
|
|
|
602 * @brief Disable the SDIO device interrupt.
|
|
|
603 * @param __INSTANCE__ : Pointer to SDIO register base
|
|
|
604 * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled.
|
|
|
605 * This parameter can be one or a combination of the following values:
|
|
|
606 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
|
|
607 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
|
|
608 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
|
|
|
609 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
|
|
|
610 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
|
|
611 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
|
|
|
612 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
|
|
|
613 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
|
|
|
614 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
|
|
|
615 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
|
|
|
616 * bus mode interrupt
|
|
|
617 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
|
|
618 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
|
|
|
619 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
|
|
|
620 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
|
|
|
621 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
|
|
622 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
|
|
623 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
|
|
|
624 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
|
|
|
625 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
|
|
|
626 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
|
|
|
627 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
|
|
|
628 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
|
|
|
629 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
|
|
|
630 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
|
|
|
631 * @retval None
|
|
|
632 */
|
|
|
633 #define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
|
|
|
634
|
|
|
635 /**
|
|
|
636 * @brief Checks whether the specified SDIO flag is set or not.
|
|
|
637 * @param __INSTANCE__ : Pointer to SDIO register base
|
|
|
638 * @param __FLAG__: specifies the flag to check.
|
|
|
639 * This parameter can be one of the following values:
|
|
|
640 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
|
|
|
641 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
|
|
|
642 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
|
|
|
643 * @arg SDIO_FLAG_DTIMEOUT: Data timeout
|
|
|
644 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
|
|
|
645 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
|
|
|
646 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
|
|
|
647 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
|
|
|
648 * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
|
|
|
649 * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
|
|
|
650 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
|
|
|
651 * @arg SDIO_FLAG_CMDACT: Command transfer in progress
|
|
|
652 * @arg SDIO_FLAG_TXACT: Data transmit in progress
|
|
|
653 * @arg SDIO_FLAG_RXACT: Data receive in progress
|
|
|
654 * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
|
|
|
655 * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
|
|
|
656 * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
|
|
|
657 * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
|
|
|
658 * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
|
|
|
659 * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
|
|
|
660 * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
|
|
|
661 * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
|
|
|
662 * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
|
|
|
663 * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
|
|
|
664 * @retval The new state of SDIO_FLAG (SET or RESET).
|
|
|
665 */
|
|
|
666 #define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
|
|
|
667
|
|
|
668
|
|
|
669 /**
|
|
|
670 * @brief Clears the SDIO pending flags.
|
|
|
671 * @param __INSTANCE__ : Pointer to SDIO register base
|
|
|
672 * @param __FLAG__: specifies the flag to clear.
|
|
|
673 * This parameter can be one or a combination of the following values:
|
|
|
674 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
|
|
|
675 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
|
|
|
676 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
|
|
|
677 * @arg SDIO_FLAG_DTIMEOUT: Data timeout
|
|
|
678 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
|
|
|
679 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
|
|
|
680 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
|
|
|
681 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
|
|
|
682 * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
|
|
|
683 * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
|
|
|
684 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
|
|
|
685 * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
|
|
|
686 * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
|
|
|
687 * @retval None
|
|
|
688 */
|
|
|
689 #define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
|
|
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690
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691 /**
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692 * @brief Checks whether the specified SDIO interrupt has occurred or not.
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693 * @param __INSTANCE__ : Pointer to SDIO register base
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694 * @param __INTERRUPT__: specifies the SDIO interrupt source to check.
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695 * This parameter can be one of the following values:
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696 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
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697 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
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698 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
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699 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
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700 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
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701 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
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702 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
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703 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
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704 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
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705 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
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706 * bus mode interrupt
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707 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
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708 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
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709 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
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710 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
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711 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
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712 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
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713 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
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714 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
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715 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
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716 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
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717 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
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718 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
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719 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
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720 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
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721 * @retval The new state of SDIO_IT (SET or RESET).
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722 */
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723 #define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
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724
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725 /**
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726 * @brief Clears the SDIO's interrupt pending bits.
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727 * @param __INSTANCE__ : Pointer to SDIO register base
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728 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
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729 * This parameter can be one or a combination of the following values:
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730 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
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731 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
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732 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
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733 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
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734 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
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735 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
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736 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
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737 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
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738 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
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739 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
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740 * bus mode interrupt
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741 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
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742 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
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743 * @retval None
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744 */
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745 #define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
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746
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747 /**
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748 * @brief Enable Start the SD I/O Read Wait operation.
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749 * @retval None
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750 */
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751 #define __SDIO_START_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE)
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752
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753 /**
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754 * @brief Disable Start the SD I/O Read Wait operations.
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755 * @retval None
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756 */
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757 #define __SDIO_START_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE)
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758
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759 /**
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760 * @brief Enable Start the SD I/O Read Wait operation.
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761 * @retval None
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762 */
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763 #define __SDIO_STOP_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE)
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764
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765 /**
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766 * @brief Disable Stop the SD I/O Read Wait operations.
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767 * @retval None
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768 */
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769 #define __SDIO_STOP_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE)
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770
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771 /**
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772 * @brief Enable the SD I/O Mode Operation.
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773 * @retval None
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774 */
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775 #define __SDIO_OPERATION_ENABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE)
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776
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777 /**
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778 * @brief Disable the SD I/O Mode Operation.
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779 * @retval None
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780 */
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781 #define __SDIO_OPERATION_DISABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE)
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782
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783 /**
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784 * @brief Enable the SD I/O Suspend command sending.
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785 * @retval None
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786 */
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787 #define __SDIO_SUSPEND_CMD_ENABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE)
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788
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789 /**
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790 * @brief Disable the SD I/O Suspend command sending.
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791 * @retval None
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792 */
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793 #define __SDIO_SUSPEND_CMD_DISABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)
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794
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795 /**
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796 * @brief Enable the command completion signal.
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797 * @retval None
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798 */
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799 #define __SDIO_CEATA_CMD_COMPLETION_ENABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE)
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800
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801 /**
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802 * @brief Disable the command completion signal.
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803 * @retval None
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804 */
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805 #define __SDIO_CEATA_CMD_COMPLETION_DISABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE)
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806
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807 /**
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808 * @brief Enable the CE-ATA interrupt.
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809 * @retval None
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810 */
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811 #define __SDIO_CEATA_ENABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0)
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812
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813 /**
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814 * @brief Disable the CE-ATA interrupt.
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815 * @retval None
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816 */
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817 #define __SDIO_CEATA_DISABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1)
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818
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819 /**
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820 * @brief Enable send CE-ATA command (CMD61).
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821 * @retval None
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822 */
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823 #define __SDIO_CEATA_SENDCMD_ENABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE)
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824
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825 /**
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826 * @brief Disable send CE-ATA command (CMD61).
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827 * @retval None
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828 */
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829 #define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE)
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830
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831 /**
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832 * @}
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833 */
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834
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835 /**
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836 * @}
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837 */
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838
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839 /* Exported functions --------------------------------------------------------*/
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840 /** @addtogroup SDMMC_LL_Exported_Functions
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841 * @{
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842 */
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843
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844 /* Initialization/de-initialization functions **********************************/
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845 /** @addtogroup HAL_SDMMC_LL_Group1
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846 * @{
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847 */
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848 HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
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849 /**
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850 * @}
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851 */
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852
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853 /* I/O operation functions *****************************************************/
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854 /** @addtogroup HAL_SDMMC_LL_Group2
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855 * @{
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856 */
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857 /* Blocking mode: Polling */
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858 uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
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859 HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData);
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860 /**
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861 * @}
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862 */
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863
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864 /* Peripheral Control functions ************************************************/
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865 /** @addtogroup HAL_SDMMC_LL_Group3
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866 * @{
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867 */
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868 HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
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869 HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
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870 uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
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871
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872 /* Command path state machine (CPSM) management functions */
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873 HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
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874 uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
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875 uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
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876
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877 /* Data path state machine (DPSM) management functions */
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878 HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDIO_DataInitStruct);
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879 uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
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880 uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
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881
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882 /* SDIO IO Cards mode management functions */
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883 HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
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884
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885 /**
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886 * @}
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887 */
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888
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889 /**
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890 * @}
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891 */
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892
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893 /**
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894 * @}
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895 */
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896
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897 /**
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898 * @}
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899 */
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900
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901 #ifdef __cplusplus
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902 }
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903 #endif
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904
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905 #endif /* __STM32F4xx_LL_SDMMC_H */
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906
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907 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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