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annotate Common/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h @ 704:f1b40364b0af

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Added protocol functions for UART DiveO2 sensor: The code has been modified to support the handling of several protocols (including baud rate changes). The data is requested by polling and passed via DMA into a ringbuffer which is then parsed by a cyclic function call in the main loop. At the moment only the O2 values are forwarded but because the sensor send several types of data within a signle message already more is extracted but yet discarded.
author Ideenmodellierer
date Fri, 28 Oct 2022 20:49:21 +0200
parents c78bcbd5deda
children
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1 /**
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2 ******************************************************************************
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3 * @file stm32f4xx_ll_utils.h
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4 * @author MCD Application Team
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5 * @brief Header file of UTILS LL module.
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6 @verbatim
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7 ==============================================================================
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8 ##### How to use this driver #####
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9 ==============================================================================
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10 [..]
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11 The LL UTILS driver contains a set of generic APIs that can be
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12 used by user:
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13 (+) Device electronic signature
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14 (+) Timing functions
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15 (+) PLL configuration functions
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16
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17 @endverbatim
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18 ******************************************************************************
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19 * @attention
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20 *
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21 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
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22 *
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23 * Redistribution and use in source and binary forms, with or without modification,
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24 * are permitted provided that the following conditions are met:
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25 * 1. Redistributions of source code must retain the above copyright notice,
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26 * this list of conditions and the following disclaimer.
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27 * 2. Redistributions in binary form must reproduce the above copyright notice,
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28 * this list of conditions and the following disclaimer in the documentation
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29 * and/or other materials provided with the distribution.
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30 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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31 * may be used to endorse or promote products derived from this software
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32 * without specific prior written permission.
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33 *
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34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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35 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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36 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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37 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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38 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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39 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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40 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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41 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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42 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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43 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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44 *
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45 ******************************************************************************
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46 */
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47
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48 /* Define to prevent recursive inclusion -------------------------------------*/
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49 #ifndef __STM32F4xx_LL_UTILS_H
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50 #define __STM32F4xx_LL_UTILS_H
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51
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52 #ifdef __cplusplus
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53 extern "C" {
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54 #endif
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55
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56 /* Includes ------------------------------------------------------------------*/
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57 #include "stm32f4xx.h"
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58
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59 /** @addtogroup STM32F4xx_LL_Driver
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60 * @{
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61 */
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62
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63 /** @defgroup UTILS_LL UTILS
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64 * @{
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65 */
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66
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67 /* Private types -------------------------------------------------------------*/
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68 /* Private variables ---------------------------------------------------------*/
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69
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70 /* Private constants ---------------------------------------------------------*/
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71 /** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
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72 * @{
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73 */
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74
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75 /* Max delay can be used in LL_mDelay */
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76 #define LL_MAX_DELAY 0xFFFFFFFFU
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77
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78 /**
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79 * @brief Unique device ID register base address
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80 */
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81 #define UID_BASE_ADDRESS UID_BASE
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82
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83 /**
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84 * @brief Flash size data register base address
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85 */
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86 #define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
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87
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88 /**
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89 * @brief Package data register base address
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90 */
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91 #define PACKAGE_BASE_ADDRESS PACKAGE_BASE
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92
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93 /**
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94 * @}
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95 */
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96
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97 /* Private macros ------------------------------------------------------------*/
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98 /** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
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99 * @{
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100 */
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101 /**
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102 * @}
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103 */
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104 /* Exported types ------------------------------------------------------------*/
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105 /** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
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106 * @{
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107 */
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108 /**
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109 * @brief UTILS PLL structure definition
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110 */
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111 typedef struct
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112 {
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113 uint32_t PLLM; /*!< Division factor for PLL VCO input clock.
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114 This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV
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115
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116 This feature can be modified afterwards using unitary function
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117 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
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118
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119 uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock.
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120 This parameter must be a number between Min_Data = @ref RCC_PLLN_MIN_VALUE
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121 and Max_Data = @ref RCC_PLLN_MIN_VALUE
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122
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123 This feature can be modified afterwards using unitary function
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124 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
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125
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126 uint32_t PLLP; /*!< Division for the main system clock.
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127 This parameter can be a value of @ref RCC_LL_EC_PLLP_DIV
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128
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129 This feature can be modified afterwards using unitary function
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130 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
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131 } LL_UTILS_PLLInitTypeDef;
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132
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133 /**
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134 * @brief UTILS System, AHB and APB buses clock configuration structure definition
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135 */
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136 typedef struct
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137 {
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138 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
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139 This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
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140
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141 This feature can be modified afterwards using unitary function
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142 @ref LL_RCC_SetAHBPrescaler(). */
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143
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144 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
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145 This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
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146
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147 This feature can be modified afterwards using unitary function
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148 @ref LL_RCC_SetAPB1Prescaler(). */
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149
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150 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
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151 This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
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152
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153 This feature can be modified afterwards using unitary function
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154 @ref LL_RCC_SetAPB2Prescaler(). */
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155
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156 } LL_UTILS_ClkInitTypeDef;
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157
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158 /**
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159 * @}
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160 */
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161
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162 /* Exported constants --------------------------------------------------------*/
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163 /** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
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164 * @{
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165 */
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166
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167 /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
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168 * @{
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169 */
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170 #define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
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171 #define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
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172 /**
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173 * @}
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174 */
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175
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176 /** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
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177 * @{
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178 */
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179 #define LL_UTILS_PACKAGETYPE_WLCSP36_UFQFPN48_LQFP64 0x00000000U /*!< WLCSP36 or UFQFPN48 or LQFP64 package type */
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180 #define LL_UTILS_PACKAGETYPE_WLCSP168_FBGA169_LQFP100_LQFP64_UFQFPN48 0x00000100U /*!< WLCSP168 or FBGA169 or LQFP100 or LQFP64 or UFQFPN48 package type */
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181 #define LL_UTILS_PACKAGETYPE_WLCSP64_WLCSP81_LQFP176_UFBGA176 0x00000200U /*!< WLCSP64 or WLCSP81 or LQFP176 or UFBGA176 package type */
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182 #define LL_UTILS_PACKAGETYPE_LQFP144_UFBGA144_UFBGA144_UFBGA100 0x00000300U /*!< LQFP144 or UFBGA144 or UFBGA144 or UFBGA100 package type */
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183 #define LL_UTILS_PACKAGETYPE_LQFP100_LQFP208_TFBGA216 0x00000400U /*!< LQFP100 or LQFP208 or TFBGA216 package type */
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184 #define LL_UTILS_PACKAGETYPE_LQFP208_TFBGA216 0x00000500U /*!< LQFP208 or TFBGA216 package type */
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185 #define LL_UTILS_PACKAGETYPE_TQFP64_UFBGA144_LQFP144 0x00000700U /*!< TQFP64 or UFBGA144 or LQFP144 package type */
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186 /**
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187 * @}
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188 */
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189
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190 /**
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191 * @}
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192 */
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193
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194 /* Exported macro ------------------------------------------------------------*/
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195
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196 /* Exported functions --------------------------------------------------------*/
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197 /** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
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198 * @{
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199 */
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200
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201 /** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
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202 * @{
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203 */
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204
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205 /**
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206 * @brief Get Word0 of the unique device identifier (UID based on 96 bits)
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207 * @retval UID[31:0]
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208 */
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209 __STATIC_INLINE uint32_t LL_GetUID_Word0(void)
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210 {
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211 return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
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212 }
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213
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214 /**
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215 * @brief Get Word1 of the unique device identifier (UID based on 96 bits)
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216 * @retval UID[63:32]
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217 */
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218 __STATIC_INLINE uint32_t LL_GetUID_Word1(void)
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219 {
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220 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
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221 }
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222
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223 /**
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224 * @brief Get Word2 of the unique device identifier (UID based on 96 bits)
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225 * @retval UID[95:64]
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226 */
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227 __STATIC_INLINE uint32_t LL_GetUID_Word2(void)
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228 {
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229 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
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230 }
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231
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232 /**
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233 * @brief Get Flash memory size
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234 * @note This bitfield indicates the size of the device Flash memory expressed in
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235 * Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
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236 * @retval FLASH_SIZE[15:0]: Flash memory size
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237 */
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238 __STATIC_INLINE uint32_t LL_GetFlashSize(void)
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239 {
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240 return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
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241 }
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242
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243 /**
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244 * @brief Get Package type
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245 * @retval Returned value can be one of the following values:
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246 * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP36_UFQFPN48_LQFP64 (*)
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247 * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP168_FBGA169_LQFP100_LQFP64_UFQFPN48 (*)
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248 * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP64_WLCSP81_LQFP176_UFBGA176 (*)
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249 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_UFBGA144_UFBGA144_UFBGA100 (*)
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250 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_LQFP208_TFBGA216 (*)
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251 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP208_TFBGA216 (*)
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252 * @arg @ref LL_UTILS_PACKAGETYPE_TQFP64_UFBGA144_LQFP144 (*)
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253 *
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254 * (*) value not defined in all devices.
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255 */
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256 __STATIC_INLINE uint32_t LL_GetPackageType(void)
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257 {
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258 return (uint8_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x0700U);
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259 }
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260
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261 /**
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262 * @}
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263 */
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264
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265 /** @defgroup UTILS_LL_EF_DELAY DELAY
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266 * @{
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267 */
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268
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269 /**
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270 * @brief This function configures the Cortex-M SysTick source of the time base.
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271 * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
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272 * @note When a RTOS is used, it is recommended to avoid changing the SysTick
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273 * configuration by calling this function, for a delay use rather osDelay RTOS service.
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274 * @param Ticks Number of ticks
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275 * @retval None
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276 */
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277 __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
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278 {
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279 /* Configure the SysTick to have interrupt in 1ms time base */
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280 SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
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281 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
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282 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
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283 SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
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284 }
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285
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286 void LL_Init1msTick(uint32_t HCLKFrequency);
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287 void LL_mDelay(uint32_t Delay);
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288
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289 /**
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290 * @}
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291 */
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292
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293 /** @defgroup UTILS_EF_SYSTEM SYSTEM
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294 * @{
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295 */
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296
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297 void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
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298 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
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299 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
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300 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
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301 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
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302
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303 /**
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304 * @}
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305 */
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306
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307 /**
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308 * @}
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309 */
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310
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311 /**
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312 * @}
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313 */
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314
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315 /**
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316 * @}
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317 */
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318
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319 #ifdef __cplusplus
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320 }
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321 #endif
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322
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323 #endif /* __STM32F4xx_LL_UTILS_H */
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324
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325 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/