Mercurial > public > ostc4
annotate Common/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_nand.h @ 704:f1b40364b0af
Added protocol functions for UART DiveO2 sensor:
The code has been modified to support the handling of several protocols (including baud rate changes). The data is requested by polling and passed via DMA into a ringbuffer which is then parsed by a cyclic function call in the main loop. At the moment only the O2 values are forwarded but because the sensor send several types of data within a signle message already more is extracted but yet discarded.
author | Ideenmodellierer |
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date | Fri, 28 Oct 2022 20:49:21 +0200 |
parents | c78bcbd5deda |
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rev | line source |
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128
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1 /** |
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2 ****************************************************************************** |
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3 * @file stm32f4xx_hal_nand.h |
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4 * @author MCD Application Team |
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5 * @brief Header file of NAND HAL module. |
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6 ****************************************************************************** |
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7 * @attention |
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8 * |
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9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
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10 * |
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11 * Redistribution and use in source and binary forms, with or without modification, |
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12 * are permitted provided that the following conditions are met: |
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13 * 1. Redistributions of source code must retain the above copyright notice, |
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14 * this list of conditions and the following disclaimer. |
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15 * 2. Redistributions in binary form must reproduce the above copyright notice, |
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16 * this list of conditions and the following disclaimer in the documentation |
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17 * and/or other materials provided with the distribution. |
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18 * 3. Neither the name of STMicroelectronics nor the names of its contributors |
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19 * may be used to endorse or promote products derived from this software |
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20 * without specific prior written permission. |
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21 * |
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22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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32 * |
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33 ****************************************************************************** |
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34 */ |
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35 |
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36 /* Define to prevent recursive inclusion -------------------------------------*/ |
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37 #ifndef __STM32F4xx_HAL_NAND_H |
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38 #define __STM32F4xx_HAL_NAND_H |
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39 |
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40 #ifdef __cplusplus |
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41 extern "C" { |
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42 #endif |
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43 |
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44 /* Includes ------------------------------------------------------------------*/ |
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45 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) |
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46 #include "stm32f4xx_ll_fsmc.h" |
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47 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
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48 |
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49 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ |
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50 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) |
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51 #include "stm32f4xx_ll_fmc.h" |
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52 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ |
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53 STM32F479xx */ |
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54 |
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55 /** @addtogroup STM32F4xx_HAL_Driver |
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56 * @{ |
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57 */ |
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58 |
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59 /** @addtogroup NAND |
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60 * @{ |
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61 */ |
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62 |
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63 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ |
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64 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ |
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65 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) |
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66 |
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67 /* Exported typedef ----------------------------------------------------------*/ |
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68 /* Exported types ------------------------------------------------------------*/ |
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69 /** @defgroup NAND_Exported_Types NAND Exported Types |
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70 * @{ |
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71 */ |
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72 |
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73 /** |
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74 * @brief HAL NAND State structures definition |
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75 */ |
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76 typedef enum |
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77 { |
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78 HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */ |
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79 HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */ |
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80 HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */ |
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81 HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */ |
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82 }HAL_NAND_StateTypeDef; |
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83 |
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84 /** |
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85 * @brief NAND Memory electronic signature Structure definition |
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86 */ |
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87 typedef struct |
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88 { |
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89 /*<! NAND memory electronic signature maker and device IDs */ |
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90 |
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91 uint8_t Maker_Id; |
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92 |
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93 uint8_t Device_Id; |
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94 |
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95 uint8_t Third_Id; |
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96 |
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97 uint8_t Fourth_Id; |
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98 }NAND_IDTypeDef; |
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99 |
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100 /** |
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101 * @brief NAND Memory address Structure definition |
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102 */ |
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103 typedef struct |
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104 { |
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105 uint16_t Page; /*!< NAND memory Page address */ |
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106 |
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107 uint16_t Plane; /*!< NAND memory Plane address */ |
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108 |
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109 uint16_t Block; /*!< NAND memory Block address */ |
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110 |
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111 }NAND_AddressTypeDef; |
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112 |
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113 /** |
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114 * @brief NAND Memory info Structure definition |
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115 */ |
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116 typedef struct |
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117 { |
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118 uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes |
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119 for 8 bits adressing or words for 16 bits addressing */ |
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120 |
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121 uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes |
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122 for 8 bits adressing or words for 16 bits addressing */ |
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123 |
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124 uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */ |
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125 |
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126 uint32_t BlockNbr; /*!< NAND memory number of total blocks */ |
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127 |
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128 uint32_t PlaneNbr; /*!< NAND memory number of planes */ |
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129 |
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130 uint32_t PlaneSize; /*!< NAND memory plane size measured in number of blocks */ |
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131 |
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132 FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This |
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133 parameter is mandatory for some NAND parts after the read |
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134 command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence. |
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135 Example: Toshiba THTH58BYG3S0HBAI6. |
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136 This parameter could be ENABLE or DISABLE |
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137 Please check the Read Mode sequnece in the NAND device datasheet */ |
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138 }NAND_DeviceConfigTypeDef; |
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139 |
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140 /** |
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141 * @brief NAND handle Structure definition |
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142 */ |
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143 typedef struct |
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144 { |
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145 FMC_NAND_TypeDef *Instance; /*!< Register base address */ |
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146 |
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147 FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */ |
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148 |
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149 HAL_LockTypeDef Lock; /*!< NAND locking object */ |
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150 |
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151 __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */ |
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152 |
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153 NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */ |
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154 |
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155 }NAND_HandleTypeDef; |
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156 /** |
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157 * @} |
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158 */ |
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159 |
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160 /* Exported constants --------------------------------------------------------*/ |
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161 /* Exported macros ------------------------------------------------------------*/ |
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162 /** @defgroup NAND_Exported_Macros NAND Exported Macros |
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163 * @{ |
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164 */ |
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165 |
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166 /** @brief Reset NAND handle state |
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167 * @param __HANDLE__ specifies the NAND handle. |
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168 * @retval None |
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169 */ |
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170 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET) |
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171 |
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172 /** |
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173 * @} |
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174 */ |
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175 |
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176 /* Exported functions --------------------------------------------------------*/ |
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177 /** @addtogroup NAND_Exported_Functions NAND Exported Functions |
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178 * @{ |
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179 */ |
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180 |
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181 /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions |
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182 * @{ |
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183 */ |
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184 |
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185 /* Initialization/de-initialization functions ********************************/ |
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186 /* Initialization/de-initialization functions ********************************/ |
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187 HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); |
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188 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); |
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189 |
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190 HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig); |
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191 |
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192 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID); |
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193 |
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194 void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand); |
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195 void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand); |
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196 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand); |
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197 void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand); |
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198 |
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199 /** |
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200 * @} |
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201 */ |
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202 |
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203 /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions |
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204 * @{ |
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205 */ |
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206 |
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207 /* IO operation functions ****************************************************/ |
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208 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand); |
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209 |
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210 HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead); |
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211 HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite); |
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212 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead); |
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213 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); |
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214 |
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215 HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead); |
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216 HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite); |
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217 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead); |
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218 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite); |
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219 |
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220 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); |
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221 |
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222 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); |
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223 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); |
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224 |
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225 /** |
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226 * @} |
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227 */ |
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228 |
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229 /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions |
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230 * @{ |
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231 */ |
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232 |
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233 /* NAND Control functions ****************************************************/ |
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234 HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand); |
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235 HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand); |
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236 HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout); |
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237 |
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238 /** |
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239 * @} |
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240 */ |
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241 |
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242 /** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions |
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243 * @{ |
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244 */ |
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245 /* NAND State functions *******************************************************/ |
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246 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand); |
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247 /** |
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248 * @} |
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249 */ |
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250 |
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251 /** |
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252 * @} |
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253 */ |
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254 |
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255 /* Private types -------------------------------------------------------------*/ |
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256 /* Private variables ---------------------------------------------------------*/ |
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257 /* Private constants ---------------------------------------------------------*/ |
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258 /** @defgroup NAND_Private_Constants NAND Private Constants |
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259 * @{ |
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260 */ |
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261 #define NAND_DEVICE1 0x70000000U |
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262 #define NAND_DEVICE2 0x80000000U |
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263 #define NAND_WRITE_TIMEOUT 0x01000000U |
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264 |
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265 #define CMD_AREA ((uint32_t)(1U<<16U)) /* A16 = CLE high */ |
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266 #define ADDR_AREA ((uint32_t)(1U<<17U)) /* A17 = ALE high */ |
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267 |
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268 #define NAND_CMD_AREA_A ((uint8_t)0x00) |
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269 #define NAND_CMD_AREA_B ((uint8_t)0x01) |
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270 #define NAND_CMD_AREA_C ((uint8_t)0x50) |
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271 #define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30) |
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272 |
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273 #define NAND_CMD_WRITE0 ((uint8_t)0x80) |
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274 #define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10) |
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275 #define NAND_CMD_ERASE0 ((uint8_t)0x60) |
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276 #define NAND_CMD_ERASE1 ((uint8_t)0xD0) |
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277 #define NAND_CMD_READID ((uint8_t)0x90) |
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278 #define NAND_CMD_STATUS ((uint8_t)0x70) |
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279 #define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A) |
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280 #define NAND_CMD_RESET ((uint8_t)0xFF) |
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281 |
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282 /* NAND memory status */ |
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283 #define NAND_VALID_ADDRESS 0x00000100U |
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284 #define NAND_INVALID_ADDRESS 0x00000200U |
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285 #define NAND_TIMEOUT_ERROR 0x00000400U |
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286 #define NAND_BUSY 0x00000000U |
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287 #define NAND_ERROR 0x00000001U |
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288 #define NAND_READY 0x00000040U |
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289 /** |
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290 * @} |
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291 */ |
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292 |
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293 /* Private macros ------------------------------------------------------------*/ |
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294 /** @defgroup NAND_Private_Macros NAND Private Macros |
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295 * @{ |
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296 */ |
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297 |
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298 /** |
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299 * @brief NAND memory address computation. |
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300 * @param __ADDRESS__ NAND memory address. |
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301 * @param __HANDLE__ NAND handle. |
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302 * @retval NAND Raw address value |
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303 */ |
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304 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \ |
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305 (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize))) |
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306 |
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307 /** |
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308 * @brief NAND memory Column address computation. |
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309 * @param __HANDLE__ NAND handle. |
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310 * @retval NAND Raw address value |
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311 */ |
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312 #define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize) |
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313 |
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314 /** |
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315 * @brief NAND memory address cycling. |
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316 * @param __ADDRESS__ NAND memory address. |
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317 * @retval NAND address cycling value. |
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318 */ |
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319 #define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */ |
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320 #define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */ |
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321 #define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */ |
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322 #define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */ |
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323 |
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324 /** |
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325 * @brief NAND memory Columns cycling. |
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326 * @param __ADDRESS__ NAND memory address. |
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327 * @retval NAND Column address cycling value. |
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328 */ |
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329 #define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st Column addressing cycle */ |
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330 #define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */ |
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331 |
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332 /** |
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333 * @} |
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334 */ |
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335 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\ |
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336 STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\ |
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337 STM32F446xx || STM32F469xx || STM32F479xx */ |
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338 |
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339 /** |
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340 * @} |
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341 */ |
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342 /** |
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343 * @} |
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344 */ |
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345 |
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346 /** |
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347 * @} |
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348 */ |
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349 |
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350 #ifdef __cplusplus |
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351 } |
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352 #endif |
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353 |
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354 #endif /* __STM32F4xx_HAL_NAND_H */ |
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355 |
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356 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |