Mercurial > public > ostc4
annotate Small_CPU/Src/uart.c @ 932:effadaa3a1f7 Evo_2_23
Cleanup Gnss UART implementation:
The first draft of the internal UART implementation was just a copy of the external UART handling. To avoid duplicated code and maintainance issue both UARTs (external/internal 6/1) share the same functions. To enable this a control structure has to be used as function input which defines the none shared resources like DMA control and rx/tx buffers
author | Ideenmodellierer |
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date | Sat, 07 Dec 2024 21:28:08 +0100 |
parents | 7c996354b8ac |
children | 43055e069bd1 |
rev | line source |
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38 | 1 /** |
2 ****************************************************************************** | |
3 * @file uart.c | |
4 * @author heinrichs weikamp gmbh | |
5 * @version V0.0.1 | |
6 * @date 27-March-2014 | |
7 * @brief button control | |
8 * | |
9 @verbatim | |
10 ============================================================================== | |
11 ##### How to use ##### | |
12 ============================================================================== | |
13 @endverbatim | |
14 ****************************************************************************** | |
15 * @attention | |
16 * | |
17 * <h2><center>© COPYRIGHT(c) 2015 heinrichs weikamp</center></h2> | |
18 * | |
19 ****************************************************************************** | |
20 */ | |
21 /* Includes ------------------------------------------------------------------*/ | |
22 #include "uart.h" | |
794 | 23 #include "uartProtocol_O2.h" |
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24 #include "uartProtocol_Co2.h" |
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25 #include "uartProtocol_Sentinel.h" |
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26 #include "uartProtocol_GNSS.h" |
662 | 27 #include "externalInterface.h" |
28 #include "data_exchange.h" | |
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29 #include <string.h> /* memset */ |
38 | 30 |
922 | 31 #ifdef ENABLE_GPIO_V2 |
32 extern UART_HandleTypeDef huart6; | |
932 | 33 extern sUartComCtrl Uart6Ctrl; |
922 | 34 #endif |
889 | 35 |
38 | 36 /* Private variables ---------------------------------------------------------*/ |
37 | |
922 | 38 DMA_HandleTypeDef hdma_usart1_rx, hdma_usart1_tx; |
38 | 39 |
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40 uint8_t rxBuffer[CHUNK_SIZE * CHUNKS_PER_BUFFER]; /* The complete buffer has a X * chunk size to allow variations in buffer read time */ |
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41 uint8_t txBuffer[CHUNK_SIZE]; /* tx uses less bytes */ |
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42 uint8_t txBufferQue[TX_BUF_SIZE]; /* In MUX mode command may be send shortly after each other => allow q 1 entry que */ |
932 | 43 |
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44 |
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45 static uint8_t lastCmdIndex; /* Index of last command which has not been completely received */ |
932 | 46 |
47 sUartComCtrl Uart1Ctrl; | |
48 static sUartComCtrl* pGnssCtrl = NULL; | |
794 | 49 |
921 | 50 static uint32_t LastCmdRequestTick = 0; /* Used by ADC handler to avoid interferance with UART communication */ |
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51 |
38 | 52 /* Exported functions --------------------------------------------------------*/ |
53 | |
932 | 54 |
55 void UART_SetGnssCtrl(sUartComCtrl* pTarget) | |
56 { | |
57 pGnssCtrl = pTarget; | |
58 } | |
59 | |
60 sUartComCtrl* UART_GetGnssCtrl() | |
61 { | |
62 return pGnssCtrl; | |
63 } | |
64 | |
65 | |
66 void UART_clearRxBuffer(sUartComCtrl* pUartCtrl) | |
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67 { |
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68 uint16_t index = 0; |
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69 do |
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70 { |
932 | 71 pUartCtrl->pRxBuffer[index++] = BUFFER_NODATA_LOW; |
72 pUartCtrl->pRxBuffer[index++] = BUFFER_NODATA_HIGH; | |
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73 } while (index < sizeof(rxBuffer)); |
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74 |
932 | 75 pUartCtrl->rxReadIndex = 0; |
76 pUartCtrl->rxWriteIndex = 0; | |
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77 } |
794 | 78 |
662 | 79 void MX_USART1_UART_Init(void) |
38 | 80 { |
662 | 81 /* regular init */ |
82 huart1.Instance = USART1; | |
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83 huart1.Init.BaudRate = 19200; |
662 | 84 huart1.Init.WordLength = UART_WORDLENGTH_8B; |
85 huart1.Init.StopBits = UART_STOPBITS_1; | |
86 huart1.Init.Parity = UART_PARITY_NONE; | |
87 huart1.Init.Mode = UART_MODE_TX_RX; | |
88 huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; | |
89 huart1.Init.OverSampling = UART_OVERSAMPLING_16; | |
90 | |
91 HAL_UART_Init(&huart1); | |
92 | |
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93 MX_USART1_DMA_Init(); |
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94 |
932 | 95 UART_clearRxBuffer(&Uart1Ctrl); |
662 | 96 lastCmdIndex = 0; |
932 | 97 |
98 Uart1Ctrl.pHandle = &huart1; | |
99 Uart1Ctrl.rxWriteIndex = 0; | |
100 Uart1Ctrl.rxReadIndex = 0; | |
101 Uart1Ctrl.dmaRxActive = 0; | |
102 Uart1Ctrl.dmaTxActive = 0; | |
103 Uart1Ctrl.pRxBuffer = rxBuffer; | |
104 Uart1Ctrl.pTxBuffer = txBuffer; | |
105 Uart1Ctrl.txBufferQueLen = 0; | |
106 | |
107 #ifndef ENABLE_GPIO_V2 | |
108 UART_SetGnssCtrl(&Uart1Ctrl); | |
109 #endif | |
662 | 110 } |
38 | 111 |
889 | 112 |
113 | |
662 | 114 void MX_USART1_UART_DeInit(void) |
115 { | |
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116 HAL_DMA_Abort(&hdma_usart1_rx); |
662 | 117 HAL_DMA_DeInit(&hdma_usart1_rx); |
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118 HAL_DMA_Abort(&hdma_usart1_tx); |
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119 HAL_DMA_DeInit(&hdma_usart1_tx); |
662 | 120 HAL_UART_DeInit(&huart1); |
932 | 121 Uart1Ctrl.dmaRxActive = 0; |
122 Uart1Ctrl.dmaTxActive = 0; | |
123 Uart1Ctrl.txBufferQueLen = 0; | |
662 | 124 } |
125 | |
126 void MX_USART1_DMA_Init() | |
127 { | |
128 /* DMA controller clock enable */ | |
129 __DMA2_CLK_ENABLE(); | |
130 | |
131 /* Peripheral DMA init*/ | |
132 hdma_usart1_rx.Instance = DMA2_Stream5; | |
133 hdma_usart1_rx.Init.Channel = DMA_CHANNEL_4; | |
134 hdma_usart1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; //DMA_MEMORY_TO_PERIPH; | |
135 hdma_usart1_rx.Init.PeriphInc = DMA_PINC_DISABLE; | |
136 hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE; | |
137 hdma_usart1_rx.Init.PeriphDataAlignment = DMA_MDATAALIGN_BYTE; | |
138 hdma_usart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; | |
139 hdma_usart1_rx.Init.Mode = DMA_NORMAL; | |
140 hdma_usart1_rx.Init.Priority = DMA_PRIORITY_LOW; | |
141 hdma_usart1_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; | |
142 HAL_DMA_Init(&hdma_usart1_rx); | |
143 | |
144 __HAL_LINKDMA(&huart1,hdmarx,hdma_usart1_rx); | |
145 | |
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146 hdma_usart1_tx.Instance = DMA2_Stream7; |
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147 hdma_usart1_tx.Init.Channel = DMA_CHANNEL_4; |
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148 hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; |
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149 hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE; |
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150 hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE; |
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151 hdma_usart1_tx.Init.PeriphDataAlignment = DMA_MDATAALIGN_BYTE; |
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152 hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; |
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153 hdma_usart1_tx.Init.Mode = DMA_NORMAL; |
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154 hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW; |
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155 hdma_usart1_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; |
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156 HAL_DMA_Init(&hdma_usart1_tx); |
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157 |
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158 __HAL_LINKDMA(&huart1,hdmatx,hdma_usart1_tx); |
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159 |
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160 |
662 | 161 /* DMA interrupt init */ |
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162 HAL_NVIC_SetPriority(DMA2_Stream5_IRQn, 2, 2); |
662 | 163 HAL_NVIC_EnableIRQ(DMA2_Stream5_IRQn); |
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164 HAL_NVIC_SetPriority(DMA2_Stream7_IRQn, 2, 1); |
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165 HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn); |
38 | 166 } |
167 | |
932 | 168 void UART_MUX_SelectAddress(uint8_t muxAddress) |
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169 { |
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170 uint8_t indexstr[4]; |
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171 |
794 | 172 if(muxAddress <= MAX_MUX_CHANNEL) |
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173 { |
794 | 174 indexstr[0] = '~'; |
175 indexstr[1] = muxAddress; | |
176 indexstr[2] = 0x0D; | |
177 indexstr[3] = 0x0A; | |
932 | 178 if(!Uart1Ctrl.dmaTxActive) |
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179 { |
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180 memcpy(txBuffer, indexstr, 4); |
932 | 181 Uart1Ctrl.dmaTxActive = 0; |
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182 if(HAL_OK == HAL_UART_Transmit_DMA(&huart1,txBuffer,4)) |
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183 { |
932 | 184 Uart1Ctrl.dmaTxActive = 1; |
185 while(Uart1Ctrl.dmaTxActive) | |
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186 { |
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187 HAL_Delay(1); |
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188 } |
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189 } |
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190 } |
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191 else |
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192 { |
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193 memcpy(txBufferQue, indexstr, 4); |
932 | 194 Uart1Ctrl.txBufferQueLen = 4; |
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195 } |
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196 } |
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197 } |
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198 |
794 | 199 |
200 void UART_SendCmdString(uint8_t *cmdString) | |
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201 { |
794 | 202 uint8_t cmdLength = strlen((char*)cmdString); |
203 | |
932 | 204 if(Uart1Ctrl.dmaTxActive == 0) |
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205 { |
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206 if(cmdLength < TX_BUF_SIZE) /* A longer string is an indication for a missing 0 termination */ |
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207 { |
932 | 208 if(Uart1Ctrl.dmaRxActive == 0) |
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209 { |
932 | 210 UART_StartDMA_Receiption(&Uart1Ctrl); |
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211 } |
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212 memcpy(txBuffer, cmdString, cmdLength); |
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213 if(HAL_OK == HAL_UART_Transmit_DMA(&huart1,txBuffer,cmdLength)) |
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214 { |
932 | 215 Uart1Ctrl.dmaTxActive = 1; |
921 | 216 LastCmdRequestTick = HAL_GetTick(); |
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217 } |
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218 } |
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219 } |
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220 else |
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221 { |
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222 memcpy(txBufferQue, cmdString, cmdLength); |
932 | 223 Uart1Ctrl.txBufferQueLen = cmdLength; |
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224 } |
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225 } |
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226 |
922 | 227 void UART_SendCmdUbx(const uint8_t *cmd, uint8_t len) |
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228 { |
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229 if(len < TX_BUF_SIZE) /* A longer string is an indication for a missing 0 termination */ |
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230 { |
932 | 231 if(pGnssCtrl != NULL) |
794 | 232 { |
932 | 233 if(pGnssCtrl->dmaRxActive == 0) |
234 { | |
235 UART_StartDMA_Receiption(pGnssCtrl); | |
236 } | |
237 memcpy(pGnssCtrl->pTxBuffer, cmd, len); | |
238 if(HAL_OK == HAL_UART_Transmit_DMA(pGnssCtrl->pHandle,pGnssCtrl->pTxBuffer,len)) | |
239 { | |
240 pGnssCtrl->dmaTxActive = 1; | |
241 LastCmdRequestTick = HAL_GetTick(); | |
242 } | |
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243 } |
794 | 244 } |
245 } | |
246 | |
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247 |
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248 void StringToInt(char *pstr, uint32_t *puInt32) |
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249 { |
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250 uint8_t index = 0; |
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251 uint32_t result = 0; |
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252 while((pstr[index] >= '0') && (pstr[index] <= '9')) |
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253 { |
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254 result *=10; |
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255 result += pstr[index] - '0'; |
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256 index++; |
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257 } |
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258 *puInt32 = result; |
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259 } |
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260 |
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261 void StringToUInt64(char *pstr, uint64_t *puint64) |
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262 { |
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263 uint8_t index = 0; |
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264 uint64_t result = 0; |
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265 while((pstr[index] >= '0') && (pstr[index] <= '9')) |
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266 { |
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267 result *=10; |
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268 result += pstr[index] - '0'; |
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269 index++; |
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270 } |
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271 *puint64 = result; |
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272 } |
662 | 273 |
932 | 274 void UART_StartDMA_Receiption(sUartComCtrl* pUartCtrl) |
742 | 275 { |
932 | 276 if(pUartCtrl->dmaRxActive == 0) |
742 | 277 { |
932 | 278 if(((pUartCtrl->rxWriteIndex / CHUNK_SIZE) != (pUartCtrl->rxReadIndex / CHUNK_SIZE)) || ((UART_isEndIndication(pUartCtrl, pUartCtrl->rxWriteIndex)) && (UART_isEndIndication(pUartCtrl, pUartCtrl->rxWriteIndex + 1)))) /* start next transfer if we did not catch up with read index */ |
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279 { |
932 | 280 if(HAL_OK == HAL_UART_Receive_DMA (pUartCtrl->pHandle, &pUartCtrl->pRxBuffer[pUartCtrl->rxWriteIndex], CHUNK_SIZE)) |
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281 { |
932 | 282 pUartCtrl->dmaRxActive = 1; |
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283 } |
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284 } |
742 | 285 } |
286 } | |
690 | 287 |
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288 void UART_ChangeBaudrate(uint32_t newBaudrate) |
38 | 289 { |
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290 MX_USART1_UART_DeInit(); |
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291 huart1.Init.BaudRate = newBaudrate; |
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292 HAL_UART_Init(&huart1); |
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293 MX_USART1_DMA_Init(); |
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294 HAL_NVIC_SetPriority(USART1_IRQn, 1, 3); |
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295 HAL_NVIC_EnableIRQ(USART1_IRQn); |
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296 |
932 | 297 UART_clearRxBuffer(&Uart1Ctrl); |
298 Uart1Ctrl.rxReadIndex = 0; | |
299 Uart1Ctrl.rxWriteIndex = 0; | |
300 Uart1Ctrl.dmaRxActive = 0; | |
301 Uart1Ctrl.txBufferQueLen = 0; | |
38 | 302 } |
690 | 303 |
932 | 304 void UART_HandleRxComplete(sUartComCtrl* pUartCtrl) |
305 { | |
306 pUartCtrl->dmaRxActive = 0; | |
307 pUartCtrl->rxWriteIndex+=CHUNK_SIZE; | |
308 if(pUartCtrl->rxWriteIndex >= CHUNK_SIZE * CHUNKS_PER_BUFFER) | |
309 { | |
310 pUartCtrl->rxWriteIndex = 0; | |
311 } | |
312 UART_StartDMA_Receiption(pUartCtrl); | |
313 } | |
662 | 314 void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) |
38 | 315 { |
932 | 316 if(huart == &huart1) |
317 { | |
318 UART_HandleRxComplete(&Uart1Ctrl); | |
319 } | |
922 | 320 #ifdef ENABLE_GPIO_V2 |
932 | 321 if(huart == &huart6) |
322 { | |
323 UART_HandleRxComplete(&Uart6Ctrl); | |
324 } | |
922 | 325 #endif |
38 | 326 } |
932 | 327 |
328 void UART_HandleTxComplete(sUartComCtrl* pUartCtrl) | |
329 { | |
330 pUartCtrl->dmaTxActive = 0; | |
331 UART_WriteData(pUartCtrl); | |
332 if(pUartCtrl->txBufferQueLen) | |
333 { | |
334 memcpy(pUartCtrl->pTxBuffer, pUartCtrl->pTxQue, pUartCtrl->txBufferQueLen); | |
335 HAL_UART_Transmit_DMA(pUartCtrl->pHandle,pUartCtrl->pTxBuffer,pUartCtrl->txBufferQueLen); | |
336 pUartCtrl->dmaTxActive = 1; | |
337 pUartCtrl->txBufferQueLen = 0; | |
338 } | |
339 } | |
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340 void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) |
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341 { |
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342 if(huart == &huart1) |
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343 { |
932 | 344 UART_HandleTxComplete(&Uart1Ctrl); |
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345 } |
922 | 346 #ifdef ENABLE_GPIO_V2 |
347 if(huart == &huart6) | |
348 { | |
932 | 349 UART_HandleTxComplete(&Uart6Ctrl); |
922 | 350 } |
351 #endif | |
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352 } |
38 | 353 |
932 | 354 uint8_t UART_isEndIndication(sUartComCtrl* pCtrl, uint8_t index) |
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355 { |
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356 uint8_t ret = 0; |
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357 if(index % 2) |
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358 { |
932 | 359 if(pCtrl->pRxBuffer[index] == BUFFER_NODATA_HIGH) |
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360 { |
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361 ret = 1; |
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362 } |
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363 } |
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364 else |
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365 { |
932 | 366 if(pCtrl->pRxBuffer[index] == BUFFER_NODATA_LOW) |
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367 { |
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368 ret = 1; |
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369 } |
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370 } |
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371 |
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372 return ret; |
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373 } |
794 | 374 void UART_ReadData(uint8_t sensorType) |
375 { | |
932 | 376 uint8_t localRX; |
377 uint8_t futureIndex; | |
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378 uint8_t moreData = 0; |
38 | 379 |
932 | 380 sUartComCtrl* pUartCtrl; |
381 | |
382 if(sensorType == SENSOR_GNSS) | |
383 { | |
384 #ifdef ENABLE_GPIO_V2 | |
385 pUartCtrl = &Uart6Ctrl; | |
386 #else | |
387 pUartCtrl = &Uart1Ctrl; | |
388 #endif | |
389 } | |
390 else | |
391 { | |
392 pUartCtrl = &Uart1Ctrl; | |
393 } | |
394 localRX = pUartCtrl->rxReadIndex; | |
395 futureIndex = pUartCtrl->rxReadIndex + 1; | |
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396 if(futureIndex >= CHUNK_SIZE * CHUNKS_PER_BUFFER) |
794 | 397 { |
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398 futureIndex = 0; |
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399 } |
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400 |
932 | 401 if(!UART_isEndIndication(pUartCtrl, futureIndex)) |
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402 { |
932 | 403 moreData = 1; |
404 } | |
405 | |
406 //if((!isEndIndication(pUartCtrl, localRX)) || (!isEndIndication(pUartCtrl,futureIndex))) do | |
407 if((!UART_isEndIndication(pUartCtrl, localRX)) || (moreData)) | |
408 do | |
409 { | |
410 while((!UART_isEndIndication(pUartCtrl, localRX)) || (moreData)) | |
794 | 411 { |
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412 moreData = 0; |
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413 switch (sensorType) |
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414 { |
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415 case SENSOR_MUX: |
932 | 416 case SENSOR_DIGO2: uartO2_ProcessData(pUartCtrl->pRxBuffer[localRX]); |
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417 break; |
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418 #ifdef ENABLE_CO2_SUPPORT |
932 | 419 case SENSOR_CO2: uartCo2_ProcessData(pUartCtrl->pRxBuffer[localRX]); |
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420 break; |
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421 #endif |
932 | 422 #if defined ENABLE_GNSS_SUPPORT || defined ENABLE_GPIO_V2 |
423 case SENSOR_GNSS: uartGnss_ProcessData(pUartCtrl->pRxBuffer[localRX]); | |
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424 break; |
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425 #endif |
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426 #ifdef ENABLE_SENTINEL_MODE |
932 | 427 case SENSOR_SENTINEL: uartSentinel_ProcessData(pUartCtrl->pRxBuffer[localRX]); |
916
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428 break; |
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429 #endif |
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430 default: |
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431 break; |
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432 } |
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433 if(localRX % 2) |
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434 { |
932 | 435 pUartCtrl->pRxBuffer[localRX] = BUFFER_NODATA_HIGH; |
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436 } |
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437 else |
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438 { |
932 | 439 pUartCtrl->pRxBuffer[localRX] = BUFFER_NODATA_LOW; |
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440 } |
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441 |
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442 localRX++; |
932 | 443 pUartCtrl->rxReadIndex++; |
444 if(pUartCtrl->rxReadIndex >= CHUNK_SIZE * CHUNKS_PER_BUFFER) | |
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445 { |
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446 localRX = 0; |
932 | 447 pUartCtrl->rxReadIndex = 0; |
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448 } |
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449 futureIndex++; |
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450 if(futureIndex >= CHUNK_SIZE * CHUNKS_PER_BUFFER) |
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451 { |
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452 futureIndex = 0; |
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453 } |
794 | 454 } |
932 | 455 if(!UART_isEndIndication(pUartCtrl, futureIndex)) |
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456 { |
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457 moreData = 1; |
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458 } |
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459 } while(moreData); |
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460 } |
794 | 461 |
932 | 462 void UART_WriteData(sUartComCtrl* pUartCtrl) |
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463 { |
932 | 464 if(pUartCtrl->pHandle->hdmatx->State == HAL_DMA_STATE_READY) |
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465 { |
932 | 466 pUartCtrl->pHandle->gState = HAL_UART_STATE_READY; |
467 pUartCtrl->dmaTxActive = 0; | |
794 | 468 } |
932 | 469 if(pUartCtrl->pHandle->hdmarx->State == HAL_DMA_STATE_READY) |
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470 { |
932 | 471 pUartCtrl->pHandle->RxState = HAL_UART_STATE_READY; |
472 pUartCtrl->dmaRxActive = 0; | |
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473 } |
794 | 474 } |
475 | |
476 void UART_FlushRxBuffer(void) | |
477 { | |
932 | 478 uint8_t futureIndex = Uart1Ctrl.rxReadIndex + 1; |
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479 |
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480 if(futureIndex >= CHUNK_SIZE * CHUNKS_PER_BUFFER) |
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481 { |
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482 futureIndex = 0; |
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483 } |
932 | 484 while((rxBuffer[Uart1Ctrl.rxReadIndex] != BUFFER_NODATA_LOW) && (rxBuffer[futureIndex] != BUFFER_NODATA_HIGH)) |
794 | 485 { |
932 | 486 if(Uart1Ctrl.rxReadIndex % 2) |
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487 { |
932 | 488 rxBuffer[Uart1Ctrl.rxReadIndex++] = BUFFER_NODATA_HIGH; |
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489 } |
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490 else |
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491 { |
932 | 492 rxBuffer[Uart1Ctrl.rxReadIndex++] = BUFFER_NODATA_LOW; |
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493 } |
932 | 494 if(Uart1Ctrl.rxReadIndex >= CHUNK_SIZE * CHUNKS_PER_BUFFER) |
794 | 495 { |
932 | 496 Uart1Ctrl.rxReadIndex = 0; |
794 | 497 } |
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498 futureIndex++; |
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499 if(futureIndex >= CHUNK_SIZE * CHUNKS_PER_BUFFER) |
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500 { |
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501 futureIndex = 0; |
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502 } |
794 | 503 } |
504 } | |
662 | 505 |
861 | 506 uint8_t UART_isComActive(uint8_t sensorId) |
507 { | |
508 uint8_t active = 1; | |
809 | 509 |
921 | 510 if(time_elapsed_ms(LastCmdRequestTick, HAL_GetTick()) > 300) /* UART activity should be inactive 300ms after last command */ |
861 | 511 { |
512 active = 0; | |
513 } | |
514 return active; | |
515 } | |
809 | 516 |
921 | 517 |
38 | 518 /************************ (C) COPYRIGHT heinrichs weikamp *****END OF FILE****/ |