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annotate Common/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_utils.c @ 484:eea282e733e8 FixLayout_Header_LogView
Small corrections layout Divelog page 1:
Reading the code the information on the right side of the page should be aligned to the right border. That was not done because of e.g. a to small field of view for a certain string. Introduced a define to have all information aligned to the same position
author | ideenmodellierer |
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date | Tue, 26 May 2020 21:12:46 +0200 |
parents | c78bcbd5deda |
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rev | line source |
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1 /** |
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2 ****************************************************************************** |
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3 * @file stm32f4xx_ll_utils.c |
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4 * @author MCD Application Team |
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5 * @brief UTILS LL module driver. |
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6 ****************************************************************************** |
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7 * @attention |
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8 * |
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9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
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10 * |
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11 * Redistribution and use in source and binary forms, with or without modification, |
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12 * are permitted provided that the following conditions are met: |
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13 * 1. Redistributions of source code must retain the above copyright notice, |
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14 * this list of conditions and the following disclaimer. |
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15 * 2. Redistributions in binary form must reproduce the above copyright notice, |
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16 * this list of conditions and the following disclaimer in the documentation |
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17 * and/or other materials provided with the distribution. |
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18 * 3. Neither the name of STMicroelectronics nor the names of its contributors |
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19 * may be used to endorse or promote products derived from this software |
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20 * without specific prior written permission. |
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21 * |
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22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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32 * |
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33 ****************************************************************************** |
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34 */ |
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35 /* Includes ------------------------------------------------------------------*/ |
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36 #include "stm32f4xx_ll_utils.h" |
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37 #include "stm32f4xx_ll_rcc.h" |
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38 #include "stm32f4xx_ll_system.h" |
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39 #include "stm32f4xx_ll_pwr.h" |
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40 #ifdef USE_FULL_ASSERT |
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41 #include "stm32_assert.h" |
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42 #else |
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43 #define assert_param(expr) ((void)0U) |
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44 #endif /* USE_FULL_ASSERT */ |
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45 |
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46 /** @addtogroup STM32F4xx_LL_Driver |
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47 * @{ |
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48 */ |
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49 |
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50 /** @addtogroup UTILS_LL |
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51 * @{ |
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52 */ |
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53 |
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54 /* Private types -------------------------------------------------------------*/ |
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55 /* Private variables ---------------------------------------------------------*/ |
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56 /* Private constants ---------------------------------------------------------*/ |
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57 /** @addtogroup UTILS_LL_Private_Constants |
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58 * @{ |
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59 */ |
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60 #if defined(RCC_MAX_FREQUENCY_SCALE1) |
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61 #define UTILS_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */ |
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62 #endif /*RCC_MAX_FREQUENCY_SCALE1 */ |
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63 #define UTILS_MAX_FREQUENCY_SCALE2 RCC_MAX_FREQUENCY_SCALE2 /*!< Maximum frequency for system clock at power scale2, in Hz */ |
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64 #if defined(RCC_MAX_FREQUENCY_SCALE3) |
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65 #define UTILS_MAX_FREQUENCY_SCALE3 RCC_MAX_FREQUENCY_SCALE3 /*!< Maximum frequency for system clock at power scale3, in Hz */ |
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66 #endif /* MAX_FREQUENCY_SCALE3 */ |
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67 |
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68 /* Defines used for PLL range */ |
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69 #define UTILS_PLLVCO_INPUT_MIN RCC_PLLVCO_INPUT_MIN /*!< Frequency min for PLLVCO input, in Hz */ |
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70 #define UTILS_PLLVCO_INPUT_MAX RCC_PLLVCO_INPUT_MAX /*!< Frequency max for PLLVCO input, in Hz */ |
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71 #define UTILS_PLLVCO_OUTPUT_MIN RCC_PLLVCO_OUTPUT_MIN /*!< Frequency min for PLLVCO output, in Hz */ |
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72 #define UTILS_PLLVCO_OUTPUT_MAX RCC_PLLVCO_OUTPUT_MAX /*!< Frequency max for PLLVCO output, in Hz */ |
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73 |
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74 /* Defines used for HSE range */ |
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75 #define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */ |
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76 #define UTILS_HSE_FREQUENCY_MAX 26000000U /*!< Frequency max for HSE frequency, in Hz */ |
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77 |
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78 /* Defines used for FLASH latency according to HCLK Frequency */ |
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79 #if defined(FLASH_SCALE1_LATENCY1_FREQ) |
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80 #define UTILS_SCALE1_LATENCY1_FREQ FLASH_SCALE1_LATENCY1_FREQ /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */ |
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81 #endif |
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82 #if defined(FLASH_SCALE1_LATENCY2_FREQ) |
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83 #define UTILS_SCALE1_LATENCY2_FREQ FLASH_SCALE1_LATENCY2_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */ |
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84 #endif |
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85 #if defined(FLASH_SCALE1_LATENCY3_FREQ) |
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86 #define UTILS_SCALE1_LATENCY3_FREQ FLASH_SCALE1_LATENCY3_FREQ /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */ |
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87 #endif |
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88 #if defined(FLASH_SCALE1_LATENCY4_FREQ) |
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89 #define UTILS_SCALE1_LATENCY4_FREQ FLASH_SCALE1_LATENCY4_FREQ /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */ |
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90 #endif |
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91 #if defined(FLASH_SCALE1_LATENCY5_FREQ) |
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92 #define UTILS_SCALE1_LATENCY5_FREQ FLASH_SCALE1_LATENCY5_FREQ /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */ |
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93 #endif |
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94 #define UTILS_SCALE2_LATENCY1_FREQ FLASH_SCALE2_LATENCY1_FREQ /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */ |
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95 #define UTILS_SCALE2_LATENCY2_FREQ FLASH_SCALE2_LATENCY2_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */ |
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96 #if defined(FLASH_SCALE2_LATENCY3_FREQ) |
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97 #define UTILS_SCALE2_LATENCY3_FREQ FLASH_SCALE2_LATENCY3_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */ |
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98 #endif |
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99 #if defined(FLASH_SCALE2_LATENCY4_FREQ) |
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100 #define UTILS_SCALE2_LATENCY4_FREQ FLASH_SCALE2_LATENCY4_FREQ /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */ |
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101 #endif |
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102 #if defined(FLASH_SCALE2_LATENCY5_FREQ) |
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103 #define UTILS_SCALE2_LATENCY5_FREQ FLASH_SCALE2_LATENCY5_FREQ /*!< HCLK frequency to set FLASH latency 5 in power scale 2 */ |
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104 #endif |
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105 #if defined(FLASH_SCALE3_LATENCY1_FREQ) |
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106 #define UTILS_SCALE3_LATENCY1_FREQ FLASH_SCALE3_LATENCY1_FREQ /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */ |
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107 #endif |
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108 #if defined(FLASH_SCALE3_LATENCY2_FREQ) |
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109 #define UTILS_SCALE3_LATENCY2_FREQ FLASH_SCALE3_LATENCY2_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */ |
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110 #endif |
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111 #if defined(FLASH_SCALE3_LATENCY3_FREQ) |
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112 #define UTILS_SCALE3_LATENCY3_FREQ FLASH_SCALE3_LATENCY3_FREQ /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */ |
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113 #endif |
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114 #if defined(FLASH_SCALE3_LATENCY4_FREQ) |
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115 #define UTILS_SCALE3_LATENCY4_FREQ FLASH_SCALE3_LATENCY4_FREQ /*!< HCLK frequency to set FLASH latency 4 in power scale 3 */ |
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116 #endif |
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117 #if defined(FLASH_SCALE3_LATENCY5_FREQ) |
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118 #define UTILS_SCALE3_LATENCY5_FREQ FLASH_SCALE3_LATENCY5_FREQ /*!< HCLK frequency to set FLASH latency 5 in power scale 3 */ |
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119 #endif |
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120 /** |
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121 * @} |
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122 */ |
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123 |
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124 /* Private macros ------------------------------------------------------------*/ |
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125 /** @addtogroup UTILS_LL_Private_Macros |
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126 * @{ |
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127 */ |
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128 #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \ |
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129 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \ |
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130 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \ |
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131 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \ |
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132 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \ |
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133 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \ |
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134 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \ |
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135 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \ |
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136 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512)) |
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137 |
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138 #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \ |
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139 || ((__VALUE__) == LL_RCC_APB1_DIV_2) \ |
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140 || ((__VALUE__) == LL_RCC_APB1_DIV_4) \ |
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141 || ((__VALUE__) == LL_RCC_APB1_DIV_8) \ |
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142 || ((__VALUE__) == LL_RCC_APB1_DIV_16)) |
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143 |
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144 #define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \ |
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145 || ((__VALUE__) == LL_RCC_APB2_DIV_2) \ |
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146 || ((__VALUE__) == LL_RCC_APB2_DIV_4) \ |
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147 || ((__VALUE__) == LL_RCC_APB2_DIV_8) \ |
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148 || ((__VALUE__) == LL_RCC_APB2_DIV_16)) |
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149 |
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150 #define IS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_2) \ |
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151 || ((__VALUE__) == LL_RCC_PLLM_DIV_3) \ |
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152 || ((__VALUE__) == LL_RCC_PLLM_DIV_4) \ |
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153 || ((__VALUE__) == LL_RCC_PLLM_DIV_5) \ |
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154 || ((__VALUE__) == LL_RCC_PLLM_DIV_6) \ |
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155 || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \ |
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156 || ((__VALUE__) == LL_RCC_PLLM_DIV_8) \ |
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157 || ((__VALUE__) == LL_RCC_PLLM_DIV_9) \ |
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158 || ((__VALUE__) == LL_RCC_PLLM_DIV_10) \ |
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159 || ((__VALUE__) == LL_RCC_PLLM_DIV_11) \ |
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160 || ((__VALUE__) == LL_RCC_PLLM_DIV_12) \ |
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161 || ((__VALUE__) == LL_RCC_PLLM_DIV_13) \ |
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162 || ((__VALUE__) == LL_RCC_PLLM_DIV_14) \ |
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163 || ((__VALUE__) == LL_RCC_PLLM_DIV_15) \ |
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164 || ((__VALUE__) == LL_RCC_PLLM_DIV_16) \ |
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165 || ((__VALUE__) == LL_RCC_PLLM_DIV_17) \ |
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166 || ((__VALUE__) == LL_RCC_PLLM_DIV_18) \ |
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167 || ((__VALUE__) == LL_RCC_PLLM_DIV_19) \ |
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168 || ((__VALUE__) == LL_RCC_PLLM_DIV_20) \ |
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169 || ((__VALUE__) == LL_RCC_PLLM_DIV_21) \ |
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170 || ((__VALUE__) == LL_RCC_PLLM_DIV_22) \ |
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171 || ((__VALUE__) == LL_RCC_PLLM_DIV_23) \ |
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172 || ((__VALUE__) == LL_RCC_PLLM_DIV_24) \ |
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173 || ((__VALUE__) == LL_RCC_PLLM_DIV_25) \ |
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174 || ((__VALUE__) == LL_RCC_PLLM_DIV_26) \ |
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175 || ((__VALUE__) == LL_RCC_PLLM_DIV_27) \ |
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176 || ((__VALUE__) == LL_RCC_PLLM_DIV_28) \ |
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177 || ((__VALUE__) == LL_RCC_PLLM_DIV_29) \ |
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178 || ((__VALUE__) == LL_RCC_PLLM_DIV_30) \ |
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179 || ((__VALUE__) == LL_RCC_PLLM_DIV_31) \ |
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180 || ((__VALUE__) == LL_RCC_PLLM_DIV_32) \ |
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181 || ((__VALUE__) == LL_RCC_PLLM_DIV_33) \ |
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182 || ((__VALUE__) == LL_RCC_PLLM_DIV_34) \ |
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183 || ((__VALUE__) == LL_RCC_PLLM_DIV_35) \ |
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184 || ((__VALUE__) == LL_RCC_PLLM_DIV_36) \ |
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185 || ((__VALUE__) == LL_RCC_PLLM_DIV_37) \ |
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186 || ((__VALUE__) == LL_RCC_PLLM_DIV_38) \ |
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187 || ((__VALUE__) == LL_RCC_PLLM_DIV_39) \ |
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188 || ((__VALUE__) == LL_RCC_PLLM_DIV_40) \ |
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189 || ((__VALUE__) == LL_RCC_PLLM_DIV_41) \ |
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190 || ((__VALUE__) == LL_RCC_PLLM_DIV_42) \ |
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191 || ((__VALUE__) == LL_RCC_PLLM_DIV_43) \ |
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192 || ((__VALUE__) == LL_RCC_PLLM_DIV_44) \ |
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193 || ((__VALUE__) == LL_RCC_PLLM_DIV_45) \ |
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194 || ((__VALUE__) == LL_RCC_PLLM_DIV_46) \ |
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195 || ((__VALUE__) == LL_RCC_PLLM_DIV_47) \ |
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196 || ((__VALUE__) == LL_RCC_PLLM_DIV_48) \ |
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197 || ((__VALUE__) == LL_RCC_PLLM_DIV_49) \ |
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198 || ((__VALUE__) == LL_RCC_PLLM_DIV_50) \ |
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199 || ((__VALUE__) == LL_RCC_PLLM_DIV_51) \ |
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200 || ((__VALUE__) == LL_RCC_PLLM_DIV_52) \ |
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201 || ((__VALUE__) == LL_RCC_PLLM_DIV_53) \ |
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202 || ((__VALUE__) == LL_RCC_PLLM_DIV_54) \ |
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203 || ((__VALUE__) == LL_RCC_PLLM_DIV_55) \ |
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204 || ((__VALUE__) == LL_RCC_PLLM_DIV_56) \ |
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205 || ((__VALUE__) == LL_RCC_PLLM_DIV_57) \ |
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206 || ((__VALUE__) == LL_RCC_PLLM_DIV_58) \ |
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207 || ((__VALUE__) == LL_RCC_PLLM_DIV_59) \ |
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208 || ((__VALUE__) == LL_RCC_PLLM_DIV_60) \ |
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209 || ((__VALUE__) == LL_RCC_PLLM_DIV_61) \ |
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210 || ((__VALUE__) == LL_RCC_PLLM_DIV_62) \ |
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211 || ((__VALUE__) == LL_RCC_PLLM_DIV_63)) |
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212 |
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213 #define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((RCC_PLLN_MIN_VALUE <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLN_MAX_VALUE)) |
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214 |
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215 #define IS_LL_UTILS_PLLP_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLP_DIV_2) \ |
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216 || ((__VALUE__) == LL_RCC_PLLP_DIV_4) \ |
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217 || ((__VALUE__) == LL_RCC_PLLP_DIV_6) \ |
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218 || ((__VALUE__) == LL_RCC_PLLP_DIV_8)) |
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219 |
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220 #define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX)) |
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221 |
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222 #define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX)) |
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223 |
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224 #if !defined(RCC_MAX_FREQUENCY_SCALE1) |
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225 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \ |
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226 ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3)) |
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227 |
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228 #elif defined(RCC_MAX_FREQUENCY_SCALE3) |
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229 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \ |
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230 (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \ |
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231 ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3)) |
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232 |
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233 #else |
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234 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \ |
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235 ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2)) |
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236 |
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237 #endif /* RCC_MAX_FREQUENCY_SCALE1*/ |
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238 #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \ |
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239 || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF)) |
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240 |
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241 #define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX)) |
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242 /** |
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243 * @} |
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244 */ |
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245 /* Private function prototypes -----------------------------------------------*/ |
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246 /** @defgroup UTILS_LL_Private_Functions UTILS Private functions |
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247 * @{ |
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248 */ |
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249 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, |
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250 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct); |
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251 static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency); |
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252 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); |
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253 static ErrorStatus UTILS_PLL_IsBusy(void); |
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254 /** |
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255 * @} |
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256 */ |
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257 |
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258 /* Exported functions --------------------------------------------------------*/ |
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259 /** @addtogroup UTILS_LL_Exported_Functions |
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260 * @{ |
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261 */ |
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262 |
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263 /** @addtogroup UTILS_LL_EF_DELAY |
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264 * @{ |
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265 */ |
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266 |
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267 /** |
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268 * @brief This function configures the Cortex-M SysTick source to have 1ms time base. |
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269 * @note When a RTOS is used, it is recommended to avoid changing the Systick |
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270 * configuration by calling this function, for a delay use rather osDelay RTOS service. |
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271 * @param HCLKFrequency HCLK frequency in Hz |
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272 * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq |
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273 * @retval None |
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274 */ |
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275 void LL_Init1msTick(uint32_t HCLKFrequency) |
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276 { |
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277 /* Use frequency provided in argument */ |
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278 LL_InitTick(HCLKFrequency, 1000U); |
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279 } |
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280 |
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281 /** |
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282 * @brief This function provides accurate delay (in milliseconds) based |
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283 * on SysTick counter flag |
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284 * @note When a RTOS is used, it is recommended to avoid using blocking delay |
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285 * and use rather osDelay service. |
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286 * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which |
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287 * will configure Systick to 1ms |
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288 * @param Delay specifies the delay time length, in milliseconds. |
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289 * @retval None |
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290 */ |
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291 void LL_mDelay(uint32_t Delay) |
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292 { |
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293 __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */ |
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294 /* Add this code to indicate that local variable is not used */ |
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295 ((void)tmp); |
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296 |
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297 /* Add a period to guaranty minimum wait */ |
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298 if(Delay < LL_MAX_DELAY) |
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299 { |
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300 Delay++; |
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301 } |
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302 |
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303 while (Delay) |
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304 { |
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305 if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U) |
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306 { |
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307 Delay--; |
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308 } |
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309 } |
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310 } |
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311 |
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312 /** |
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313 * @} |
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314 */ |
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315 |
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316 /** @addtogroup UTILS_EF_SYSTEM |
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317 * @brief System Configuration functions |
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318 * |
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319 @verbatim |
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320 =============================================================================== |
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321 ##### System Configuration functions ##### |
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322 =============================================================================== |
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323 [..] |
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324 System, AHB and APB buses clocks configuration |
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325 |
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326 (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 180000000 Hz. |
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327 @endverbatim |
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328 @internal |
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329 Depending on the device voltage range, the maximum frequency should be |
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330 adapted accordingly to the Refenece manual. |
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331 @endinternal |
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332 * @{ |
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333 */ |
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334 |
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335 /** |
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336 * @brief This function sets directly SystemCoreClock CMSIS variable. |
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337 * @note Variable can be calculated also through SystemCoreClockUpdate function. |
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338 * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) |
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339 * @retval None |
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340 */ |
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341 void LL_SetSystemCoreClock(uint32_t HCLKFrequency) |
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342 { |
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343 /* HCLK clock frequency */ |
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344 SystemCoreClock = HCLKFrequency; |
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345 } |
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346 |
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347 /** |
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348 * @brief This function configures system clock at maximum frequency with HSI as clock source of the PLL |
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349 * @note The application need to ensure that PLL is disabled. |
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350 * @note Function is based on the following formula: |
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351 * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP) |
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352 * - PLLM: ensure that the VCO input frequency ranges from @ref RCC_PLLVCO_INPUT_MIN to @ref RCC_PLLVCO_INPUT_MAX (PLLVCO_input = HSI frequency / PLLM) |
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353 * - PLLN: ensure that the VCO output frequency is between @ref RCC_PLLVCO_OUTPUT_MIN and @ref RCC_PLLVCO_OUTPUT_MAX (PLLVCO_output = PLLVCO_input * PLLN) |
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354 * - PLLP: ensure that max frequency at 180000000 Hz is reach (PLLVCO_output / PLLP) |
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355 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains |
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356 * the configuration information for the PLL. |
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357 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains |
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358 * the configuration information for the BUS prescalers. |
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359 * @retval An ErrorStatus enumeration value: |
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360 * - SUCCESS: Max frequency configuration done |
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361 * - ERROR: Max frequency configuration not done |
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362 */ |
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363 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, |
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364 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) |
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365 { |
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366 ErrorStatus status = SUCCESS; |
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367 uint32_t pllfreq = 0U; |
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368 |
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369 /* Check if one of the PLL is enabled */ |
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370 if(UTILS_PLL_IsBusy() == SUCCESS) |
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371 { |
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372 /* Calculate the new PLL output frequency */ |
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373 pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct); |
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374 |
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375 /* Enable HSI if not enabled */ |
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376 if(LL_RCC_HSI_IsReady() != 1U) |
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377 { |
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378 LL_RCC_HSI_Enable(); |
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379 while (LL_RCC_HSI_IsReady() != 1U) |
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380 { |
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381 /* Wait for HSI ready */ |
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382 } |
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383 } |
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384 |
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385 /* Configure PLL */ |
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386 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, |
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387 UTILS_PLLInitStruct->PLLP); |
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388 |
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389 /* Enable PLL and switch system clock to PLL */ |
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390 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); |
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391 } |
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392 else |
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393 { |
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394 /* Current PLL configuration cannot be modified */ |
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395 status = ERROR; |
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396 } |
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397 |
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398 return status; |
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399 } |
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400 |
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401 /** |
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402 * @brief This function configures system clock with HSE as clock source of the PLL |
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403 * @note The application need to ensure that PLL is disabled. |
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404 * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP) |
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405 * - PLLM: ensure that the VCO input frequency ranges from @ref RCC_PLLVCO_INPUT_MIN to @ref RCC_PLLVCO_INPUT_MAX (PLLVCO_input = HSI frequency / PLLM) |
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406 * - PLLN: ensure that the VCO output frequency is between @ref RCC_PLLVCO_OUTPUT_MIN and @ref RCC_PLLVCO_OUTPUT_MAX (PLLVCO_output = PLLVCO_input * PLLN) |
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407 * - PLLP: ensure that max frequency at 180000000 Hz is reach (PLLVCO_output / PLLP) |
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408 * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 26000000 |
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409 * @param HSEBypass This parameter can be one of the following values: |
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410 * @arg @ref LL_UTILS_HSEBYPASS_ON |
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411 * @arg @ref LL_UTILS_HSEBYPASS_OFF |
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412 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains |
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413 * the configuration information for the PLL. |
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414 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains |
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415 * the configuration information for the BUS prescalers. |
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416 * @retval An ErrorStatus enumeration value: |
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417 * - SUCCESS: Max frequency configuration done |
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418 * - ERROR: Max frequency configuration not done |
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419 */ |
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420 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, |
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421 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) |
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422 { |
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423 ErrorStatus status = SUCCESS; |
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424 uint32_t pllfreq = 0U; |
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425 |
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426 /* Check the parameters */ |
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427 assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency)); |
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428 assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass)); |
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429 |
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430 /* Check if one of the PLL is enabled */ |
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431 if(UTILS_PLL_IsBusy() == SUCCESS) |
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432 { |
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433 /* Calculate the new PLL output frequency */ |
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434 pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct); |
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435 |
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436 /* Enable HSE if not enabled */ |
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437 if(LL_RCC_HSE_IsReady() != 1U) |
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438 { |
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439 /* Check if need to enable HSE bypass feature or not */ |
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440 if(HSEBypass == LL_UTILS_HSEBYPASS_ON) |
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441 { |
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442 LL_RCC_HSE_EnableBypass(); |
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443 } |
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444 else |
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445 { |
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446 LL_RCC_HSE_DisableBypass(); |
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447 } |
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448 |
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449 /* Enable HSE */ |
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450 LL_RCC_HSE_Enable(); |
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451 while (LL_RCC_HSE_IsReady() != 1U) |
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452 { |
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453 /* Wait for HSE ready */ |
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454 } |
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455 } |
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456 |
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457 /* Configure PLL */ |
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458 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, |
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459 UTILS_PLLInitStruct->PLLP); |
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460 |
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461 /* Enable PLL and switch system clock to PLL */ |
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462 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); |
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463 } |
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464 else |
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465 { |
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466 /* Current PLL configuration cannot be modified */ |
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467 status = ERROR; |
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468 } |
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469 |
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470 return status; |
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471 } |
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472 |
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473 /** |
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474 * @} |
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475 */ |
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476 |
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477 /** |
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478 * @} |
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479 */ |
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480 |
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481 /** @addtogroup UTILS_LL_Private_Functions |
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482 * @{ |
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483 */ |
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484 /** |
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485 * @brief Update number of Flash wait states in line with new frequency and current |
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486 voltage range. |
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487 * @note This Function support ONLY devices with supply voltage (voltage range) between 2.7V and 3.6V |
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488 * @param HCLK_Frequency HCLK frequency |
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489 * @retval An ErrorStatus enumeration value: |
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490 * - SUCCESS: Latency has been modified |
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491 * - ERROR: Latency cannot be modified |
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492 */ |
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493 static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency) |
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494 { |
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495 ErrorStatus status = SUCCESS; |
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496 |
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497 uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */ |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
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changeset
|
498 |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
499 /* Frequency cannot be equal to 0 */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
500 if(HCLK_Frequency == 0U) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
501 { |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
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changeset
|
502 status = ERROR; |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
503 } |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
504 else |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
505 { |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
506 if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
507 { |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
508 #if defined (UTILS_SCALE1_LATENCY5_FREQ) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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|
509 if((HCLK_Frequency > UTILS_SCALE1_LATENCY5_FREQ)&&(latency == LL_FLASH_LATENCY_0)) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
510 { |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
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|
511 latency = LL_FLASH_LATENCY_5; |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
512 } |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
513 #endif /*UTILS_SCALE1_LATENCY5_FREQ */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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|
514 #if defined (UTILS_SCALE1_LATENCY4_FREQ) |
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Added current STM32 standandard libraries in version independend folder structure
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diff
changeset
|
515 if((HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ)&&(latency == LL_FLASH_LATENCY_0)) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
516 { |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
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|
517 latency = LL_FLASH_LATENCY_4; |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
518 } |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
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|
519 #endif /* UTILS_SCALE1_LATENCY4_FREQ */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
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|
520 #if defined (UTILS_SCALE1_LATENCY3_FREQ) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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diff
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|
521 if((HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0)) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
522 { |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff
changeset
|
523 latency = LL_FLASH_LATENCY_3; |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
524 } |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
525 #endif /* UTILS_SCALE1_LATENCY3_FREQ */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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|
526 #if defined (UTILS_SCALE1_LATENCY2_FREQ) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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|
527 if((HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0)) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
528 { |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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|
529 latency = LL_FLASH_LATENCY_2; |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
530 } |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
531 else |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
532 { |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
533 if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0)) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
534 { |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
535 latency = LL_FLASH_LATENCY_1; |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
536 } |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
537 } |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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parents:
diff
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|
538 #endif /* UTILS_SCALE1_LATENCY2_FREQ */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
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|
539 } |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
540 if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
541 { |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
542 #if defined (UTILS_SCALE2_LATENCY5_FREQ) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff
changeset
|
543 if((HCLK_Frequency > UTILS_SCALE2_LATENCY5_FREQ)&&(latency == LL_FLASH_LATENCY_0)) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
544 { |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
545 latency = LL_FLASH_LATENCY_5; |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
546 } |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
547 #endif /*UTILS_SCALE1_LATENCY5_FREQ */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
548 #if defined (UTILS_SCALE2_LATENCY4_FREQ) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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diff
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|
549 if((HCLK_Frequency > UTILS_SCALE2_LATENCY4_FREQ)&&(latency == LL_FLASH_LATENCY_0)) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
550 { |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
551 latency = LL_FLASH_LATENCY_4; |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
552 } |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
553 #endif /*UTILS_SCALE1_LATENCY4_FREQ */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
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|
554 #if defined (UTILS_SCALE2_LATENCY3_FREQ) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
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changeset
|
555 if((HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0)) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
556 { |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
557 latency = LL_FLASH_LATENCY_3; |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
558 } |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
559 #endif /*UTILS_SCALE1_LATENCY3_FREQ */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
560 if((HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0)) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
561 { |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
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|
562 latency = LL_FLASH_LATENCY_2; |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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parents:
diff
changeset
|
563 } |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
564 else |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
565 { |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
566 if((HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0)) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
567 { |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
568 latency = LL_FLASH_LATENCY_1; |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
569 } |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
570 } |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
571 } |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
572 #if defined (LL_PWR_REGU_VOLTAGE_SCALE3) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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parents:
diff
changeset
|
573 if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE3) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
574 { |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
575 #if defined (UTILS_SCALE3_LATENCY3_FREQ) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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parents:
diff
changeset
|
576 if((HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0)) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
577 { |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
578 latency = LL_FLASH_LATENCY_3; |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
579 } |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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parents:
diff
changeset
|
580 #endif /*UTILS_SCALE1_LATENCY3_FREQ */ |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
581 #if defined (UTILS_SCALE3_LATENCY2_FREQ) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
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|
582 if((HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0)) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
583 { |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
584 latency = LL_FLASH_LATENCY_2; |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
585 } |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
586 else |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
587 { |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
588 if((HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0)) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
589 { |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
590 latency = LL_FLASH_LATENCY_1; |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
591 } |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
592 } |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
593 } |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
594 #endif /*UTILS_SCALE1_LATENCY2_FREQ */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
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|
595 #endif /* LL_PWR_REGU_VOLTAGE_SCALE3 */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
596 |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
597 LL_FLASH_SetLatency(latency); |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
598 |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
599 /* Check that the new number of wait states is taken into account to access the Flash |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff
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|
600 memory by reading the FLASH_ACR register */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff
changeset
|
601 if(LL_FLASH_GetLatency() != latency) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
602 { |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
603 status = ERROR; |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
604 } |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
605 } |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
606 return status; |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
607 } |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
608 |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
609 /** |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
610 * @brief Function to check that PLL can be modified |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
611 * @param PLL_InputFrequency PLL input frequency (in Hz) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
612 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff
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|
613 * the configuration information for the PLL. |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
614 * @retval PLL output frequency (in Hz) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
615 */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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parents:
diff
changeset
|
616 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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parents:
diff
changeset
|
617 { |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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diff
changeset
|
618 uint32_t pllfreq = 0U; |
c78bcbd5deda
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parents:
diff
changeset
|
619 |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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parents:
diff
changeset
|
620 /* Check the parameters */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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diff
changeset
|
621 assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM)); |
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Added current STM32 standandard libraries in version independend folder structure
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parents:
diff
changeset
|
622 assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN)); |
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Added current STM32 standandard libraries in version independend folder structure
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diff
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|
623 assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP)); |
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624 |
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625 /* Check different PLL parameters according to RM */ |
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626 /* - PLLM: ensure that the VCO input frequency ranges from @ref UTILS_PLLVCO_INPUT_MIN to @ref UTILS_PLLVCO_INPUT_MAX MHz. */ |
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627 pllfreq = PLL_InputFrequency / (UTILS_PLLInitStruct->PLLM & (RCC_PLLCFGR_PLLM >> RCC_PLLCFGR_PLLM_Pos)); |
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628 assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq)); |
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629 |
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630 /* - PLLN: ensure that the VCO output frequency is between @ref UTILS_PLLVCO_OUTPUT_MIN and @ref UTILS_PLLVCO_OUTPUT_MAX .*/ |
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631 pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_PLLCFGR_PLLN_Pos)); |
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632 assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq)); |
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633 |
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634 /* - PLLP: ensure that max frequency at @ref RCC_MAX_FREQUENCY Hz is reached */ |
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635 pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLP >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2); |
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636 assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq)); |
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637 |
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638 return pllfreq; |
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639 } |
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640 |
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641 /** |
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642 * @brief Function to check that PLL can be modified |
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643 * @retval An ErrorStatus enumeration value: |
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644 * - SUCCESS: PLL modification can be done |
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645 * - ERROR: PLL is busy |
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646 */ |
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647 static ErrorStatus UTILS_PLL_IsBusy(void) |
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648 { |
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649 ErrorStatus status = SUCCESS; |
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650 |
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651 /* Check if PLL is busy*/ |
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652 if(LL_RCC_PLL_IsReady() != 0U) |
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653 { |
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654 /* PLL configuration cannot be modified */ |
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655 status = ERROR; |
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656 } |
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657 |
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658 #if defined(RCC_PLLSAI_SUPPORT) |
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659 /* Check if PLLSAI is busy*/ |
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660 if(LL_RCC_PLLSAI_IsReady() != 0U) |
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661 { |
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662 /* PLLSAI1 configuration cannot be modified */ |
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663 status = ERROR; |
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664 } |
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665 #endif /*RCC_PLLSAI_SUPPORT*/ |
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666 #if defined(RCC_PLLI2S_SUPPORT) |
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667 /* Check if PLLI2S is busy*/ |
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668 if(LL_RCC_PLLI2S_IsReady() != 0U) |
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669 { |
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670 /* PLLI2S configuration cannot be modified */ |
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671 status = ERROR; |
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672 } |
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673 #endif /*RCC_PLLI2S_SUPPORT*/ |
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674 return status; |
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|
675 } |
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676 |
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677 /** |
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678 * @brief Function to enable PLL and switch system clock to PLL |
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679 * @param SYSCLK_Frequency SYSCLK frequency |
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680 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains |
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681 * the configuration information for the BUS prescalers. |
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682 * @retval An ErrorStatus enumeration value: |
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683 * - SUCCESS: No problem to switch system to PLL |
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684 * - ERROR: Problem to switch system to PLL |
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685 */ |
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686 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) |
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687 { |
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688 ErrorStatus status = SUCCESS; |
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689 uint32_t hclk_frequency = 0U; |
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|
690 |
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691 assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider)); |
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692 assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider)); |
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693 assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider)); |
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|
694 |
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|
695 /* Calculate HCLK frequency */ |
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696 hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider); |
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|
697 |
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|
698 /* Increasing the number of wait states because of higher CPU frequency */ |
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|
699 if(SystemCoreClock < hclk_frequency) |
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|
700 { |
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|
701 /* Set FLASH latency to highest latency */ |
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702 status = UTILS_SetFlashLatency(hclk_frequency); |
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|
703 } |
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|
704 |
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|
705 /* Update system clock configuration */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
706 if(status == SUCCESS) |
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Added current STM32 standandard libraries in version independend folder structure
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|
707 { |
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|
708 /* Enable PLL */ |
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|
709 LL_RCC_PLL_Enable(); |
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710 while (LL_RCC_PLL_IsReady() != 1U) |
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|
711 { |
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|
712 /* Wait for PLL ready */ |
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|
713 } |
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|
714 |
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|
715 /* Sysclk activation on the main PLL */ |
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|
716 LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); |
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717 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); |
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718 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) |
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|
719 { |
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|
720 /* Wait for system clock switch to PLL */ |
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|
721 } |
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|
722 |
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723 /* Set APB1 & APB2 prescaler*/ |
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724 LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider); |
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725 LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider); |
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|
726 } |
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|
727 |
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728 /* Decreasing the number of wait states because of lower CPU frequency */ |
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729 if(SystemCoreClock > hclk_frequency) |
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|
730 { |
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|
731 /* Set FLASH latency to lowest latency */ |
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732 status = UTILS_SetFlashLatency(hclk_frequency); |
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|
733 } |
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|
734 |
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735 /* Update SystemCoreClock variable */ |
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736 if(status == SUCCESS) |
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|
737 { |
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|
738 LL_SetSystemCoreClock(hclk_frequency); |
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739 } |
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|
740 |
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741 return status; |
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|
742 } |
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743 |
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|
744 /** |
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745 * @} |
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746 */ |
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|
747 |
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748 /** |
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749 * @} |
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|
750 */ |
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751 |
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|
752 /** |
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753 * @} |
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|
754 */ |
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755 |
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756 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |