Mercurial > public > ostc4
annotate Common/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c @ 473:edfc1a464b42 Improve_Button_Sleep
Do not signal power on reset in case of a "warm" reset:
The RTE signaled at every startup a coldstart to the firmware causing a reset of the button responsitivness to default. Even for example after a firmware update. The reset of the values is a wanted behavior in case a value was set which makes it impossible to operate the buttons. This is still possible by removing the battery => real cold start
author | ideenmodellierer |
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date | Tue, 12 May 2020 22:39:18 +0200 |
parents | c78bcbd5deda |
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rev | line source |
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128
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1 /** |
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2 ****************************************************************************** |
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3 * @file stm32f4xx_ll_fmc.c |
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4 * @author MCD Application Team |
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5 * @brief FMC Low Layer HAL module driver. |
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6 * |
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7 * This file provides firmware functions to manage the following |
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8 * functionalities of the Flexible Memory Controller (FMC) peripheral memories: |
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9 * + Initialization/de-initialization functions |
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10 * + Peripheral Control functions |
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11 * + Peripheral State functions |
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12 * |
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13 @verbatim |
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14 ============================================================================== |
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15 ##### FMC peripheral features ##### |
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16 ============================================================================== |
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17 [..] The Flexible memory controller (FMC) includes three memory controllers: |
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18 (+) The NOR/PSRAM memory controller |
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19 (+) The NAND/PC Card memory controller |
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20 (+) The Synchronous DRAM (SDRAM) controller |
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21 |
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22 [..] The FMC functional block makes the interface with synchronous and asynchronous static |
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23 memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are: |
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24 (+) to translate AHB transactions into the appropriate external device protocol |
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25 (+) to meet the access time requirements of the external memory devices |
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26 |
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27 [..] All external memories share the addresses, data and control signals with the controller. |
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28 Each external device is accessed by means of a unique Chip Select. The FMC performs |
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29 only one access at a time to an external device. |
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30 The main features of the FMC controller are the following: |
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31 (+) Interface with static-memory mapped devices including: |
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32 (++) Static random access memory (SRAM) |
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33 (++) Read-only memory (ROM) |
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34 (++) NOR Flash memory/OneNAND Flash memory |
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35 (++) PSRAM (4 memory banks) |
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36 (++) 16-bit PC Card compatible devices |
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37 (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of |
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38 data |
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39 (+) Interface with synchronous DRAM (SDRAM) memories |
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40 (+) Independent Chip Select control for each memory bank |
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41 (+) Independent configuration for each memory bank |
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42 |
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43 @endverbatim |
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44 ****************************************************************************** |
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45 * @attention |
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46 * |
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47 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
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48 * |
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49 * Redistribution and use in source and binary forms, with or without modification, |
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50 * are permitted provided that the following conditions are met: |
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51 * 1. Redistributions of source code must retain the above copyright notice, |
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52 * this list of conditions and the following disclaimer. |
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53 * 2. Redistributions in binary form must reproduce the above copyright notice, |
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54 * this list of conditions and the following disclaimer in the documentation |
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55 * and/or other materials provided with the distribution. |
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56 * 3. Neither the name of STMicroelectronics nor the names of its contributors |
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57 * may be used to endorse or promote products derived from this software |
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58 * without specific prior written permission. |
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59 * |
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60 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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61 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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62 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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63 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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64 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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65 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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66 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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67 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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68 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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69 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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70 * |
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71 ****************************************************************************** |
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72 */ |
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73 |
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74 /* Includes ------------------------------------------------------------------*/ |
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75 #include "stm32f4xx_hal.h" |
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76 |
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77 /** @addtogroup STM32F4xx_HAL_Driver |
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78 * @{ |
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79 */ |
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80 |
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81 /** @defgroup FMC_LL FMC Low Layer |
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82 * @brief FMC driver modules |
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83 * @{ |
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84 */ |
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85 |
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86 #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED) |
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87 |
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88 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) |
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89 |
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90 /* Private typedef -----------------------------------------------------------*/ |
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91 /* Private define ------------------------------------------------------------*/ |
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92 /* Private macro -------------------------------------------------------------*/ |
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93 /* Private variables ---------------------------------------------------------*/ |
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94 /* Private function prototypes -----------------------------------------------*/ |
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95 /* Private functions ---------------------------------------------------------*/ |
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96 /** @addtogroup FMC_LL_Private_Functions |
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97 * @{ |
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98 */ |
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99 |
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100 /** @addtogroup FMC_LL_NORSRAM |
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101 * @brief NORSRAM Controller functions |
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102 * |
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103 @verbatim |
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104 ============================================================================== |
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105 ##### How to use NORSRAM device driver ##### |
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106 ============================================================================== |
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107 |
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108 [..] |
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109 This driver contains a set of APIs to interface with the FMC NORSRAM banks in order |
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110 to run the NORSRAM external devices. |
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111 |
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112 (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit() |
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113 (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init() |
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114 (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init() |
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115 (+) FMC NORSRAM bank extended timing configuration using the function |
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116 FMC_NORSRAM_Extended_Timing_Init() |
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117 (+) FMC NORSRAM bank enable/disable write operation using the functions |
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118 FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable() |
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119 |
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120 |
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121 @endverbatim |
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122 * @{ |
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123 */ |
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124 |
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125 /** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group1 |
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126 * @brief Initialization and Configuration functions |
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127 * |
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128 @verbatim |
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129 ============================================================================== |
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130 ##### Initialization and de_initialization functions ##### |
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131 ============================================================================== |
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132 [..] |
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133 This section provides functions allowing to: |
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134 (+) Initialize and configure the FMC NORSRAM interface |
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135 (+) De-initialize the FMC NORSRAM interface |
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136 (+) Configure the FMC clock and associated GPIOs |
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137 |
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138 @endverbatim |
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139 * @{ |
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140 */ |
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141 |
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142 /** |
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143 * @brief Initialize the FMC_NORSRAM device according to the specified |
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144 * control parameters in the FMC_NORSRAM_InitTypeDef |
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145 * @param Device Pointer to NORSRAM device instance |
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146 * @param Init Pointer to NORSRAM Initialization structure |
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147 * @retval HAL status |
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148 */ |
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149 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init) |
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150 { |
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151 uint32_t tmpr = 0U; |
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152 |
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153 /* Check the parameters */ |
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154 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); |
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155 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank)); |
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156 assert_param(IS_FMC_MUX(Init->DataAddressMux)); |
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157 assert_param(IS_FMC_MEMORY(Init->MemoryType)); |
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158 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); |
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159 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode)); |
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160 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity)); |
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161 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) |
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162 assert_param(IS_FMC_WRAP_MODE(Init->WrapMode)); |
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163 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
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164 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); |
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165 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation)); |
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166 assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal)); |
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167 assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode)); |
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168 assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait)); |
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169 assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst)); |
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170 assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock)); |
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171 assert_param(IS_FMC_PAGESIZE(Init->PageSize)); |
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172 #if defined (STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) |
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173 assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo)); |
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174 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */ |
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175 |
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176 /* Get the BTCR register value */ |
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177 tmpr = Device->BTCR[Init->NSBank]; |
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178 |
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179 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) |
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180 /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN, |
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181 WAITEN, EXTMOD, ASYNCWAIT, CPSIZE, CBURSTRW and CCLKEN bits */ |
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182 tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \ |
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183 FMC_BCR1_MWID | FMC_BCR1_FACCEN | FMC_BCR1_BURSTEN | \ |
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184 FMC_BCR1_WAITPOL | FMC_BCR1_WRAPMOD | FMC_BCR1_WAITCFG | \ |
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185 FMC_BCR1_WREN | FMC_BCR1_WAITEN | FMC_BCR1_EXTMOD | \ |
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186 FMC_BCR1_ASYNCWAIT | FMC_BCR1_CPSIZE | FMC_BCR1_CBURSTRW | \ |
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187 FMC_BCR1_CCLKEN)); |
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188 |
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189 /* Set NORSRAM device control parameters */ |
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190 tmpr |= (uint32_t)(Init->DataAddressMux |\ |
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191 Init->MemoryType |\ |
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192 Init->MemoryDataWidth |\ |
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193 Init->BurstAccessMode |\ |
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194 Init->WaitSignalPolarity |\ |
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195 Init->WrapMode |\ |
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196 Init->WaitSignalActive |\ |
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197 Init->WriteOperation |\ |
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198 Init->WaitSignal |\ |
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199 Init->ExtendedMode |\ |
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200 Init->AsynchronousWait |\ |
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201 Init->PageSize |\ |
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202 Init->WriteBurst |\ |
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203 Init->ContinuousClock); |
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204 #else /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */ |
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205 /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, CPSIZE, WAITCFG, WREN, |
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206 WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW, CCLKEN and WFDIS bits */ |
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207 tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \ |
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208 FMC_BCR1_MWID | FMC_BCR1_FACCEN | FMC_BCR1_BURSTEN | \ |
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209 FMC_BCR1_WAITPOL | FMC_BCR1_WAITCFG | FMC_BCR1_CPSIZE | \ |
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210 FMC_BCR1_WREN | FMC_BCR1_WAITEN | FMC_BCR1_EXTMOD | \ |
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211 FMC_BCR1_ASYNCWAIT | FMC_BCR1_CBURSTRW | FMC_BCR1_CCLKEN | \ |
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212 FMC_BCR1_WFDIS)); |
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213 |
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214 /* Set NORSRAM device control parameters */ |
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215 tmpr |= (uint32_t)(Init->DataAddressMux |\ |
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216 Init->MemoryType |\ |
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217 Init->MemoryDataWidth |\ |
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218 Init->BurstAccessMode |\ |
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219 Init->WaitSignalPolarity |\ |
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220 Init->WaitSignalActive |\ |
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221 Init->WriteOperation |\ |
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222 Init->WaitSignal |\ |
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223 Init->ExtendedMode |\ |
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224 Init->AsynchronousWait |\ |
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225 Init->WriteBurst |\ |
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226 Init->ContinuousClock |\ |
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227 Init->PageSize |\ |
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228 Init->WriteFifo); |
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229 #endif /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */ |
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230 |
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231 if(Init->MemoryType == FMC_MEMORY_TYPE_NOR) |
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232 { |
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233 tmpr |= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE; |
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234 } |
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235 |
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236 Device->BTCR[Init->NSBank] = tmpr; |
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237 |
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238 /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */ |
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239 if((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1)) |
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240 { |
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241 Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->ContinuousClock); |
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242 } |
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243 |
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244 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) |
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245 if(Init->NSBank != FMC_NORSRAM_BANK1) |
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246 { |
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247 Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->WriteFifo); |
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248 } |
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249 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */ |
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250 |
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251 return HAL_OK; |
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252 } |
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253 |
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254 /** |
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255 * @brief DeInitialize the FMC_NORSRAM peripheral |
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256 * @param Device Pointer to NORSRAM device instance |
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257 * @param ExDevice Pointer to NORSRAM extended mode device instance |
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258 * @param Bank NORSRAM bank number |
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259 * @retval HAL status |
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260 */ |
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261 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) |
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262 { |
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263 /* Check the parameters */ |
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264 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); |
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265 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice)); |
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266 assert_param(IS_FMC_NORSRAM_BANK(Bank)); |
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267 |
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268 /* Disable the FMC_NORSRAM device */ |
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269 __FMC_NORSRAM_DISABLE(Device, Bank); |
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270 |
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271 /* De-initialize the FMC_NORSRAM device */ |
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272 /* FMC_NORSRAM_BANK1 */ |
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273 if(Bank == FMC_NORSRAM_BANK1) |
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274 { |
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275 Device->BTCR[Bank] = 0x000030DBU; |
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276 } |
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277 /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */ |
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278 else |
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279 { |
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280 Device->BTCR[Bank] = 0x000030D2U; |
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281 } |
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282 |
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283 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; |
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284 ExDevice->BWTR[Bank] = 0x0FFFFFFFU; |
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285 |
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286 return HAL_OK; |
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287 } |
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288 |
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289 /** |
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290 * @brief Initialize the FMC_NORSRAM Timing according to the specified |
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291 * parameters in the FMC_NORSRAM_TimingTypeDef |
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292 * @param Device Pointer to NORSRAM device instance |
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293 * @param Timing Pointer to NORSRAM Timing structure |
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294 * @param Bank NORSRAM bank number |
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295 * @retval HAL status |
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296 */ |
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297 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) |
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298 { |
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299 uint32_t tmpr = 0U; |
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300 |
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301 /* Check the parameters */ |
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302 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); |
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303 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); |
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304 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); |
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305 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); |
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306 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); |
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307 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); |
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308 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); |
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309 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); |
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310 assert_param(IS_FMC_NORSRAM_BANK(Bank)); |
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311 |
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312 /* Get the BTCR register value */ |
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313 tmpr = Device->BTCR[Bank + 1U]; |
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314 |
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315 /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */ |
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316 tmpr &= ((uint32_t)~(FMC_BTR1_ADDSET | FMC_BTR1_ADDHLD | FMC_BTR1_DATAST | \ |
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317 FMC_BTR1_BUSTURN | FMC_BTR1_CLKDIV | FMC_BTR1_DATLAT | \ |
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318 FMC_BTR1_ACCMOD)); |
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319 |
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320 /* Set FMC_NORSRAM device timing parameters */ |
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321 tmpr |= (uint32_t)(Timing->AddressSetupTime |\ |
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322 ((Timing->AddressHoldTime) << 4U) |\ |
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323 ((Timing->DataSetupTime) << 8U) |\ |
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324 ((Timing->BusTurnAroundDuration) << 16U) |\ |
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325 (((Timing->CLKDivision) - 1U) << 20U) |\ |
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326 (((Timing->DataLatency) - 2U) << 24U) |\ |
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327 (Timing->AccessMode)); |
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328 |
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329 Device->BTCR[Bank + 1U] = tmpr; |
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330 |
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331 /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ |
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332 if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) |
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333 { |
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334 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~(0x0FU << 20U)); |
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335 tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << 20U); |
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336 Device->BTCR[FMC_NORSRAM_BANK1 + 1U] = tmpr; |
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337 } |
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338 |
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339 return HAL_OK; |
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340 } |
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341 |
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342 /** |
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343 * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified |
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344 * parameters in the FMC_NORSRAM_TimingTypeDef |
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345 * @param Device Pointer to NORSRAM device instance |
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346 * @param Timing Pointer to NORSRAM Timing structure |
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347 * @param Bank NORSRAM bank number |
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348 * @retval HAL status |
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349 */ |
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350 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) |
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351 { |
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352 uint32_t tmpr = 0U; |
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353 |
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354 /* Check the parameters */ |
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355 assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode)); |
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356 |
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357 /* Set NORSRAM device timing register for write configuration, if extended mode is used */ |
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358 if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE) |
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359 { |
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360 /* Check the parameters */ |
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361 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device)); |
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362 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); |
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363 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); |
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364 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); |
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365 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); |
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366 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); |
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367 assert_param(IS_FMC_NORSRAM_BANK(Bank)); |
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368 |
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369 /* Get the BWTR register value */ |
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370 tmpr = Device->BWTR[Bank]; |
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371 |
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372 /* Clear ADDSET, ADDHLD, DATAST, BUSTURN and ACCMOD bits */ |
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373 tmpr &= ((uint32_t)~(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD | FMC_BWTR1_DATAST | \ |
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374 FMC_BWTR1_BUSTURN | FMC_BWTR1_ACCMOD)); |
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375 |
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376 tmpr |= (uint32_t)(Timing->AddressSetupTime |\ |
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377 ((Timing->AddressHoldTime) << 4U) |\ |
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378 ((Timing->DataSetupTime) << 8U) |\ |
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379 ((Timing->BusTurnAroundDuration) << 16U) |\ |
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380 (Timing->AccessMode)); |
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381 |
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382 Device->BWTR[Bank] = tmpr; |
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383 } |
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384 else |
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385 { |
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386 Device->BWTR[Bank] = 0x0FFFFFFFU; |
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387 } |
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388 |
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389 return HAL_OK; |
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390 } |
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391 /** |
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392 * @} |
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393 */ |
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394 |
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395 /** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2 |
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396 * @brief management functions |
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397 * |
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398 @verbatim |
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399 ============================================================================== |
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400 ##### FMC_NORSRAM Control functions ##### |
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401 ============================================================================== |
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402 [..] |
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403 This subsection provides a set of functions allowing to control dynamically |
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404 the FMC NORSRAM interface. |
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405 |
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406 @endverbatim |
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407 * @{ |
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408 */ |
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409 /** |
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410 * @brief Enables dynamically FMC_NORSRAM write operation. |
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411 * @param Device Pointer to NORSRAM device instance |
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412 * @param Bank NORSRAM bank number |
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413 * @retval HAL status |
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414 */ |
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415 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) |
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416 { |
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417 /* Check the parameters */ |
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418 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); |
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419 assert_param(IS_FMC_NORSRAM_BANK(Bank)); |
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420 |
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421 /* Enable write operation */ |
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422 Device->BTCR[Bank] |= FMC_WRITE_OPERATION_ENABLE; |
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423 |
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424 return HAL_OK; |
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425 } |
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426 |
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427 /** |
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428 * @brief Disables dynamically FMC_NORSRAM write operation. |
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429 * @param Device Pointer to NORSRAM device instance |
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430 * @param Bank NORSRAM bank number |
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431 * @retval HAL status |
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432 */ |
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433 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) |
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434 { |
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435 /* Check the parameters */ |
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436 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); |
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437 assert_param(IS_FMC_NORSRAM_BANK(Bank)); |
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438 |
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439 /* Disable write operation */ |
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440 Device->BTCR[Bank] &= ~FMC_WRITE_OPERATION_ENABLE; |
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441 |
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442 return HAL_OK; |
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443 } |
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444 |
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445 /** |
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446 * @} |
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447 */ |
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448 |
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449 /** |
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450 * @} |
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451 */ |
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452 |
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453 /** @addtogroup FMC_LL_NAND |
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454 * @brief NAND Controller functions |
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455 * |
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456 @verbatim |
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457 ============================================================================== |
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458 ##### How to use NAND device driver ##### |
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459 ============================================================================== |
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460 [..] |
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461 This driver contains a set of APIs to interface with the FMC NAND banks in order |
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462 to run the NAND external devices. |
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463 |
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464 (+) FMC NAND bank reset using the function FMC_NAND_DeInit() |
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465 (+) FMC NAND bank control configuration using the function FMC_NAND_Init() |
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466 (+) FMC NAND bank common space timing configuration using the function |
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467 FMC_NAND_CommonSpace_Timing_Init() |
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468 (+) FMC NAND bank attribute space timing configuration using the function |
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469 FMC_NAND_AttributeSpace_Timing_Init() |
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470 (+) FMC NAND bank enable/disable ECC correction feature using the functions |
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471 FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable() |
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472 (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC() |
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473 |
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474 @endverbatim |
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475 * @{ |
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476 */ |
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477 |
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478 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) |
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479 /** @defgroup HAL_FMC_NAND_Group1 Initialization/de-initialization functions |
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480 * @brief Initialization and Configuration functions |
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481 * |
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482 @verbatim |
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483 ============================================================================== |
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484 ##### Initialization and de_initialization functions ##### |
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485 ============================================================================== |
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486 [..] |
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487 This section provides functions allowing to: |
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488 (+) Initialize and configure the FMC NAND interface |
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489 (+) De-initialize the FMC NAND interface |
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490 (+) Configure the FMC clock and associated GPIOs |
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491 |
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492 @endverbatim |
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493 * @{ |
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494 */ |
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495 |
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496 /** |
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497 * @brief Initializes the FMC_NAND device according to the specified |
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498 * control parameters in the FMC_NAND_HandleTypeDef |
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499 * @param Device Pointer to NAND device instance |
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500 * @param Init Pointer to NAND Initialization structure |
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501 * @retval HAL status |
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502 */ |
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503 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init) |
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504 { |
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505 uint32_t tmpr = 0U; |
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506 |
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507 /* Check the parameters */ |
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508 assert_param(IS_FMC_NAND_DEVICE(Device)); |
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509 assert_param(IS_FMC_NAND_BANK(Init->NandBank)); |
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510 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature)); |
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511 assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth)); |
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512 assert_param(IS_FMC_ECC_STATE(Init->EccComputation)); |
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513 assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize)); |
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514 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime)); |
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515 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); |
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516 |
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517 /* Get the NAND bank register value */ |
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518 tmpr = Device->PCR; |
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519 |
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520 /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */ |
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521 tmpr &= ((uint32_t)~(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | FMC_PCR_PTYP | \ |
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522 FMC_PCR_PWID | FMC_PCR_ECCEN | FMC_PCR_TCLR | \ |
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523 FMC_PCR_TAR | FMC_PCR_ECCPS)); |
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524 |
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525 /* Set NAND device control parameters */ |
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526 tmpr |= (uint32_t)(Init->Waitfeature |\ |
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527 FMC_PCR_MEMORY_TYPE_NAND |\ |
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528 Init->MemoryDataWidth |\ |
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529 Init->EccComputation |\ |
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530 Init->ECCPageSize |\ |
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531 ((Init->TCLRSetupTime) << 9U) |\ |
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532 ((Init->TARSetupTime) << 13U)); |
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533 |
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534 /* NAND bank registers configuration */ |
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535 Device->PCR = tmpr; |
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536 |
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537 return HAL_OK; |
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538 } |
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539 |
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540 /** |
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541 * @brief Initializes the FMC_NAND Common space Timing according to the specified |
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542 * parameters in the FMC_NAND_PCC_TimingTypeDef |
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543 * @param Device Pointer to NAND device instance |
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544 * @param Timing Pointer to NAND timing structure |
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545 * @param Bank NAND bank number |
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546 * @retval HAL status |
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547 */ |
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548 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) |
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549 { |
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550 uint32_t tmpr = 0U; |
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551 |
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552 /* Check the parameters */ |
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553 assert_param(IS_FMC_NAND_DEVICE(Device)); |
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554 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); |
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555 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); |
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|
556 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); |
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557 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); |
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558 assert_param(IS_FMC_NAND_BANK(Bank)); |
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559 |
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|
560 /* Get the NAND bank 2 register value */ |
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561 tmpr = Device->PMEM; |
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562 |
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563 |
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564 /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */ |
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565 tmpr &= ((uint32_t)~(FMC_PMEM_MEMSET2 | FMC_PMEM_MEMWAIT2 | FMC_PMEM_MEMHOLD2 | \ |
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566 FMC_PMEM_MEMHIZ2)); |
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567 |
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568 /* Set FMC_NAND device timing parameters */ |
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569 tmpr |= (uint32_t)(Timing->SetupTime |\ |
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570 ((Timing->WaitSetupTime) << 8U) |\ |
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571 ((Timing->HoldSetupTime) << 16U) |\ |
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572 ((Timing->HiZSetupTime) << 24U) |
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573 ); |
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574 |
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575 /* NAND bank registers configuration */ |
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576 Device->PMEM = tmpr; |
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577 |
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578 return HAL_OK; |
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579 } |
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580 |
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581 /** |
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582 * @brief Initializes the FMC_NAND Attribute space Timing according to the specified |
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583 * parameters in the FMC_NAND_PCC_TimingTypeDef |
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584 * @param Device Pointer to NAND device instance |
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585 * @param Timing Pointer to NAND timing structure |
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586 * @param Bank NAND bank number |
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587 * @retval HAL status |
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588 */ |
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589 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) |
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590 { |
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591 uint32_t tmpr = 0U; |
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|
592 |
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593 /* Check the parameters */ |
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594 assert_param(IS_FMC_NAND_DEVICE(Device)); |
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595 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); |
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596 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); |
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597 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); |
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598 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); |
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599 assert_param(IS_FMC_NAND_BANK(Bank)); |
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600 |
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|
601 /* Get the NAND bank register value */ |
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602 tmpr = Device->PATT; |
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603 |
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|
604 /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */ |
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605 tmpr &= ((uint32_t)~(FMC_PATT_ATTSET2 | FMC_PATT_ATTWAIT2 | FMC_PATT_ATTHOLD2 | \ |
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606 FMC_PATT_ATTHIZ2)); |
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607 |
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|
608 /* Set FMC_NAND device timing parameters */ |
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609 tmpr |= (uint32_t)(Timing->SetupTime |\ |
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610 ((Timing->WaitSetupTime) << 8U) |\ |
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611 ((Timing->HoldSetupTime) << 16U) |\ |
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612 ((Timing->HiZSetupTime) << 24U)); |
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|
613 |
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614 /* NAND bank registers configuration */ |
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615 Device->PATT = tmpr; |
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616 |
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617 return HAL_OK; |
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618 } |
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619 |
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620 |
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|
621 /** |
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622 * @brief DeInitializes the FMC_NAND device |
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623 * @param Device Pointer to NAND device instance |
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624 * @param Bank NAND bank number |
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625 * @retval HAL status |
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626 */ |
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627 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) |
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628 { |
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629 /* Check the parameters */ |
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630 assert_param(IS_FMC_NAND_DEVICE(Device)); |
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631 assert_param(IS_FMC_NAND_BANK(Bank)); |
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632 |
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633 /* Disable the NAND Bank */ |
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634 __FMC_NAND_DISABLE(Device, Bank); |
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635 |
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636 /* De-initialize the NAND Bank */ |
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637 /* Set the FMC_NAND_BANK registers to their reset values */ |
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638 Device->PCR = 0x00000018U; |
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639 Device->SR = 0x00000040U; |
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640 Device->PMEM = 0xFCFCFCFCU; |
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641 Device->PATT = 0xFCFCFCFCU; |
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642 |
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643 return HAL_OK; |
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644 } |
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645 |
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646 /** |
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647 * @} |
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648 */ |
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649 |
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650 |
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651 /** @defgroup HAL_FMC_NAND_Group2 Control functions |
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652 * @brief management functions |
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653 * |
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654 @verbatim |
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655 ============================================================================== |
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656 ##### FMC_NAND Control functions ##### |
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657 ============================================================================== |
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658 [..] |
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659 This subsection provides a set of functions allowing to control dynamically |
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660 the FMC NAND interface. |
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661 |
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662 @endverbatim |
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663 * @{ |
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664 */ |
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665 |
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666 |
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667 /** |
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668 * @brief Enables dynamically FMC_NAND ECC feature. |
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669 * @param Device Pointer to NAND device instance |
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670 * @param Bank NAND bank number |
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671 * @retval HAL status |
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672 */ |
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673 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank) |
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674 { |
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675 /* Check the parameters */ |
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676 assert_param(IS_FMC_NAND_DEVICE(Device)); |
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677 assert_param(IS_FMC_NAND_BANK(Bank)); |
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678 |
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679 /* Enable ECC feature */ |
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680 Device->PCR |= FMC_PCR_ECCEN; |
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681 |
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682 return HAL_OK; |
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683 } |
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684 |
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685 |
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686 /** |
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687 * @brief Disables dynamically FMC_NAND ECC feature. |
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688 * @param Device Pointer to NAND device instance |
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689 * @param Bank NAND bank number |
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690 * @retval HAL status |
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691 */ |
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692 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) |
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693 { |
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694 /* Check the parameters */ |
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695 assert_param(IS_FMC_NAND_DEVICE(Device)); |
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696 assert_param(IS_FMC_NAND_BANK(Bank)); |
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697 |
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698 /* Disable ECC feature */ |
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699 Device->PCR &= ~FMC_PCR_ECCEN; |
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700 |
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701 return HAL_OK; |
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702 } |
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703 |
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704 /** |
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705 * @brief Disables dynamically FMC_NAND ECC feature. |
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706 * @param Device Pointer to NAND device instance |
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707 * @param ECCval Pointer to ECC value |
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708 * @param Bank NAND bank number |
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709 * @param Timeout Timeout wait value |
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710 * @retval HAL status |
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711 */ |
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712 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) |
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713 { |
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714 uint32_t tickstart = 0U; |
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715 |
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716 /* Check the parameters */ |
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717 assert_param(IS_FMC_NAND_DEVICE(Device)); |
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718 assert_param(IS_FMC_NAND_BANK(Bank)); |
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719 |
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720 /* Get tick */ |
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721 tickstart = HAL_GetTick(); |
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722 |
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723 /* Wait until FIFO is empty */ |
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724 while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET) |
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725 { |
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726 /* Check for the Timeout */ |
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727 if(Timeout != HAL_MAX_DELAY) |
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728 { |
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729 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) |
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730 { |
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731 return HAL_TIMEOUT; |
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732 } |
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733 } |
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734 } |
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735 |
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736 /* Get the ECCR register value */ |
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737 *ECCval = (uint32_t)Device->ECCR; |
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738 |
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739 return HAL_OK; |
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740 } |
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741 |
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742 /** |
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743 * @} |
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744 */ |
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745 |
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746 #else /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */ |
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747 /** @defgroup HAL_FMC_NAND_Group1 Initialization/de-initialization functions |
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748 * @brief Initialization and Configuration functions |
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749 * |
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750 @verbatim |
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751 ============================================================================== |
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752 ##### Initialization and de_initialization functions ##### |
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753 ============================================================================== |
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754 [..] |
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755 This section provides functions allowing to: |
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756 (+) Initialize and configure the FMC NAND interface |
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757 (+) De-initialize the FMC NAND interface |
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758 (+) Configure the FMC clock and associated GPIOs |
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759 |
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760 @endverbatim |
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761 * @{ |
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762 */ |
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763 /** |
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764 * @brief Initializes the FMC_NAND device according to the specified |
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765 * control parameters in the FMC_NAND_HandleTypeDef |
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766 * @param Device Pointer to NAND device instance |
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767 * @param Init Pointer to NAND Initialization structure |
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768 * @retval HAL status |
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769 */ |
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770 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init) |
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771 { |
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772 uint32_t tmpr = 0U; |
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773 |
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774 /* Check the parameters */ |
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775 assert_param(IS_FMC_NAND_DEVICE(Device)); |
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776 assert_param(IS_FMC_NAND_BANK(Init->NandBank)); |
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777 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature)); |
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778 assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth)); |
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779 assert_param(IS_FMC_ECC_STATE(Init->EccComputation)); |
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780 assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize)); |
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781 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime)); |
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782 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); |
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783 |
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784 if(Init->NandBank == FMC_NAND_BANK2) |
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|
785 { |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
786 /* Get the NAND bank 2 register value */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
787 tmpr = Device->PCR2; |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
788 } |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
789 else |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
790 { |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
791 /* Get the NAND bank 3 register value */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
792 tmpr = Device->PCR3; |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
793 } |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
794 |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
795 /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
796 tmpr &= ((uint32_t)~(FMC_PCR2_PWAITEN | FMC_PCR2_PBKEN | FMC_PCR2_PTYP | \ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
797 FMC_PCR2_PWID | FMC_PCR2_ECCEN | FMC_PCR2_TCLR | \ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
798 FMC_PCR2_TAR | FMC_PCR2_ECCPS)); |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
799 |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
800 /* Set NAND device control parameters */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
801 tmpr |= (uint32_t)(Init->Waitfeature |\ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
802 FMC_PCR_MEMORY_TYPE_NAND |\ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
803 Init->MemoryDataWidth |\ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
804 Init->EccComputation |\ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
805 Init->ECCPageSize |\ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
806 ((Init->TCLRSetupTime) << 9U) |\ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
807 ((Init->TARSetupTime) << 13U)); |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
808 |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
809 if(Init->NandBank == FMC_NAND_BANK2) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
810 { |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
811 /* NAND bank 2 registers configuration */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
812 Device->PCR2 = tmpr; |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
813 } |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
814 else |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
815 { |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
816 /* NAND bank 3 registers configuration */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
817 Device->PCR3 = tmpr; |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
818 } |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
819 |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
820 return HAL_OK; |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
821 |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
822 } |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
823 |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
824 /** |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
825 * @brief Initializes the FMC_NAND Common space Timing according to the specified |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
826 * parameters in the FMC_NAND_PCC_TimingTypeDef |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
827 * @param Device Pointer to NAND device instance |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
828 * @param Timing Pointer to NAND timing structure |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
829 * @param Bank NAND bank number |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
830 * @retval HAL status |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
831 */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
832 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
833 { |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
834 uint32_t tmpr = 0U; |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
835 |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
836 /* Check the parameters */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
837 assert_param(IS_FMC_NAND_DEVICE(Device)); |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
838 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
839 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
840 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
841 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
842 assert_param(IS_FMC_NAND_BANK(Bank)); |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
843 |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
844 if(Bank == FMC_NAND_BANK2) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
845 { |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
846 /* Get the NAND bank 2 register value */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
847 tmpr = Device->PMEM2; |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
848 } |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
849 else |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
850 { |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
851 /* Get the NAND bank 3 register value */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
852 tmpr = Device->PMEM3; |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
853 } |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
854 |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
855 /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
856 tmpr &= ((uint32_t)~(FMC_PMEM2_MEMSET2 | FMC_PMEM2_MEMWAIT2 | FMC_PMEM2_MEMHOLD2 | \ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
857 FMC_PMEM2_MEMHIZ2)); |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
858 |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
859 /* Set FMC_NAND device timing parameters */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
860 tmpr |= (uint32_t)(Timing->SetupTime |\ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
861 ((Timing->WaitSetupTime) << 8U) |\ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
862 ((Timing->HoldSetupTime) << 16U) |\ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
863 ((Timing->HiZSetupTime) << 24U) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
864 ); |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
865 |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
866 if(Bank == FMC_NAND_BANK2) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
867 { |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
868 /* NAND bank 2 registers configuration */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
869 Device->PMEM2 = tmpr; |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
870 } |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
871 else |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
872 { |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
873 /* NAND bank 3 registers configuration */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
874 Device->PMEM3 = tmpr; |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
875 } |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
876 |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
877 return HAL_OK; |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
878 } |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
879 |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
880 /** |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
881 * @brief Initializes the FMC_NAND Attribute space Timing according to the specified |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
882 * parameters in the FMC_NAND_PCC_TimingTypeDef |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
883 * @param Device Pointer to NAND device instance |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
884 * @param Timing Pointer to NAND timing structure |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
885 * @param Bank NAND bank number |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
886 * @retval HAL status |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
887 */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
888 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
889 { |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
890 uint32_t tmpr = 0U; |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
891 |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
892 /* Check the parameters */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
893 assert_param(IS_FMC_NAND_DEVICE(Device)); |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
894 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
895 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
896 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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parents:
diff
changeset
|
897 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
898 assert_param(IS_FMC_NAND_BANK(Bank)); |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
899 |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
900 if(Bank == FMC_NAND_BANK2) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
901 { |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
902 /* Get the NAND bank 2 register value */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
903 tmpr = Device->PATT2; |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
904 } |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
905 else |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
906 { |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
907 /* Get the NAND bank 3 register value */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
908 tmpr = Device->PATT3; |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
909 } |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
910 |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
911 /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
912 tmpr &= ((uint32_t)~(FMC_PATT2_ATTSET2 | FMC_PATT2_ATTWAIT2 | FMC_PATT2_ATTHOLD2 | \ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
913 FMC_PATT2_ATTHIZ2)); |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
914 |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
915 /* Set FMC_NAND device timing parameters */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
916 tmpr |= (uint32_t)(Timing->SetupTime |\ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
917 ((Timing->WaitSetupTime) << 8U) |\ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
918 ((Timing->HoldSetupTime) << 16U) |\ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
919 ((Timing->HiZSetupTime) << 24U)); |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
920 |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
921 if(Bank == FMC_NAND_BANK2) |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
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|
922 { |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
923 /* NAND bank 2 registers configuration */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
924 Device->PATT2 = tmpr; |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
925 } |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
926 else |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
927 { |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
928 /* NAND bank 3 registers configuration */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
929 Device->PATT3 = tmpr; |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
930 } |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
931 |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
932 return HAL_OK; |
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Added current STM32 standandard libraries in version independend folder structure
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parents:
diff
changeset
|
933 } |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
934 |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
935 /** |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
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|
936 * @brief DeInitializes the FMC_NAND device |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
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|
937 * @param Device Pointer to NAND device instance |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
938 * @param Bank NAND bank number |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
939 * @retval HAL status |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
940 */ |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
941 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff
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|
942 { |
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Added current STM32 standandard libraries in version independend folder structure
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parents:
diff
changeset
|
943 /* Check the parameters */ |
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Added current STM32 standandard libraries in version independend folder structure
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parents:
diff
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|
944 assert_param(IS_FMC_NAND_DEVICE(Device)); |
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Added current STM32 standandard libraries in version independend folder structure
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diff
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|
945 assert_param(IS_FMC_NAND_BANK(Bank)); |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
946 |
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Added current STM32 standandard libraries in version independend folder structure
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parents:
diff
changeset
|
947 /* Disable the NAND Bank */ |
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Added current STM32 standandard libraries in version independend folder structure
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diff
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|
948 __FMC_NAND_DISABLE(Device, Bank); |
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|
949 |
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diff
changeset
|
950 /* De-initialize the NAND Bank */ |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff
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|
951 if(Bank == FMC_NAND_BANK2) |
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Added current STM32 standandard libraries in version independend folder structure
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diff
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|
952 { |
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Added current STM32 standandard libraries in version independend folder structure
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diff
changeset
|
953 /* Set the FMC_NAND_BANK2 registers to their reset values */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
954 Device->PCR2 = 0x00000018U; |
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|
955 Device->SR2 = 0x00000040U; |
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|
956 Device->PMEM2 = 0xFCFCFCFCU; |
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Added current STM32 standandard libraries in version independend folder structure
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|
957 Device->PATT2 = 0xFCFCFCFCU; |
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|
958 } |
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|
959 /* FMC_Bank3_NAND */ |
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diff
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|
960 else |
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Added current STM32 standandard libraries in version independend folder structure
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diff
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|
961 { |
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|
962 /* Set the FMC_NAND_BANK3 registers to their reset values */ |
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|
963 Device->PCR3 = 0x00000018U; |
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|
964 Device->SR3 = 0x00000040U; |
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|
965 Device->PMEM3 = 0xFCFCFCFCU; |
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|
966 Device->PATT3 = 0xFCFCFCFCU; |
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|
967 } |
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|
968 |
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diff
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|
969 return HAL_OK; |
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diff
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|
970 } |
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|
971 |
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|
972 /** |
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|
973 * @} |
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|
974 */ |
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|
975 |
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|
976 /** @addtogroup FMC_LL_NAND_Private_Functions_Group2 |
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|
977 * @brief management functions |
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|
978 * |
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|
979 @verbatim |
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|
980 ============================================================================== |
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|
981 ##### FMC_NAND Control functions ##### |
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|
982 ============================================================================== |
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|
983 [..] |
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|
984 This subsection provides a set of functions allowing to control dynamically |
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|
985 the FMC NAND interface. |
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|
986 |
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|
987 @endverbatim |
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|
988 * @{ |
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|
989 */ |
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|
990 /** |
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|
991 * @brief Enables dynamically FMC_NAND ECC feature. |
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|
992 * @param Device Pointer to NAND device instance |
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|
993 * @param Bank NAND bank number |
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|
994 * @retval HAL status |
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|
995 */ |
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|
996 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank) |
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|
997 { |
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|
998 /* Check the parameters */ |
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|
999 assert_param(IS_FMC_NAND_DEVICE(Device)); |
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|
1000 assert_param(IS_FMC_NAND_BANK(Bank)); |
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|
1001 |
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|
1002 /* Enable ECC feature */ |
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|
1003 if(Bank == FMC_NAND_BANK2) |
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|
1004 { |
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|
1005 Device->PCR2 |= FMC_PCR2_ECCEN; |
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|
1006 } |
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|
1007 else |
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|
1008 { |
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|
1009 Device->PCR3 |= FMC_PCR3_ECCEN; |
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|
1010 } |
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|
1011 |
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|
1012 return HAL_OK; |
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|
1013 } |
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|
1014 |
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|
1015 /** |
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|
1016 * @brief Disables dynamically FMC_NAND ECC feature. |
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|
1017 * @param Device Pointer to NAND device instance |
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|
1018 * @param Bank NAND bank number |
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|
1019 * @retval HAL status |
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|
1020 */ |
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|
1021 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) |
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|
1022 { |
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|
1023 /* Check the parameters */ |
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|
1024 assert_param(IS_FMC_NAND_DEVICE(Device)); |
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1025 assert_param(IS_FMC_NAND_BANK(Bank)); |
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|
1026 |
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|
1027 /* Disable ECC feature */ |
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|
1028 if(Bank == FMC_NAND_BANK2) |
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|
1029 { |
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|
1030 Device->PCR2 &= ~FMC_PCR2_ECCEN; |
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|
1031 } |
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|
1032 else |
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|
1033 { |
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|
1034 Device->PCR3 &= ~FMC_PCR3_ECCEN; |
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|
1035 } |
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|
1036 |
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|
1037 return HAL_OK; |
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|
1038 } |
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|
1039 |
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|
1040 /** |
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|
1041 * @brief Disables dynamically FMC_NAND ECC feature. |
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|
1042 * @param Device Pointer to NAND device instance |
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|
1043 * @param ECCval Pointer to ECC value |
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|
1044 * @param Bank NAND bank number |
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|
1045 * @param Timeout Timeout wait value |
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|
1046 * @retval HAL status |
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|
1047 */ |
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|
1048 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) |
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|
1049 { |
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|
1050 uint32_t tickstart = 0U; |
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|
1051 |
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|
1052 /* Check the parameters */ |
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|
1053 assert_param(IS_FMC_NAND_DEVICE(Device)); |
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1054 assert_param(IS_FMC_NAND_BANK(Bank)); |
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1055 |
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1056 /* Get tick */ |
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1057 tickstart = HAL_GetTick(); |
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1058 |
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1059 /* Wait until FIFO is empty */ |
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1060 while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET) |
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1061 { |
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1062 /* Check for the Timeout */ |
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1063 if(Timeout != HAL_MAX_DELAY) |
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1064 { |
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1065 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) |
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1066 { |
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1067 return HAL_TIMEOUT; |
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1068 } |
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1069 } |
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1070 } |
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1071 |
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1072 if(Bank == FMC_NAND_BANK2) |
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1073 { |
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1074 /* Get the ECCR2 register value */ |
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1075 *ECCval = (uint32_t)Device->ECCR2; |
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1076 } |
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1077 else |
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1078 { |
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1079 /* Get the ECCR3 register value */ |
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1080 *ECCval = (uint32_t)Device->ECCR3; |
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1081 } |
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1082 |
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1083 return HAL_OK; |
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1084 } |
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1085 |
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1086 /** |
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1087 * @} |
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1088 */ |
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1089 |
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1090 #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */ |
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1091 /** |
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1092 * @} |
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1093 */ |
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1094 |
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1095 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) |
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1096 /** @addtogroup FMC_LL_PCCARD |
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1097 * @brief PCCARD Controller functions |
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1098 * |
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1099 @verbatim |
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1100 ============================================================================== |
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1101 ##### How to use PCCARD device driver ##### |
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1102 ============================================================================== |
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1103 [..] |
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1104 This driver contains a set of APIs to interface with the FMC PCCARD bank in order |
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1105 to run the PCCARD/compact flash external devices. |
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1106 |
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1107 (+) FMC PCCARD bank reset using the function FMC_PCCARD_DeInit() |
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1108 (+) FMC PCCARD bank control configuration using the function FMC_PCCARD_Init() |
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1109 (+) FMC PCCARD bank common space timing configuration using the function |
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1110 FMC_PCCARD_CommonSpace_Timing_Init() |
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1111 (+) FMC PCCARD bank attribute space timing configuration using the function |
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1112 FMC_PCCARD_AttributeSpace_Timing_Init() |
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1113 (+) FMC PCCARD bank IO space timing configuration using the function |
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1114 FMC_PCCARD_IOSpace_Timing_Init() |
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1115 @endverbatim |
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1116 * @{ |
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1117 */ |
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1118 |
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1119 /** @addtogroup FMC_LL_PCCARD_Private_Functions_Group1 |
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1120 * @brief Initialization and Configuration functions |
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1121 * |
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1122 @verbatim |
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1123 ============================================================================== |
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1124 ##### Initialization and de_initialization functions ##### |
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1125 ============================================================================== |
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1126 [..] |
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1127 This section provides functions allowing to: |
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1128 (+) Initialize and configure the FMC PCCARD interface |
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1129 (+) De-initialize the FMC PCCARD interface |
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1130 (+) Configure the FMC clock and associated GPIOs |
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1131 |
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1132 @endverbatim |
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1133 * @{ |
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1134 */ |
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1135 |
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1136 /** |
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1137 * @brief Initializes the FMC_PCCARD device according to the specified |
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1138 * control parameters in the FMC_PCCARD_HandleTypeDef |
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1139 * @param Device Pointer to PCCARD device instance |
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1140 * @param Init Pointer to PCCARD Initialization structure |
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1141 * @retval HAL status |
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1142 */ |
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1143 HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init) |
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1144 { |
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1145 uint32_t tmpr = 0U; |
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1146 |
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1147 /* Check the parameters */ |
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1148 assert_param(IS_FMC_PCCARD_DEVICE(Device)); |
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1149 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature)); |
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1150 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime)); |
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1151 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); |
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1152 |
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1153 /* Get PCCARD control register value */ |
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1154 tmpr = Device->PCR4; |
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1155 |
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1156 /* Clear TAR, TCLR, PWAITEN and PWID bits */ |
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1157 tmpr &= ((uint32_t)~(FMC_PCR4_TAR | FMC_PCR4_TCLR | FMC_PCR4_PWAITEN | \ |
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1158 FMC_PCR4_PWID | FMC_PCR4_PTYP)); |
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1159 |
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1160 /* Set FMC_PCCARD device control parameters */ |
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1161 tmpr |= (uint32_t)(Init->Waitfeature |\ |
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1162 FMC_NAND_PCC_MEM_BUS_WIDTH_16 |\ |
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1163 (Init->TCLRSetupTime << 9U) |\ |
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1164 (Init->TARSetupTime << 13U)); |
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1165 |
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1166 Device->PCR4 = tmpr; |
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1167 |
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1168 return HAL_OK; |
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1169 } |
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1170 |
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1171 /** |
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1172 * @brief Initializes the FMC_PCCARD Common space Timing according to the specified |
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1173 * parameters in the FMC_NAND_PCC_TimingTypeDef |
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1174 * @param Device Pointer to PCCARD device instance |
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1175 * @param Timing Pointer to PCCARD timing structure |
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1176 * @retval HAL status |
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1177 */ |
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1178 HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing) |
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1179 { |
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1180 uint32_t tmpr = 0U; |
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1181 |
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1182 /* Check the parameters */ |
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1183 assert_param(IS_FMC_PCCARD_DEVICE(Device)); |
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1184 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); |
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1185 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); |
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1186 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); |
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1187 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); |
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1188 |
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1189 /* Get PCCARD common space timing register value */ |
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1190 tmpr = Device->PMEM4; |
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1191 |
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1192 /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */ |
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1193 tmpr &= ((uint32_t)~(FMC_PMEM4_MEMSET4 | FMC_PMEM4_MEMWAIT4 | FMC_PMEM4_MEMHOLD4 | \ |
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1194 FMC_PMEM4_MEMHIZ4)); |
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1195 /* Set PCCARD timing parameters */ |
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1196 tmpr |= (uint32_t)(Timing->SetupTime |\ |
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1197 ((Timing->WaitSetupTime) << 8U) |\ |
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1198 ((Timing->HoldSetupTime) << 16U) |\ |
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1199 ((Timing->HiZSetupTime) << 24U)); |
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1200 |
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1201 Device->PMEM4 = tmpr; |
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1202 |
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1203 return HAL_OK; |
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1204 } |
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1205 |
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1206 /** |
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1207 * @brief Initializes the FMC_PCCARD Attribute space Timing according to the specified |
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1208 * parameters in the FMC_NAND_PCC_TimingTypeDef |
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1209 * @param Device Pointer to PCCARD device instance |
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1210 * @param Timing Pointer to PCCARD timing structure |
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1211 * @retval HAL status |
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1212 */ |
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1213 HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing) |
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1214 { |
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1215 uint32_t tmpr = 0U; |
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1216 |
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1217 /* Check the parameters */ |
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1218 assert_param(IS_FMC_PCCARD_DEVICE(Device)); |
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1219 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); |
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1220 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); |
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1221 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); |
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1222 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); |
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1223 |
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1224 /* Get PCCARD timing parameters */ |
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1225 tmpr = Device->PATT4; |
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|
1226 |
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1227 /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */ |
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1228 tmpr &= ((uint32_t)~(FMC_PATT4_ATTSET4 | FMC_PATT4_ATTWAIT4 | FMC_PATT4_ATTHOLD4 | \ |
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1229 FMC_PATT4_ATTHIZ4)); |
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1230 |
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1231 /* Set PCCARD timing parameters */ |
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1232 tmpr |= (uint32_t)(Timing->SetupTime |\ |
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1233 ((Timing->WaitSetupTime) << 8U) |\ |
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1234 ((Timing->HoldSetupTime) << 16U) |\ |
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1235 ((Timing->HiZSetupTime) << 24U)); |
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1236 Device->PATT4 = tmpr; |
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1237 |
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1238 return HAL_OK; |
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1239 } |
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1240 |
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|
1241 /** |
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1242 * @brief Initializes the FMC_PCCARD IO space Timing according to the specified |
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1243 * parameters in the FMC_NAND_PCC_TimingTypeDef |
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1244 * @param Device Pointer to PCCARD device instance |
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1245 * @param Timing Pointer to PCCARD timing structure |
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1246 * @retval HAL status |
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1247 */ |
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1248 HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing) |
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1249 { |
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1250 uint32_t tmpr = 0; |
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1251 |
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1252 /* Check the parameters */ |
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1253 assert_param(IS_FMC_PCCARD_DEVICE(Device)); |
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1254 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); |
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1255 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); |
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1256 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); |
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1257 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); |
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1258 |
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1259 /* Get FMC_PCCARD device timing parameters */ |
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1260 tmpr = Device->PIO4; |
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|
1261 |
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1262 /* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */ |
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1263 tmpr &= ((uint32_t)~(FMC_PIO4_IOSET4 | FMC_PIO4_IOWAIT4 | FMC_PIO4_IOHOLD4 | \ |
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1264 FMC_PIO4_IOHIZ4)); |
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|
1265 |
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1266 /* Set FMC_PCCARD device timing parameters */ |
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1267 tmpr |= (uint32_t)(Timing->SetupTime |\ |
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1268 ((Timing->WaitSetupTime) << 8U) |\ |
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1269 ((Timing->HoldSetupTime) << 16U) |\ |
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1270 ((Timing->HiZSetupTime) << 24U)); |
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1271 |
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1272 Device->PIO4 = tmpr; |
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1273 |
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1274 return HAL_OK; |
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1275 } |
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1276 |
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1277 /** |
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1278 * @brief DeInitializes the FMC_PCCARD device |
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1279 * @param Device Pointer to PCCARD device instance |
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1280 * @retval HAL status |
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1281 */ |
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1282 HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device) |
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1283 { |
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1284 /* Check the parameters */ |
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1285 assert_param(IS_FMC_PCCARD_DEVICE(Device)); |
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1286 |
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1287 /* Disable the FMC_PCCARD device */ |
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1288 __FMC_PCCARD_DISABLE(Device); |
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1289 |
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1290 /* De-initialize the FMC_PCCARD device */ |
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1291 Device->PCR4 = 0x00000018U; |
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1292 Device->SR4 = 0x00000000U; |
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1293 Device->PMEM4 = 0xFCFCFCFCU; |
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1294 Device->PATT4 = 0xFCFCFCFCU; |
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1295 Device->PIO4 = 0xFCFCFCFCU; |
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1296 |
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1297 return HAL_OK; |
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1298 } |
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1299 |
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1300 /** |
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1301 * @} |
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1302 */ |
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1303 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
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1304 |
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1305 |
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1306 /** @addtogroup FMC_LL_SDRAM |
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1307 * @brief SDRAM Controller functions |
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1308 * |
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1309 @verbatim |
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1310 ============================================================================== |
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1311 ##### How to use SDRAM device driver ##### |
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1312 ============================================================================== |
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1313 [..] |
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1314 This driver contains a set of APIs to interface with the FMC SDRAM banks in order |
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1315 to run the SDRAM external devices. |
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1316 |
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1317 (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit() |
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1318 (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init() |
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1319 (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init() |
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1320 (+) FMC SDRAM bank enable/disable write operation using the functions |
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1321 FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable() |
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1322 (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand() |
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1323 |
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1324 @endverbatim |
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1325 * @{ |
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1326 */ |
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|
1327 |
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1328 /** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1 |
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1329 * @brief Initialization and Configuration functions |
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|
1330 * |
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1331 @verbatim |
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|
1332 ============================================================================== |
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1333 ##### Initialization and de_initialization functions ##### |
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1334 ============================================================================== |
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|
1335 [..] |
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|
1336 This section provides functions allowing to: |
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1337 (+) Initialize and configure the FMC SDRAM interface |
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1338 (+) De-initialize the FMC SDRAM interface |
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1339 (+) Configure the FMC clock and associated GPIOs |
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1340 |
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1341 @endverbatim |
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1342 * @{ |
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1343 */ |
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1344 |
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1345 /** |
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1346 * @brief Initializes the FMC_SDRAM device according to the specified |
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1347 * control parameters in the FMC_SDRAM_InitTypeDef |
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1348 * @param Device Pointer to SDRAM device instance |
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1349 * @param Init Pointer to SDRAM Initialization structure |
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1350 * @retval HAL status |
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1351 */ |
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1352 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init) |
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1353 { |
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1354 uint32_t tmpr1 = 0U; |
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1355 uint32_t tmpr2 = 0U; |
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1356 |
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1357 /* Check the parameters */ |
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1358 assert_param(IS_FMC_SDRAM_DEVICE(Device)); |
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1359 assert_param(IS_FMC_SDRAM_BANK(Init->SDBank)); |
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1360 assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber)); |
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1361 assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber)); |
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1362 assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth)); |
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1363 assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber)); |
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1364 assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency)); |
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1365 assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection)); |
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1366 assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod)); |
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1367 assert_param(IS_FMC_READ_BURST(Init->ReadBurst)); |
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1368 assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay)); |
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1369 |
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1370 /* Set SDRAM bank configuration parameters */ |
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1371 if (Init->SDBank != FMC_SDRAM_BANK2) |
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1372 { |
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1373 tmpr1 = Device->SDCR[FMC_SDRAM_BANK1]; |
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1374 |
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1375 /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ |
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1376 tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ |
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1377 FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \ |
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1378 FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); |
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1379 |
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|
1380 |
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1381 tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\ |
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1382 Init->RowBitsNumber |\ |
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1383 Init->MemoryDataWidth |\ |
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1384 Init->InternalBankNumber |\ |
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1385 Init->CASLatency |\ |
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1386 Init->WriteProtection |\ |
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1387 Init->SDClockPeriod |\ |
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1388 Init->ReadBurst |\ |
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1389 Init->ReadPipeDelay |
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|
1390 ); |
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1391 Device->SDCR[FMC_SDRAM_BANK1] = tmpr1; |
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1392 } |
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1393 else /* FMC_Bank2_SDRAM */ |
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1394 { |
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1395 tmpr1 = Device->SDCR[FMC_SDRAM_BANK1]; |
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1396 |
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1397 /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ |
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1398 tmpr1 &= ((uint32_t)~(FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); |
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1399 |
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1400 tmpr1 |= (uint32_t)(Init->SDClockPeriod |\ |
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1401 Init->ReadBurst |\ |
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1402 Init->ReadPipeDelay); |
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1403 |
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1404 tmpr2 = Device->SDCR[FMC_SDRAM_BANK2]; |
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1405 |
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1406 /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ |
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1407 tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ |
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1408 FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \ |
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1409 FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); |
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1410 |
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1411 tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\ |
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1412 Init->RowBitsNumber |\ |
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1413 Init->MemoryDataWidth |\ |
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1414 Init->InternalBankNumber |\ |
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1415 Init->CASLatency |\ |
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1416 Init->WriteProtection); |
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1417 |
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1418 Device->SDCR[FMC_SDRAM_BANK1] = tmpr1; |
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1419 Device->SDCR[FMC_SDRAM_BANK2] = tmpr2; |
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1420 } |
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1421 |
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1422 return HAL_OK; |
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1423 } |
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1424 |
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1425 /** |
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1426 * @brief Initializes the FMC_SDRAM device timing according to the specified |
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1427 * parameters in the FMC_SDRAM_TimingTypeDef |
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1428 * @param Device Pointer to SDRAM device instance |
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1429 * @param Timing Pointer to SDRAM Timing structure |
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1430 * @param Bank SDRAM bank number |
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1431 * @retval HAL status |
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1432 */ |
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1433 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank) |
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1434 { |
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1435 uint32_t tmpr1 = 0U; |
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1436 uint32_t tmpr2 = 0U; |
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1437 |
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1438 /* Check the parameters */ |
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1439 assert_param(IS_FMC_SDRAM_DEVICE(Device)); |
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1440 assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay)); |
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1441 assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay)); |
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1442 assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime)); |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
1443 assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay)); |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
1444 assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime)); |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
1445 assert_param(IS_FMC_RP_DELAY(Timing->RPDelay)); |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
1446 assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay)); |
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Added current STM32 standandard libraries in version independend folder structure
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parents:
diff
changeset
|
1447 assert_param(IS_FMC_SDRAM_BANK(Bank)); |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
1448 |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
1449 /* Set SDRAM device timing parameters */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
1450 if (Bank != FMC_SDRAM_BANK2) |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
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|
1451 { |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
1452 tmpr1 = Device->SDTR[FMC_SDRAM_BANK1]; |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
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|
1453 |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
1454 /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */ |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
1455 tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
1456 FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
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|
1457 FMC_SDTR1_TRCD)); |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
1458 |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
1459 tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1U) |\ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
1460 (((Timing->ExitSelfRefreshDelay)-1U) << 4U) |\ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
1461 (((Timing->SelfRefreshTime)-1U) << 8U) |\ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
1462 (((Timing->RowCycleDelay)-1U) << 12U) |\ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
1463 (((Timing->WriteRecoveryTime)-1U) <<16U) |\ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
1464 (((Timing->RPDelay)-1U) << 20U) |\ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
1465 (((Timing->RCDDelay)-1U) << 24U)); |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
1466 Device->SDTR[FMC_SDRAM_BANK1] = tmpr1; |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
1467 } |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
1468 else /* FMC_Bank2_SDRAM */ |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
1469 { |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
1470 tmpr1 = Device->SDTR[FMC_SDRAM_BANK1]; |
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Added current STM32 standandard libraries in version independend folder structure
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parents:
diff
changeset
|
1471 |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
1472 /* Clear TRC and TRP bits */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
1473 tmpr1 &= ((uint32_t)~(FMC_SDTR1_TRC | FMC_SDTR1_TRP)); |
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Added current STM32 standandard libraries in version independend folder structure
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|
1474 |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
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|
1475 tmpr1 |= (uint32_t)((((Timing->RowCycleDelay)-1U) << 12U) |\ |
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Added current STM32 standandard libraries in version independend folder structure
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|
1476 (((Timing->RPDelay)-1U) << 20U)); |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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diff
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|
1477 |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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diff
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|
1478 tmpr2 = Device->SDTR[FMC_SDRAM_BANK2]; |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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diff
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|
1479 |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
1480 /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */ |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
1481 tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
1482 FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
1483 FMC_SDTR1_TRCD)); |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
1484 |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
1485 tmpr2 |= (uint32_t)((((Timing->LoadToActiveDelay)-1U) |\ |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
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|
1486 (((Timing->ExitSelfRefreshDelay)-1U) << 4U) |\ |
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Added current STM32 standandard libraries in version independend folder structure
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diff
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|
1487 (((Timing->SelfRefreshTime)-1U) << 8U) |\ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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parents:
diff
changeset
|
1488 (((Timing->WriteRecoveryTime)-1U) <<16U) |\ |
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Added current STM32 standandard libraries in version independend folder structure
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parents:
diff
changeset
|
1489 (((Timing->RCDDelay)-1U) << 24U))); |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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parents:
diff
changeset
|
1490 |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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parents:
diff
changeset
|
1491 Device->SDTR[FMC_SDRAM_BANK1] = tmpr1; |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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parents:
diff
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|
1492 Device->SDTR[FMC_SDRAM_BANK2] = tmpr2; |
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diff
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|
1493 } |
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Added current STM32 standandard libraries in version independend folder structure
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diff
changeset
|
1494 return HAL_OK; |
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diff
changeset
|
1495 } |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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parents:
diff
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|
1496 |
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Added current STM32 standandard libraries in version independend folder structure
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parents:
diff
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|
1497 /** |
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|
1498 * @brief DeInitializes the FMC_SDRAM peripheral |
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Added current STM32 standandard libraries in version independend folder structure
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|
1499 * @param Device Pointer to SDRAM device instance |
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Added current STM32 standandard libraries in version independend folder structure
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|
1500 * @retval HAL status |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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parents:
diff
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|
1501 */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
1502 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank) |
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Added current STM32 standandard libraries in version independend folder structure
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parents:
diff
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|
1503 { |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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parents:
diff
changeset
|
1504 /* Check the parameters */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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diff
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|
1505 assert_param(IS_FMC_SDRAM_DEVICE(Device)); |
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Added current STM32 standandard libraries in version independend folder structure
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diff
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|
1506 assert_param(IS_FMC_SDRAM_BANK(Bank)); |
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Added current STM32 standandard libraries in version independend folder structure
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diff
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|
1507 |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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parents:
diff
changeset
|
1508 /* De-initialize the SDRAM device */ |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff
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|
1509 Device->SDCR[Bank] = 0x000002D0U; |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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|
1510 Device->SDTR[Bank] = 0x0FFFFFFFU; |
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Added current STM32 standandard libraries in version independend folder structure
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diff
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|
1511 Device->SDCMR = 0x00000000U; |
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Added current STM32 standandard libraries in version independend folder structure
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parents:
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|
1512 Device->SDRTR = 0x00000000U; |
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Added current STM32 standandard libraries in version independend folder structure
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|
1513 Device->SDSR = 0x00000000U; |
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Added current STM32 standandard libraries in version independend folder structure
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diff
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|
1514 |
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Added current STM32 standandard libraries in version independend folder structure
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diff
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|
1515 return HAL_OK; |
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Added current STM32 standandard libraries in version independend folder structure
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diff
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|
1516 } |
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Added current STM32 standandard libraries in version independend folder structure
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diff
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|
1517 |
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Ideenmodellierer
parents:
diff
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|
1518 /** |
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diff
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|
1519 * @} |
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diff
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|
1520 */ |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
1521 |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
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|
1522 /** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2 |
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Added current STM32 standandard libraries in version independend folder structure
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parents:
diff
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|
1523 * @brief management functions |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
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|
1524 * |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff
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|
1525 @verbatim |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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|
1526 ============================================================================== |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff
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|
1527 ##### FMC_SDRAM Control functions ##### |
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Added current STM32 standandard libraries in version independend folder structure
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parents:
diff
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|
1528 ============================================================================== |
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Ideenmodellierer
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|
1529 [..] |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff
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|
1530 This subsection provides a set of functions allowing to control dynamically |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff
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|
1531 the FMC SDRAM interface. |
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Ideenmodellierer
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|
1532 |
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|
1533 @endverbatim |
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|
1534 * @{ |
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|
1535 */ |
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|
1536 /** |
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|
1537 * @brief Enables dynamically FMC_SDRAM write protection. |
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|
1538 * @param Device Pointer to SDRAM device instance |
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|
1539 * @param Bank SDRAM bank number |
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Added current STM32 standandard libraries in version independend folder structure
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|
1540 * @retval HAL status |
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|
1541 */ |
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|
1542 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank) |
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|
1543 { |
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diff
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|
1544 /* Check the parameters */ |
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|
1545 assert_param(IS_FMC_SDRAM_DEVICE(Device)); |
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|
1546 assert_param(IS_FMC_SDRAM_BANK(Bank)); |
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|
1547 |
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|
1548 /* Enable write protection */ |
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|
1549 Device->SDCR[Bank] |= FMC_SDRAM_WRITE_PROTECTION_ENABLE; |
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|
1550 |
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|
1551 return HAL_OK; |
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|
1552 } |
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|
1553 |
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|
1554 /** |
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|
1555 * @brief Disables dynamically FMC_SDRAM write protection. |
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|
1556 * @param hsdram FMC_SDRAM handle |
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|
1557 * @retval HAL status |
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|
1558 */ |
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|
1559 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank) |
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|
1560 { |
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|
1561 /* Check the parameters */ |
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|
1562 assert_param(IS_FMC_SDRAM_DEVICE(Device)); |
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|
1563 assert_param(IS_FMC_SDRAM_BANK(Bank)); |
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|
1564 |
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|
1565 /* Disable write protection */ |
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|
1566 Device->SDCR[Bank] &= ~FMC_SDRAM_WRITE_PROTECTION_ENABLE; |
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|
1567 |
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|
1568 return HAL_OK; |
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|
1569 } |
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|
1570 |
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|
1571 /** |
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Added current STM32 standandard libraries in version independend folder structure
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|
1572 * @brief Send Command to the FMC SDRAM bank |
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Added current STM32 standandard libraries in version independend folder structure
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|
1573 * @param Device Pointer to SDRAM device instance |
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Added current STM32 standandard libraries in version independend folder structure
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|
1574 * @param Command Pointer to SDRAM command structure |
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Added current STM32 standandard libraries in version independend folder structure
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|
1575 * @param Timing Pointer to SDRAM Timing structure |
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Added current STM32 standandard libraries in version independend folder structure
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|
1576 * @param Timeout Timeout wait value |
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Added current STM32 standandard libraries in version independend folder structure
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|
1577 * @retval HAL state |
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Added current STM32 standandard libraries in version independend folder structure
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|
1578 */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
1579 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) |
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Added current STM32 standandard libraries in version independend folder structure
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|
1580 { |
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Added current STM32 standandard libraries in version independend folder structure
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|
1581 __IO uint32_t tmpr = 0U; |
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Added current STM32 standandard libraries in version independend folder structure
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|
1582 uint32_t tickstart = 0U; |
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Added current STM32 standandard libraries in version independend folder structure
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|
1583 |
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Added current STM32 standandard libraries in version independend folder structure
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|
1584 /* Check the parameters */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
1585 assert_param(IS_FMC_SDRAM_DEVICE(Device)); |
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Added current STM32 standandard libraries in version independend folder structure
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|
1586 assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode)); |
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Added current STM32 standandard libraries in version independend folder structure
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|
1587 assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget)); |
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Added current STM32 standandard libraries in version independend folder structure
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|
1588 assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber)); |
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Added current STM32 standandard libraries in version independend folder structure
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|
1589 assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition)); |
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|
1590 |
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Added current STM32 standandard libraries in version independend folder structure
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|
1591 /* Set command register */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
1592 tmpr = (uint32_t)((Command->CommandMode) |\ |
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Added current STM32 standandard libraries in version independend folder structure
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|
1593 (Command->CommandTarget) |\ |
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Added current STM32 standandard libraries in version independend folder structure
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|
1594 (((Command->AutoRefreshNumber)-1U) << 5U) |\ |
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Added current STM32 standandard libraries in version independend folder structure
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|
1595 ((Command->ModeRegisterDefinition) << 9U) |
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Added current STM32 standandard libraries in version independend folder structure
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|
1596 ); |
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Added current STM32 standandard libraries in version independend folder structure
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|
1597 |
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Added current STM32 standandard libraries in version independend folder structure
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|
1598 Device->SDCMR = tmpr; |
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Added current STM32 standandard libraries in version independend folder structure
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|
1599 |
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|
1600 /* Get tick */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
1601 tickstart = HAL_GetTick(); |
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Added current STM32 standandard libraries in version independend folder structure
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|
1602 |
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Added current STM32 standandard libraries in version independend folder structure
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|
1603 /* Wait until command is send */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
1604 while(HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY)) |
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|
1605 { |
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|
1606 /* Check for the Timeout */ |
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|
1607 if(Timeout != HAL_MAX_DELAY) |
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Added current STM32 standandard libraries in version independend folder structure
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|
1608 { |
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Added current STM32 standandard libraries in version independend folder structure
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|
1609 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) |
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Added current STM32 standandard libraries in version independend folder structure
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|
1610 { |
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Added current STM32 standandard libraries in version independend folder structure
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|
1611 return HAL_TIMEOUT; |
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|
1612 } |
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|
1613 } |
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|
1614 } |
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Added current STM32 standandard libraries in version independend folder structure
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|
1615 |
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|
1616 return HAL_OK; |
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Added current STM32 standandard libraries in version independend folder structure
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|
1617 } |
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Added current STM32 standandard libraries in version independend folder structure
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|
1618 |
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Added current STM32 standandard libraries in version independend folder structure
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|
1619 /** |
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|
1620 * @brief Program the SDRAM Memory Refresh rate. |
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Added current STM32 standandard libraries in version independend folder structure
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|
1621 * @param Device Pointer to SDRAM device instance |
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Added current STM32 standandard libraries in version independend folder structure
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|
1622 * @param RefreshRate The SDRAM refresh rate value. |
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Added current STM32 standandard libraries in version independend folder structure
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|
1623 * @retval HAL state |
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Added current STM32 standandard libraries in version independend folder structure
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|
1624 */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
1625 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate) |
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Added current STM32 standandard libraries in version independend folder structure
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|
1626 { |
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Added current STM32 standandard libraries in version independend folder structure
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|
1627 /* Check the parameters */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
1628 assert_param(IS_FMC_SDRAM_DEVICE(Device)); |
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Added current STM32 standandard libraries in version independend folder structure
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|
1629 assert_param(IS_FMC_REFRESH_RATE(RefreshRate)); |
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Added current STM32 standandard libraries in version independend folder structure
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|
1630 |
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Added current STM32 standandard libraries in version independend folder structure
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|
1631 /* Set the refresh rate in command register */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
1632 Device->SDRTR |= (RefreshRate<<1U); |
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Added current STM32 standandard libraries in version independend folder structure
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|
1633 |
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|
1634 return HAL_OK; |
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Added current STM32 standandard libraries in version independend folder structure
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|
1635 } |
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Added current STM32 standandard libraries in version independend folder structure
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|
1636 |
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|
1637 /** |
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Added current STM32 standandard libraries in version independend folder structure
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|
1638 * @brief Set the Number of consecutive SDRAM Memory auto Refresh commands. |
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Added current STM32 standandard libraries in version independend folder structure
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|
1639 * @param Device Pointer to SDRAM device instance |
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Added current STM32 standandard libraries in version independend folder structure
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|
1640 * @param AutoRefreshNumber Specifies the auto Refresh number. |
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Added current STM32 standandard libraries in version independend folder structure
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|
1641 * @retval None |
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Added current STM32 standandard libraries in version independend folder structure
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|
1642 */ |
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|
1643 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber) |
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|
1644 { |
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|
1645 /* Check the parameters */ |
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|
1646 assert_param(IS_FMC_SDRAM_DEVICE(Device)); |
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|
1647 assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber)); |
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|
1648 |
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|
1649 /* Set the Auto-refresh number in command register */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
1650 Device->SDCMR |= (AutoRefreshNumber << 5U); |
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Added current STM32 standandard libraries in version independend folder structure
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|
1651 |
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|
1652 return HAL_OK; |
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|
1653 } |
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|
1654 |
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|
1655 /** |
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|
1656 * @brief Returns the indicated FMC SDRAM bank mode status. |
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Added current STM32 standandard libraries in version independend folder structure
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|
1657 * @param Device Pointer to SDRAM device instance |
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|
1658 * @param Bank Defines the FMC SDRAM bank. This parameter can be |
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Added current STM32 standandard libraries in version independend folder structure
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|
1659 * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM. |
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Added current STM32 standandard libraries in version independend folder structure
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|
1660 * @retval The FMC SDRAM bank mode status, could be on of the following values: |
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|
1661 * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or |
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1662 * FMC_SDRAM_POWER_DOWN_MODE. |
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|
1663 */ |
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|
1664 uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank) |
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|
1665 { |
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|
1666 uint32_t tmpreg = 0U; |
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|
1667 |
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|
1668 /* Check the parameters */ |
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|
1669 assert_param(IS_FMC_SDRAM_DEVICE(Device)); |
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|
1670 assert_param(IS_FMC_SDRAM_BANK(Bank)); |
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|
1671 |
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|
1672 /* Get the corresponding bank mode */ |
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|
1673 if(Bank == FMC_SDRAM_BANK1) |
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|
1674 { |
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|
1675 tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1); |
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|
1676 } |
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|
1677 else |
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|
1678 { |
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|
1679 tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2U); |
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|
1680 } |
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|
1681 |
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|
1682 /* Return the mode status */ |
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|
1683 return tmpreg; |
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|
1684 } |
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|
1685 |
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|
1686 /** |
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|
1687 * @} |
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|
1688 */ |
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|
1689 |
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|
1690 /** |
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|
1691 * @} |
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|
1692 */ |
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|
1693 |
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|
1694 /** |
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|
1695 * @} |
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|
1696 */ |
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1697 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ |
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1698 #endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED || HAL_SDRAM_MODULE_ENABLED */ |
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|
1699 |
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|
1700 /** |
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|
1701 * @} |
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|
1702 */ |
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|
1703 |
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1704 /** |
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1705 * @} |
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1706 */ |
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1707 |
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1708 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |