Mercurial > public > ostc4
annotate Common/Drivers/CMSIS/Include/core_cm0plus.h @ 473:edfc1a464b42 Improve_Button_Sleep
Do not signal power on reset in case of a "warm" reset:
The RTE signaled at every startup a coldstart to the firmware causing a reset of the button responsitivness to default. Even for example after a firmware update. The reset of the values is a wanted behavior in case a value was set which makes it impossible to operate the buttons. This is still possible by removing the battery => real cold start
author | ideenmodellierer |
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date | Tue, 12 May 2020 22:39:18 +0200 |
parents | c78bcbd5deda |
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rev | line source |
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1 /**************************************************************************//** |
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2 * @file core_cm0plus.h |
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3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File |
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4 * @version V4.30 |
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5 * @date 20. October 2015 |
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6 ******************************************************************************/ |
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7 /* Copyright (c) 2009 - 2015 ARM LIMITED |
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8 |
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9 All rights reserved. |
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10 Redistribution and use in source and binary forms, with or without |
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11 modification, are permitted provided that the following conditions are met: |
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12 - Redistributions of source code must retain the above copyright |
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13 notice, this list of conditions and the following disclaimer. |
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14 - Redistributions in binary form must reproduce the above copyright |
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15 notice, this list of conditions and the following disclaimer in the |
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16 documentation and/or other materials provided with the distribution. |
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17 - Neither the name of ARM nor the names of its contributors may be used |
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18 to endorse or promote products derived from this software without |
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19 specific prior written permission. |
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20 * |
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21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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24 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
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25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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31 POSSIBILITY OF SUCH DAMAGE. |
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32 ---------------------------------------------------------------------------*/ |
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33 |
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34 |
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35 #if defined ( __ICCARM__ ) |
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36 #pragma system_include /* treat file as system include file for MISRA check */ |
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37 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
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38 #pragma clang system_header /* treat file as system include file */ |
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39 #endif |
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40 |
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41 #ifndef __CORE_CM0PLUS_H_GENERIC |
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42 #define __CORE_CM0PLUS_H_GENERIC |
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43 |
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44 #include <stdint.h> |
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45 |
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46 #ifdef __cplusplus |
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47 extern "C" { |
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48 #endif |
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49 |
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50 /** |
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51 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions |
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52 CMSIS violates the following MISRA-C:2004 rules: |
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53 |
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54 \li Required Rule 8.5, object/function definition in header file.<br> |
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55 Function definitions in header files are used to allow 'inlining'. |
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56 |
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57 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> |
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58 Unions are used for effective representation of core registers. |
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59 |
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60 \li Advisory Rule 19.7, Function-like macro defined.<br> |
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61 Function-like macros are used to allow more efficient code. |
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62 */ |
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63 |
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64 |
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65 /******************************************************************************* |
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66 * CMSIS definitions |
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67 ******************************************************************************/ |
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68 /** |
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69 \ingroup Cortex-M0+ |
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70 @{ |
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71 */ |
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72 |
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73 /* CMSIS CM0+ definitions */ |
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74 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ |
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75 #define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ |
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76 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ |
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77 __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ |
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78 |
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79 #define __CORTEX_M (0x00U) /*!< Cortex-M Core */ |
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80 |
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81 |
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82 #if defined ( __CC_ARM ) |
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83 #define __ASM __asm /*!< asm keyword for ARM Compiler */ |
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84 #define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
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85 #define __STATIC_INLINE static __inline |
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86 |
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87 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
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88 #define __ASM __asm /*!< asm keyword for ARM Compiler */ |
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89 #define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
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90 #define __STATIC_INLINE static __inline |
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91 |
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92 #elif defined ( __GNUC__ ) |
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93 #define __ASM __asm /*!< asm keyword for GNU Compiler */ |
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94 #define __INLINE inline /*!< inline keyword for GNU Compiler */ |
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95 #define __STATIC_INLINE static inline |
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96 |
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97 #elif defined ( __ICCARM__ ) |
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98 #define __ASM __asm /*!< asm keyword for IAR Compiler */ |
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99 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ |
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100 #define __STATIC_INLINE static inline |
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101 |
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102 #elif defined ( __TMS470__ ) |
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103 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ |
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104 #define __STATIC_INLINE static inline |
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105 |
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106 #elif defined ( __TASKING__ ) |
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107 #define __ASM __asm /*!< asm keyword for TASKING Compiler */ |
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108 #define __INLINE inline /*!< inline keyword for TASKING Compiler */ |
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109 #define __STATIC_INLINE static inline |
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110 |
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111 #elif defined ( __CSMC__ ) |
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112 #define __packed |
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113 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ |
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114 #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ |
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115 #define __STATIC_INLINE static inline |
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116 |
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117 #else |
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118 #error Unknown compiler |
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119 #endif |
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120 |
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121 /** __FPU_USED indicates whether an FPU is used or not. |
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122 This core does not support an FPU at all |
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123 */ |
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124 #define __FPU_USED 0U |
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125 |
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126 #if defined ( __CC_ARM ) |
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127 #if defined __TARGET_FPU_VFP |
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128 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
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129 #endif |
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130 |
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131 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
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132 #if defined __ARM_PCS_VFP |
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133 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
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134 #endif |
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135 |
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136 #elif defined ( __GNUC__ ) |
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137 #if defined (__VFP_FP__) && !defined(__SOFTFP__) |
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138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
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139 #endif |
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140 |
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141 #elif defined ( __ICCARM__ ) |
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142 #if defined __ARMVFP__ |
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143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
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144 #endif |
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145 |
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146 #elif defined ( __TMS470__ ) |
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147 #if defined __TI_VFP_SUPPORT__ |
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148 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
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149 #endif |
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150 |
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151 #elif defined ( __TASKING__ ) |
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152 #if defined __FPU_VFP__ |
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153 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
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154 #endif |
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155 |
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156 #elif defined ( __CSMC__ ) |
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157 #if ( __CSMC__ & 0x400U) |
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158 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
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159 #endif |
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160 |
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161 #endif |
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162 |
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163 #include "core_cmInstr.h" /* Core Instruction Access */ |
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164 #include "core_cmFunc.h" /* Core Function Access */ |
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165 |
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166 #ifdef __cplusplus |
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167 } |
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168 #endif |
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169 |
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170 #endif /* __CORE_CM0PLUS_H_GENERIC */ |
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171 |
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172 #ifndef __CMSIS_GENERIC |
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173 |
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174 #ifndef __CORE_CM0PLUS_H_DEPENDANT |
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175 #define __CORE_CM0PLUS_H_DEPENDANT |
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176 |
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177 #ifdef __cplusplus |
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178 extern "C" { |
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179 #endif |
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180 |
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181 /* check device defines and use defaults */ |
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182 #if defined __CHECK_DEVICE_DEFINES |
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183 #ifndef __CM0PLUS_REV |
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184 #define __CM0PLUS_REV 0x0000U |
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185 #warning "__CM0PLUS_REV not defined in device header file; using default!" |
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186 #endif |
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187 |
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188 #ifndef __MPU_PRESENT |
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189 #define __MPU_PRESENT 0U |
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190 #warning "__MPU_PRESENT not defined in device header file; using default!" |
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191 #endif |
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192 |
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193 #ifndef __VTOR_PRESENT |
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194 #define __VTOR_PRESENT 0U |
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195 #warning "__VTOR_PRESENT not defined in device header file; using default!" |
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196 #endif |
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197 |
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198 #ifndef __NVIC_PRIO_BITS |
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199 #define __NVIC_PRIO_BITS 2U |
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200 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" |
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201 #endif |
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202 |
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203 #ifndef __Vendor_SysTickConfig |
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204 #define __Vendor_SysTickConfig 0U |
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205 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" |
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206 #endif |
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207 #endif |
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208 |
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209 /* IO definitions (access restrictions to peripheral registers) */ |
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210 /** |
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211 \defgroup CMSIS_glob_defs CMSIS Global Defines |
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212 |
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213 <strong>IO Type Qualifiers</strong> are used |
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214 \li to specify the access to peripheral variables. |
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215 \li for automatic generation of peripheral register debug information. |
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216 */ |
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217 #ifdef __cplusplus |
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218 #define __I volatile /*!< Defines 'read only' permissions */ |
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219 #else |
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220 #define __I volatile const /*!< Defines 'read only' permissions */ |
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221 #endif |
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222 #define __O volatile /*!< Defines 'write only' permissions */ |
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223 #define __IO volatile /*!< Defines 'read / write' permissions */ |
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224 |
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225 /* following defines should be used for structure members */ |
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226 #define __IM volatile const /*! Defines 'read only' structure member permissions */ |
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227 #define __OM volatile /*! Defines 'write only' structure member permissions */ |
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228 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ |
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229 |
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230 /*@} end of group Cortex-M0+ */ |
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231 |
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232 |
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233 |
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234 /******************************************************************************* |
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235 * Register Abstraction |
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236 Core Register contain: |
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237 - Core Register |
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238 - Core NVIC Register |
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239 - Core SCB Register |
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240 - Core SysTick Register |
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241 - Core MPU Register |
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242 ******************************************************************************/ |
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243 /** |
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244 \defgroup CMSIS_core_register Defines and Type Definitions |
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245 \brief Type definitions and defines for Cortex-M processor based devices. |
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246 */ |
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247 |
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248 /** |
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249 \ingroup CMSIS_core_register |
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250 \defgroup CMSIS_CORE Status and Control Registers |
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251 \brief Core Register type definitions. |
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252 @{ |
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253 */ |
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254 |
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255 /** |
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256 \brief Union type to access the Application Program Status Register (APSR). |
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257 */ |
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258 typedef union |
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259 { |
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260 struct |
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261 { |
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262 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ |
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263 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
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264 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
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265 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
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266 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
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267 } b; /*!< Structure used for bit access */ |
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268 uint32_t w; /*!< Type used for word access */ |
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269 } APSR_Type; |
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270 |
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271 /* APSR Register Definitions */ |
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272 #define APSR_N_Pos 31U /*!< APSR: N Position */ |
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273 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ |
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274 |
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275 #define APSR_Z_Pos 30U /*!< APSR: Z Position */ |
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276 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ |
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277 |
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278 #define APSR_C_Pos 29U /*!< APSR: C Position */ |
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279 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ |
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280 |
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281 #define APSR_V_Pos 28U /*!< APSR: V Position */ |
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282 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ |
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283 |
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284 |
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285 /** |
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286 \brief Union type to access the Interrupt Program Status Register (IPSR). |
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287 */ |
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288 typedef union |
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289 { |
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290 struct |
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291 { |
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292 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
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293 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ |
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294 } b; /*!< Structure used for bit access */ |
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295 uint32_t w; /*!< Type used for word access */ |
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296 } IPSR_Type; |
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297 |
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298 /* IPSR Register Definitions */ |
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299 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ |
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300 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ |
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301 |
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302 |
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303 /** |
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304 \brief Union type to access the Special-Purpose Program Status Registers (xPSR). |
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305 */ |
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306 typedef union |
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307 { |
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308 struct |
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309 { |
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310 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
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311 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ |
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312 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ |
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313 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ |
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314 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
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315 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
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316 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
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317 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
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318 } b; /*!< Structure used for bit access */ |
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319 uint32_t w; /*!< Type used for word access */ |
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320 } xPSR_Type; |
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321 |
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322 /* xPSR Register Definitions */ |
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323 #define xPSR_N_Pos 31U /*!< xPSR: N Position */ |
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324 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ |
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325 |
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326 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ |
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327 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ |
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328 |
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329 #define xPSR_C_Pos 29U /*!< xPSR: C Position */ |
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330 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ |
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331 |
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332 #define xPSR_V_Pos 28U /*!< xPSR: V Position */ |
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333 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ |
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334 |
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335 #define xPSR_T_Pos 24U /*!< xPSR: T Position */ |
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336 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ |
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337 |
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338 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ |
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339 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ |
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340 |
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341 |
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342 /** |
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343 \brief Union type to access the Control Registers (CONTROL). |
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344 */ |
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345 typedef union |
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346 { |
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347 struct |
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348 { |
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349 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ |
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350 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ |
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351 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ |
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352 } b; /*!< Structure used for bit access */ |
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353 uint32_t w; /*!< Type used for word access */ |
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354 } CONTROL_Type; |
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355 |
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356 /* CONTROL Register Definitions */ |
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357 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ |
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358 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ |
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359 |
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360 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ |
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361 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ |
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362 |
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363 /*@} end of group CMSIS_CORE */ |
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364 |
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365 |
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366 /** |
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367 \ingroup CMSIS_core_register |
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368 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) |
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369 \brief Type definitions for the NVIC Registers |
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370 @{ |
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371 */ |
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372 |
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373 /** |
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374 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). |
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375 */ |
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376 typedef struct |
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377 { |
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378 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ |
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379 uint32_t RESERVED0[31U]; |
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380 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ |
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381 uint32_t RSERVED1[31U]; |
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382 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ |
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383 uint32_t RESERVED2[31U]; |
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384 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ |
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385 uint32_t RESERVED3[31U]; |
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386 uint32_t RESERVED4[64U]; |
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387 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ |
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388 } NVIC_Type; |
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389 |
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390 /*@} end of group CMSIS_NVIC */ |
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391 |
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392 |
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393 /** |
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394 \ingroup CMSIS_core_register |
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395 \defgroup CMSIS_SCB System Control Block (SCB) |
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396 \brief Type definitions for the System Control Block Registers |
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397 @{ |
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398 */ |
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399 |
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400 /** |
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401 \brief Structure type to access the System Control Block (SCB). |
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402 */ |
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403 typedef struct |
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404 { |
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405 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ |
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406 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ |
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407 #if (__VTOR_PRESENT == 1U) |
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408 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ |
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409 #else |
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410 uint32_t RESERVED0; |
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411 #endif |
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412 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ |
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413 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ |
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414 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ |
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415 uint32_t RESERVED1; |
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416 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ |
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417 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ |
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418 } SCB_Type; |
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419 |
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420 /* SCB CPUID Register Definitions */ |
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421 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ |
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422 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ |
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423 |
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424 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ |
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425 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ |
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426 |
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427 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ |
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428 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ |
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429 |
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430 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ |
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431 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ |
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432 |
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433 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ |
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434 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ |
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435 |
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436 /* SCB Interrupt Control State Register Definitions */ |
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437 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ |
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438 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ |
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439 |
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440 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ |
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441 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ |
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442 |
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443 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ |
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444 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ |
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445 |
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446 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ |
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447 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ |
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448 |
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449 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ |
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450 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ |
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451 |
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452 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ |
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453 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ |
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454 |
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455 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ |
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456 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ |
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457 |
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458 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ |
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459 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ |
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460 |
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461 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ |
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462 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ |
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463 |
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464 #if (__VTOR_PRESENT == 1U) |
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465 /* SCB Interrupt Control State Register Definitions */ |
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466 #define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ |
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467 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ |
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468 #endif |
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469 |
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470 /* SCB Application Interrupt and Reset Control Register Definitions */ |
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471 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ |
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472 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ |
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473 |
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474 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ |
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475 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ |
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476 |
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477 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ |
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478 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ |
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479 |
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480 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ |
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481 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ |
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482 |
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483 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ |
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484 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ |
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485 |
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486 /* SCB System Control Register Definitions */ |
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487 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ |
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488 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ |
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489 |
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490 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ |
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491 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ |
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492 |
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493 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ |
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494 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ |
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495 |
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496 /* SCB Configuration Control Register Definitions */ |
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497 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ |
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498 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ |
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499 |
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500 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ |
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501 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ |
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502 |
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503 /* SCB System Handler Control and State Register Definitions */ |
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504 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ |
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505 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ |
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506 |
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507 /*@} end of group CMSIS_SCB */ |
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508 |
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509 |
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510 /** |
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511 \ingroup CMSIS_core_register |
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512 \defgroup CMSIS_SysTick System Tick Timer (SysTick) |
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513 \brief Type definitions for the System Timer Registers. |
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514 @{ |
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515 */ |
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516 |
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517 /** |
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518 \brief Structure type to access the System Timer (SysTick). |
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519 */ |
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520 typedef struct |
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521 { |
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522 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ |
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523 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ |
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524 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ |
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525 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ |
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526 } SysTick_Type; |
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527 |
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528 /* SysTick Control / Status Register Definitions */ |
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529 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ |
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530 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ |
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531 |
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532 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ |
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533 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ |
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534 |
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535 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ |
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536 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ |
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537 |
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538 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ |
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539 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ |
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540 |
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541 /* SysTick Reload Register Definitions */ |
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542 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ |
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543 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ |
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544 |
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545 /* SysTick Current Register Definitions */ |
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546 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ |
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547 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ |
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548 |
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549 /* SysTick Calibration Register Definitions */ |
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550 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ |
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551 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ |
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552 |
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553 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ |
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554 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ |
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555 |
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556 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ |
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557 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ |
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558 |
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559 /*@} end of group CMSIS_SysTick */ |
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560 |
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561 #if (__MPU_PRESENT == 1U) |
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562 /** |
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563 \ingroup CMSIS_core_register |
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564 \defgroup CMSIS_MPU Memory Protection Unit (MPU) |
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565 \brief Type definitions for the Memory Protection Unit (MPU) |
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566 @{ |
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567 */ |
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568 |
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569 /** |
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570 \brief Structure type to access the Memory Protection Unit (MPU). |
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571 */ |
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572 typedef struct |
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573 { |
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574 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ |
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575 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ |
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576 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ |
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577 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ |
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578 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ |
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579 } MPU_Type; |
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580 |
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581 /* MPU Type Register Definitions */ |
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582 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ |
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583 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ |
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584 |
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585 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ |
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586 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ |
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587 |
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588 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ |
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589 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ |
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590 |
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591 /* MPU Control Register Definitions */ |
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592 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ |
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593 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ |
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594 |
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595 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ |
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596 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ |
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597 |
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598 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ |
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599 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ |
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600 |
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601 /* MPU Region Number Register Definitions */ |
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602 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ |
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603 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ |
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604 |
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605 /* MPU Region Base Address Register Definitions */ |
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606 #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ |
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607 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ |
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608 |
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609 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ |
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610 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ |
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611 |
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612 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ |
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613 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ |
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614 |
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615 /* MPU Region Attribute and Size Register Definitions */ |
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616 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ |
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617 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ |
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618 |
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619 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ |
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620 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ |
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621 |
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622 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ |
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623 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ |
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624 |
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625 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ |
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626 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ |
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627 |
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628 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ |
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629 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ |
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630 |
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631 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ |
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632 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ |
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633 |
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634 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ |
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635 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ |
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636 |
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637 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ |
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638 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ |
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639 |
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640 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ |
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641 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ |
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642 |
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643 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ |
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644 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ |
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645 |
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646 /*@} end of group CMSIS_MPU */ |
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647 #endif |
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648 |
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649 |
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650 /** |
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651 \ingroup CMSIS_core_register |
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652 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) |
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653 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. |
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654 Therefore they are not covered by the Cortex-M0+ header file. |
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655 @{ |
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656 */ |
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657 /*@} end of group CMSIS_CoreDebug */ |
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658 |
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659 |
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660 /** |
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661 \ingroup CMSIS_core_register |
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662 \defgroup CMSIS_core_bitfield Core register bit field macros |
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663 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). |
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664 @{ |
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665 */ |
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666 |
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667 /** |
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668 \brief Mask and shift a bit field value for use in a register bit range. |
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669 \param[in] field Name of the register bit field. |
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670 \param[in] value Value of the bit field. |
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671 \return Masked and shifted value. |
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672 */ |
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673 #define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) |
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674 |
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675 /** |
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676 \brief Mask and shift a register value to extract a bit filed value. |
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677 \param[in] field Name of the register bit field. |
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678 \param[in] value Value of register. |
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679 \return Masked and shifted bit field value. |
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680 */ |
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681 #define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) |
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682 |
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683 /*@} end of group CMSIS_core_bitfield */ |
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684 |
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685 |
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686 /** |
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687 \ingroup CMSIS_core_register |
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688 \defgroup CMSIS_core_base Core Definitions |
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689 \brief Definitions for base addresses, unions, and structures. |
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690 @{ |
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691 */ |
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692 |
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693 /* Memory mapping of Cortex-M0+ Hardware */ |
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694 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ |
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695 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ |
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696 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ |
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697 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ |
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698 |
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699 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ |
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700 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ |
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701 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ |
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702 |
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703 #if (__MPU_PRESENT == 1U) |
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704 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ |
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705 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ |
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706 #endif |
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707 |
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708 /*@} */ |
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709 |
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710 |
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711 |
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712 /******************************************************************************* |
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713 * Hardware Abstraction Layer |
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714 Core Function Interface contains: |
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715 - Core NVIC Functions |
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716 - Core SysTick Functions |
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717 - Core Register Access Functions |
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718 ******************************************************************************/ |
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719 /** |
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720 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference |
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721 */ |
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722 |
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723 |
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724 |
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725 /* ########################## NVIC functions #################################### */ |
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726 /** |
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727 \ingroup CMSIS_Core_FunctionInterface |
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728 \defgroup CMSIS_Core_NVICFunctions NVIC Functions |
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729 \brief Functions that manage interrupts and exceptions via the NVIC. |
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730 @{ |
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731 */ |
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732 |
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733 /* Interrupt Priorities are WORD accessible only under ARMv6M */ |
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734 /* The following MACROS handle generation of the register offset and byte masks */ |
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735 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) |
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736 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) |
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737 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) |
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738 |
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739 |
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740 /** |
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741 \brief Enable External Interrupt |
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742 \details Enables a device-specific interrupt in the NVIC interrupt controller. |
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743 \param [in] IRQn External interrupt number. Value cannot be negative. |
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744 */ |
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745 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) |
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746 { |
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747 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
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748 } |
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749 |
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750 |
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751 /** |
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752 \brief Disable External Interrupt |
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753 \details Disables a device-specific interrupt in the NVIC interrupt controller. |
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754 \param [in] IRQn External interrupt number. Value cannot be negative. |
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755 */ |
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756 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) |
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757 { |
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758 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
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759 } |
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760 |
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761 |
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|
762 /** |
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|
763 \brief Get Pending Interrupt |
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|
764 \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. |
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765 \param [in] IRQn Interrupt number. |
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766 \return 0 Interrupt status is not pending. |
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767 \return 1 Interrupt status is pending. |
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|
768 */ |
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|
769 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) |
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770 { |
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771 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
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772 } |
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|
773 |
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|
774 |
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|
775 /** |
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|
776 \brief Set Pending Interrupt |
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|
777 \details Sets the pending bit of an external interrupt. |
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|
778 \param [in] IRQn Interrupt number. Value cannot be negative. |
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779 */ |
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780 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) |
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781 { |
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782 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
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783 } |
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784 |
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785 |
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|
786 /** |
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|
787 \brief Clear Pending Interrupt |
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|
788 \details Clears the pending bit of an external interrupt. |
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789 \param [in] IRQn External interrupt number. Value cannot be negative. |
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790 */ |
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|
791 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
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792 { |
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|
793 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
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794 } |
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|
795 |
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|
796 |
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797 /** |
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798 \brief Set Interrupt Priority |
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799 \details Sets the priority of an interrupt. |
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800 \note The priority cannot be set for every core interrupt. |
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801 \param [in] IRQn Interrupt number. |
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|
802 \param [in] priority Priority to set. |
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|
803 */ |
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|
804 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
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805 { |
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806 if ((int32_t)(IRQn) < 0) |
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807 { |
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808 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
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809 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
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810 } |
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811 else |
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812 { |
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813 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
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814 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
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815 } |
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816 } |
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817 |
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818 |
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|
819 /** |
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820 \brief Get Interrupt Priority |
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821 \details Reads the priority of an interrupt. |
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822 The interrupt number can be positive to specify an external (device specific) interrupt, |
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823 or negative to specify an internal (core) interrupt. |
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824 \param [in] IRQn Interrupt number. |
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825 \return Interrupt Priority. |
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826 Value is aligned automatically to the implemented priority bits of the microcontroller. |
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827 */ |
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828 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) |
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829 { |
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830 |
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831 if ((int32_t)(IRQn) < 0) |
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832 { |
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833 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); |
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834 } |
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835 else |
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836 { |
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837 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); |
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838 } |
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839 } |
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840 |
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841 |
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842 /** |
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843 \brief System Reset |
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844 \details Initiates a system reset request to reset the MCU. |
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845 */ |
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846 __STATIC_INLINE void NVIC_SystemReset(void) |
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847 { |
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848 __DSB(); /* Ensure all outstanding memory accesses included |
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849 buffered write are completed before reset */ |
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850 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | |
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851 SCB_AIRCR_SYSRESETREQ_Msk); |
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852 __DSB(); /* Ensure completion of memory access */ |
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853 |
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854 for(;;) /* wait until reset */ |
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855 { |
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856 __NOP(); |
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857 } |
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858 } |
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859 |
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860 /*@} end of CMSIS_Core_NVICFunctions */ |
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861 |
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862 |
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863 |
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864 /* ################################## SysTick function ############################################ */ |
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865 /** |
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866 \ingroup CMSIS_Core_FunctionInterface |
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867 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions |
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868 \brief Functions that configure the System. |
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869 @{ |
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870 */ |
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871 |
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872 #if (__Vendor_SysTickConfig == 0U) |
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873 |
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874 /** |
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875 \brief System Tick Configuration |
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876 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. |
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877 Counter is in free running mode to generate periodic interrupts. |
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878 \param [in] ticks Number of ticks between two interrupts. |
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879 \return 0 Function succeeded. |
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880 \return 1 Function failed. |
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881 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the |
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882 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> |
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883 must contain a vendor-specific implementation of this function. |
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884 */ |
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885 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) |
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886 { |
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887 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) |
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888 { |
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889 return (1UL); /* Reload value impossible */ |
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890 } |
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891 |
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892 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ |
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893 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ |
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894 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ |
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895 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | |
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896 SysTick_CTRL_TICKINT_Msk | |
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897 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ |
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898 return (0UL); /* Function successful */ |
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899 } |
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900 |
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901 #endif |
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902 |
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903 /*@} end of CMSIS_Core_SysTickFunctions */ |
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904 |
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905 |
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906 |
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907 |
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908 #ifdef __cplusplus |
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909 } |
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910 #endif |
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911 |
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912 #endif /* __CORE_CM0PLUS_H_DEPENDANT */ |
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913 |
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914 #endif /* __CMSIS_GENERIC */ |