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annotate Common/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h @ 943:e7f87ade3037 Evo_2_23 tip

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Added missing compile switches
author Ideenmodellierer
date Mon, 16 Dec 2024 19:33:20 +0100
parents c78bcbd5deda
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1 /**
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2 ******************************************************************************
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3 * @file stm32f4xx_hal_pwr_ex.h
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4 * @author MCD Application Team
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5 * @brief Header file of PWR HAL Extension module.
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6 ******************************************************************************
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7 * @attention
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8 *
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9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
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10 *
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11 * Redistribution and use in source and binary forms, with or without modification,
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12 * are permitted provided that the following conditions are met:
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13 * 1. Redistributions of source code must retain the above copyright notice,
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14 * this list of conditions and the following disclaimer.
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15 * 2. Redistributions in binary form must reproduce the above copyright notice,
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16 * this list of conditions and the following disclaimer in the documentation
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17 * and/or other materials provided with the distribution.
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18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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19 * may be used to endorse or promote products derived from this software
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20 * without specific prior written permission.
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21 *
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22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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32 *
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33 ******************************************************************************
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34 */
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35
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36 /* Define to prevent recursive inclusion -------------------------------------*/
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37 #ifndef __STM32F4xx_HAL_PWR_EX_H
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38 #define __STM32F4xx_HAL_PWR_EX_H
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39
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40 #ifdef __cplusplus
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41 extern "C" {
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42 #endif
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43
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44 /* Includes ------------------------------------------------------------------*/
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45 #include "stm32f4xx_hal_def.h"
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46
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47 /** @addtogroup STM32F4xx_HAL_Driver
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48 * @{
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49 */
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50
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51 /** @addtogroup PWREx
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52 * @{
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53 */
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54
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55 /* Exported types ------------------------------------------------------------*/
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56 /* Exported constants --------------------------------------------------------*/
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57 /** @defgroup PWREx_Exported_Constants PWREx Exported Constants
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58 * @{
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59 */
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60 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
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61 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
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62
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63 /** @defgroup PWREx_Regulator_state_in_UnderDrive_mode PWREx Regulator state in UnderDrive mode
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64 * @{
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65 */
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66 #define PWR_MAINREGULATOR_UNDERDRIVE_ON PWR_CR_MRUDS
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67 #define PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON ((uint32_t)(PWR_CR_LPDS | PWR_CR_LPUDS))
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68 /**
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69 * @}
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70 */
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71
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72 /** @defgroup PWREx_Over_Under_Drive_Flag PWREx Over Under Drive Flag
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73 * @{
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74 */
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75 #define PWR_FLAG_ODRDY PWR_CSR_ODRDY
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76 #define PWR_FLAG_ODSWRDY PWR_CSR_ODSWRDY
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77 #define PWR_FLAG_UDRDY PWR_CSR_UDSWRDY
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78 /**
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79 * @}
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80 */
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81 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
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82
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83 /** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale
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84 * @{
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85 */
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86 #if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)
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87 #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS /* Scale 1 mode(default value at reset): the maximum value of fHCLK = 168 MHz. */
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88 #define PWR_REGULATOR_VOLTAGE_SCALE2 0x00000000U /* Scale 2 mode: the maximum value of fHCLK = 144 MHz. */
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89 #else
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90 #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS /* Scale 1 mode(default value at reset): the maximum value of fHCLK is 168 MHz. It can be extended to
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91 180 MHz by activating the over-drive mode. */
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92 #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1 /* Scale 2 mode: the maximum value of fHCLK is 144 MHz. It can be extended to
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93 168 MHz by activating the over-drive mode. */
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94 #define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS_0 /* Scale 3 mode: the maximum value of fHCLK is 120 MHz. */
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95 #endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */
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96 /**
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97 * @}
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98 */
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99 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
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100 defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
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101 /** @defgroup PWREx_WakeUp_Pins PWREx WakeUp Pins
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102 * @{
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103 */
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104 #define PWR_WAKEUP_PIN2 0x00000080U
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105 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
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106 defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
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107 #define PWR_WAKEUP_PIN3 0x00000040U
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108 #endif /* STM32F410xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Zx || STM32F412Vx || \
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109 STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
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110 /**
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111 * @}
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112 */
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113 #endif /* STM32F410xx || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx ||
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114 STM32F413xx || STM32F423xx */
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115
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116 /**
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117 * @}
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118 */
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119
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120 /* Exported macro ------------------------------------------------------------*/
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121 /** @defgroup PWREx_Exported_Constants PWREx Exported Constants
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122 * @{
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123 */
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124
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125 #if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)
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126 /** @brief macros configure the main internal regulator output voltage.
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127 * @param __REGULATOR__ specifies the regulator output voltage to achieve
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128 * a tradeoff between performance and power consumption when the device does
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129 * not operate at the maximum frequency (refer to the datasheets for more details).
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130 * This parameter can be one of the following values:
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131 * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
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132 * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
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133 * @retval None
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134 */
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135 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \
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136 __IO uint32_t tmpreg = 0x00U; \
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137 MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)); \
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138 /* Delay after an RCC peripheral clock enabling */ \
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139 tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); \
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140 UNUSED(tmpreg); \
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141 } while(0U)
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142 #else
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143 /** @brief macros configure the main internal regulator output voltage.
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144 * @param __REGULATOR__ specifies the regulator output voltage to achieve
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145 * a tradeoff between performance and power consumption when the device does
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146 * not operate at the maximum frequency (refer to the datasheets for more details).
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147 * This parameter can be one of the following values:
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148 * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
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149 * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
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150 * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
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151 * @retval None
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152 */
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153 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \
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154 __IO uint32_t tmpreg = 0x00U; \
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155 MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)); \
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156 /* Delay after an RCC peripheral clock enabling */ \
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157 tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); \
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158 UNUSED(tmpreg); \
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159 } while(0U)
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160 #endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */
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161
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162 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
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163 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
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164 /** @brief Macros to enable or disable the Over drive mode.
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165 * @note These macros can be used only for STM32F42xx/STM3243xx devices.
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166 */
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167 #define __HAL_PWR_OVERDRIVE_ENABLE() (*(__IO uint32_t *) CR_ODEN_BB = ENABLE)
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168 #define __HAL_PWR_OVERDRIVE_DISABLE() (*(__IO uint32_t *) CR_ODEN_BB = DISABLE)
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169
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170 /** @brief Macros to enable or disable the Over drive switching.
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171 * @note These macros can be used only for STM32F42xx/STM3243xx devices.
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172 */
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173 #define __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = ENABLE)
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174 #define __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = DISABLE)
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175
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176 /** @brief Macros to enable or disable the Under drive mode.
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177 * @note This mode is enabled only with STOP low power mode.
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178 * In this mode, the 1.2V domain is preserved in reduced leakage mode. This
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179 * mode is only available when the main regulator or the low power regulator
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180 * is in low voltage mode.
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181 * @note If the Under-drive mode was enabled, it is automatically disabled after
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182 * exiting Stop mode.
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183 * When the voltage regulator operates in Under-drive mode, an additional
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184 * startup delay is induced when waking up from Stop mode.
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185 */
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186 #define __HAL_PWR_UNDERDRIVE_ENABLE() (PWR->CR |= (uint32_t)PWR_CR_UDEN)
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187 #define __HAL_PWR_UNDERDRIVE_DISABLE() (PWR->CR &= (uint32_t)(~PWR_CR_UDEN))
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188
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189 /** @brief Check PWR flag is set or not.
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190 * @note These macros can be used only for STM32F42xx/STM3243xx devices.
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191 * @param __FLAG__ specifies the flag to check.
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192 * This parameter can be one of the following values:
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193 * @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode
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194 * is ready
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195 * @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode
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196 * switching is ready
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197 * @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode
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198 * is enabled in Stop mode
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199 * @retval The new state of __FLAG__ (TRUE or FALSE).
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200 */
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201 #define __HAL_PWR_GET_ODRUDR_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
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202
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203 /** @brief Clear the Under-Drive Ready flag.
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204 * @note These macros can be used only for STM32F42xx/STM3243xx devices.
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205 */
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206 #define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR |= PWR_FLAG_UDRDY)
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207
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208 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
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209 /**
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210 * @}
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211 */
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212
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213 /* Exported functions --------------------------------------------------------*/
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214 /** @addtogroup PWREx_Exported_Functions PWREx Exported Functions
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215 * @{
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216 */
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217
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218 /** @addtogroup PWREx_Exported_Functions_Group1
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219 * @{
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220 */
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221 void HAL_PWREx_EnableFlashPowerDown(void);
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222 void HAL_PWREx_DisableFlashPowerDown(void);
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223 HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);
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224 HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);
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225 uint32_t HAL_PWREx_GetVoltageRange(void);
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226 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
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227
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228 #if defined(STM32F469xx) || defined(STM32F479xx)
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229 void HAL_PWREx_EnableWakeUpPinPolarityRisingEdge(void);
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230 void HAL_PWREx_EnableWakeUpPinPolarityFallingEdge(void);
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231 #endif /* STM32F469xx || STM32F479xx */
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232
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233 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F401xC) ||\
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234 defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
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235 defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
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236 void HAL_PWREx_EnableMainRegulatorLowVoltage(void);
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237 void HAL_PWREx_DisableMainRegulatorLowVoltage(void);
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238 void HAL_PWREx_EnableLowRegulatorLowVoltage(void);
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239 void HAL_PWREx_DisableLowRegulatorLowVoltage(void);
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240 #endif /* STM32F410xx || STM32F401xC || STM32F401xE || STM32F411xE || STM32F412Zx || STM32F412Vx ||\
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241 STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
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242
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243 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\
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244 defined(STM32F469xx) || defined(STM32F479xx)
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245 HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void);
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246 HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void);
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247 HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
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248 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
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249
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250 /**
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251 * @}
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252 */
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253
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254 /**
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255 * @}
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256 */
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257 /* Private types -------------------------------------------------------------*/
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258 /* Private variables ---------------------------------------------------------*/
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259 /* Private constants ---------------------------------------------------------*/
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260 /** @defgroup PWREx_Private_Constants PWREx Private Constants
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261 * @{
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262 */
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263
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264 /** @defgroup PWREx_register_alias_address PWREx Register alias address
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265 * @{
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266 */
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267 /* ------------- PWR registers bit address in the alias region ---------------*/
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268 /* --- CR Register ---*/
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269 /* Alias word address of FPDS bit */
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270 #define FPDS_BIT_NUMBER PWR_CR_FPDS_Pos
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271 #define CR_FPDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (FPDS_BIT_NUMBER * 4U))
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272
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273 /* Alias word address of ODEN bit */
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274 #define ODEN_BIT_NUMBER PWR_CR_ODEN_Pos
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275 #define CR_ODEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODEN_BIT_NUMBER * 4U))
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276
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277 /* Alias word address of ODSWEN bit */
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278 #define ODSWEN_BIT_NUMBER PWR_CR_ODSWEN_Pos
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279 #define CR_ODSWEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODSWEN_BIT_NUMBER * 4U))
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280
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281 /* Alias word address of MRLVDS bit */
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282 #define MRLVDS_BIT_NUMBER PWR_CR_MRLVDS_Pos
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283 #define CR_MRLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (MRLVDS_BIT_NUMBER * 4U))
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284
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285 /* Alias word address of LPLVDS bit */
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286 #define LPLVDS_BIT_NUMBER PWR_CR_LPLVDS_Pos
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287 #define CR_LPLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPLVDS_BIT_NUMBER * 4U))
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288
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289 /**
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290 * @}
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291 */
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292
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293 /** @defgroup PWREx_CSR_register_alias PWRx CSR Register alias address
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294 * @{
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295 */
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296 /* --- CSR Register ---*/
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297 /* Alias word address of BRE bit */
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298 #define BRE_BIT_NUMBER PWR_CSR_BRE_Pos
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299 #define CSR_BRE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (BRE_BIT_NUMBER * 4U))
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300
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301 #if defined(STM32F469xx) || defined(STM32F479xx)
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302 /* Alias word address of WUPP bit */
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303 #define WUPP_BIT_NUMBER PWR_CSR_WUPP_Pos
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304 #define CSR_WUPP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (WUPP_BIT_NUMBER * 4U))
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305 #endif /* STM32F469xx || STM32F479xx */
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306 /**
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307 * @}
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308 */
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309
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310 /**
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311 * @}
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312 */
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313
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314 /* Private macros ------------------------------------------------------------*/
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315 /** @defgroup PWREx_Private_Macros PWREx Private Macros
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316 * @{
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317 */
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318
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319 /** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters
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320 * @{
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321 */
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322 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
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323 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
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324 #define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || \
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325 ((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON))
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326 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
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327
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328 #if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)
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329 #define IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
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330 ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
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331 #else
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332 #define IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
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333 ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
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334 ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
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335 #endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */
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336
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337 #if defined(STM32F446xx)
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338 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2))
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339 #elif defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F412Zx) ||\
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340 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
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341 defined(STM32F423xx)
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342 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2) || \
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343 ((PIN) == PWR_WAKEUP_PIN3))
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344 #else
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345 #define IS_PWR_WAKEUP_PIN(PIN) ((PIN) == PWR_WAKEUP_PIN1)
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346 #endif /* STM32F446xx */
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347 /**
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348 * @}
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349 */
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350
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351 /**
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352 * @}
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353 */
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354
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355 /**
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356 * @}
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357 */
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358
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359 /**
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360 * @}
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361 */
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362
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363 #ifdef __cplusplus
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364 }
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365 #endif
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366
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367
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368 #endif /* __STM32F4xx_HAL_PWR_EX_H */
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369
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370 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/