annotate OtherSources/system_stm32f4xx.c @ 901:e4e9acfde839 Evo_2_23

Bugfix simulator/planer: For deco calculation two structures are used. The calculation structure and the input structure. During simulation fast forward (+5min) the input structure is manipulated. Especially for vpm calculation it could happen that the input structure was manipulated and then overwritten by the calculation structure => deco and tts may have wrong values. To avoid this thedeco calculation status is now checked before doing the FF manupulation. Based an calculation state deco or input structures are manipulated. Surface time stamp in planer view: The planer used its own (buggy) implementation for calculation of tts. The timestamp for the surface arrival did not match the bottom time + TTS. The new implementation uses the tts calculated by the deco loop for generation of surface time stamp.
author Ideenmodellierer
date Wed, 02 Oct 2024 22:07:13 +0200
parents 4e10a3e087a1
children
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1 /**
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2 ******************************************************************************
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3 * @file system_stm32f4xx.c
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4 * @author MCD Application Team
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5 * @version V2.1.0
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6 * @date 19-June-2014
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7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
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8 *
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9 * This file provides two functions and one global variable to be called from
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10 * user application:
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11 * - SystemInit(): This function is called at startup just after reset and
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12 * before branch to main program. This call is made inside
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13 * the "startup_stm32f4xx.s" file.
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14 *
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15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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16 * by the user application to setup the SysTick
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17 * timer or configure other parameters.
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18 *
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19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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20 * be called whenever the core clock is changed
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21 * during program execution.
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22 *
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23 *
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24 ******************************************************************************
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25 * @attention
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26 *
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27 * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
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28 *
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29 * Redistribution and use in source and binary forms, with or without modification,
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30 * are permitted provided that the following conditions are met:
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31 * 1. Redistributions of source code must retain the above copyright notice,
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32 * this list of conditions and the following disclaimer.
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33 * 2. Redistributions in binary form must reproduce the above copyright notice,
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34 * this list of conditions and the following disclaimer in the documentation
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35 * and/or other materials provided with the distribution.
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36 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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37 * may be used to endorse or promote products derived from this software
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38 * without specific prior written permission.
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39 *
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40 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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41 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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43 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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46 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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47 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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48 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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49 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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50 *
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51 ******************************************************************************
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52 */
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53
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54 /** @addtogroup CMSIS
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55 * @{
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56 */
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57
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58 /** @addtogroup stm32f4xx_system
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59 * @{
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60 */
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61
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62 /** @addtogroup STM32F4xx_System_Private_Includes
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63 * @{
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64 */
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65
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66
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67 #include "stm32f4xx.h"
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68
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69 #if !defined (HSE_VALUE)
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70 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
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71 #endif /* HSE_VALUE */
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72
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73 #if !defined (HSI_VALUE)
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74 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
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75 #endif /* HSI_VALUE */
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76
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77
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78 const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
7
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79 /**
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80 * @}
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81 */
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82
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83 /** @addtogroup STM32F4xx_System_Private_TypesDefinitions
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84 * @{
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85 */
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86
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87 /**
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88 * @}
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89 */
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90
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91 /** @addtogroup STM32F4xx_System_Private_Defines
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92 * @{
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93 */
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94
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95 /************************* Miscellaneous Configuration ************************/
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96 /*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
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97 on STM324xG_EVAL/STM324x9I_EVAL boards as data memory */
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98 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
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99 /* #define DATA_IN_ExtSRAM */
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100 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
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101
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102 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
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103 /* #define DATA_IN_ExtSDRAM */
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104 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
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105
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106 #if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
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107 #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM "
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108 #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
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109
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110 /*!< Uncomment the following line if you need to relocate your vector Table in
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111 Internal SRAM. */
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112 /* #define VECT_TAB_SRAM */
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113 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
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114 This value must be a multiple of 0x200. */
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115 /******************************************************************************/
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116
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117 /**
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118 * @}
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119 */
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120
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121 /** @addtogroup STM32F4xx_System_Private_Macros
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122 * @{
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123 */
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124
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125 /**
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126 * @}
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127 */
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128
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129 /** @addtogroup STM32F4xx_System_Private_Variables
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130 * @{
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131 */
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132 /* This variable is updated in three ways:
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133 1) by calling CMSIS function SystemCoreClockUpdate()
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134 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
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135 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
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136 Note: If you use this function to configure the system clock; then there
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137 is no need to call the 2 first functions listed above, since SystemCoreClock
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138 variable is updated automatically.
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139 */
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140 uint32_t SystemCoreClock = 16000000;
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141 __IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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142
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143 /**
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144 * @}
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145 */
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146
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147 /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
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148 * @{
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149 */
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150
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151 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
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152 static void SystemInit_ExtMemCtl(void);
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153 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
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154
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155 /**
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156 * @}
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157 */
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158
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159 /** @addtogroup STM32F4xx_System_Private_Functions
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160 * @{
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161 */
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162
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163 /**
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164 * @brief Setup the microcontroller system
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165 * Initialize the FPU setting, vector table location and External memory
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166 * configuration.
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167 * @param None
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168 * @retval None
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169 */
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170 void SystemInit(void)
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171 {
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172 /* FPU settings ------------------------------------------------------------*/
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173 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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174 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
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175 #endif
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176 /* Reset the RCC clock configuration to the default reset state ------------*/
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177 /* Set HSION bit */
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178 RCC->CR |= (uint32_t)0x00000001;
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179
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180 /* Reset CFGR register */
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181 RCC->CFGR = 0x00000000;
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182
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183 /* Reset HSEON, CSSON and PLLON bits */
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184 RCC->CR &= (uint32_t)0xFEF6FFFF;
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185
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186 /* Reset PLLCFGR register */
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187 RCC->PLLCFGR = 0x24003010;
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188
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189 /* Reset HSEBYP bit */
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190 RCC->CR &= (uint32_t)0xFFFBFFFF;
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191
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192 /* Disable all interrupts */
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193 RCC->CIR = 0x00000000;
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194
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195 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
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196 SystemInit_ExtMemCtl();
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197 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
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198
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199 /* Configure the Vector Table location add offset address ------------------*/
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200 #ifdef VECT_TAB_SRAM
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201 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
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202 #else
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203 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
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204 #endif
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205 }
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206
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207 /**
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208 * @brief Update SystemCoreClock variable according to Clock Register Values.
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209 * The SystemCoreClock variable contains the core clock (HCLK), it can
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210 * be used by the user application to setup the SysTick timer or configure
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211 * other parameters.
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212 *
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213 * @note Each time the core clock (HCLK) changes, this function must be called
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214 * to update SystemCoreClock variable value. Otherwise, any configuration
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215 * based on this variable will be incorrect.
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216 *
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217 * @note - The system frequency computed by this function is not the real
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218 * frequency in the chip. It is calculated based on the predefined
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219 * constant and the selected clock source:
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220 *
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221 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
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222 *
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223 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
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224 *
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225 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
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226 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
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227 *
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228 * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
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229 * 16 MHz) but the real value may vary depending on the variations
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230 * in voltage and temperature.
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231 *
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232 * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
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233 * depends on the application requirements), user has to ensure that HSE_VALUE
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234 * is same as the real frequency of the crystal used. Otherwise, this function
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235 * may have wrong result.
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236 *
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237 * - The result of this function could be not correct when using fractional
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238 * value for HSE crystal.
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239 *
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240 * @param None
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241 * @retval None
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242 */
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243 void SystemCoreClockUpdate(void)
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244 {
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245 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
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246
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247 /* Get SYSCLK source -------------------------------------------------------*/
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248 tmp = RCC->CFGR & RCC_CFGR_SWS;
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249
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250 switch (tmp)
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251 {
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252 case 0x00: /* HSI used as system clock source */
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253 SystemCoreClock = HSI_VALUE;
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254 break;
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255 case 0x04: /* HSE used as system clock source */
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256 SystemCoreClock = HSE_VALUE;
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257 break;
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258 case 0x08: /* PLL used as system clock source */
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259
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260 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
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261 SYSCLK = PLL_VCO / PLL_P
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262 */
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263 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
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264 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
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265
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266 if (pllsource != 0)
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267 {
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268 /* HSE used as PLL clock source */
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269 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
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270 }
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271 else
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272 {
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273 /* HSI used as PLL clock source */
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274 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
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275 }
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276
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277 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
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278 SystemCoreClock = pllvco/pllp;
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279 break;
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280 default:
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281 SystemCoreClock = HSI_VALUE;
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282 break;
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283 }
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284 /* Compute HCLK frequency --------------------------------------------------*/
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285 /* Get HCLK prescaler */
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286 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
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287 /* HCLK frequency */
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288 SystemCoreClock >>= tmp;
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289 }
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290
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291 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
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292 /**
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293 * @brief Setup the external memory controller.
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294 * Called in startup_stm32f4xx.s before jump to main.
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295 * This function configures the external memories (SRAM/SDRAM)
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296 * This SRAM/SDRAM will be used as program data memory (including heap and stack).
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297 * @param None
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298 * @retval None
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299 */
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300 void SystemInit_ExtMemCtl(void)
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301 {
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302 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
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303 #if defined (DATA_IN_ExtSDRAM)
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304 register uint32_t tmpreg = 0, timeout = 0xFFFF;
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305 register uint32_t index;
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306
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307 /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
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308 clock */
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309 RCC->AHB1ENR |= 0x000001F8;
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310
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311 /* Connect PDx pins to FMC Alternate function */
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312 GPIOD->AFR[0] = 0x000000CC;
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313 GPIOD->AFR[1] = 0xCC000CCC;
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314 /* Configure PDx pins in Alternate function mode */
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315 GPIOD->MODER = 0xA02A000A;
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316 /* Configure PDx pins speed to 50 MHz */
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317 GPIOD->OSPEEDR = 0xA02A000A;
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318 /* Configure PDx pins Output type to push-pull */
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319 GPIOD->OTYPER = 0x00000000;
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320 /* No pull-up, pull-down for PDx pins */
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321 GPIOD->PUPDR = 0x00000000;
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322
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323 /* Connect PEx pins to FMC Alternate function */
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324 GPIOE->AFR[0] = 0xC00000CC;
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325 GPIOE->AFR[1] = 0xCCCCCCCC;
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326 /* Configure PEx pins in Alternate function mode */
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327 GPIOE->MODER = 0xAAAA800A;
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328 /* Configure PEx pins speed to 50 MHz */
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329 GPIOE->OSPEEDR = 0xAAAA800A;
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330 /* Configure PEx pins Output type to push-pull */
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331 GPIOE->OTYPER = 0x00000000;
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332 /* No pull-up, pull-down for PEx pins */
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333 GPIOE->PUPDR = 0x00000000;
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334
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335 /* Connect PFx pins to FMC Alternate function */
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336 GPIOF->AFR[0] = 0xCCCCCCCC;
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337 GPIOF->AFR[1] = 0xCCCCCCCC;
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338 /* Configure PFx pins in Alternate function mode */
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339 GPIOF->MODER = 0xAA800AAA;
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340 /* Configure PFx pins speed to 50 MHz */
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341 GPIOF->OSPEEDR = 0xAA800AAA;
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342 /* Configure PFx pins Output type to push-pull */
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343 GPIOF->OTYPER = 0x00000000;
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344 /* No pull-up, pull-down for PFx pins */
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345 GPIOF->PUPDR = 0x00000000;
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346
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diff changeset
347 /* Connect PGx pins to FMC Alternate function */
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jDG
parents:
diff changeset
348 GPIOG->AFR[0] = 0xCCCCCCCC;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
349 GPIOG->AFR[1] = 0xCCCCCCCC;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
350 /* Configure PGx pins in Alternate function mode */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
351 GPIOG->MODER = 0xAAAAAAAA;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
352 /* Configure PGx pins speed to 50 MHz */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
353 GPIOG->OSPEEDR = 0xAAAAAAAA;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
354 /* Configure PGx pins Output type to push-pull */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
355 GPIOG->OTYPER = 0x00000000;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
356 /* No pull-up, pull-down for PGx pins */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
357 GPIOG->PUPDR = 0x00000000;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
358
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
359 /* Connect PHx pins to FMC Alternate function */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
360 GPIOH->AFR[0] = 0x00C0CC00;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
361 GPIOH->AFR[1] = 0xCCCCCCCC;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
362 /* Configure PHx pins in Alternate function mode */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
363 GPIOH->MODER = 0xAAAA08A0;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
364 /* Configure PHx pins speed to 50 MHz */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
365 GPIOH->OSPEEDR = 0xAAAA08A0;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
366 /* Configure PHx pins Output type to push-pull */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
367 GPIOH->OTYPER = 0x00000000;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
368 /* No pull-up, pull-down for PHx pins */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
369 GPIOH->PUPDR = 0x00000000;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
370
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
371 /* Connect PIx pins to FMC Alternate function */
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jDG
parents:
diff changeset
372 GPIOI->AFR[0] = 0xCCCCCCCC;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
373 GPIOI->AFR[1] = 0x00000CC0;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
374 /* Configure PIx pins in Alternate function mode */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
375 GPIOI->MODER = 0x0028AAAA;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
376 /* Configure PIx pins speed to 50 MHz */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
377 GPIOI->OSPEEDR = 0x0028AAAA;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
378 /* Configure PIx pins Output type to push-pull */
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jDG
parents:
diff changeset
379 GPIOI->OTYPER = 0x00000000;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
380 /* No pull-up, pull-down for PIx pins */
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jDG
parents:
diff changeset
381 GPIOI->PUPDR = 0x00000000;
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jDG
parents:
diff changeset
382
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jDG
parents:
diff changeset
383 /*-- FMC Configuration ------------------------------------------------------*/
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jDG
parents:
diff changeset
384 /* Enable the FMC interface clock */
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jDG
parents:
diff changeset
385 RCC->AHB3ENR |= 0x00000001;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
386
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
387 /* Configure and enable SDRAM bank1 */
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jDG
parents:
diff changeset
388 FMC_Bank5_6->SDCR[0] = 0x000019E0;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
389 FMC_Bank5_6->SDTR[0] = 0x01115351;
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jDG
parents:
diff changeset
390
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
391 /* SDRAM initialization sequence */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
392 /* Clock enable command */
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jDG
parents:
diff changeset
393 FMC_Bank5_6->SDCMR = 0x00000011;
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jDG
parents:
diff changeset
394 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
395 while((tmpreg != 0) && (timeout-- > 0))
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
396 {
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
397 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
398 }
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jDG
parents:
diff changeset
399
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
400 /* Delay */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
401 for (index = 0; index<1000; index++);
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jDG
parents:
diff changeset
402
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
403 /* PALL command */
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jDG
parents:
diff changeset
404 FMC_Bank5_6->SDCMR = 0x00000012;
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jDG
parents:
diff changeset
405 timeout = 0xFFFF;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
406 while((tmpreg != 0) && (timeout-- > 0))
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
407 {
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
408 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
409 }
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jDG
parents:
diff changeset
410
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
411 /* Auto refresh command */
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jDG
parents:
diff changeset
412 FMC_Bank5_6->SDCMR = 0x00000073;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
413 timeout = 0xFFFF;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
414 while((tmpreg != 0) && (timeout-- > 0))
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
415 {
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
416 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
417 }
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jDG
parents:
diff changeset
418
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
419 /* MRD register program */
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jDG
parents:
diff changeset
420 FMC_Bank5_6->SDCMR = 0x00046014;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
421 timeout = 0xFFFF;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
422 while((tmpreg != 0) && (timeout-- > 0))
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
423 {
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
424 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
425 }
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
426
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
427 /* Set refresh count */
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jDG
parents:
diff changeset
428 tmpreg = FMC_Bank5_6->SDRTR;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
429 FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
430
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
431 /* Disable write protection */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
432 tmpreg = FMC_Bank5_6->SDCR[0];
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
433 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
434 #endif /* DATA_IN_ExtSDRAM */
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jDG
parents:
diff changeset
435 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
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jDG
parents:
diff changeset
436
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
437 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
438 #if defined(DATA_IN_ExtSRAM)
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jDG
parents:
diff changeset
439 /*-- GPIOs Configuration -----------------------------------------------------*/
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
440 /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
441 RCC->AHB1ENR |= 0x00000078;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
442
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
443 /* Connect PDx pins to FMC Alternate function */
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jDG
parents:
diff changeset
444 GPIOD->AFR[0] = 0x00CCC0CC;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
445 GPIOD->AFR[1] = 0xCCCCCCCC;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
446 /* Configure PDx pins in Alternate function mode */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
447 GPIOD->MODER = 0xAAAA0A8A;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
448 /* Configure PDx pins speed to 100 MHz */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
449 GPIOD->OSPEEDR = 0xFFFF0FCF;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
450 /* Configure PDx pins Output type to push-pull */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
451 GPIOD->OTYPER = 0x00000000;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
452 /* No pull-up, pull-down for PDx pins */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
453 GPIOD->PUPDR = 0x00000000;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
454
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
455 /* Connect PEx pins to FMC Alternate function */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
456 GPIOE->AFR[0] = 0xC00CC0CC;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
457 GPIOE->AFR[1] = 0xCCCCCCCC;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
458 /* Configure PEx pins in Alternate function mode */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
459 GPIOE->MODER = 0xAAAA828A;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
460 /* Configure PEx pins speed to 100 MHz */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
461 GPIOE->OSPEEDR = 0xFFFFC3CF;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
462 /* Configure PEx pins Output type to push-pull */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
463 GPIOE->OTYPER = 0x00000000;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
464 /* No pull-up, pull-down for PEx pins */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
465 GPIOE->PUPDR = 0x00000000;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
466
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
467 /* Connect PFx pins to FMC Alternate function */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
468 GPIOF->AFR[0] = 0x00CCCCCC;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
469 GPIOF->AFR[1] = 0xCCCC0000;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
470 /* Configure PFx pins in Alternate function mode */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
471 GPIOF->MODER = 0xAA000AAA;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
472 /* Configure PFx pins speed to 100 MHz */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
473 GPIOF->OSPEEDR = 0xFF000FFF;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
474 /* Configure PFx pins Output type to push-pull */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
475 GPIOF->OTYPER = 0x00000000;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
476 /* No pull-up, pull-down for PFx pins */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
477 GPIOF->PUPDR = 0x00000000;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
478
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
479 /* Connect PGx pins to FMC Alternate function */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
480 GPIOG->AFR[0] = 0x00CCCCCC;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
481 GPIOG->AFR[1] = 0x000000C0;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
482 /* Configure PGx pins in Alternate function mode */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
483 GPIOG->MODER = 0x00085AAA;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
484 /* Configure PGx pins speed to 100 MHz */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
485 GPIOG->OSPEEDR = 0x000CAFFF;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
486 /* Configure PGx pins Output type to push-pull */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
487 GPIOG->OTYPER = 0x00000000;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
488 /* No pull-up, pull-down for PGx pins */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
489 GPIOG->PUPDR = 0x00000000;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
490
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
491 /*-- FMC/FSMC Configuration --------------------------------------------------*/
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
492 /* Enable the FMC/FSMC interface clock */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
493 RCC->AHB3ENR |= 0x00000001;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
494
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
495 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
496 /* Configure and enable Bank1_SRAM2 */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
497 FMC_Bank1->BTCR[2] = 0x00001011;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
498 FMC_Bank1->BTCR[3] = 0x00000201;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
499 FMC_Bank1E->BWTR[2] = 0x0fffffff;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
500 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
501
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
502 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
503 /* Configure and enable Bank1_SRAM2 */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
504 FSMC_Bank1->BTCR[2] = 0x00001011;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
505 FSMC_Bank1->BTCR[3] = 0x00000201;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
506 FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
507 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
508
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
509 #endif /* DATA_IN_ExtSRAM */
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jDG
parents:
diff changeset
510 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
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jDG
parents:
diff changeset
511 }
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jDG
parents:
diff changeset
512 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
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jDG
parents:
diff changeset
513 /**
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
514 * @}
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
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515 */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
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516
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
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517 /**
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
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518 * @}
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
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519 */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
520
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
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521 /**
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
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522 * @}
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
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523 */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
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524 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/