Mercurial > public > ostc4
annotate Common/Drivers/CMSIS/Include/core_cm0.h @ 311:ddbe8bed5096 cleanup-4
bugfix: make stopwatch and divetime run in sync
And this shows the fundamental issue in the difference between dive time and
stopwatch time. The dive time is constructed on the RTE, and rather
independently, the stopwatch time is constructed on CPU1.
This works rather well, but not perfect. This commit fixes things in
a relatively straightforward way. Instead of incrementing the stopwatch
locally on CPU1, simply use the same time data that is coming from the
RTE. Some logic was added to make this stopwatch resettable again.
Signed-off-by: Jan Mulder <jlmulder@xs4all.nl>
author | Jan Mulder <jlmulder@xs4all.nl> |
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date | Wed, 29 May 2019 14:02:27 +0200 |
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rev | line source |
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128
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1 /**************************************************************************//** |
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2 * @file core_cm0.h |
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3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File |
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4 * @version V4.30 |
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5 * @date 20. October 2015 |
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6 ******************************************************************************/ |
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7 /* Copyright (c) 2009 - 2015 ARM LIMITED |
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8 |
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9 All rights reserved. |
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10 Redistribution and use in source and binary forms, with or without |
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11 modification, are permitted provided that the following conditions are met: |
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12 - Redistributions of source code must retain the above copyright |
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13 notice, this list of conditions and the following disclaimer. |
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14 - Redistributions in binary form must reproduce the above copyright |
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15 notice, this list of conditions and the following disclaimer in the |
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16 documentation and/or other materials provided with the distribution. |
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17 - Neither the name of ARM nor the names of its contributors may be used |
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18 to endorse or promote products derived from this software without |
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19 specific prior written permission. |
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20 * |
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21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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24 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
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25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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31 POSSIBILITY OF SUCH DAMAGE. |
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32 ---------------------------------------------------------------------------*/ |
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33 |
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34 |
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35 #if defined ( __ICCARM__ ) |
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36 #pragma system_include /* treat file as system include file for MISRA check */ |
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37 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
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38 #pragma clang system_header /* treat file as system include file */ |
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39 #endif |
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40 |
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41 #ifndef __CORE_CM0_H_GENERIC |
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42 #define __CORE_CM0_H_GENERIC |
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43 |
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44 #include <stdint.h> |
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45 |
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46 #ifdef __cplusplus |
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47 extern "C" { |
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48 #endif |
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49 |
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50 /** |
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51 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions |
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52 CMSIS violates the following MISRA-C:2004 rules: |
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53 |
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54 \li Required Rule 8.5, object/function definition in header file.<br> |
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55 Function definitions in header files are used to allow 'inlining'. |
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56 |
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57 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> |
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58 Unions are used for effective representation of core registers. |
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59 |
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60 \li Advisory Rule 19.7, Function-like macro defined.<br> |
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61 Function-like macros are used to allow more efficient code. |
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62 */ |
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63 |
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64 |
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65 /******************************************************************************* |
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66 * CMSIS definitions |
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67 ******************************************************************************/ |
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68 /** |
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69 \ingroup Cortex_M0 |
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70 @{ |
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71 */ |
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72 |
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73 /* CMSIS CM0 definitions */ |
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74 #define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ |
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75 #define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ |
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76 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ |
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77 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ |
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78 |
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79 #define __CORTEX_M (0x00U) /*!< Cortex-M Core */ |
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80 |
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81 |
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82 #if defined ( __CC_ARM ) |
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83 #define __ASM __asm /*!< asm keyword for ARM Compiler */ |
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84 #define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
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85 #define __STATIC_INLINE static __inline |
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86 |
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87 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
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88 #define __ASM __asm /*!< asm keyword for ARM Compiler */ |
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89 #define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
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90 #define __STATIC_INLINE static __inline |
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91 |
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92 #elif defined ( __GNUC__ ) |
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93 #define __ASM __asm /*!< asm keyword for GNU Compiler */ |
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94 #define __INLINE inline /*!< inline keyword for GNU Compiler */ |
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95 #define __STATIC_INLINE static inline |
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96 |
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97 #elif defined ( __ICCARM__ ) |
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98 #define __ASM __asm /*!< asm keyword for IAR Compiler */ |
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99 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ |
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100 #define __STATIC_INLINE static inline |
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101 |
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102 #elif defined ( __TMS470__ ) |
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103 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ |
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104 #define __STATIC_INLINE static inline |
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105 |
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106 #elif defined ( __TASKING__ ) |
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107 #define __ASM __asm /*!< asm keyword for TASKING Compiler */ |
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108 #define __INLINE inline /*!< inline keyword for TASKING Compiler */ |
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109 #define __STATIC_INLINE static inline |
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110 |
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111 #elif defined ( __CSMC__ ) |
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112 #define __packed |
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113 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ |
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114 #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ |
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115 #define __STATIC_INLINE static inline |
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116 |
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117 #else |
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118 #error Unknown compiler |
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119 #endif |
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120 |
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121 /** __FPU_USED indicates whether an FPU is used or not. |
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122 This core does not support an FPU at all |
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123 */ |
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124 #define __FPU_USED 0U |
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125 |
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126 #if defined ( __CC_ARM ) |
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127 #if defined __TARGET_FPU_VFP |
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128 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
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129 #endif |
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130 |
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131 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
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132 #if defined __ARM_PCS_VFP |
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133 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
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134 #endif |
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135 |
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136 #elif defined ( __GNUC__ ) |
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137 #if defined (__VFP_FP__) && !defined(__SOFTFP__) |
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138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
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139 #endif |
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140 |
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141 #elif defined ( __ICCARM__ ) |
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142 #if defined __ARMVFP__ |
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143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
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144 #endif |
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145 |
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146 #elif defined ( __TMS470__ ) |
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147 #if defined __TI_VFP_SUPPORT__ |
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148 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
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149 #endif |
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150 |
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151 #elif defined ( __TASKING__ ) |
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152 #if defined __FPU_VFP__ |
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153 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
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154 #endif |
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155 |
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156 #elif defined ( __CSMC__ ) |
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157 #if ( __CSMC__ & 0x400U) |
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158 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
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159 #endif |
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160 |
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161 #endif |
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162 |
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163 #include "core_cmInstr.h" /* Core Instruction Access */ |
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164 #include "core_cmFunc.h" /* Core Function Access */ |
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165 |
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166 #ifdef __cplusplus |
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167 } |
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168 #endif |
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169 |
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170 #endif /* __CORE_CM0_H_GENERIC */ |
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171 |
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172 #ifndef __CMSIS_GENERIC |
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173 |
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174 #ifndef __CORE_CM0_H_DEPENDANT |
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175 #define __CORE_CM0_H_DEPENDANT |
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176 |
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177 #ifdef __cplusplus |
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178 extern "C" { |
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179 #endif |
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180 |
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181 /* check device defines and use defaults */ |
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182 #if defined __CHECK_DEVICE_DEFINES |
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183 #ifndef __CM0_REV |
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184 #define __CM0_REV 0x0000U |
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185 #warning "__CM0_REV not defined in device header file; using default!" |
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186 #endif |
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187 |
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188 #ifndef __NVIC_PRIO_BITS |
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189 #define __NVIC_PRIO_BITS 2U |
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190 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" |
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191 #endif |
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192 |
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193 #ifndef __Vendor_SysTickConfig |
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194 #define __Vendor_SysTickConfig 0U |
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195 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" |
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196 #endif |
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197 #endif |
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198 |
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199 /* IO definitions (access restrictions to peripheral registers) */ |
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200 /** |
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201 \defgroup CMSIS_glob_defs CMSIS Global Defines |
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202 |
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203 <strong>IO Type Qualifiers</strong> are used |
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204 \li to specify the access to peripheral variables. |
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205 \li for automatic generation of peripheral register debug information. |
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206 */ |
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207 #ifdef __cplusplus |
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208 #define __I volatile /*!< Defines 'read only' permissions */ |
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209 #else |
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210 #define __I volatile const /*!< Defines 'read only' permissions */ |
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211 #endif |
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212 #define __O volatile /*!< Defines 'write only' permissions */ |
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213 #define __IO volatile /*!< Defines 'read / write' permissions */ |
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214 |
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215 /* following defines should be used for structure members */ |
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216 #define __IM volatile const /*! Defines 'read only' structure member permissions */ |
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217 #define __OM volatile /*! Defines 'write only' structure member permissions */ |
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218 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ |
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219 |
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220 /*@} end of group Cortex_M0 */ |
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221 |
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222 |
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223 |
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224 /******************************************************************************* |
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225 * Register Abstraction |
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226 Core Register contain: |
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227 - Core Register |
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228 - Core NVIC Register |
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229 - Core SCB Register |
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230 - Core SysTick Register |
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231 ******************************************************************************/ |
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232 /** |
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233 \defgroup CMSIS_core_register Defines and Type Definitions |
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234 \brief Type definitions and defines for Cortex-M processor based devices. |
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235 */ |
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236 |
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237 /** |
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238 \ingroup CMSIS_core_register |
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239 \defgroup CMSIS_CORE Status and Control Registers |
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240 \brief Core Register type definitions. |
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241 @{ |
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242 */ |
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243 |
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244 /** |
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245 \brief Union type to access the Application Program Status Register (APSR). |
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246 */ |
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247 typedef union |
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248 { |
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249 struct |
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250 { |
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251 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ |
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252 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
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253 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
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254 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
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255 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
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256 } b; /*!< Structure used for bit access */ |
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257 uint32_t w; /*!< Type used for word access */ |
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258 } APSR_Type; |
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259 |
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260 /* APSR Register Definitions */ |
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261 #define APSR_N_Pos 31U /*!< APSR: N Position */ |
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262 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ |
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263 |
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264 #define APSR_Z_Pos 30U /*!< APSR: Z Position */ |
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265 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ |
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266 |
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267 #define APSR_C_Pos 29U /*!< APSR: C Position */ |
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268 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ |
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269 |
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270 #define APSR_V_Pos 28U /*!< APSR: V Position */ |
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271 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ |
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272 |
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273 |
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274 /** |
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275 \brief Union type to access the Interrupt Program Status Register (IPSR). |
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276 */ |
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277 typedef union |
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278 { |
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279 struct |
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280 { |
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281 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
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282 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ |
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283 } b; /*!< Structure used for bit access */ |
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284 uint32_t w; /*!< Type used for word access */ |
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285 } IPSR_Type; |
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286 |
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287 /* IPSR Register Definitions */ |
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288 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ |
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289 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ |
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290 |
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291 |
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292 /** |
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293 \brief Union type to access the Special-Purpose Program Status Registers (xPSR). |
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294 */ |
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295 typedef union |
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296 { |
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297 struct |
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298 { |
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299 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
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300 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ |
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301 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ |
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302 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ |
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303 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
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304 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
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305 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
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306 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
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307 } b; /*!< Structure used for bit access */ |
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308 uint32_t w; /*!< Type used for word access */ |
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309 } xPSR_Type; |
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310 |
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311 /* xPSR Register Definitions */ |
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312 #define xPSR_N_Pos 31U /*!< xPSR: N Position */ |
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313 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ |
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314 |
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315 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ |
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316 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ |
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317 |
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318 #define xPSR_C_Pos 29U /*!< xPSR: C Position */ |
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319 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ |
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320 |
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321 #define xPSR_V_Pos 28U /*!< xPSR: V Position */ |
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322 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ |
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323 |
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324 #define xPSR_T_Pos 24U /*!< xPSR: T Position */ |
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325 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ |
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326 |
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327 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ |
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328 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ |
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329 |
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330 |
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331 /** |
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332 \brief Union type to access the Control Registers (CONTROL). |
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333 */ |
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334 typedef union |
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335 { |
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336 struct |
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337 { |
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338 uint32_t _reserved0:1; /*!< bit: 0 Reserved */ |
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339 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ |
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340 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ |
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341 } b; /*!< Structure used for bit access */ |
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342 uint32_t w; /*!< Type used for word access */ |
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343 } CONTROL_Type; |
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344 |
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345 /* CONTROL Register Definitions */ |
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346 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ |
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347 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ |
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348 |
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349 /*@} end of group CMSIS_CORE */ |
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350 |
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351 |
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352 /** |
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353 \ingroup CMSIS_core_register |
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354 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) |
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355 \brief Type definitions for the NVIC Registers |
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356 @{ |
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357 */ |
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358 |
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359 /** |
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360 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). |
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361 */ |
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362 typedef struct |
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363 { |
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364 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ |
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365 uint32_t RESERVED0[31U]; |
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366 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ |
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367 uint32_t RSERVED1[31U]; |
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368 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ |
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369 uint32_t RESERVED2[31U]; |
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370 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ |
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371 uint32_t RESERVED3[31U]; |
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372 uint32_t RESERVED4[64U]; |
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373 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ |
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374 } NVIC_Type; |
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375 |
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376 /*@} end of group CMSIS_NVIC */ |
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377 |
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378 |
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379 /** |
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380 \ingroup CMSIS_core_register |
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381 \defgroup CMSIS_SCB System Control Block (SCB) |
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382 \brief Type definitions for the System Control Block Registers |
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383 @{ |
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384 */ |
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385 |
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386 /** |
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387 \brief Structure type to access the System Control Block (SCB). |
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388 */ |
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389 typedef struct |
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390 { |
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391 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ |
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392 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ |
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393 uint32_t RESERVED0; |
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394 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ |
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395 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ |
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396 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ |
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397 uint32_t RESERVED1; |
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398 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ |
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399 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ |
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400 } SCB_Type; |
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401 |
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402 /* SCB CPUID Register Definitions */ |
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403 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ |
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404 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ |
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405 |
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406 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ |
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407 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ |
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408 |
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409 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ |
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410 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ |
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411 |
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412 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ |
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413 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ |
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414 |
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415 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ |
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416 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ |
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417 |
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418 /* SCB Interrupt Control State Register Definitions */ |
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419 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ |
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420 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ |
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421 |
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422 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ |
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423 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ |
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424 |
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425 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ |
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426 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ |
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427 |
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428 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ |
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429 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ |
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430 |
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431 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ |
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432 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ |
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433 |
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434 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ |
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435 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ |
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436 |
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437 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ |
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438 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ |
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439 |
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440 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ |
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441 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ |
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442 |
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443 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ |
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444 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ |
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445 |
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446 /* SCB Application Interrupt and Reset Control Register Definitions */ |
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447 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ |
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448 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ |
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449 |
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450 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ |
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451 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ |
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452 |
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453 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ |
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454 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ |
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455 |
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456 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ |
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457 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ |
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458 |
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459 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ |
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460 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ |
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461 |
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462 /* SCB System Control Register Definitions */ |
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463 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ |
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464 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ |
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465 |
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466 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ |
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467 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ |
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468 |
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469 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ |
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470 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ |
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471 |
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472 /* SCB Configuration Control Register Definitions */ |
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473 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ |
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474 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ |
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475 |
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476 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ |
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477 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ |
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478 |
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479 /* SCB System Handler Control and State Register Definitions */ |
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480 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ |
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481 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ |
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482 |
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483 /*@} end of group CMSIS_SCB */ |
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484 |
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485 |
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486 /** |
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487 \ingroup CMSIS_core_register |
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488 \defgroup CMSIS_SysTick System Tick Timer (SysTick) |
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489 \brief Type definitions for the System Timer Registers. |
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490 @{ |
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491 */ |
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492 |
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493 /** |
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494 \brief Structure type to access the System Timer (SysTick). |
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495 */ |
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496 typedef struct |
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497 { |
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498 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ |
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499 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ |
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500 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ |
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501 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ |
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502 } SysTick_Type; |
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503 |
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504 /* SysTick Control / Status Register Definitions */ |
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505 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ |
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506 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ |
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507 |
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508 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ |
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509 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ |
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510 |
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511 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ |
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512 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ |
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513 |
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514 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ |
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515 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ |
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516 |
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517 /* SysTick Reload Register Definitions */ |
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518 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ |
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519 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ |
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520 |
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521 /* SysTick Current Register Definitions */ |
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522 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ |
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523 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ |
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524 |
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525 /* SysTick Calibration Register Definitions */ |
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526 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ |
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527 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ |
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528 |
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529 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ |
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530 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ |
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531 |
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532 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ |
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533 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ |
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534 |
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535 /*@} end of group CMSIS_SysTick */ |
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536 |
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537 |
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538 /** |
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539 \ingroup CMSIS_core_register |
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540 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) |
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541 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. |
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542 Therefore they are not covered by the Cortex-M0 header file. |
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543 @{ |
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544 */ |
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545 /*@} end of group CMSIS_CoreDebug */ |
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546 |
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547 |
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548 /** |
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549 \ingroup CMSIS_core_register |
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550 \defgroup CMSIS_core_bitfield Core register bit field macros |
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551 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). |
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552 @{ |
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553 */ |
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554 |
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555 /** |
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556 \brief Mask and shift a bit field value for use in a register bit range. |
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557 \param[in] field Name of the register bit field. |
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558 \param[in] value Value of the bit field. |
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559 \return Masked and shifted value. |
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560 */ |
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561 #define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) |
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562 |
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563 /** |
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564 \brief Mask and shift a register value to extract a bit filed value. |
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565 \param[in] field Name of the register bit field. |
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566 \param[in] value Value of register. |
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567 \return Masked and shifted bit field value. |
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568 */ |
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569 #define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) |
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570 |
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571 /*@} end of group CMSIS_core_bitfield */ |
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572 |
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573 |
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574 /** |
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575 \ingroup CMSIS_core_register |
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576 \defgroup CMSIS_core_base Core Definitions |
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577 \brief Definitions for base addresses, unions, and structures. |
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578 @{ |
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579 */ |
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580 |
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581 /* Memory mapping of Cortex-M0 Hardware */ |
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582 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ |
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583 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ |
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584 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ |
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585 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ |
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586 |
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587 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ |
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588 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ |
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589 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ |
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590 |
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591 |
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592 /*@} */ |
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593 |
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594 |
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595 |
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596 /******************************************************************************* |
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597 * Hardware Abstraction Layer |
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598 Core Function Interface contains: |
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599 - Core NVIC Functions |
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600 - Core SysTick Functions |
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601 - Core Register Access Functions |
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602 ******************************************************************************/ |
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603 /** |
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604 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference |
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605 */ |
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606 |
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607 |
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608 |
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609 /* ########################## NVIC functions #################################### */ |
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610 /** |
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611 \ingroup CMSIS_Core_FunctionInterface |
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612 \defgroup CMSIS_Core_NVICFunctions NVIC Functions |
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613 \brief Functions that manage interrupts and exceptions via the NVIC. |
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614 @{ |
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615 */ |
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616 |
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617 /* Interrupt Priorities are WORD accessible only under ARMv6M */ |
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618 /* The following MACROS handle generation of the register offset and byte masks */ |
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619 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) |
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620 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) |
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621 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) |
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622 |
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623 |
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624 /** |
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625 \brief Enable External Interrupt |
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626 \details Enables a device-specific interrupt in the NVIC interrupt controller. |
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627 \param [in] IRQn External interrupt number. Value cannot be negative. |
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628 */ |
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629 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) |
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630 { |
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631 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
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632 } |
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633 |
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634 |
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635 /** |
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636 \brief Disable External Interrupt |
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637 \details Disables a device-specific interrupt in the NVIC interrupt controller. |
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638 \param [in] IRQn External interrupt number. Value cannot be negative. |
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639 */ |
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640 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) |
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641 { |
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642 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
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643 } |
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644 |
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645 |
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646 /** |
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647 \brief Get Pending Interrupt |
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648 \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. |
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649 \param [in] IRQn Interrupt number. |
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650 \return 0 Interrupt status is not pending. |
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651 \return 1 Interrupt status is pending. |
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652 */ |
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653 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) |
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654 { |
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655 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
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656 } |
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657 |
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658 |
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659 /** |
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660 \brief Set Pending Interrupt |
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661 \details Sets the pending bit of an external interrupt. |
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662 \param [in] IRQn Interrupt number. Value cannot be negative. |
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663 */ |
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664 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) |
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665 { |
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666 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
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667 } |
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668 |
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669 |
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670 /** |
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671 \brief Clear Pending Interrupt |
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672 \details Clears the pending bit of an external interrupt. |
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673 \param [in] IRQn External interrupt number. Value cannot be negative. |
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674 */ |
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675 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
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676 { |
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677 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
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678 } |
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679 |
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680 |
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681 /** |
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682 \brief Set Interrupt Priority |
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683 \details Sets the priority of an interrupt. |
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684 \note The priority cannot be set for every core interrupt. |
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685 \param [in] IRQn Interrupt number. |
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686 \param [in] priority Priority to set. |
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687 */ |
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|
688 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
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689 { |
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690 if ((int32_t)(IRQn) < 0) |
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691 { |
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692 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
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693 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
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694 } |
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695 else |
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696 { |
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697 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
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698 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
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699 } |
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700 } |
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701 |
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|
702 |
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703 /** |
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704 \brief Get Interrupt Priority |
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705 \details Reads the priority of an interrupt. |
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706 The interrupt number can be positive to specify an external (device specific) interrupt, |
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707 or negative to specify an internal (core) interrupt. |
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|
708 \param [in] IRQn Interrupt number. |
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709 \return Interrupt Priority. |
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710 Value is aligned automatically to the implemented priority bits of the microcontroller. |
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711 */ |
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712 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) |
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713 { |
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714 |
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715 if ((int32_t)(IRQn) < 0) |
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716 { |
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717 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); |
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718 } |
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719 else |
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720 { |
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721 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); |
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722 } |
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723 } |
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|
724 |
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725 |
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726 /** |
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727 \brief System Reset |
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728 \details Initiates a system reset request to reset the MCU. |
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729 */ |
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730 __STATIC_INLINE void NVIC_SystemReset(void) |
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731 { |
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732 __DSB(); /* Ensure all outstanding memory accesses included |
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733 buffered write are completed before reset */ |
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734 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | |
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735 SCB_AIRCR_SYSRESETREQ_Msk); |
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736 __DSB(); /* Ensure completion of memory access */ |
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737 |
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738 for(;;) /* wait until reset */ |
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739 { |
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740 __NOP(); |
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741 } |
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742 } |
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743 |
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744 /*@} end of CMSIS_Core_NVICFunctions */ |
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745 |
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746 |
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747 |
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748 /* ################################## SysTick function ############################################ */ |
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749 /** |
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750 \ingroup CMSIS_Core_FunctionInterface |
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751 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions |
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752 \brief Functions that configure the System. |
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753 @{ |
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754 */ |
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755 |
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756 #if (__Vendor_SysTickConfig == 0U) |
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757 |
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758 /** |
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759 \brief System Tick Configuration |
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760 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. |
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761 Counter is in free running mode to generate periodic interrupts. |
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762 \param [in] ticks Number of ticks between two interrupts. |
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763 \return 0 Function succeeded. |
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764 \return 1 Function failed. |
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765 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the |
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766 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> |
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767 must contain a vendor-specific implementation of this function. |
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768 */ |
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769 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) |
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770 { |
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771 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) |
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772 { |
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773 return (1UL); /* Reload value impossible */ |
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774 } |
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775 |
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776 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ |
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777 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ |
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778 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ |
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779 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | |
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780 SysTick_CTRL_TICKINT_Msk | |
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781 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ |
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782 return (0UL); /* Function successful */ |
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783 } |
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784 |
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785 #endif |
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786 |
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787 /*@} end of CMSIS_Core_SysTickFunctions */ |
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788 |
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789 |
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790 |
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791 |
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792 #ifdef __cplusplus |
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793 } |
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794 #endif |
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795 |
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796 #endif /* __CORE_CM0_H_DEPENDANT */ |
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797 |
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798 #endif /* __CMSIS_GENERIC */ |