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annotate Common/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sram.c @ 514:d9dbfa496f7e

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Properly send compass 3 into sleepmode (end-2019 hardware)
author heinrichsweikamp
date Wed, 16 Sep 2020 10:30:28 +0200
parents c78bcbd5deda
children
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128
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1 /**
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2 ******************************************************************************
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3 * @file stm32f4xx_hal_sram.c
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4 * @author MCD Application Team
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5 * @brief SRAM HAL module driver.
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6 * This file provides a generic firmware to drive SRAM memories
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7 * mounted as external device.
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8 *
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9 @verbatim
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10 ==============================================================================
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11 ##### How to use this driver #####
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12 ==============================================================================
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13 [..]
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14 This driver is a generic layered driver which contains a set of APIs used to
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15 control SRAM memories. It uses the FMC layer functions to interface
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16 with SRAM devices.
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17 The following sequence should be followed to configure the FMC/FSMC to interface
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18 with SRAM/PSRAM memories:
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19
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20 (#) Declare a SRAM_HandleTypeDef handle structure, for example:
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21 SRAM_HandleTypeDef hsram; and:
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22
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23 (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
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24 values of the structure member.
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25
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26 (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
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27 base register instance for NOR or SRAM device
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28
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29 (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
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30 base register instance for NOR or SRAM extended mode
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31
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32 (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
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33 mode timings; for example:
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34 FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming;
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35 and fill its fields with the allowed values of the structure member.
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36
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37 (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
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38 performs the following sequence:
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39
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40 (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
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41 (##) Control register configuration using the FMC NORSRAM interface function
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42 FMC_NORSRAM_Init()
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43 (##) Timing register configuration using the FMC NORSRAM interface function
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44 FMC_NORSRAM_Timing_Init()
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45 (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
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46 FMC_NORSRAM_Extended_Timing_Init()
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47 (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
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48
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49 (#) At this stage you can perform read/write accesses from/to the memory connected
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50 to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
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51 following APIs:
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52 (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
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53 (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
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54
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55 (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
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56 HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
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57
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58 (#) You can continuously monitor the SRAM device HAL state by calling the function
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59 HAL_SRAM_GetState()
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60
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61 @endverbatim
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62 ******************************************************************************
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63 * @attention
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64 *
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65 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
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66 *
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67 * Redistribution and use in source and binary forms, with or without modification,
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68 * are permitted provided that the following conditions are met:
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69 * 1. Redistributions of source code must retain the above copyright notice,
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70 * this list of conditions and the following disclaimer.
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71 * 2. Redistributions in binary form must reproduce the above copyright notice,
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72 * this list of conditions and the following disclaimer in the documentation
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73 * and/or other materials provided with the distribution.
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74 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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75 * may be used to endorse or promote products derived from this software
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76 * without specific prior written permission.
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77 *
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78 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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79 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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80 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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81 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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82 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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83 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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84 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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85 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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86 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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87 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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88 *
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89 ******************************************************************************
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90 */
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91
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92 /* Includes ------------------------------------------------------------------*/
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93 #include "stm32f4xx_hal.h"
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94
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95 /** @addtogroup STM32F4xx_HAL_Driver
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96 * @{
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97 */
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98
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99 /** @defgroup SRAM SRAM
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100 * @brief SRAM driver modules
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101 * @{
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102 */
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103 #ifdef HAL_SRAM_MODULE_ENABLED
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104
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105 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
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106 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
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107 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
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108 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
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109
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110 /* Private typedef -----------------------------------------------------------*/
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111 /* Private define ------------------------------------------------------------*/
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112 /* Private macro -------------------------------------------------------------*/
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113 /* Private variables ---------------------------------------------------------*/
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114 /* Private functions ---------------------------------------------------------*/
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115
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116 /* Exported functions --------------------------------------------------------*/
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117 /** @defgroup SRAM_Exported_Functions SRAM Exported Functions
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118 * @{
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119 */
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120 /** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
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121 * @brief Initialization and Configuration functions
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122 *
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123 @verbatim
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124 ==============================================================================
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125 ##### SRAM Initialization and de_initialization functions #####
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126 ==============================================================================
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127 [..] This section provides functions allowing to initialize/de-initialize
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128 the SRAM memory
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129
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130 @endverbatim
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131 * @{
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132 */
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133
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134 /**
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135 * @brief Performs the SRAM device initialization sequence
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136 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
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137 * the configuration information for SRAM module.
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138 * @param Timing Pointer to SRAM control timing structure
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139 * @param ExtTiming Pointer to SRAM extended mode timing structure
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140 * @retval HAL status
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141 */
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142 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
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143 {
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144 /* Check the SRAM handle parameter */
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145 if(hsram == NULL)
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146 {
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147 return HAL_ERROR;
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148 }
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149
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150 if(hsram->State == HAL_SRAM_STATE_RESET)
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151 {
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152 /* Allocate lock resource and initialize it */
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153 hsram->Lock = HAL_UNLOCKED;
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154 /* Initialize the low level hardware (MSP) */
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155 HAL_SRAM_MspInit(hsram);
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156 }
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157
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158 /* Initialize SRAM control Interface */
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159 FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
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160
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161 /* Initialize SRAM timing Interface */
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162 FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
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163
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164 /* Initialize SRAM extended mode timing Interface */
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165 FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
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166
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167 /* Enable the NORSRAM device */
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168 __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
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169
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170 return HAL_OK;
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171 }
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172
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173 /**
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174 * @brief Performs the SRAM device De-initialization sequence.
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175 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
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176 * the configuration information for SRAM module.
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177 * @retval HAL status
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178 */
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179 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
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180 {
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181 /* De-Initialize the low level hardware (MSP) */
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182 HAL_SRAM_MspDeInit(hsram);
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183
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184 /* Configure the SRAM registers with their reset values */
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185 FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
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186
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187 hsram->State = HAL_SRAM_STATE_RESET;
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188
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189 /* Release Lock */
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190 __HAL_UNLOCK(hsram);
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191
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192 return HAL_OK;
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193 }
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194
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195 /**
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196 * @brief SRAM MSP Init.
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197 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
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198 * the configuration information for SRAM module.
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199 * @retval None
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200 */
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201 __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
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202 {
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203 /* Prevent unused argument(s) compilation warning */
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204 UNUSED(hsram);
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205 /* NOTE : This function Should not be modified, when the callback is needed,
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206 the HAL_SRAM_MspInit could be implemented in the user file
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207 */
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208 }
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209
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210 /**
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211 * @brief SRAM MSP DeInit.
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212 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
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213 * the configuration information for SRAM module.
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214 * @retval None
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215 */
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216 __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
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217 {
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218 /* Prevent unused argument(s) compilation warning */
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219 UNUSED(hsram);
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220 /* NOTE : This function Should not be modified, when the callback is needed,
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221 the HAL_SRAM_MspDeInit could be implemented in the user file
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222 */
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223 }
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224
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225 /**
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226 * @brief DMA transfer complete callback.
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227 * @param hdma pointer to a SRAM_HandleTypeDef structure that contains
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228 * the configuration information for SRAM module.
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229 * @retval None
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230 */
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231 __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
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232 {
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233 /* Prevent unused argument(s) compilation warning */
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234 UNUSED(hdma);
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235 /* NOTE : This function Should not be modified, when the callback is needed,
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236 the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
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237 */
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238 }
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239
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240 /**
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241 * @brief DMA transfer complete error callback.
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242 * @param hdma pointer to a SRAM_HandleTypeDef structure that contains
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243 * the configuration information for SRAM module.
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244 * @retval None
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245 */
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246 __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
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247 {
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248 /* Prevent unused argument(s) compilation warning */
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249 UNUSED(hdma);
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250 /* NOTE : This function Should not be modified, when the callback is needed,
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251 the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
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252 */
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253 }
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254
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255 /**
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256 * @}
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257 */
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258
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259 /** @defgroup SRAM_Exported_Functions_Group2 Input and Output functions
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260 * @brief Input Output and memory control functions
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261 *
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262 @verbatim
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263 ==============================================================================
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264 ##### SRAM Input and Output functions #####
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265 ==============================================================================
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266 [..]
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267 This section provides functions allowing to use and control the SRAM memory
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268
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269 @endverbatim
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270 * @{
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271 */
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272
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273 /**
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274 * @brief Reads 8-bit buffer from SRAM memory.
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275 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
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276 * the configuration information for SRAM module.
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277 * @param pAddress Pointer to read start address
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278 * @param pDstBuffer Pointer to destination buffer
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279 * @param BufferSize Size of the buffer to read from memory
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280 * @retval HAL status
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281 */
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282 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
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283 {
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284 __IO uint8_t * pSramAddress = (uint8_t *)pAddress;
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285
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286 /* Process Locked */
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287 __HAL_LOCK(hsram);
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288
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289 /* Update the SRAM controller state */
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290 hsram->State = HAL_SRAM_STATE_BUSY;
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291
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292 /* Read data from memory */
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293 for(; BufferSize != 0U; BufferSize--)
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294 {
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295 *pDstBuffer = *(__IO uint8_t *)pSramAddress;
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296 pDstBuffer++;
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297 pSramAddress++;
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298 }
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299
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300 /* Update the SRAM controller state */
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301 hsram->State = HAL_SRAM_STATE_READY;
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302
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303 /* Process unlocked */
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304 __HAL_UNLOCK(hsram);
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305
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306 return HAL_OK;
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307 }
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308
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309 /**
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310 * @brief Writes 8-bit buffer to SRAM memory.
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311 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
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312 * the configuration information for SRAM module.
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313 * @param pAddress Pointer to write start address
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314 * @param pSrcBuffer Pointer to source buffer to write
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315 * @param BufferSize Size of the buffer to write to memory
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316 * @retval HAL status
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317 */
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318 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
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319 {
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320 __IO uint8_t * pSramAddress = (uint8_t *)pAddress;
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321
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322 /* Check the SRAM controller state */
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323 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
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324 {
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325 return HAL_ERROR;
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326 }
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327
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328 /* Process Locked */
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329 __HAL_LOCK(hsram);
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330
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331 /* Update the SRAM controller state */
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332 hsram->State = HAL_SRAM_STATE_BUSY;
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333
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334 /* Write data to memory */
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335 for(; BufferSize != 0U; BufferSize--)
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336 {
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337 *(__IO uint8_t *)pSramAddress = *pSrcBuffer;
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338 pSrcBuffer++;
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339 pSramAddress++;
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340 }
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341
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342 /* Update the SRAM controller state */
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343 hsram->State = HAL_SRAM_STATE_READY;
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344
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345 /* Process unlocked */
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346 __HAL_UNLOCK(hsram);
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347
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348 return HAL_OK;
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349 }
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350
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351 /**
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352 * @brief Reads 16-bit buffer from SRAM memory.
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353 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
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354 * the configuration information for SRAM module.
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355 * @param pAddress Pointer to read start address
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356 * @param pDstBuffer Pointer to destination buffer
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357 * @param BufferSize Size of the buffer to read from memory
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358 * @retval HAL status
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359 */
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360 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
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361 {
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362 __IO uint16_t * pSramAddress = (uint16_t *)pAddress;
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363
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364 /* Process Locked */
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365 __HAL_LOCK(hsram);
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366
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367 /* Update the SRAM controller state */
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368 hsram->State = HAL_SRAM_STATE_BUSY;
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369
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370 /* Read data from memory */
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371 for(; BufferSize != 0U; BufferSize--)
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372 {
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373 *pDstBuffer = *(__IO uint16_t *)pSramAddress;
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374 pDstBuffer++;
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375 pSramAddress++;
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376 }
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377
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378 /* Update the SRAM controller state */
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379 hsram->State = HAL_SRAM_STATE_READY;
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380
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381 /* Process unlocked */
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382 __HAL_UNLOCK(hsram);
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383
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384 return HAL_OK;
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385 }
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386
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387 /**
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388 * @brief Writes 16-bit buffer to SRAM memory.
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389 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
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390 * the configuration information for SRAM module.
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391 * @param pAddress Pointer to write start address
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392 * @param pSrcBuffer Pointer to source buffer to write
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393 * @param BufferSize Size of the buffer to write to memory
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394 * @retval HAL status
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395 */
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396 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
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397 {
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398 __IO uint16_t * pSramAddress = (uint16_t *)pAddress;
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399
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400 /* Check the SRAM controller state */
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401 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
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402 {
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403 return HAL_ERROR;
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404 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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405
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406 /* Process Locked */
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407 __HAL_LOCK(hsram);
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408
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409 /* Update the SRAM controller state */
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410 hsram->State = HAL_SRAM_STATE_BUSY;
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411
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412 /* Write data to memory */
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413 for(; BufferSize != 0U; BufferSize--)
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414 {
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415 *(__IO uint16_t *)pSramAddress = *pSrcBuffer;
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416 pSrcBuffer++;
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417 pSramAddress++;
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418 }
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419
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420 /* Update the SRAM controller state */
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421 hsram->State = HAL_SRAM_STATE_READY;
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422
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423 /* Process unlocked */
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424 __HAL_UNLOCK(hsram);
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425
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426 return HAL_OK;
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427 }
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428
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429 /**
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430 * @brief Reads 32-bit buffer from SRAM memory.
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431 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
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432 * the configuration information for SRAM module.
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433 * @param pAddress Pointer to read start address
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434 * @param pDstBuffer Pointer to destination buffer
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435 * @param BufferSize Size of the buffer to read from memory
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436 * @retval HAL status
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437 */
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438 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
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439 {
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440 /* Process Locked */
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441 __HAL_LOCK(hsram);
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442
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443 /* Update the SRAM controller state */
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444 hsram->State = HAL_SRAM_STATE_BUSY;
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445
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446 /* Read data from memory */
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447 for(; BufferSize != 0U; BufferSize--)
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448 {
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449 *pDstBuffer = *(__IO uint32_t *)pAddress;
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450 pDstBuffer++;
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451 pAddress++;
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452 }
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453
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454 /* Update the SRAM controller state */
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455 hsram->State = HAL_SRAM_STATE_READY;
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456
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457 /* Process unlocked */
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458 __HAL_UNLOCK(hsram);
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459
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460 return HAL_OK;
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461 }
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462
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463 /**
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464 * @brief Writes 32-bit buffer to SRAM memory.
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465 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
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466 * the configuration information for SRAM module.
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467 * @param pAddress Pointer to write start address
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468 * @param pSrcBuffer Pointer to source buffer to write
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diff changeset
469 * @param BufferSize Size of the buffer to write to memory
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470 * @retval HAL status
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471 */
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472 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
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473 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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474 /* Check the SRAM controller state */
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475 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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476 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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477 return HAL_ERROR;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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478 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
479
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
480 /* Process Locked */
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481 __HAL_LOCK(hsram);
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diff changeset
482
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
483 /* Update the SRAM controller state */
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484 hsram->State = HAL_SRAM_STATE_BUSY;
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diff changeset
485
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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486 /* Write data to memory */
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487 for(; BufferSize != 0U; BufferSize--)
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488 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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489 *(__IO uint32_t *)pAddress = *pSrcBuffer;
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490 pSrcBuffer++;
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491 pAddress++;
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492 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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493
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
494 /* Update the SRAM controller state */
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495 hsram->State = HAL_SRAM_STATE_READY;
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496
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
497 /* Process unlocked */
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498 __HAL_UNLOCK(hsram);
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499
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500 return HAL_OK;
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501 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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502
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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503 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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504 * @brief Reads a Words data from the SRAM memory using DMA transfer.
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505 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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506 * the configuration information for SRAM module.
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507 * @param pAddress Pointer to read start address
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508 * @param pDstBuffer Pointer to destination buffer
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509 * @param BufferSize Size of the buffer to read from memory
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510 * @retval HAL status
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511 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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512 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
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513 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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514 /* Process Locked */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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515 __HAL_LOCK(hsram);
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516
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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517 /* Update the SRAM controller state */
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518 hsram->State = HAL_SRAM_STATE_BUSY;
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parents:
diff changeset
519
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
520 /* Configure DMA user callbacks */
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521 hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
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522 hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
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523
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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524 /* Enable the DMA Stream */
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525 HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
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526
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
527 /* Update the SRAM controller state */
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528 hsram->State = HAL_SRAM_STATE_READY;
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diff changeset
529
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
530 /* Process unlocked */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
531 __HAL_UNLOCK(hsram);
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
532
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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533 return HAL_OK;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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534 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff changeset
535
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
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536 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
537 * @brief Writes a Words data buffer to SRAM memory using DMA transfer.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
538 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
539 * the configuration information for SRAM module.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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540 * @param pAddress Pointer to write start address
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff changeset
541 * @param pSrcBuffer Pointer to source buffer to write
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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542 * @param BufferSize Size of the buffer to write to memory
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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543 * @retval HAL status
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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544 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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545 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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546 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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547 /* Check the SRAM controller state */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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548 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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549 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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550 return HAL_ERROR;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
551 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
552
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
553 /* Process Locked */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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554 __HAL_LOCK(hsram);
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
555
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
556 /* Update the SRAM controller state */
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diff changeset
557 hsram->State = HAL_SRAM_STATE_BUSY;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
558
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
559 /* Configure DMA user callbacks */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
560 hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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561 hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
562
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
563 /* Enable the DMA Stream */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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564 HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
565
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
566 /* Update the SRAM controller state */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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567 hsram->State = HAL_SRAM_STATE_READY;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
568
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
569 /* Process unlocked */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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570 __HAL_UNLOCK(hsram);
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
571
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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572 return HAL_OK;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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573 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
574
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
575 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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576 * @}
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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577 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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578
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
579 /** @defgroup SRAM_Exported_Functions_Group3 Control functions
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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580 * @brief management functions
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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581 *
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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582 @verbatim
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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583 ==============================================================================
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
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584 ##### SRAM Control functions #####
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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585 ==============================================================================
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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586 [..]
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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587 This subsection provides a set of functions allowing to control dynamically
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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588 the SRAM interface.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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589
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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590 @endverbatim
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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591 * @{
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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592 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
593
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
594 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
595 * @brief Enables dynamically SRAM write operation.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
596 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
597 * the configuration information for SRAM module.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
598 * @retval HAL status
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
599 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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600 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
601 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
602 /* Process Locked */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
603 __HAL_LOCK(hsram);
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
604
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
605 /* Enable write operation */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
606 FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
607
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
608 /* Update the SRAM controller state */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
609 hsram->State = HAL_SRAM_STATE_READY;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
610
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
611 /* Process unlocked */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
612 __HAL_UNLOCK(hsram);
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
613
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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614 return HAL_OK;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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615 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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616
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
617 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
618 * @brief Disables dynamically SRAM write operation.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff changeset
619 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
620 * the configuration information for SRAM module.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
621 * @retval HAL status
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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622 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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623 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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624 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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625 /* Process Locked */
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626 __HAL_LOCK(hsram);
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627
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628 /* Update the SRAM controller state */
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629 hsram->State = HAL_SRAM_STATE_BUSY;
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630
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631 /* Disable write operation */
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632 FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
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633
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634 /* Update the SRAM controller state */
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635 hsram->State = HAL_SRAM_STATE_PROTECTED;
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636
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637 /* Process unlocked */
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638 __HAL_UNLOCK(hsram);
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639
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640 return HAL_OK;
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641 }
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642
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643 /**
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644 * @}
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645 */
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646
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647 /** @defgroup SRAM_Exported_Functions_Group4 State functions
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648 * @brief Peripheral State functions
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649 *
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650 @verbatim
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651 ==============================================================================
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652 ##### SRAM State functions #####
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653 ==============================================================================
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654 [..]
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655 This subsection permits to get in run-time the status of the SRAM controller
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656 and the data flow.
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657
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658 @endverbatim
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659 * @{
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660 */
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661
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662 /**
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663 * @brief Returns the SRAM controller state
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664 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
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665 * the configuration information for SRAM module.
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666 * @retval HAL state
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667 */
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668 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
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669 {
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670 return hsram->State;
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671 }
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672 /**
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673 * @}
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674 */
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675
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676 /**
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677 * @}
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678 */
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679 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
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680 STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
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681 STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
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682 #endif /* HAL_SRAM_MODULE_ENABLED */
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683 /**
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684 * @}
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685 */
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686
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687 /**
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688 * @}
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689 */
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690
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691 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/