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annotate Common/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h @ 937:d461d9e89e3c Evo_2_23

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Compile switch for RTE sleep debug: there was already a compiler switch for enabling debugging while RTE is in sleep but the switches were distributed across the code => to make selection easier they are now part of the configuration.h
author Ideenmodellierer
date Tue, 10 Dec 2024 20:59:37 +0100
parents c78bcbd5deda
children
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1 /**
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2 ******************************************************************************
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3 * @file stm32f4xx_hal.h
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4 * @author MCD Application Team
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5 * @brief This file contains all the functions prototypes for the HAL
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6 * module driver.
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7 ******************************************************************************
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8 * @attention
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9 *
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10 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
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11 *
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12 * Redistribution and use in source and binary forms, with or without modification,
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13 * are permitted provided that the following conditions are met:
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14 * 1. Redistributions of source code must retain the above copyright notice,
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15 * this list of conditions and the following disclaimer.
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16 * 2. Redistributions in binary form must reproduce the above copyright notice,
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17 * this list of conditions and the following disclaimer in the documentation
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18 * and/or other materials provided with the distribution.
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19 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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20 * may be used to endorse or promote products derived from this software
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21 * without specific prior written permission.
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22 *
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23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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33 *
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34 ******************************************************************************
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35 */
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36
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37 /* Define to prevent recursive inclusion -------------------------------------*/
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38 #ifndef __STM32F4xx_HAL_H
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39 #define __STM32F4xx_HAL_H
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40
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41 #ifdef __cplusplus
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42 extern "C" {
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43 #endif
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44
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45 /* Includes ------------------------------------------------------------------*/
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46 #include "stm32f4xx_hal_conf.h"
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47
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48 /** @addtogroup STM32F4xx_HAL_Driver
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49 * @{
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50 */
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51
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52 /** @addtogroup HAL
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53 * @{
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54 */
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55
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56 /* Exported types ------------------------------------------------------------*/
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57 /* Exported constants --------------------------------------------------------*/
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58
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59 /** @defgroup HAL_Exported_Constants HAL Exported Constants
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60 * @{
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61 */
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62
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63 /** @defgroup HAL_TICK_FREQ Tick Frequency
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64 * @{
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65 */
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66 typedef enum
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67 {
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68 HAL_TICK_FREQ_10HZ = 100U,
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69 HAL_TICK_FREQ_100HZ = 10U,
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70 HAL_TICK_FREQ_1KHZ = 1U,
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71 HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
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72 } HAL_TickFreqTypeDef;
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73 /**
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74 * @}
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75 */
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76
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77 /**
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78 * @}
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79 */
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80
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81 /* Exported macro ------------------------------------------------------------*/
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82 /** @defgroup HAL_Exported_Macros HAL Exported Macros
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83 * @{
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84 */
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85
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86 /** @brief Freeze/Unfreeze Peripherals in Debug mode
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87 */
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88 #define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
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89 #define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
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90 #define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
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91 #define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
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92 #define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
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93 #define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
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94 #define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
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95 #define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
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96 #define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
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97 #define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
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98 #define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
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99 #define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
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100 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
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101 #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
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102 #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
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103 #define __HAL_DBGMCU_FREEZE_CAN1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP))
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104 #define __HAL_DBGMCU_FREEZE_CAN2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP))
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105 #define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
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106 #define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
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107 #define __HAL_DBGMCU_FREEZE_TIM9() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP))
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108 #define __HAL_DBGMCU_FREEZE_TIM10() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP))
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109 #define __HAL_DBGMCU_FREEZE_TIM11() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP))
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110
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111 #define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
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112 #define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
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113 #define __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
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114 #define __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
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115 #define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
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116 #define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
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117 #define __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
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118 #define __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
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119 #define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
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120 #define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
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121 #define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
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122 #define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
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123 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
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124 #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
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125 #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
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126 #define __HAL_DBGMCU_UNFREEZE_CAN1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP))
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127 #define __HAL_DBGMCU_UNFREEZE_CAN2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP))
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128 #define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
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129 #define __HAL_DBGMCU_UNFREEZE_TIM8() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
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130 #define __HAL_DBGMCU_UNFREEZE_TIM9() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP))
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131 #define __HAL_DBGMCU_UNFREEZE_TIM10() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP))
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132 #define __HAL_DBGMCU_UNFREEZE_TIM11() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP))
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133
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134 /** @brief Main Flash memory mapped at 0x00000000
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135 */
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136 #define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE))
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137
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138 /** @brief System Flash memory mapped at 0x00000000
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139 */
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140 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
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141 SYSCFG->MEMRMP |= SYSCFG_MEMRMP_MEM_MODE_0;\
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142 }while(0);
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143
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144 /** @brief Embedded SRAM mapped at 0x00000000
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145 */
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146 #define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
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147 SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1);\
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148 }while(0);
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149
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150 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
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151 /** @brief FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
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152 */
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153 #define __HAL_SYSCFG_REMAPMEMORY_FSMC() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
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154 SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\
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155 }while(0);
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156 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
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157
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158 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
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159 defined(STM32F469xx) || defined(STM32F479xx)
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160 /** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
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161 */
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162 #define __HAL_SYSCFG_REMAPMEMORY_FMC() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
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163 SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\
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164 }while(0);
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165
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166 /** @brief FMC/SDRAM Bank 1 and 2 mapped at 0x00000000
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167 */
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168 #define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
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169 SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_2);\
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170 }while(0);
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171 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
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172
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173 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F413xx) || defined(STM32F423xx)
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174 /** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable
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175 * @{
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176 */
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177 /** @brief SYSCFG Break Lockup lock
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178 * Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8 input
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179 * @note The selected configuration is locked and can be unlocked by system reset
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180 */
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181 #define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
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182 SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \
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183 }while(0)
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184 /**
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185 * @}
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186 */
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187
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188 /** @defgroup PVD_Lock_Enable PVD Lock
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189 * @{
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190 */
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191 /** @brief SYSCFG Break PVD lock
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192 * Enables and locks the PVD connection with Timer1/8 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register
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193 * @note The selected configuration is locked and can be unlocked by system reset
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194 */
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195 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
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196 SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \
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197 }while(0)
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198 /**
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199 * @}
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200 */
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201 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx || STM32F413xx || STM32F423xx */
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202 /**
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203 * @}
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204 */
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205
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206 /** @defgroup HAL_Private_Macros HAL Private Macros
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207 * @{
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208 */
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209 #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
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210 ((FREQ) == HAL_TICK_FREQ_100HZ) || \
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211 ((FREQ) == HAL_TICK_FREQ_1KHZ))
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212 /**
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213 * @}
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214 */
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215
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216 /* Exported functions --------------------------------------------------------*/
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217 /** @addtogroup HAL_Exported_Functions
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218 * @{
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219 */
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220 /** @addtogroup HAL_Exported_Functions_Group1
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221 * @{
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222 */
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223 /* Initialization and Configuration functions ******************************/
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224 HAL_StatusTypeDef HAL_Init(void);
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225 HAL_StatusTypeDef HAL_DeInit(void);
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226 void HAL_MspInit(void);
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227 void HAL_MspDeInit(void);
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228 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
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229 /**
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230 * @}
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231 */
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232
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233 /** @addtogroup HAL_Exported_Functions_Group2
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234 * @{
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235 */
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236 /* Peripheral Control functions ************************************************/
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237 void HAL_IncTick(void);
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238 void HAL_Delay(uint32_t Delay);
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239 uint32_t HAL_GetTick(void);
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240 uint32_t HAL_GetTickPrio(void);
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241 HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
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242 HAL_TickFreqTypeDef HAL_GetTickFreq(void);
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243 void HAL_SuspendTick(void);
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244 void HAL_ResumeTick(void);
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245 uint32_t HAL_GetHalVersion(void);
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246 uint32_t HAL_GetREVID(void);
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247 uint32_t HAL_GetDEVID(void);
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248 void HAL_DBGMCU_EnableDBGSleepMode(void);
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249 void HAL_DBGMCU_DisableDBGSleepMode(void);
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250 void HAL_DBGMCU_EnableDBGStopMode(void);
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251 void HAL_DBGMCU_DisableDBGStopMode(void);
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252 void HAL_DBGMCU_EnableDBGStandbyMode(void);
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253 void HAL_DBGMCU_DisableDBGStandbyMode(void);
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254 void HAL_EnableCompensationCell(void);
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255 void HAL_DisableCompensationCell(void);
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256 void HAL_GetUID(uint32_t *UID);
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257 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
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258 defined(STM32F469xx) || defined(STM32F479xx)
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259 void HAL_EnableMemorySwappingBank(void);
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260 void HAL_DisableMemorySwappingBank(void);
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261 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
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262 /**
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263 * @}
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264 */
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265
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266 /**
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267 * @}
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268 */
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269 /* Private types -------------------------------------------------------------*/
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270 /* Private variables ---------------------------------------------------------*/
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271 /** @defgroup HAL_Private_Variables HAL Private Variables
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272 * @{
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273 */
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274 /**
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275 * @}
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276 */
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277 /* Private constants ---------------------------------------------------------*/
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278 /** @defgroup HAL_Private_Constants HAL Private Constants
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279 * @{
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280 */
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281 /**
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282 * @}
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283 */
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284 /* Private macros ------------------------------------------------------------*/
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285 /* Private functions ---------------------------------------------------------*/
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286 /**
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287 * @}
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288 */
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289
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290 /**
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291 * @}
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292 */
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293
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294 #ifdef __cplusplus
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295 }
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296 #endif
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297
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298 #endif /* __STM32F4xx_HAL_H */
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299
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300 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/