Mercurial > public > ostc4
annotate Common/Drivers/CMSIS/Include/core_cm3.h @ 937:d461d9e89e3c Evo_2_23
Compile switch for RTE sleep debug:
there was already a compiler switch for enabling debugging while RTE is in sleep but the switches were distributed across the code => to make selection easier they are now part of the configuration.h
author | Ideenmodellierer |
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date | Tue, 10 Dec 2024 20:59:37 +0100 |
parents | c78bcbd5deda |
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rev | line source |
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1 /**************************************************************************//** |
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2 * @file core_cm3.h |
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3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File |
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4 * @version V4.30 |
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5 * @date 20. October 2015 |
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6 ******************************************************************************/ |
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7 /* Copyright (c) 2009 - 2015 ARM LIMITED |
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8 |
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9 All rights reserved. |
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10 Redistribution and use in source and binary forms, with or without |
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11 modification, are permitted provided that the following conditions are met: |
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12 - Redistributions of source code must retain the above copyright |
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13 notice, this list of conditions and the following disclaimer. |
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14 - Redistributions in binary form must reproduce the above copyright |
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15 notice, this list of conditions and the following disclaimer in the |
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16 documentation and/or other materials provided with the distribution. |
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17 - Neither the name of ARM nor the names of its contributors may be used |
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18 to endorse or promote products derived from this software without |
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19 specific prior written permission. |
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20 * |
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21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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24 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
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25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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31 POSSIBILITY OF SUCH DAMAGE. |
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32 ---------------------------------------------------------------------------*/ |
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33 |
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34 |
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35 #if defined ( __ICCARM__ ) |
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36 #pragma system_include /* treat file as system include file for MISRA check */ |
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37 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
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38 #pragma clang system_header /* treat file as system include file */ |
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39 #endif |
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40 |
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41 #ifndef __CORE_CM3_H_GENERIC |
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42 #define __CORE_CM3_H_GENERIC |
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43 |
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44 #include <stdint.h> |
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45 |
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46 #ifdef __cplusplus |
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47 extern "C" { |
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48 #endif |
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49 |
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50 /** |
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51 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions |
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52 CMSIS violates the following MISRA-C:2004 rules: |
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53 |
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54 \li Required Rule 8.5, object/function definition in header file.<br> |
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55 Function definitions in header files are used to allow 'inlining'. |
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56 |
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57 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> |
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58 Unions are used for effective representation of core registers. |
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59 |
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60 \li Advisory Rule 19.7, Function-like macro defined.<br> |
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61 Function-like macros are used to allow more efficient code. |
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62 */ |
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63 |
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64 |
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65 /******************************************************************************* |
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66 * CMSIS definitions |
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67 ******************************************************************************/ |
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68 /** |
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69 \ingroup Cortex_M3 |
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70 @{ |
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71 */ |
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72 |
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73 /* CMSIS CM3 definitions */ |
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74 #define __CM3_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ |
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75 #define __CM3_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ |
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76 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ |
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77 __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ |
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78 |
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79 #define __CORTEX_M (0x03U) /*!< Cortex-M Core */ |
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80 |
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81 |
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82 #if defined ( __CC_ARM ) |
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83 #define __ASM __asm /*!< asm keyword for ARM Compiler */ |
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84 #define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
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85 #define __STATIC_INLINE static __inline |
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86 |
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87 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
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88 #define __ASM __asm /*!< asm keyword for ARM Compiler */ |
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89 #define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
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90 #define __STATIC_INLINE static __inline |
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91 |
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92 #elif defined ( __GNUC__ ) |
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93 #define __ASM __asm /*!< asm keyword for GNU Compiler */ |
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94 #define __INLINE inline /*!< inline keyword for GNU Compiler */ |
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95 #define __STATIC_INLINE static inline |
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96 |
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97 #elif defined ( __ICCARM__ ) |
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98 #define __ASM __asm /*!< asm keyword for IAR Compiler */ |
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99 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ |
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100 #define __STATIC_INLINE static inline |
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101 |
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102 #elif defined ( __TMS470__ ) |
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103 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ |
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104 #define __STATIC_INLINE static inline |
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105 |
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106 #elif defined ( __TASKING__ ) |
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107 #define __ASM __asm /*!< asm keyword for TASKING Compiler */ |
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108 #define __INLINE inline /*!< inline keyword for TASKING Compiler */ |
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109 #define __STATIC_INLINE static inline |
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110 |
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111 #elif defined ( __CSMC__ ) |
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112 #define __packed |
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113 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ |
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114 #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ |
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115 #define __STATIC_INLINE static inline |
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116 |
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117 #else |
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118 #error Unknown compiler |
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119 #endif |
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120 |
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121 /** __FPU_USED indicates whether an FPU is used or not. |
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122 This core does not support an FPU at all |
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123 */ |
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124 #define __FPU_USED 0U |
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125 |
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126 #if defined ( __CC_ARM ) |
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127 #if defined __TARGET_FPU_VFP |
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128 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
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129 #endif |
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130 |
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131 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
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132 #if defined __ARM_PCS_VFP |
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133 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
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134 #endif |
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135 |
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136 #elif defined ( __GNUC__ ) |
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137 #if defined (__VFP_FP__) && !defined(__SOFTFP__) |
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138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
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139 #endif |
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140 |
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141 #elif defined ( __ICCARM__ ) |
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142 #if defined __ARMVFP__ |
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143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
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144 #endif |
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145 |
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146 #elif defined ( __TMS470__ ) |
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147 #if defined __TI_VFP_SUPPORT__ |
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148 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
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149 #endif |
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150 |
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151 #elif defined ( __TASKING__ ) |
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152 #if defined __FPU_VFP__ |
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153 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
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154 #endif |
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155 |
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156 #elif defined ( __CSMC__ ) |
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157 #if ( __CSMC__ & 0x400U) |
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158 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
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159 #endif |
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160 |
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161 #endif |
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162 |
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163 #include "core_cmInstr.h" /* Core Instruction Access */ |
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164 #include "core_cmFunc.h" /* Core Function Access */ |
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165 |
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166 #ifdef __cplusplus |
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167 } |
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168 #endif |
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169 |
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170 #endif /* __CORE_CM3_H_GENERIC */ |
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171 |
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172 #ifndef __CMSIS_GENERIC |
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173 |
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174 #ifndef __CORE_CM3_H_DEPENDANT |
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175 #define __CORE_CM3_H_DEPENDANT |
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176 |
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177 #ifdef __cplusplus |
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178 extern "C" { |
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179 #endif |
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180 |
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181 /* check device defines and use defaults */ |
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182 #if defined __CHECK_DEVICE_DEFINES |
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183 #ifndef __CM3_REV |
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184 #define __CM3_REV 0x0200U |
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185 #warning "__CM3_REV not defined in device header file; using default!" |
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186 #endif |
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187 |
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188 #ifndef __MPU_PRESENT |
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189 #define __MPU_PRESENT 0U |
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190 #warning "__MPU_PRESENT not defined in device header file; using default!" |
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191 #endif |
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192 |
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193 #ifndef __NVIC_PRIO_BITS |
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194 #define __NVIC_PRIO_BITS 4U |
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195 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" |
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196 #endif |
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197 |
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198 #ifndef __Vendor_SysTickConfig |
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199 #define __Vendor_SysTickConfig 0U |
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200 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" |
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201 #endif |
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202 #endif |
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203 |
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204 /* IO definitions (access restrictions to peripheral registers) */ |
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205 /** |
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206 \defgroup CMSIS_glob_defs CMSIS Global Defines |
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207 |
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208 <strong>IO Type Qualifiers</strong> are used |
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209 \li to specify the access to peripheral variables. |
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210 \li for automatic generation of peripheral register debug information. |
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211 */ |
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212 #ifdef __cplusplus |
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213 #define __I volatile /*!< Defines 'read only' permissions */ |
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214 #else |
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215 #define __I volatile const /*!< Defines 'read only' permissions */ |
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216 #endif |
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217 #define __O volatile /*!< Defines 'write only' permissions */ |
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218 #define __IO volatile /*!< Defines 'read / write' permissions */ |
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219 |
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220 /* following defines should be used for structure members */ |
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221 #define __IM volatile const /*! Defines 'read only' structure member permissions */ |
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222 #define __OM volatile /*! Defines 'write only' structure member permissions */ |
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223 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ |
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224 |
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225 /*@} end of group Cortex_M3 */ |
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226 |
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227 |
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228 |
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229 /******************************************************************************* |
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230 * Register Abstraction |
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231 Core Register contain: |
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232 - Core Register |
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233 - Core NVIC Register |
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234 - Core SCB Register |
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235 - Core SysTick Register |
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236 - Core Debug Register |
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237 - Core MPU Register |
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238 ******************************************************************************/ |
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239 /** |
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240 \defgroup CMSIS_core_register Defines and Type Definitions |
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241 \brief Type definitions and defines for Cortex-M processor based devices. |
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242 */ |
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243 |
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244 /** |
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245 \ingroup CMSIS_core_register |
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246 \defgroup CMSIS_CORE Status and Control Registers |
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247 \brief Core Register type definitions. |
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248 @{ |
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249 */ |
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250 |
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251 /** |
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252 \brief Union type to access the Application Program Status Register (APSR). |
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253 */ |
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254 typedef union |
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255 { |
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256 struct |
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257 { |
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258 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ |
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259 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ |
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260 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
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261 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
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262 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
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263 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
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264 } b; /*!< Structure used for bit access */ |
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265 uint32_t w; /*!< Type used for word access */ |
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266 } APSR_Type; |
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267 |
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268 /* APSR Register Definitions */ |
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269 #define APSR_N_Pos 31U /*!< APSR: N Position */ |
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270 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ |
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271 |
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272 #define APSR_Z_Pos 30U /*!< APSR: Z Position */ |
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273 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ |
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274 |
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275 #define APSR_C_Pos 29U /*!< APSR: C Position */ |
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276 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ |
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277 |
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278 #define APSR_V_Pos 28U /*!< APSR: V Position */ |
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279 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ |
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280 |
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281 #define APSR_Q_Pos 27U /*!< APSR: Q Position */ |
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282 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ |
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283 |
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284 |
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285 /** |
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286 \brief Union type to access the Interrupt Program Status Register (IPSR). |
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287 */ |
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288 typedef union |
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289 { |
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290 struct |
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291 { |
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292 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
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293 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ |
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294 } b; /*!< Structure used for bit access */ |
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295 uint32_t w; /*!< Type used for word access */ |
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296 } IPSR_Type; |
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297 |
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298 /* IPSR Register Definitions */ |
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299 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ |
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300 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ |
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301 |
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302 |
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303 /** |
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304 \brief Union type to access the Special-Purpose Program Status Registers (xPSR). |
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305 */ |
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306 typedef union |
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307 { |
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308 struct |
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309 { |
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310 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
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311 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ |
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312 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ |
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313 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ |
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314 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ |
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315 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
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316 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
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317 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
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318 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
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319 } b; /*!< Structure used for bit access */ |
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320 uint32_t w; /*!< Type used for word access */ |
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321 } xPSR_Type; |
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322 |
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323 /* xPSR Register Definitions */ |
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324 #define xPSR_N_Pos 31U /*!< xPSR: N Position */ |
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325 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ |
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326 |
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327 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ |
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328 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ |
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329 |
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330 #define xPSR_C_Pos 29U /*!< xPSR: C Position */ |
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331 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ |
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332 |
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333 #define xPSR_V_Pos 28U /*!< xPSR: V Position */ |
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334 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ |
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335 |
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336 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ |
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337 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ |
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338 |
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339 #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ |
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340 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ |
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341 |
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342 #define xPSR_T_Pos 24U /*!< xPSR: T Position */ |
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343 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ |
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344 |
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345 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ |
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346 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ |
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347 |
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348 |
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349 /** |
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350 \brief Union type to access the Control Registers (CONTROL). |
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351 */ |
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352 typedef union |
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353 { |
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354 struct |
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355 { |
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356 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ |
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357 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ |
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358 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ |
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359 } b; /*!< Structure used for bit access */ |
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360 uint32_t w; /*!< Type used for word access */ |
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361 } CONTROL_Type; |
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362 |
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363 /* CONTROL Register Definitions */ |
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364 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ |
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365 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ |
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366 |
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367 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ |
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368 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ |
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369 |
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370 /*@} end of group CMSIS_CORE */ |
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371 |
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372 |
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373 /** |
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374 \ingroup CMSIS_core_register |
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375 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) |
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376 \brief Type definitions for the NVIC Registers |
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377 @{ |
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378 */ |
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379 |
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380 /** |
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381 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). |
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382 */ |
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383 typedef struct |
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384 { |
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385 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ |
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386 uint32_t RESERVED0[24U]; |
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387 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ |
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388 uint32_t RSERVED1[24U]; |
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389 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ |
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390 uint32_t RESERVED2[24U]; |
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391 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ |
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392 uint32_t RESERVED3[24U]; |
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393 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ |
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394 uint32_t RESERVED4[56U]; |
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395 __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ |
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396 uint32_t RESERVED5[644U]; |
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397 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ |
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398 } NVIC_Type; |
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399 |
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400 /* Software Triggered Interrupt Register Definitions */ |
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401 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ |
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402 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ |
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403 |
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404 /*@} end of group CMSIS_NVIC */ |
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405 |
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406 |
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407 /** |
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408 \ingroup CMSIS_core_register |
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409 \defgroup CMSIS_SCB System Control Block (SCB) |
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410 \brief Type definitions for the System Control Block Registers |
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411 @{ |
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412 */ |
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413 |
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414 /** |
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415 \brief Structure type to access the System Control Block (SCB). |
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416 */ |
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417 typedef struct |
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418 { |
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419 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ |
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420 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ |
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421 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ |
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422 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ |
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423 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ |
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424 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ |
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425 __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ |
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426 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ |
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427 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ |
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428 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ |
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429 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ |
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430 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ |
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431 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ |
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432 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ |
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433 __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ |
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434 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ |
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435 __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ |
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436 __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ |
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437 __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ |
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438 uint32_t RESERVED0[5U]; |
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439 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ |
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440 } SCB_Type; |
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441 |
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442 /* SCB CPUID Register Definitions */ |
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443 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ |
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444 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ |
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445 |
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446 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ |
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447 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ |
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448 |
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449 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ |
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450 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ |
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451 |
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452 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ |
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453 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ |
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454 |
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455 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ |
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456 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ |
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457 |
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458 /* SCB Interrupt Control State Register Definitions */ |
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459 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ |
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460 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ |
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461 |
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462 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ |
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463 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ |
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464 |
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465 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ |
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466 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ |
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467 |
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468 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ |
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469 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ |
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470 |
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471 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ |
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472 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ |
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473 |
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474 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ |
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475 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ |
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476 |
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477 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ |
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478 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ |
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479 |
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480 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ |
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481 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ |
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482 |
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483 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ |
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484 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ |
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485 |
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486 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ |
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487 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ |
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488 |
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489 /* SCB Vector Table Offset Register Definitions */ |
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490 #if (__CM3_REV < 0x0201U) /* core r2p1 */ |
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491 #define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ |
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492 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ |
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493 |
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494 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ |
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495 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ |
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496 #else |
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497 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ |
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498 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ |
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499 #endif |
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500 |
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501 /* SCB Application Interrupt and Reset Control Register Definitions */ |
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502 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ |
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503 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ |
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504 |
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505 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ |
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506 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ |
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507 |
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508 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ |
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509 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ |
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Added current STM32 standandard libraries in version independend folder structure
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510 |
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Added current STM32 standandard libraries in version independend folder structure
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511 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ |
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512 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ |
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513 |
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514 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ |
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Added current STM32 standandard libraries in version independend folder structure
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515 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ |
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516 |
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|
517 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ |
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518 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ |
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519 |
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|
520 #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ |
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521 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ |
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522 |
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523 /* SCB System Control Register Definitions */ |
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524 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ |
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525 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ |
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526 |
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527 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ |
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528 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ |
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529 |
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530 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ |
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531 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ |
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532 |
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533 /* SCB Configuration Control Register Definitions */ |
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534 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ |
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535 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ |
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|
536 |
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537 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ |
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538 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ |
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539 |
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540 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ |
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541 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ |
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|
542 |
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543 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ |
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544 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ |
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545 |
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546 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ |
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547 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ |
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548 |
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549 #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ |
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Added current STM32 standandard libraries in version independend folder structure
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550 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ |
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551 |
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552 /* SCB System Handler Control and State Register Definitions */ |
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553 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ |
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554 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ |
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|
555 |
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|
556 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ |
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557 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ |
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|
558 |
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559 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ |
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560 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ |
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Added current STM32 standandard libraries in version independend folder structure
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561 |
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562 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ |
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563 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
564 |
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565 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ |
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566 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ |
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Added current STM32 standandard libraries in version independend folder structure
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567 |
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568 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ |
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Added current STM32 standandard libraries in version independend folder structure
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569 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
570 |
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571 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ |
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Added current STM32 standandard libraries in version independend folder structure
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572 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ |
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573 |
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574 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ |
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Added current STM32 standandard libraries in version independend folder structure
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575 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ |
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576 |
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577 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ |
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578 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ |
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579 |
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580 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ |
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581 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ |
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582 |
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583 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ |
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584 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ |
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585 |
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586 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ |
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587 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ |
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588 |
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589 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ |
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590 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ |
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|
591 |
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592 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ |
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593 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ |
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|
594 |
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595 /* SCB Configurable Fault Status Register Definitions */ |
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596 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ |
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597 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ |
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Added current STM32 standandard libraries in version independend folder structure
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598 |
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|
599 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ |
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600 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ |
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Added current STM32 standandard libraries in version independend folder structure
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601 |
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602 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ |
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603 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ |
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|
604 |
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605 /* SCB Hard Fault Status Register Definitions */ |
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606 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ |
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607 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ |
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608 |
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609 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ |
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610 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ |
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|
611 |
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612 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ |
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613 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ |
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614 |
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615 /* SCB Debug Fault Status Register Definitions */ |
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616 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ |
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617 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ |
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618 |
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619 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ |
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620 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ |
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621 |
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622 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ |
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623 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ |
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624 |
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625 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ |
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626 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ |
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627 |
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628 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ |
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629 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ |
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630 |
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631 /*@} end of group CMSIS_SCB */ |
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632 |
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633 |
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634 /** |
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635 \ingroup CMSIS_core_register |
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636 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) |
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637 \brief Type definitions for the System Control and ID Register not in the SCB |
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638 @{ |
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639 */ |
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640 |
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641 /** |
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642 \brief Structure type to access the System Control and ID Register not in the SCB. |
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643 */ |
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644 typedef struct |
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645 { |
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646 uint32_t RESERVED0[1U]; |
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647 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ |
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648 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200U)) |
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649 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ |
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650 #else |
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651 uint32_t RESERVED1[1U]; |
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652 #endif |
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653 } SCnSCB_Type; |
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654 |
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655 /* Interrupt Controller Type Register Definitions */ |
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656 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ |
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657 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ |
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658 |
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659 /* Auxiliary Control Register Definitions */ |
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660 |
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661 #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ |
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662 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ |
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663 |
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664 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ |
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665 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ |
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666 |
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667 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ |
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668 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ |
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669 |
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670 /*@} end of group CMSIS_SCnotSCB */ |
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671 |
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672 |
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673 /** |
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674 \ingroup CMSIS_core_register |
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675 \defgroup CMSIS_SysTick System Tick Timer (SysTick) |
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676 \brief Type definitions for the System Timer Registers. |
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677 @{ |
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678 */ |
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679 |
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680 /** |
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681 \brief Structure type to access the System Timer (SysTick). |
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682 */ |
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683 typedef struct |
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684 { |
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685 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ |
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686 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ |
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687 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ |
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688 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ |
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689 } SysTick_Type; |
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690 |
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691 /* SysTick Control / Status Register Definitions */ |
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692 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ |
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693 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ |
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694 |
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695 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ |
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696 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ |
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697 |
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698 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ |
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699 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ |
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700 |
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701 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ |
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702 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ |
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703 |
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704 /* SysTick Reload Register Definitions */ |
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705 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ |
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706 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ |
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707 |
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708 /* SysTick Current Register Definitions */ |
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709 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ |
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710 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ |
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711 |
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712 /* SysTick Calibration Register Definitions */ |
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713 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ |
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714 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ |
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715 |
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716 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ |
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717 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ |
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718 |
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719 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ |
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720 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ |
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721 |
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722 /*@} end of group CMSIS_SysTick */ |
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723 |
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724 |
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725 /** |
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726 \ingroup CMSIS_core_register |
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727 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) |
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728 \brief Type definitions for the Instrumentation Trace Macrocell (ITM) |
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729 @{ |
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730 */ |
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731 |
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732 /** |
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733 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). |
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734 */ |
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735 typedef struct |
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736 { |
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737 __OM union |
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738 { |
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739 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ |
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740 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ |
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741 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ |
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742 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ |
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743 uint32_t RESERVED0[864U]; |
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744 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ |
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745 uint32_t RESERVED1[15U]; |
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746 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ |
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747 uint32_t RESERVED2[15U]; |
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748 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ |
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749 uint32_t RESERVED3[29U]; |
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750 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ |
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751 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ |
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752 __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ |
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753 uint32_t RESERVED4[43U]; |
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754 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ |
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755 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ |
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756 uint32_t RESERVED5[6U]; |
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757 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ |
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758 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ |
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759 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ |
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760 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ |
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761 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ |
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762 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ |
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763 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ |
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764 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ |
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765 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ |
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766 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ |
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767 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ |
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768 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ |
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769 } ITM_Type; |
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770 |
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771 /* ITM Trace Privilege Register Definitions */ |
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772 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ |
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773 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ |
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774 |
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775 /* ITM Trace Control Register Definitions */ |
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776 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ |
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777 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ |
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778 |
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779 #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ |
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780 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ |
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781 |
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782 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ |
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783 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ |
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784 |
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785 #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ |
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786 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ |
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787 |
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788 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ |
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789 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ |
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790 |
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791 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ |
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792 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ |
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793 |
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794 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ |
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795 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ |
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796 |
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797 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ |
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798 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ |
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799 |
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800 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ |
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801 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ |
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802 |
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803 /* ITM Integration Write Register Definitions */ |
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804 #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ |
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805 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ |
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806 |
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807 /* ITM Integration Read Register Definitions */ |
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808 #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ |
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809 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ |
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810 |
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811 /* ITM Integration Mode Control Register Definitions */ |
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812 #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ |
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813 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ |
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814 |
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815 /* ITM Lock Status Register Definitions */ |
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816 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ |
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817 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ |
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818 |
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819 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ |
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820 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ |
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821 |
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822 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ |
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823 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ |
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824 |
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825 /*@}*/ /* end of group CMSIS_ITM */ |
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826 |
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827 |
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828 /** |
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829 \ingroup CMSIS_core_register |
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830 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) |
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831 \brief Type definitions for the Data Watchpoint and Trace (DWT) |
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832 @{ |
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833 */ |
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834 |
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835 /** |
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836 \brief Structure type to access the Data Watchpoint and Trace Register (DWT). |
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837 */ |
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838 typedef struct |
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839 { |
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840 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ |
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841 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ |
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842 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ |
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843 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ |
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844 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ |
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845 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ |
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846 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ |
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847 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ |
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848 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ |
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849 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
850 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ |
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|
851 uint32_t RESERVED0[1U]; |
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|
852 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
853 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
854 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
855 uint32_t RESERVED1[1U]; |
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Added current STM32 standandard libraries in version independend folder structure
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|
856 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ |
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Added current STM32 standandard libraries in version independend folder structure
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diff
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|
857 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ |
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|
858 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
859 uint32_t RESERVED2[1U]; |
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Added current STM32 standandard libraries in version independend folder structure
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|
860 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
861 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
862 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ |
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|
863 } DWT_Type; |
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Added current STM32 standandard libraries in version independend folder structure
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|
864 |
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|
865 /* DWT Control Register Definitions */ |
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|
866 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
867 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
868 |
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|
869 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
870 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
871 |
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|
872 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ |
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|
873 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
874 |
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|
875 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
876 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
877 |
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Added current STM32 standandard libraries in version independend folder structure
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|
878 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
879 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
880 |
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Added current STM32 standandard libraries in version independend folder structure
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|
881 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
882 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
883 |
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|
884 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
885 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
886 |
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|
887 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
888 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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diff
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|
889 |
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|
890 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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|
891 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
892 |
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|
893 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
894 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
895 |
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|
896 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ |
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Added current STM32 standandard libraries in version independend folder structure
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897 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
898 |
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|
899 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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|
900 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
901 |
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|
902 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
903 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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|
904 |
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Added current STM32 standandard libraries in version independend folder structure
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|
905 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
906 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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|
907 |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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|
908 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
909 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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|
910 |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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|
911 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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|
912 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
913 |
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Added current STM32 standandard libraries in version independend folder structure
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|
914 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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|
915 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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|
916 |
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|
917 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
918 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
919 |
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|
920 /* DWT CPI Count Register Definitions */ |
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|
921 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
922 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ |
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|
923 |
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|
924 /* DWT Exception Overhead Count Register Definitions */ |
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|
925 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ |
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|
926 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ |
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|
927 |
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|
928 /* DWT Sleep Count Register Definitions */ |
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|
929 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ |
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|
930 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ |
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|
931 |
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|
932 /* DWT LSU Count Register Definitions */ |
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|
933 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ |
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|
934 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ |
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|
935 |
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|
936 /* DWT Folded-instruction Count Register Definitions */ |
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|
937 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ |
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938 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ |
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|
939 |
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|
940 /* DWT Comparator Mask Register Definitions */ |
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|
941 #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ |
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942 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ |
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|
943 |
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|
944 /* DWT Comparator Function Register Definitions */ |
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945 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ |
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946 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ |
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|
947 |
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948 #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ |
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949 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ |
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|
950 |
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|
951 #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ |
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952 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ |
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|
953 |
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|
954 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ |
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955 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ |
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|
956 |
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|
957 #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ |
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958 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ |
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959 |
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960 #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ |
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961 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ |
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962 |
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963 #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ |
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964 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ |
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965 |
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966 #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ |
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967 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ |
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968 |
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969 #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ |
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970 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ |
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971 |
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972 /*@}*/ /* end of group CMSIS_DWT */ |
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973 |
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974 |
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975 /** |
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976 \ingroup CMSIS_core_register |
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977 \defgroup CMSIS_TPI Trace Port Interface (TPI) |
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978 \brief Type definitions for the Trace Port Interface (TPI) |
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979 @{ |
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980 */ |
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981 |
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982 /** |
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983 \brief Structure type to access the Trace Port Interface Register (TPI). |
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984 */ |
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985 typedef struct |
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986 { |
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987 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ |
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988 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ |
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989 uint32_t RESERVED0[2U]; |
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990 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ |
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991 uint32_t RESERVED1[55U]; |
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992 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ |
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993 uint32_t RESERVED2[131U]; |
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994 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ |
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995 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ |
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996 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ |
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997 uint32_t RESERVED3[759U]; |
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998 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ |
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999 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ |
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1000 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ |
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1001 uint32_t RESERVED4[1U]; |
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1002 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ |
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1003 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ |
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1004 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ |
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1005 uint32_t RESERVED5[39U]; |
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1006 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ |
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1007 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ |
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1008 uint32_t RESERVED7[8U]; |
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1009 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ |
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1010 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ |
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1011 } TPI_Type; |
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1012 |
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1013 /* TPI Asynchronous Clock Prescaler Register Definitions */ |
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1014 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ |
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1015 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ |
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1016 |
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1017 /* TPI Selected Pin Protocol Register Definitions */ |
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1018 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ |
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1019 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ |
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1020 |
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1021 /* TPI Formatter and Flush Status Register Definitions */ |
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1022 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ |
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1023 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ |
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1024 |
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1025 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ |
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1026 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ |
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1027 |
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1028 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ |
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1029 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ |
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1030 |
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1031 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ |
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1032 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ |
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1033 |
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1034 /* TPI Formatter and Flush Control Register Definitions */ |
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1035 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ |
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1036 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ |
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1037 |
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1038 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ |
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1039 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ |
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1040 |
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1041 /* TPI TRIGGER Register Definitions */ |
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1042 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ |
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1043 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ |
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1044 |
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1045 /* TPI Integration ETM Data Register Definitions (FIFO0) */ |
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1046 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ |
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1047 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ |
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1048 |
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1049 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ |
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1050 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ |
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1051 |
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1052 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ |
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1053 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ |
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1054 |
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1055 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ |
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1056 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ |
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1057 |
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1058 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ |
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1059 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ |
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1060 |
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1061 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ |
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1062 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ |
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1063 |
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1064 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ |
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1065 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ |
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1066 |
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1067 /* TPI ITATBCTR2 Register Definitions */ |
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1068 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ |
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1069 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ |
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1070 |
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1071 /* TPI Integration ITM Data Register Definitions (FIFO1) */ |
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1072 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ |
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1073 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ |
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1074 |
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1075 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ |
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1076 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ |
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1077 |
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1078 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ |
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1079 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ |
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1080 |
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1081 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ |
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1082 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ |
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1083 |
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1084 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ |
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1085 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ |
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1086 |
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1087 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ |
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1088 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ |
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1089 |
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1090 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ |
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1091 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ |
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1092 |
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1093 /* TPI ITATBCTR0 Register Definitions */ |
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1094 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ |
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1095 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ |
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1096 |
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1097 /* TPI Integration Mode Control Register Definitions */ |
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1098 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ |
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1099 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ |
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1100 |
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1101 /* TPI DEVID Register Definitions */ |
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1102 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ |
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1103 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ |
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1104 |
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1105 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ |
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1106 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ |
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1107 |
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1108 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ |
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1109 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ |
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1110 |
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1111 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ |
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1112 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ |
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1113 |
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1114 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ |
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1115 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ |
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1116 |
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1117 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ |
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1118 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ |
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1119 |
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1120 /* TPI DEVTYPE Register Definitions */ |
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1121 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ |
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1122 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ |
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1123 |
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1124 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ |
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1125 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ |
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1126 |
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1127 /*@}*/ /* end of group CMSIS_TPI */ |
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1128 |
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1129 |
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1130 #if (__MPU_PRESENT == 1U) |
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1131 /** |
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1132 \ingroup CMSIS_core_register |
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1133 \defgroup CMSIS_MPU Memory Protection Unit (MPU) |
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1134 \brief Type definitions for the Memory Protection Unit (MPU) |
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1135 @{ |
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1136 */ |
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1137 |
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1138 /** |
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1139 \brief Structure type to access the Memory Protection Unit (MPU). |
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1140 */ |
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1141 typedef struct |
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1142 { |
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1143 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ |
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1144 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ |
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1145 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ |
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1146 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ |
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1147 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ |
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1148 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ |
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1149 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ |
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1150 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ |
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1151 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ |
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1152 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ |
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1153 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ |
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1154 } MPU_Type; |
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1155 |
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1156 /* MPU Type Register Definitions */ |
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1157 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ |
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1158 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ |
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1159 |
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1160 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ |
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1161 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ |
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1162 |
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1163 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ |
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1164 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ |
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1165 |
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1166 /* MPU Control Register Definitions */ |
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1167 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ |
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1168 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ |
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1169 |
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1170 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ |
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1171 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ |
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1172 |
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1173 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ |
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1174 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ |
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1175 |
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1176 /* MPU Region Number Register Definitions */ |
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1177 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ |
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1178 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ |
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1179 |
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1180 /* MPU Region Base Address Register Definitions */ |
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1181 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ |
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1182 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ |
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1183 |
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1184 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ |
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1185 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ |
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1186 |
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1187 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ |
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1188 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ |
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1189 |
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1190 /* MPU Region Attribute and Size Register Definitions */ |
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1191 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ |
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1192 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ |
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1193 |
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1194 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ |
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1195 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ |
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1196 |
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1197 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ |
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1198 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ |
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1199 |
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1200 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ |
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1201 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ |
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1202 |
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1203 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ |
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1204 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ |
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1205 |
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1206 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ |
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1207 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ |
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1208 |
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1209 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ |
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1210 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ |
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1211 |
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1212 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ |
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1213 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ |
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1214 |
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1215 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ |
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1216 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ |
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1217 |
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1218 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ |
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1219 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ |
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1220 |
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1221 /*@} end of group CMSIS_MPU */ |
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1222 #endif |
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1223 |
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1224 |
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1225 /** |
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1226 \ingroup CMSIS_core_register |
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1227 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) |
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1228 \brief Type definitions for the Core Debug Registers |
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1229 @{ |
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1230 */ |
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1231 |
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1232 /** |
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1233 \brief Structure type to access the Core Debug Register (CoreDebug). |
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1234 */ |
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1235 typedef struct |
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1236 { |
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1237 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ |
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1238 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ |
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1239 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ |
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1240 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ |
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1241 } CoreDebug_Type; |
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1242 |
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1243 /* Debug Halting Control and Status Register Definitions */ |
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1244 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ |
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1245 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ |
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1246 |
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1247 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ |
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1248 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ |
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1249 |
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1250 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ |
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1251 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ |
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1252 |
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1253 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ |
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1254 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ |
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1255 |
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1256 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ |
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1257 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ |
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1258 |
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1259 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ |
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1260 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ |
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1261 |
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1262 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ |
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1263 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ |
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1264 |
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1265 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ |
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1266 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ |
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1267 |
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1268 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ |
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1269 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ |
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1270 |
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1271 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ |
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1272 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ |
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1273 |
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1274 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ |
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1275 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ |
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1276 |
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1277 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ |
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1278 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ |
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1279 |
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1280 /* Debug Core Register Selector Register Definitions */ |
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1281 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ |
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1282 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ |
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1283 |
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1284 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ |
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1285 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ |
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1286 |
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1287 /* Debug Exception and Monitor Control Register Definitions */ |
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1288 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ |
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1289 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ |
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1290 |
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1291 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ |
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1292 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ |
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1293 |
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1294 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ |
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1295 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ |
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1296 |
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1297 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ |
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1298 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ |
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1299 |
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1300 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ |
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1301 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ |
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1302 |
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1303 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ |
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1304 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ |
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1305 |
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1306 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ |
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1307 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ |
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1308 |
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1309 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ |
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1310 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ |
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1311 |
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1312 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ |
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1313 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ |
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1314 |
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1315 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ |
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1316 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ |
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1317 |
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1318 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ |
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1319 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ |
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1320 |
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1321 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ |
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1322 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ |
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1323 |
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1324 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ |
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1325 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ |
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1326 |
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1327 /*@} end of group CMSIS_CoreDebug */ |
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1328 |
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1329 |
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1330 /** |
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1331 \ingroup CMSIS_core_register |
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1332 \defgroup CMSIS_core_bitfield Core register bit field macros |
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1333 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). |
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1334 @{ |
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1335 */ |
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1336 |
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1337 /** |
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1338 \brief Mask and shift a bit field value for use in a register bit range. |
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1339 \param[in] field Name of the register bit field. |
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1340 \param[in] value Value of the bit field. |
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1341 \return Masked and shifted value. |
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1342 */ |
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1343 #define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) |
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1344 |
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1345 /** |
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1346 \brief Mask and shift a register value to extract a bit filed value. |
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1347 \param[in] field Name of the register bit field. |
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1348 \param[in] value Value of register. |
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1349 \return Masked and shifted bit field value. |
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1350 */ |
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1351 #define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) |
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1352 |
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1353 /*@} end of group CMSIS_core_bitfield */ |
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1354 |
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1355 |
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1356 /** |
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1357 \ingroup CMSIS_core_register |
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1358 \defgroup CMSIS_core_base Core Definitions |
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1359 \brief Definitions for base addresses, unions, and structures. |
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1360 @{ |
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1361 */ |
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1362 |
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1363 /* Memory mapping of Cortex-M3 Hardware */ |
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1364 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ |
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1365 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ |
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1366 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ |
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1367 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ |
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1368 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ |
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1369 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ |
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1370 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ |
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1371 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ |
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1372 |
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1373 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ |
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1374 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ |
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1375 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ |
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1376 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ |
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1377 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ |
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1378 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ |
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1379 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ |
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1380 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ |
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1381 |
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1382 #if (__MPU_PRESENT == 1U) |
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1383 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ |
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1384 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ |
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1385 #endif |
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1386 |
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1387 /*@} */ |
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1388 |
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1389 |
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1390 |
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1391 /******************************************************************************* |
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1392 * Hardware Abstraction Layer |
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1393 Core Function Interface contains: |
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1394 - Core NVIC Functions |
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1395 - Core SysTick Functions |
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1396 - Core Debug Functions |
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1397 - Core Register Access Functions |
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1398 ******************************************************************************/ |
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1399 /** |
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1400 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference |
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1401 */ |
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1402 |
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1403 |
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1404 |
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1405 /* ########################## NVIC functions #################################### */ |
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1406 /** |
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1407 \ingroup CMSIS_Core_FunctionInterface |
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1408 \defgroup CMSIS_Core_NVICFunctions NVIC Functions |
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1409 \brief Functions that manage interrupts and exceptions via the NVIC. |
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1410 @{ |
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1411 */ |
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1412 |
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1413 /** |
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1414 \brief Set Priority Grouping |
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1415 \details Sets the priority grouping field using the required unlock sequence. |
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1416 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. |
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1417 Only values from 0..7 are used. |
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1418 In case of a conflict between priority grouping and available |
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1419 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. |
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1420 \param [in] PriorityGroup Priority grouping field. |
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1421 */ |
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1422 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) |
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1423 { |
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1424 uint32_t reg_value; |
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1425 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ |
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1426 |
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1427 reg_value = SCB->AIRCR; /* read old register configuration */ |
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1428 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ |
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1429 reg_value = (reg_value | |
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1430 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | |
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1431 (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ |
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1432 SCB->AIRCR = reg_value; |
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1433 } |
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1434 |
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1435 |
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1436 /** |
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1437 \brief Get Priority Grouping |
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1438 \details Reads the priority grouping field from the NVIC Interrupt Controller. |
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1439 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). |
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1440 */ |
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1441 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) |
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1442 { |
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1443 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); |
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1444 } |
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1445 |
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1446 |
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1447 /** |
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1448 \brief Enable External Interrupt |
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1449 \details Enables a device-specific interrupt in the NVIC interrupt controller. |
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1450 \param [in] IRQn External interrupt number. Value cannot be negative. |
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1451 */ |
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1452 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) |
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1453 { |
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1454 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
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1455 } |
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1456 |
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1457 |
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1458 /** |
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1459 \brief Disable External Interrupt |
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1460 \details Disables a device-specific interrupt in the NVIC interrupt controller. |
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1461 \param [in] IRQn External interrupt number. Value cannot be negative. |
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1462 */ |
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1463 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) |
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1464 { |
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1465 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
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1466 } |
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1467 |
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1468 |
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1469 /** |
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1470 \brief Get Pending Interrupt |
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1471 \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. |
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1472 \param [in] IRQn Interrupt number. |
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1473 \return 0 Interrupt status is not pending. |
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1474 \return 1 Interrupt status is pending. |
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1475 */ |
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1476 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) |
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1477 { |
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1478 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
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1479 } |
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1480 |
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1481 |
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1482 /** |
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1483 \brief Set Pending Interrupt |
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1484 \details Sets the pending bit of an external interrupt. |
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1485 \param [in] IRQn Interrupt number. Value cannot be negative. |
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1486 */ |
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1487 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) |
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1488 { |
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1489 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
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1490 } |
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1491 |
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1492 |
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1493 /** |
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1494 \brief Clear Pending Interrupt |
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1495 \details Clears the pending bit of an external interrupt. |
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1496 \param [in] IRQn External interrupt number. Value cannot be negative. |
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1497 */ |
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1498 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
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1499 { |
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1500 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
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1501 } |
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1502 |
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1503 |
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1504 /** |
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1505 \brief Get Active Interrupt |
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1506 \details Reads the active register in NVIC and returns the active bit. |
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1507 \param [in] IRQn Interrupt number. |
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1508 \return 0 Interrupt status is not active. |
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1509 \return 1 Interrupt status is active. |
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1510 */ |
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1511 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) |
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1512 { |
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1513 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
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1514 } |
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1515 |
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1516 |
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1517 /** |
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1518 \brief Set Interrupt Priority |
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1519 \details Sets the priority of an interrupt. |
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1520 \note The priority cannot be set for every core interrupt. |
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1521 \param [in] IRQn Interrupt number. |
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1522 \param [in] priority Priority to set. |
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1523 */ |
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1524 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
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1525 { |
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1526 if ((int32_t)(IRQn) < 0) |
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1527 { |
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1528 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); |
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1529 } |
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1530 else |
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1531 { |
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1532 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); |
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1533 } |
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1534 } |
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1535 |
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1536 |
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1537 /** |
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1538 \brief Get Interrupt Priority |
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1539 \details Reads the priority of an interrupt. |
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1540 The interrupt number can be positive to specify an external (device specific) interrupt, |
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1541 or negative to specify an internal (core) interrupt. |
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1542 \param [in] IRQn Interrupt number. |
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1543 \return Interrupt Priority. |
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1544 Value is aligned automatically to the implemented priority bits of the microcontroller. |
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1545 */ |
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1546 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) |
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1547 { |
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1548 |
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1549 if ((int32_t)(IRQn) < 0) |
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1550 { |
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1551 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); |
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1552 } |
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1553 else |
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1554 { |
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1555 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); |
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1556 } |
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1557 } |
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1558 |
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1559 |
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1560 /** |
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1561 \brief Encode Priority |
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1562 \details Encodes the priority for an interrupt with the given priority group, |
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1563 preemptive priority value, and subpriority value. |
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1564 In case of a conflict between priority grouping and available |
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1565 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. |
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1566 \param [in] PriorityGroup Used priority group. |
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1567 \param [in] PreemptPriority Preemptive priority value (starting from 0). |
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1568 \param [in] SubPriority Subpriority value (starting from 0). |
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1569 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). |
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1570 */ |
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1571 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) |
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1572 { |
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1573 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ |
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1574 uint32_t PreemptPriorityBits; |
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1575 uint32_t SubPriorityBits; |
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1576 |
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1577 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); |
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1578 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); |
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1579 |
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1580 return ( |
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1581 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | |
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1582 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) |
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1583 ); |
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1584 } |
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1585 |
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1586 |
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1587 /** |
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1588 \brief Decode Priority |
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1589 \details Decodes an interrupt priority value with a given priority group to |
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1590 preemptive priority value and subpriority value. |
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1591 In case of a conflict between priority grouping and available |
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1592 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. |
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1593 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). |
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1594 \param [in] PriorityGroup Used priority group. |
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1595 \param [out] pPreemptPriority Preemptive priority value (starting from 0). |
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1596 \param [out] pSubPriority Subpriority value (starting from 0). |
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1597 */ |
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1598 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) |
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1599 { |
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1600 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ |
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1601 uint32_t PreemptPriorityBits; |
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1602 uint32_t SubPriorityBits; |
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1603 |
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1604 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); |
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1605 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); |
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1606 |
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1607 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); |
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1608 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); |
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1609 } |
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1610 |
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1611 |
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1612 /** |
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1613 \brief System Reset |
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1614 \details Initiates a system reset request to reset the MCU. |
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1615 */ |
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1616 __STATIC_INLINE void NVIC_SystemReset(void) |
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1617 { |
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1618 __DSB(); /* Ensure all outstanding memory accesses included |
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1619 buffered write are completed before reset */ |
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1620 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | |
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1621 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | |
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1622 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ |
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1623 __DSB(); /* Ensure completion of memory access */ |
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1624 |
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1625 for(;;) /* wait until reset */ |
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1626 { |
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1627 __NOP(); |
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1628 } |
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1629 } |
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1630 |
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1631 /*@} end of CMSIS_Core_NVICFunctions */ |
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1632 |
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1633 |
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1634 |
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1635 /* ################################## SysTick function ############################################ */ |
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1636 /** |
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1637 \ingroup CMSIS_Core_FunctionInterface |
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1638 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions |
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1639 \brief Functions that configure the System. |
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1640 @{ |
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1641 */ |
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1642 |
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1643 #if (__Vendor_SysTickConfig == 0U) |
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1644 |
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1645 /** |
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1646 \brief System Tick Configuration |
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1647 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. |
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1648 Counter is in free running mode to generate periodic interrupts. |
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1649 \param [in] ticks Number of ticks between two interrupts. |
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1650 \return 0 Function succeeded. |
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1651 \return 1 Function failed. |
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1652 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the |
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1653 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> |
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1654 must contain a vendor-specific implementation of this function. |
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1655 */ |
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1656 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) |
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1657 { |
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1658 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) |
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1659 { |
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1660 return (1UL); /* Reload value impossible */ |
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1661 } |
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1662 |
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1663 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ |
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1664 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ |
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1665 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ |
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1666 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | |
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1667 SysTick_CTRL_TICKINT_Msk | |
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1668 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ |
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1669 return (0UL); /* Function successful */ |
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1670 } |
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1671 |
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1672 #endif |
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1673 |
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1674 /*@} end of CMSIS_Core_SysTickFunctions */ |
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1675 |
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1676 |
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1677 |
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1678 /* ##################################### Debug In/Output function ########################################### */ |
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1679 /** |
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1680 \ingroup CMSIS_Core_FunctionInterface |
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1681 \defgroup CMSIS_core_DebugFunctions ITM Functions |
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1682 \brief Functions that access the ITM debug interface. |
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1683 @{ |
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1684 */ |
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1685 |
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1686 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ |
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1687 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ |
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1688 |
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1689 |
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1690 /** |
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1691 \brief ITM Send Character |
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1692 \details Transmits a character via the ITM channel 0, and |
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1693 \li Just returns when no debugger is connected that has booked the output. |
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1694 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. |
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1695 \param [in] ch Character to transmit. |
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1696 \returns Character to transmit. |
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1697 */ |
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1698 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) |
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1699 { |
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1700 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ |
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1701 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ |
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1702 { |
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1703 while (ITM->PORT[0U].u32 == 0UL) |
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1704 { |
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1705 __NOP(); |
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1706 } |
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1707 ITM->PORT[0U].u8 = (uint8_t)ch; |
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1708 } |
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1709 return (ch); |
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1710 } |
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1711 |
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1712 |
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1713 /** |
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1714 \brief ITM Receive Character |
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1715 \details Inputs a character via the external variable \ref ITM_RxBuffer. |
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1716 \return Received character. |
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1717 \return -1 No character pending. |
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1718 */ |
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1719 __STATIC_INLINE int32_t ITM_ReceiveChar (void) |
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1720 { |
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1721 int32_t ch = -1; /* no character available */ |
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1722 |
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1723 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) |
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1724 { |
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1725 ch = ITM_RxBuffer; |
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1726 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ |
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1727 } |
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1728 |
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1729 return (ch); |
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1730 } |
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1731 |
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1732 |
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1733 /** |
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1734 \brief ITM Check Character |
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1735 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. |
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1736 \return 0 No character available. |
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1737 \return 1 Character available. |
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1738 */ |
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1739 __STATIC_INLINE int32_t ITM_CheckChar (void) |
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1740 { |
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1741 |
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1742 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) |
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1743 { |
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1744 return (0); /* no character available */ |
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1745 } |
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1746 else |
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1747 { |
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1748 return (1); /* character available */ |
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1749 } |
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1750 } |
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1751 |
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1752 /*@} end of CMSIS_core_DebugFunctions */ |
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1753 |
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1754 |
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1755 |
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1756 |
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1757 #ifdef __cplusplus |
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1758 } |
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1759 #endif |
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1760 |
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1761 #endif /* __CORE_CM3_H_DEPENDANT */ |
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1762 |
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1763 #endif /* __CMSIS_GENERIC */ |