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annotate Common/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c @ 949:c6b858f2e025 Evo_2_23 tip

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GNSS UTC in Date-Time menu: The UTC time provided by the gnss module is not shown in the date-time settings menu. If a valid time signal is available then the OSTC RTC may be set to it by selecting the UTC menu entry. The time zone has to be selected manually. This is possible using a separate edit line.
author Ideenmodellierer
date Sun, 22 Dec 2024 21:19:21 +0100
parents c78bcbd5deda
children
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1 /**
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2 ******************************************************************************
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3 * @file stm32f4xx_hal_iwdg.c
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4 * @author MCD Application Team
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5 * @brief IWDG HAL module driver.
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6 * This file provides firmware functions to manage the following
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7 * functionalities of the Independent Watchdog (IWDG) peripheral:
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8 * + Initialization and Start functions
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9 * + IO operation functions
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10 *
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11 @verbatim
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12 ==============================================================================
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13 ##### IWDG Generic features #####
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14 ==============================================================================
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15 [..]
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16 (+) The IWDG can be started by either software or hardware (configurable
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17 through option byte).
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18
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19 (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
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20 if the main clock fails.
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21
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22 (+) Once the IWDG is started, the LSI is forced ON and both can not be
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23 disabled. The counter starts counting down from the reset value (0xFFF).
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24 When it reaches the end of count value (0x000) a reset signal is
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25 generated (IWDG reset).
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26
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27 (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
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28 the IWDG_RLR value is reloaded in the counter and the watchdog reset is
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29 prevented.
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30
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31 (+) The IWDG is implemented in the VDD voltage domain that is still functional
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32 in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
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33 IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
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34 reset occurs.
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35
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36 (+) Debug mode : When the microcontroller enters debug mode (core halted),
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37 the IWDG counter either continues to work normally or stops, depending
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38 on DBG_IWDG_STOP configuration bit in DBG module, accessible through
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39 __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros
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40
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41 [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
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42 The IWDG timeout may vary due to LSI frequency dispersion. STM32F4xx
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43 devices provide the capability to measure the LSI frequency (LSI clock
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44 connected internally to TIM5 CH4 input capture). The measured value
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45 can be used to have an IWDG timeout with an acceptable accuracy.
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46
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47 ##### How to use this driver #####
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48 ==============================================================================
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49 [..]
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50 (#) Use IWDG using HAL_IWDG_Init() function to :
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51 (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
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52 clock is forced ON and IWDG counter starts downcounting.
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53 (++) Enable write access to configuration register: IWDG_PR & IWDG_RLR.
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54 (++) Configure the IWDG prescaler and counter reload value. This reload
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55 value will be loaded in the IWDG counter each time the watchdog is
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56 reloaded, then the IWDG will start counting down from this value.
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57 (++) wait for status flags to be reset"
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58
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59 (#) Then the application program must refresh the IWDG counter at regular
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60 intervals during normal operation to prevent an MCU reset, using
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61 HAL_IWDG_Refresh() function.
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62
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63 *** IWDG HAL driver macros list ***
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64 ====================================
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65 [..]
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66 Below the list of most used macros in IWDG HAL driver:
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67 (+) __HAL_IWDG_START: Enable the IWDG peripheral
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68 (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
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69 the reload register
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70
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71 @endverbatim
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72 ******************************************************************************
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73 * @attention
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74 *
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75 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
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76 *
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77 * Redistribution and use in source and binary forms, with or without modification,
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78 * are permitted provided that the following conditions are met:
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79 * 1. Redistributions of source code must retain the above copyright notice,
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80 * this list of conditions and the following disclaimer.
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81 * 2. Redistributions in binary form must reproduce the above copyright notice,
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82 * this list of conditions and the following disclaimer in the documentation
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83 * and/or other materials provided with the distribution
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84 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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85 * may be used to endorse or promote products derived from this software
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86 * without specific prior written permission.
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87 *
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88 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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89 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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90 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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91 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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92 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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93 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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94 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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95 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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96 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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97 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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98 *
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99 ******************************************************************************
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100 */
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101
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102 /* Includes ------------------------------------------------------------------*/
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103 #include "stm32f4xx_hal.h"
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104
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105 /** @addtogroup STM32F4xx_HAL_Driver
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106 * @{
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107 */
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108
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109 #ifdef HAL_IWDG_MODULE_ENABLED
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110 /** @defgroup IWDG IWDG
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111 * @brief IWDG HAL module driver.
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112 * @{
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113 */
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114
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115 /* Private typedef -----------------------------------------------------------*/
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116 /* Private define ------------------------------------------------------------*/
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117 /** @defgroup IWDG_Private_Defines IWDG Private Defines
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118 * @{
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119 */
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120 /* Status register need 5 RC LSI divided by prescaler clock to be updated. With
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121 higher prescaler (256), and according to HSI variation, we need to wait at
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122 least 6 cycles so 48 ms. */
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123 #define HAL_IWDG_DEFAULT_TIMEOUT 48U
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124 /**
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125 * @}
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126 */
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127
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128 /* Private macro -------------------------------------------------------------*/
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129 /* Private variables ---------------------------------------------------------*/
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130 /* Private function prototypes -----------------------------------------------*/
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131 /* Exported functions --------------------------------------------------------*/
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132
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133 /** @addtogroup IWDG_Exported_Functions
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134 * @{
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135 */
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136
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137 /** @addtogroup IWDG_Exported_Functions_Group1
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138 * @brief Initialization and Start functions.
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139 *
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140 @verbatim
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141 ===============================================================================
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142 ##### Initialization and Start functions #####
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143 ===============================================================================
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144 [..] This section provides functions allowing to:
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145 (+) Initialize the IWDG according to the specified parameters in the
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146 IWDG_InitTypeDef of associated handle.
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147 (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
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148 is reloaded in order to exit function with correct time base.
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149
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150 @endverbatim
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151 * @{
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152 */
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153
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154 /**
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155 * @brief Initialize the IWDG according to the specified parameters in the
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156 * IWDG_InitTypeDef and start watchdog. Before exiting function,
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157 * watchdog is refreshed in order to have correct time base.
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158 * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
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159 * the configuration information for the specified IWDG module.
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160 * @retval HAL status
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161 */
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162 HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
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163 {
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164 uint32_t tickstart;
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165
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166 /* Check the IWDG handle allocation */
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167 if(hiwdg == NULL)
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168 {
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169 return HAL_ERROR;
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170 }
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171
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172 /* Check the parameters */
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173 assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
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174 assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
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175 assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
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176
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177 /* Enable IWDG. LSI is turned on automaticaly */
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178 __HAL_IWDG_START(hiwdg);
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179
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180 /* Enable write access to IWDG_PR and IWDG_RLR registers by writing 0x5555 in KR */
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181 IWDG_ENABLE_WRITE_ACCESS(hiwdg);
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182
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183 /* Write to IWDG registers the Prescaler & Reload values to work with */
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184 hiwdg->Instance->PR = hiwdg->Init.Prescaler;
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185 hiwdg->Instance->RLR = hiwdg->Init.Reload;
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186
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187 /* Check pending flag, if previous update not done, return timeout */
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188 tickstart = HAL_GetTick();
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189
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190 /* Wait for register to be updated */
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191 while(hiwdg->Instance->SR != RESET)
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192 {
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193 if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
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194 {
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195 return HAL_TIMEOUT;
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196 }
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197 }
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198
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199 /* Reload IWDG counter with value defined in the reload register */
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200 __HAL_IWDG_RELOAD_COUNTER(hiwdg);
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201
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202 /* Return function status */
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203 return HAL_OK;
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204 }
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205
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206 /**
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207 * @}
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208 */
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209
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210 /** @addtogroup IWDG_Exported_Functions_Group2
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211 * @brief IO operation functions
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212 *
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213 @verbatim
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214 ===============================================================================
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215 ##### IO operation functions #####
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216 ===============================================================================
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217 [..] This section provides functions allowing to:
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218 (+) Refresh the IWDG.
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219
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220 @endverbatim
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221 * @{
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222 */
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223
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224 /**
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225 * @brief Refresh the IWDG.
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226 * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
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227 * the configuration information for the specified IWDG module.
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228 * @retval HAL status
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229 */
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230 HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
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231 {
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232 /* Reload IWDG counter with value defined in the reload register */
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233 __HAL_IWDG_RELOAD_COUNTER(hiwdg);
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234
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235 /* Return function status */
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236 return HAL_OK;
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237 }
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238
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239 /**
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240 * @}
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241 */
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242
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243 /**
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244 * @}
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245 */
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246
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247 #endif /* HAL_IWDG_MODULE_ENABLED */
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248 /**
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249 * @}
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250 */
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251
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252 /**
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253 * @}
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254 */
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255
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256 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/