38
+ − 1 /**
+ − 2 ******************************************************************************
+ − 3 * @file stm32f429xx.h
+ − 4 * @author MCD Application Team
+ − 5 * @version V2.2.0
+ − 6 * @date 15-December-2014
+ − 7 * @brief CMSIS STM32F429xx Device Peripheral Access Layer Header File.
+ − 8 *
+ − 9 * This file contains:
+ − 10 * - Data structures and the address mapping for all peripherals
+ − 11 * - Peripheral's registers declarations and bits definition
+ − 12 * - Macros to access peripheral’s registers hardware
+ − 13 *
+ − 14 ******************************************************************************
+ − 15 * @attention
+ − 16 *
+ − 17 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ − 18 *
+ − 19 * Redistribution and use in source and binary forms, with or without modification,
+ − 20 * are permitted provided that the following conditions are met:
+ − 21 * 1. Redistributions of source code must retain the above copyright notice,
+ − 22 * this list of conditions and the following disclaimer.
+ − 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
+ − 24 * this list of conditions and the following disclaimer in the documentation
+ − 25 * and/or other materials provided with the distribution.
+ − 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ − 27 * may be used to endorse or promote products derived from this software
+ − 28 * without specific prior written permission.
+ − 29 *
+ − 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ − 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ − 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ − 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ − 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ − 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ − 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ − 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ − 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ − 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ − 40 *
+ − 41 ******************************************************************************
+ − 42 */
+ − 43
+ − 44 /** @addtogroup CMSIS_Device
+ − 45 * @{
+ − 46 */
+ − 47
+ − 48 /** @addtogroup stm32f429xx
+ − 49 * @{
+ − 50 */
+ − 51
+ − 52 #ifndef __STM32F429xx_H
+ − 53 #define __STM32F429xx_H
+ − 54
+ − 55 #ifdef __cplusplus
+ − 56 extern "C" {
+ − 57 #endif /* __cplusplus */
+ − 58
+ − 59 /** @addtogroup Configuration_section_for_CMSIS
+ − 60 * @{
+ − 61 */
+ − 62
+ − 63 /**
+ − 64 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ − 65 */
+ − 66 #define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+ − 67 #define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
+ − 68 #define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+ − 69 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+ − 70 #define __FPU_PRESENT 1 /*!< FPU present */
+ − 71
+ − 72 /**
+ − 73 * @}
+ − 74 */
+ − 75
+ − 76 /** @addtogroup Peripheral_interrupt_number_definition
+ − 77 * @{
+ − 78 */
+ − 79
+ − 80 /**
+ − 81 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ − 82 * in @ref Library_configuration_section
+ − 83 */
+ − 84 typedef enum
+ − 85 {
+ − 86 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ − 87 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ − 88 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ − 89 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ − 90 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ − 91 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ − 92 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ − 93 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ − 94 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+ − 95 /****** STM32 specific Interrupt Numbers **********************************************************************/
+ − 96 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ − 97 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ − 98 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ − 99 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ − 100 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ − 101 RCC_IRQn = 5, /*!< RCC global Interrupt */
+ − 102 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ − 103 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ − 104 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ − 105 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ − 106 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ − 107 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ − 108 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ − 109 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ − 110 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ − 111 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ − 112 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ − 113 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ − 114 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
+ − 115 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
+ − 116 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
+ − 117 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ − 118 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ − 119 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ − 120 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ − 121 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ − 122 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ − 123 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ − 124 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ − 125 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ − 126 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ − 127 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ − 128 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ − 129 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ − 130 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ − 131 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ − 132 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ − 133 USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ − 134 USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ − 135 USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ − 136 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ − 137 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ − 138 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ − 139 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
+ − 140 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
+ − 141 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+ − 142 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
+ − 143 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ − 144 FMC_IRQn = 48, /*!< FMC global Interrupt */
+ − 145 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ − 146 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ − 147 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ − 148 UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ − 149 UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ − 150 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
+ − 151 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
+ − 152 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ − 153 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ − 154 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ − 155 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ − 156 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ − 157 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
+ − 158 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
+ − 159 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
+ − 160 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
+ − 161 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
+ − 162 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
+ − 163 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ − 164 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ − 165 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ − 166 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ − 167 USART6_IRQn = 71, /*!< USART6 global interrupt */
+ − 168 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ − 169 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ − 170 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
+ − 171 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
+ − 172 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
+ − 173 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
+ − 174 DCMI_IRQn = 78, /*!< DCMI global interrupt */
+ − 175 HASH_RNG_IRQn = 80, /*!< Hash and RNG global interrupt */
+ − 176 FPU_IRQn = 81, /*!< FPU global interrupt */
+ − 177 UART7_IRQn = 82, /*!< UART7 global interrupt */
+ − 178 UART8_IRQn = 83, /*!< UART8 global interrupt */
+ − 179 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
+ − 180 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
+ − 181 SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
+ − 182 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
+ − 183 LTDC_IRQn = 88, /*!< LTDC global Interrupt */
+ − 184 LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
+ − 185 DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */
+ − 186 } IRQn_Type;
+ − 187
+ − 188 /**
+ − 189 * @}
+ − 190 */
+ − 191
+ − 192 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+ − 193 #include "system_stm32f4xx.h"
+ − 194 #include <stdint.h>
+ − 195
+ − 196 /** @addtogroup Peripheral_registers_structures
+ − 197 * @{
+ − 198 */
+ − 199
+ − 200 /**
+ − 201 * @brief Analog to Digital Converter
+ − 202 */
+ − 203
+ − 204 typedef struct
+ − 205 {
+ − 206 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ − 207 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ − 208 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ − 209 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ − 210 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ − 211 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ − 212 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ − 213 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ − 214 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ − 215 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ − 216 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ − 217 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ − 218 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ − 219 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ − 220 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ − 221 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ − 222 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ − 223 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ − 224 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ − 225 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+ − 226 } ADC_TypeDef;
+ − 227
+ − 228 typedef struct
+ − 229 {
+ − 230 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ − 231 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ − 232 __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ − 233 AND triple modes, Address offset: ADC1 base address + 0x308 */
+ − 234 } ADC_Common_TypeDef;
+ − 235
+ − 236
+ − 237 /**
+ − 238 * @brief Controller Area Network TxMailBox
+ − 239 */
+ − 240
+ − 241 typedef struct
+ − 242 {
+ − 243 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ − 244 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ − 245 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ − 246 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+ − 247 } CAN_TxMailBox_TypeDef;
+ − 248
+ − 249 /**
+ − 250 * @brief Controller Area Network FIFOMailBox
+ − 251 */
+ − 252
+ − 253 typedef struct
+ − 254 {
+ − 255 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ − 256 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ − 257 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ − 258 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+ − 259 } CAN_FIFOMailBox_TypeDef;
+ − 260
+ − 261 /**
+ − 262 * @brief Controller Area Network FilterRegister
+ − 263 */
+ − 264
+ − 265 typedef struct
+ − 266 {
+ − 267 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ − 268 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+ − 269 } CAN_FilterRegister_TypeDef;
+ − 270
+ − 271 /**
+ − 272 * @brief Controller Area Network
+ − 273 */
+ − 274
+ − 275 typedef struct
+ − 276 {
+ − 277 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ − 278 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ − 279 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ − 280 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ − 281 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ − 282 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ − 283 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ − 284 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ − 285 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ − 286 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ − 287 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ − 288 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ − 289 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ − 290 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ − 291 uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ − 292 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ − 293 uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ − 294 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ − 295 uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ − 296 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ − 297 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ − 298 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+ − 299 } CAN_TypeDef;
+ − 300
+ − 301 /**
+ − 302 * @brief CRC calculation unit
+ − 303 */
+ − 304
+ − 305 typedef struct
+ − 306 {
+ − 307 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ − 308 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ − 309 uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ − 310 uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ − 311 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+ − 312 } CRC_TypeDef;
+ − 313
+ − 314 /**
+ − 315 * @brief Digital to Analog Converter
+ − 316 */
+ − 317
+ − 318 typedef struct
+ − 319 {
+ − 320 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ − 321 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ − 322 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ − 323 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ − 324 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ − 325 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ − 326 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ − 327 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ − 328 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ − 329 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ − 330 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ − 331 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ − 332 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ − 333 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+ − 334 } DAC_TypeDef;
+ − 335
+ − 336 /**
+ − 337 * @brief Debug MCU
+ − 338 */
+ − 339
+ − 340 typedef struct
+ − 341 {
+ − 342 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ − 343 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ − 344 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ − 345 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+ − 346 }DBGMCU_TypeDef;
+ − 347
+ − 348 /**
+ − 349 * @brief DCMI
+ − 350 */
+ − 351
+ − 352 typedef struct
+ − 353 {
+ − 354 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
+ − 355 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
+ − 356 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
+ − 357 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
+ − 358 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
+ − 359 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
+ − 360 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
+ − 361 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+ − 362 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
+ − 363 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
+ − 364 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
+ − 365 } DCMI_TypeDef;
+ − 366
+ − 367 /**
+ − 368 * @brief DMA Controller
+ − 369 */
+ − 370
+ − 371 typedef struct
+ − 372 {
+ − 373 __IO uint32_t CR; /*!< DMA stream x configuration register */
+ − 374 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ − 375 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ − 376 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ − 377 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ − 378 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+ − 379 } DMA_Stream_TypeDef;
+ − 380
+ − 381 typedef struct
+ − 382 {
+ − 383 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ − 384 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ − 385 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ − 386 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+ − 387 } DMA_TypeDef;
+ − 388
+ − 389 /**
+ − 390 * @brief DMA2D Controller
+ − 391 */
+ − 392
+ − 393 typedef struct
+ − 394 {
+ − 395 __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
+ − 396 __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
+ − 397 __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
+ − 398 __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
+ − 399 __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
+ − 400 __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
+ − 401 __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
+ − 402 __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
+ − 403 __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
+ − 404 __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
+ − 405 __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
+ − 406 __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
+ − 407 __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
+ − 408 __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
+ − 409 __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
+ − 410 __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
+ − 411 __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
+ − 412 __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
+ − 413 __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
+ − 414 __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
+ − 415 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
+ − 416 __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
+ − 417 __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
+ − 418 } DMA2D_TypeDef;
+ − 419
+ − 420 /**
+ − 421 * @brief Ethernet MAC
+ − 422 */
+ − 423
+ − 424 typedef struct
+ − 425 {
+ − 426 __IO uint32_t MACCR;
+ − 427 __IO uint32_t MACFFR;
+ − 428 __IO uint32_t MACHTHR;
+ − 429 __IO uint32_t MACHTLR;
+ − 430 __IO uint32_t MACMIIAR;
+ − 431 __IO uint32_t MACMIIDR;
+ − 432 __IO uint32_t MACFCR;
+ − 433 __IO uint32_t MACVLANTR; /* 8 */
+ − 434 uint32_t RESERVED0[2];
+ − 435 __IO uint32_t MACRWUFFR; /* 11 */
+ − 436 __IO uint32_t MACPMTCSR;
+ − 437 uint32_t RESERVED1[2];
+ − 438 __IO uint32_t MACSR; /* 15 */
+ − 439 __IO uint32_t MACIMR;
+ − 440 __IO uint32_t MACA0HR;
+ − 441 __IO uint32_t MACA0LR;
+ − 442 __IO uint32_t MACA1HR;
+ − 443 __IO uint32_t MACA1LR;
+ − 444 __IO uint32_t MACA2HR;
+ − 445 __IO uint32_t MACA2LR;
+ − 446 __IO uint32_t MACA3HR;
+ − 447 __IO uint32_t MACA3LR; /* 24 */
+ − 448 uint32_t RESERVED2[40];
+ − 449 __IO uint32_t MMCCR; /* 65 */
+ − 450 __IO uint32_t MMCRIR;
+ − 451 __IO uint32_t MMCTIR;
+ − 452 __IO uint32_t MMCRIMR;
+ − 453 __IO uint32_t MMCTIMR; /* 69 */
+ − 454 uint32_t RESERVED3[14];
+ − 455 __IO uint32_t MMCTGFSCCR; /* 84 */
+ − 456 __IO uint32_t MMCTGFMSCCR;
+ − 457 uint32_t RESERVED4[5];
+ − 458 __IO uint32_t MMCTGFCR;
+ − 459 uint32_t RESERVED5[10];
+ − 460 __IO uint32_t MMCRFCECR;
+ − 461 __IO uint32_t MMCRFAECR;
+ − 462 uint32_t RESERVED6[10];
+ − 463 __IO uint32_t MMCRGUFCR;
+ − 464 uint32_t RESERVED7[334];
+ − 465 __IO uint32_t PTPTSCR;
+ − 466 __IO uint32_t PTPSSIR;
+ − 467 __IO uint32_t PTPTSHR;
+ − 468 __IO uint32_t PTPTSLR;
+ − 469 __IO uint32_t PTPTSHUR;
+ − 470 __IO uint32_t PTPTSLUR;
+ − 471 __IO uint32_t PTPTSAR;
+ − 472 __IO uint32_t PTPTTHR;
+ − 473 __IO uint32_t PTPTTLR;
+ − 474 __IO uint32_t RESERVED8;
+ − 475 __IO uint32_t PTPTSSR;
+ − 476 uint32_t RESERVED9[565];
+ − 477 __IO uint32_t DMABMR;
+ − 478 __IO uint32_t DMATPDR;
+ − 479 __IO uint32_t DMARPDR;
+ − 480 __IO uint32_t DMARDLAR;
+ − 481 __IO uint32_t DMATDLAR;
+ − 482 __IO uint32_t DMASR;
+ − 483 __IO uint32_t DMAOMR;
+ − 484 __IO uint32_t DMAIER;
+ − 485 __IO uint32_t DMAMFBOCR;
+ − 486 __IO uint32_t DMARSWTR;
+ − 487 uint32_t RESERVED10[8];
+ − 488 __IO uint32_t DMACHTDR;
+ − 489 __IO uint32_t DMACHRDR;
+ − 490 __IO uint32_t DMACHTBAR;
+ − 491 __IO uint32_t DMACHRBAR;
+ − 492 } ETH_TypeDef;
+ − 493
+ − 494 /**
+ − 495 * @brief External Interrupt/Event Controller
+ − 496 */
+ − 497
+ − 498 typedef struct
+ − 499 {
+ − 500 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ − 501 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ − 502 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ − 503 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ − 504 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ − 505 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+ − 506 } EXTI_TypeDef;
+ − 507
+ − 508 /**
+ − 509 * @brief FLASH Registers
+ − 510 */
+ − 511
+ − 512 typedef struct
+ − 513 {
+ − 514 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ − 515 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ − 516 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ − 517 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ − 518 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ − 519 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ − 520 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+ − 521 } FLASH_TypeDef;
+ − 522
+ − 523 /**
+ − 524 * @brief Flexible Memory Controller
+ − 525 */
+ − 526
+ − 527 typedef struct
+ − 528 {
+ − 529 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+ − 530 } FMC_Bank1_TypeDef;
+ − 531
+ − 532 /**
+ − 533 * @brief Flexible Memory Controller Bank1E
+ − 534 */
+ − 535
+ − 536 typedef struct
+ − 537 {
+ − 538 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+ − 539 } FMC_Bank1E_TypeDef;
+ − 540
+ − 541 /**
+ − 542 * @brief Flexible Memory Controller Bank2
+ − 543 */
+ − 544
+ − 545 typedef struct
+ − 546 {
+ − 547 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
+ − 548 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
+ − 549 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
+ − 550 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
+ − 551 uint32_t RESERVED0; /*!< Reserved, 0x70 */
+ − 552 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
+ − 553 uint32_t RESERVED1; /*!< Reserved, 0x78 */
+ − 554 uint32_t RESERVED2; /*!< Reserved, 0x7C */
+ − 555 __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
+ − 556 __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
+ − 557 __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
+ − 558 __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
+ − 559 uint32_t RESERVED3; /*!< Reserved, 0x90 */
+ − 560 __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
+ − 561 } FMC_Bank2_3_TypeDef;
+ − 562
+ − 563 /**
+ − 564 * @brief Flexible Memory Controller Bank4
+ − 565 */
+ − 566
+ − 567 typedef struct
+ − 568 {
+ − 569 __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
+ − 570 __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
+ − 571 __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
+ − 572 __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
+ − 573 __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
+ − 574 } FMC_Bank4_TypeDef;
+ − 575
+ − 576 /**
+ − 577 * @brief Flexible Memory Controller Bank5_6
+ − 578 */
+ − 579
+ − 580 typedef struct
+ − 581 {
+ − 582 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
+ − 583 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
+ − 584 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
+ − 585 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
+ − 586 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
+ − 587 } FMC_Bank5_6_TypeDef;
+ − 588
+ − 589 /**
+ − 590 * @brief General Purpose I/O
+ − 591 */
+ − 592
+ − 593 typedef struct
+ − 594 {
+ − 595 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ − 596 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ − 597 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ − 598 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ − 599 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ − 600 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ − 601 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ − 602 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ − 603 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+ − 604 } GPIO_TypeDef;
+ − 605
+ − 606 /**
+ − 607 * @brief System configuration controller
+ − 608 */
+ − 609
+ − 610 typedef struct
+ − 611 {
+ − 612 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ − 613 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ − 614 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ − 615 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ − 616 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+ − 617 } SYSCFG_TypeDef;
+ − 618
+ − 619 /**
+ − 620 * @brief Inter-integrated Circuit Interface
+ − 621 */
+ − 622
+ − 623 typedef struct
+ − 624 {
+ − 625 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ − 626 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ − 627 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ − 628 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ − 629 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ − 630 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ − 631 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ − 632 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ − 633 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ − 634 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+ − 635 } I2C_TypeDef;
+ − 636
+ − 637 /**
+ − 638 * @brief Independent WATCHDOG
+ − 639 */
+ − 640
+ − 641 typedef struct
+ − 642 {
+ − 643 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ − 644 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ − 645 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ − 646 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+ − 647 } IWDG_TypeDef;
+ − 648
+ − 649 /**
+ − 650 * @brief LCD-TFT Display Controller
+ − 651 */
+ − 652
+ − 653 typedef struct
+ − 654 {
+ − 655 uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
+ − 656 __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
+ − 657 __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
+ − 658 __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
+ − 659 __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
+ − 660 __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
+ − 661 uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
+ − 662 __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
+ − 663 uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
+ − 664 __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
+ − 665 uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
+ − 666 __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
+ − 667 __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
+ − 668 __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
+ − 669 __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
+ − 670 __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
+ − 671 __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
+ − 672 } LTDC_TypeDef;
+ − 673
+ − 674 /**
+ − 675 * @brief LCD-TFT Display layer x Controller
+ − 676 */
+ − 677
+ − 678 typedef struct
+ − 679 {
+ − 680 __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
+ − 681 __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
+ − 682 __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
+ − 683 __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
+ − 684 __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
+ − 685 __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
+ − 686 __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
+ − 687 __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
+ − 688 uint32_t RESERVED0[2]; /*!< Reserved */
+ − 689 __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
+ − 690 __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
+ − 691 __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
+ − 692 uint32_t RESERVED1[3]; /*!< Reserved */
+ − 693 __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
+ − 694
+ − 695 } LTDC_Layer_TypeDef;
+ − 696
+ − 697 /**
+ − 698 * @brief Power Control
+ − 699 */
+ − 700
+ − 701 typedef struct
+ − 702 {
+ − 703 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ − 704 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+ − 705 } PWR_TypeDef;
+ − 706
+ − 707 /**
+ − 708 * @brief Reset and Clock Control
+ − 709 */
+ − 710
+ − 711 typedef struct
+ − 712 {
+ − 713 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ − 714 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ − 715 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ − 716 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ − 717 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ − 718 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
+ − 719 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
+ − 720 uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ − 721 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ − 722 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ − 723 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ − 724 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ − 725 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
+ − 726 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
+ − 727 uint32_t RESERVED2; /*!< Reserved, 0x3C */
+ − 728 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ − 729 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ − 730 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ − 731 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ − 732 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+ − 733 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+ − 734 uint32_t RESERVED4; /*!< Reserved, 0x5C */
+ − 735 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ − 736 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ − 737 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ − 738 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ − 739 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ − 740 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ − 741 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ − 742 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
+ − 743 __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
+ − 744 __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
+ − 745
+ − 746 } RCC_TypeDef;
+ − 747
+ − 748 /**
+ − 749 * @brief Real-Time Clock
+ − 750 */
+ − 751
+ − 752 typedef struct
+ − 753 {
+ − 754 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ − 755 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ − 756 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ − 757 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ − 758 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ − 759 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ − 760 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ − 761 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ − 762 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ − 763 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ − 764 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ − 765 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ − 766 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ − 767 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ − 768 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ − 769 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ − 770 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ − 771 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ − 772 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ − 773 uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ − 774 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ − 775 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ − 776 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ − 777 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ − 778 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ − 779 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ − 780 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ − 781 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ − 782 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ − 783 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ − 784 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ − 785 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ − 786 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ − 787 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ − 788 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ − 789 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ − 790 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ − 791 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ − 792 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ − 793 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+ − 794 } RTC_TypeDef;
+ − 795
+ − 796 /**
+ − 797 * @brief Serial Audio Interface
+ − 798 */
+ − 799
+ − 800 typedef struct
+ − 801 {
+ − 802 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
+ − 803 } SAI_TypeDef;
+ − 804
+ − 805 typedef struct
+ − 806 {
+ − 807 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
+ − 808 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
+ − 809 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
+ − 810 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
+ − 811 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
+ − 812 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
+ − 813 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
+ − 814 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
+ − 815 } SAI_Block_TypeDef;
+ − 816
+ − 817 /**
+ − 818 * @brief SD host Interface
+ − 819 */
+ − 820
+ − 821 typedef struct
+ − 822 {
+ − 823 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ − 824 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ − 825 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ − 826 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ − 827 __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ − 828 __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ − 829 __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ − 830 __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ − 831 __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ − 832 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ − 833 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ − 834 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ − 835 __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ − 836 __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ − 837 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ − 838 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ − 839 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ − 840 __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ − 841 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ − 842 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+ − 843 } SDIO_TypeDef;
+ − 844
+ − 845 /**
+ − 846 * @brief Serial Peripheral Interface
+ − 847 */
+ − 848
+ − 849 typedef struct
+ − 850 {
+ − 851 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ − 852 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ − 853 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ − 854 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ − 855 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ − 856 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ − 857 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ − 858 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ − 859 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+ − 860 } SPI_TypeDef;
+ − 861
+ − 862 /**
+ − 863 * @brief TIM
+ − 864 */
+ − 865
+ − 866 typedef struct
+ − 867 {
+ − 868 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ − 869 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ − 870 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ − 871 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ − 872 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ − 873 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ − 874 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ − 875 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ − 876 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ − 877 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ − 878 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ − 879 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ − 880 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ − 881 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ − 882 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ − 883 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ − 884 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ − 885 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ − 886 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ − 887 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ − 888 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+ − 889 } TIM_TypeDef;
+ − 890
+ − 891 /**
+ − 892 * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ − 893 */
+ − 894
+ − 895 typedef struct
+ − 896 {
+ − 897 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ − 898 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ − 899 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ − 900 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ − 901 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ − 902 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ − 903 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+ − 904 } USART_TypeDef;
+ − 905
+ − 906 /**
+ − 907 * @brief Window WATCHDOG
+ − 908 */
+ − 909
+ − 910 typedef struct
+ − 911 {
+ − 912 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ − 913 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ − 914 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+ − 915 } WWDG_TypeDef;
+ − 916
+ − 917
+ − 918 /**
+ − 919 * @brief RNG
+ − 920 */
+ − 921
+ − 922 typedef struct
+ − 923 {
+ − 924 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ − 925 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ − 926 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+ − 927 } RNG_TypeDef;
+ − 928
+ − 929
+ − 930 /**
+ − 931 * @brief __USB_OTG_Core_register
+ − 932 */
+ − 933 typedef struct
+ − 934 {
+ − 935 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
+ − 936 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
+ − 937 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
+ − 938 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
+ − 939 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
+ − 940 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
+ − 941 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
+ − 942 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
+ − 943 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
+ − 944 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h */
+ − 945 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/
+ − 946 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
+ − 947 uint32_t Reserved30[2]; /* Reserved 030h*/
+ − 948 __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
+ − 949 __IO uint32_t CID; /* User ID Register 03Ch*/
+ − 950 uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/
+ − 951 __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
+ − 952 __IO uint32_t DIEPTXF[0x0F];/* dev Periodic Transmit FIFO */
+ − 953 }
+ − 954 USB_OTG_GlobalTypeDef;
+ − 955
+ − 956
+ − 957 /**
+ − 958 * @brief __device_Registers
+ − 959 */
+ − 960 typedef struct
+ − 961 {
+ − 962 __IO uint32_t DCFG; /* dev Configuration Register 800h*/
+ − 963 __IO uint32_t DCTL; /* dev Control Register 804h*/
+ − 964 __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
+ − 965 uint32_t Reserved0C; /* Reserved 80Ch*/
+ − 966 __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
+ − 967 __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
+ − 968 __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
+ − 969 __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
+ − 970 uint32_t Reserved20; /* Reserved 820h*/
+ − 971 uint32_t Reserved9; /* Reserved 824h*/
+ − 972 __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
+ − 973 __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
+ − 974 __IO uint32_t DTHRCTL; /* dev thr 830h*/
+ − 975 __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
+ − 976 __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/
+ − 977 __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/
+ − 978 uint32_t Reserved40; /* dedicated EP mask 840h*/
+ − 979 __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/
+ − 980 uint32_t Reserved44[15]; /* Reserved 844-87Ch*/
+ − 981 __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/
+ − 982 }
+ − 983 USB_OTG_DeviceTypeDef;
+ − 984
+ − 985
+ − 986 /**
+ − 987 * @brief __IN_Endpoint-Specific_Register
+ − 988 */
+ − 989 typedef struct
+ − 990 {
+ − 991 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
+ − 992 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
+ − 993 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
+ − 994 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
+ − 995 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
+ − 996 __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
+ − 997 __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
+ − 998 uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
+ − 999 }
+ − 1000 USB_OTG_INEndpointTypeDef;
+ − 1001
+ − 1002
+ − 1003 /**
+ − 1004 * @brief __OUT_Endpoint-Specific_Registers
+ − 1005 */
+ − 1006 typedef struct
+ − 1007 {
+ − 1008 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
+ − 1009 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
+ − 1010 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
+ − 1011 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
+ − 1012 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
+ − 1013 __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
+ − 1014 uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
+ − 1015 }
+ − 1016 USB_OTG_OUTEndpointTypeDef;
+ − 1017
+ − 1018
+ − 1019 /**
+ − 1020 * @brief __Host_Mode_Register_Structures
+ − 1021 */
+ − 1022 typedef struct
+ − 1023 {
+ − 1024 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
+ − 1025 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
+ − 1026 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
+ − 1027 uint32_t Reserved40C; /* Reserved 40Ch*/
+ − 1028 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
+ − 1029 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
+ − 1030 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
+ − 1031 }
+ − 1032 USB_OTG_HostTypeDef;
+ − 1033
+ − 1034 /**
+ − 1035 * @brief __Host_Channel_Specific_Registers
+ − 1036 */
+ − 1037 typedef struct
+ − 1038 {
+ − 1039 __IO uint32_t HCCHAR;
+ − 1040 __IO uint32_t HCSPLT;
+ − 1041 __IO uint32_t HCINT;
+ − 1042 __IO uint32_t HCINTMSK;
+ − 1043 __IO uint32_t HCTSIZ;
+ − 1044 __IO uint32_t HCDMA;
+ − 1045 uint32_t Reserved[2];
+ − 1046 }
+ − 1047 USB_OTG_HostChannelTypeDef;
+ − 1048 /**
+ − 1049 * @}
+ − 1050 */
+ − 1051
+ − 1052 /** @addtogroup Peripheral_memory_map
+ − 1053 * @{
+ − 1054 */
+ − 1055 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 2 MB) base address in the alias region */
+ − 1056 #define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
+ − 1057 #define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
+ − 1058 #define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
+ − 1059 #define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
+ − 1060 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+ − 1061 #define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
+ − 1062 #define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */
+ − 1063 #define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
+ − 1064 #define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
+ − 1065 #define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
+ − 1066 #define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
+ − 1067 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+ − 1068 #define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
+ − 1069 #define FLASH_END ((uint32_t)0x081FFFFF) /*!< FLASH end address */
+ − 1070 #define CCMDATARAM_END ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */
+ − 1071
+ − 1072 /* Legacy defines */
+ − 1073 #define SRAM_BASE SRAM1_BASE
+ − 1074 #define SRAM_BB_BASE SRAM1_BB_BASE
+ − 1075
+ − 1076
+ − 1077 /*!< Peripheral memory map */
+ − 1078 #define APB1PERIPH_BASE PERIPH_BASE
+ − 1079 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
+ − 1080 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
+ − 1081 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
+ − 1082
+ − 1083 /*!< APB1 peripherals */
+ − 1084 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
+ − 1085 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
+ − 1086 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
+ − 1087 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
+ − 1088 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
+ − 1089 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
+ − 1090 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
+ − 1091 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
+ − 1092 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
+ − 1093 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+ − 1094 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+ − 1095 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+ − 1096 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
+ − 1097 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+ − 1098 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
+ − 1099 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
+ − 1100 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+ − 1101 #define USART3_BASE (APB1PERIPH_BASE + 0x4800)
+ − 1102 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
+ − 1103 #define UART5_BASE (APB1PERIPH_BASE + 0x5000)
+ − 1104 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+ − 1105 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+ − 1106 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
+ − 1107 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
+ − 1108 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
+ − 1109 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+ − 1110 #define DAC_BASE (APB1PERIPH_BASE + 0x7400)
+ − 1111 #define UART7_BASE (APB1PERIPH_BASE + 0x7800)
+ − 1112 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00)
+ − 1113
+ − 1114 /*!< APB2 peripherals */
+ − 1115 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
+ − 1116 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
+ − 1117 #define USART1_BASE (APB2PERIPH_BASE + 0x1000)
+ − 1118 #define USART6_BASE (APB2PERIPH_BASE + 0x1400)
+ − 1119 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
+ − 1120 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
+ − 1121 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
+ − 1122 #define ADC_BASE (APB2PERIPH_BASE + 0x2300)
+ − 1123 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
+ − 1124 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+ − 1125 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
+ − 1126 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
+ − 1127 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
+ − 1128 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
+ − 1129 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
+ − 1130 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
+ − 1131 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000)
+ − 1132 #define SPI6_BASE (APB2PERIPH_BASE + 0x5400)
+ − 1133 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800)
+ − 1134 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
+ − 1135 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
+ − 1136 #define LTDC_BASE (APB2PERIPH_BASE + 0x6800)
+ − 1137 #define LTDC_Layer1_BASE (LTDC_BASE + 0x84)
+ − 1138 #define LTDC_Layer2_BASE (LTDC_BASE + 0x104)
+ − 1139
+ − 1140 /*!< AHB1 peripherals */
+ − 1141 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
+ − 1142 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
+ − 1143 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
+ − 1144 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
+ − 1145 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
+ − 1146 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
+ − 1147 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
+ − 1148 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
+ − 1149 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
+ − 1150 #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400)
+ − 1151 #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800)
+ − 1152 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
+ − 1153 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
+ − 1154 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
+ − 1155 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
+ − 1156 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
+ − 1157 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
+ − 1158 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
+ − 1159 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
+ − 1160 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
+ − 1161 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
+ − 1162 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
+ − 1163 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
+ − 1164 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
+ − 1165 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
+ − 1166 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
+ − 1167 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
+ − 1168 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
+ − 1169 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
+ − 1170 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
+ − 1171 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
+ − 1172 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
+ − 1173 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000)
+ − 1174 #define ETH_MAC_BASE (ETH_BASE)
+ − 1175 #define ETH_MMC_BASE (ETH_BASE + 0x0100)
+ − 1176 #define ETH_PTP_BASE (ETH_BASE + 0x0700)
+ − 1177 #define ETH_DMA_BASE (ETH_BASE + 0x1000)
+ − 1178 #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000)
+ − 1179
+ − 1180 /*!< AHB2 peripherals */
+ − 1181 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
+ − 1182 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
+ − 1183
+ − 1184 /*!< FMC Bankx registers base address */
+ − 1185 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
+ − 1186 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
+ − 1187 #define FMC_Bank2_3_R_BASE (FMC_R_BASE + 0x0060)
+ − 1188 #define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0)
+ − 1189 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140)
+ − 1190
+ − 1191 /* Debug MCU registers base address */
+ − 1192 #define DBGMCU_BASE ((uint32_t )0xE0042000)
+ − 1193
+ − 1194 /*!< USB registers base address */
+ − 1195 #define USB_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000)
+ − 1196 #define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
+ − 1197
+ − 1198 #define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
+ − 1199 #define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
+ − 1200 #define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
+ − 1201 #define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
+ − 1202 #define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
+ − 1203 #define USB_OTG_HOST_BASE ((uint32_t )0x400)
+ − 1204 #define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
+ − 1205 #define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
+ − 1206 #define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
+ − 1207 #define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
+ − 1208 #define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
+ − 1209 #define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
+ − 1210
+ − 1211 /**
+ − 1212 * @}
+ − 1213 */
+ − 1214
+ − 1215 /** @addtogroup Peripheral_declaration
+ − 1216 * @{
+ − 1217 */
+ − 1218 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+ − 1219 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+ − 1220 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+ − 1221 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+ − 1222 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+ − 1223 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+ − 1224 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
+ − 1225 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
+ − 1226 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+ − 1227 #define RTC ((RTC_TypeDef *) RTC_BASE)
+ − 1228 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+ − 1229 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+ − 1230 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+ − 1231 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+ − 1232 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+ − 1233 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+ − 1234 #define USART2 ((USART_TypeDef *) USART2_BASE)
+ − 1235 #define USART3 ((USART_TypeDef *) USART3_BASE)
+ − 1236 #define UART4 ((USART_TypeDef *) UART4_BASE)
+ − 1237 #define UART5 ((USART_TypeDef *) UART5_BASE)
+ − 1238 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+ − 1239 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+ − 1240 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+ − 1241 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+ − 1242 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
+ − 1243 #define PWR ((PWR_TypeDef *) PWR_BASE)
+ − 1244 #define DAC ((DAC_TypeDef *) DAC_BASE)
+ − 1245 #define UART7 ((USART_TypeDef *) UART7_BASE)
+ − 1246 #define UART8 ((USART_TypeDef *) UART8_BASE)
+ − 1247 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+ − 1248 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+ − 1249 #define USART1 ((USART_TypeDef *) USART1_BASE)
+ − 1250 #define USART6 ((USART_TypeDef *) USART6_BASE)
+ − 1251 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+ − 1252 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+ − 1253 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+ − 1254 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
+ − 1255 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+ − 1256 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+ − 1257 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
+ − 1258 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+ − 1259 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+ − 1260 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+ − 1261 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+ − 1262 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+ − 1263 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
+ − 1264 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
+ − 1265 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
+ − 1266 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+ − 1267 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+ − 1268 #define LTDC ((LTDC_TypeDef *)LTDC_BASE)
+ − 1269 #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
+ − 1270 #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
+ − 1271
+ − 1272 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+ − 1273 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+ − 1274 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+ − 1275 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+ − 1276 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+ − 1277 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+ − 1278 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+ − 1279 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+ − 1280 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
+ − 1281 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
+ − 1282 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
+ − 1283 #define CRC ((CRC_TypeDef *) CRC_BASE)
+ − 1284 #define RCC ((RCC_TypeDef *) RCC_BASE)
+ − 1285 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+ − 1286 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+ − 1287 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+ − 1288 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+ − 1289 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+ − 1290 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+ − 1291 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+ − 1292 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+ − 1293 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+ − 1294 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+ − 1295 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+ − 1296 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+ − 1297 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+ − 1298 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+ − 1299 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+ − 1300 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+ − 1301 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+ − 1302 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+ − 1303 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+ − 1304 #define ETH ((ETH_TypeDef *) ETH_BASE)
+ − 1305 #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
+ − 1306 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
+ − 1307 #define RNG ((RNG_TypeDef *) RNG_BASE)
+ − 1308 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+ − 1309 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+ − 1310 #define FMC_Bank2_3 ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
+ − 1311 #define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
+ − 1312 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
+ − 1313
+ − 1314 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+ − 1315
+ − 1316 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+ − 1317 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
+ − 1318
+ − 1319 /**
+ − 1320 * @}
+ − 1321 */
+ − 1322
+ − 1323 /** @addtogroup Exported_constants
+ − 1324 * @{
+ − 1325 */
+ − 1326
+ − 1327 /** @addtogroup Peripheral_Registers_Bits_Definition
+ − 1328 * @{
+ − 1329 */
+ − 1330
+ − 1331 /******************************************************************************/
+ − 1332 /* Peripheral Registers_Bits_Definition */
+ − 1333 /******************************************************************************/
+ − 1334
+ − 1335 /******************************************************************************/
+ − 1336 /* */
+ − 1337 /* Analog to Digital Converter */
+ − 1338 /* */
+ − 1339 /******************************************************************************/
+ − 1340 /******************** Bit definition for ADC_SR register ********************/
+ − 1341 #define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */
+ − 1342 #define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */
+ − 1343 #define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */
+ − 1344 #define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */
+ − 1345 #define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */
+ − 1346 #define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */
+ − 1347
+ − 1348 /******************* Bit definition for ADC_CR1 register ********************/
+ − 1349 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+ − 1350 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+ − 1351 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+ − 1352 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+ − 1353 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+ − 1354 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+ − 1355 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
+ − 1356 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
+ − 1357 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
+ − 1358 #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
+ − 1359 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
+ − 1360 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
+ − 1361 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
+ − 1362 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
+ − 1363 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+ − 1364 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+ − 1365 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+ − 1366 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+ − 1367 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
+ − 1368 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
+ − 1369 #define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
+ − 1370 #define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+ − 1371 #define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+ − 1372 #define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
+ − 1373
+ − 1374 /******************* Bit definition for ADC_CR2 register ********************/
+ − 1375 #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
+ − 1376 #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
+ − 1377 #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
+ − 1378 #define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
+ − 1379 #define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
+ − 1380 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
+ − 1381 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+ − 1382 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+ − 1383 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+ − 1384 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+ − 1385 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+ − 1386 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+ − 1387 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+ − 1388 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+ − 1389 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
+ − 1390 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+ − 1391 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+ − 1392 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+ − 1393 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+ − 1394 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+ − 1395 #define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+ − 1396 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+ − 1397 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+ − 1398 #define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
+ − 1399
+ − 1400 /****************** Bit definition for ADC_SMPR1 register *******************/
+ − 1401 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+ − 1402 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+ − 1403 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+ − 1404 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+ − 1405 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+ − 1406 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+ − 1407 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+ − 1408 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+ − 1409 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+ − 1410 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+ − 1411 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+ − 1412 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
+ − 1413 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+ − 1414 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+ − 1415 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+ − 1416 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+ − 1417 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+ − 1418 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+ − 1419 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+ − 1420 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+ − 1421 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+ − 1422 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+ − 1423 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+ − 1424 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+ − 1425 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+ − 1426 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+ − 1427 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+ − 1428 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
+ − 1429 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+ − 1430 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
+ − 1431 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
+ − 1432 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
+ − 1433 #define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+ − 1434 #define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+ − 1435 #define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+ − 1436 #define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+ − 1437
+ − 1438 /****************** Bit definition for ADC_SMPR2 register *******************/
+ − 1439 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+ − 1440 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+ − 1441 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+ − 1442 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+ − 1443 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+ − 1444 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+ − 1445 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+ − 1446 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+ − 1447 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+ − 1448 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+ − 1449 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+ − 1450 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
+ − 1451 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+ − 1452 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+ − 1453 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+ − 1454 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+ − 1455 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+ − 1456 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+ − 1457 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+ − 1458 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+ − 1459 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+ − 1460 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+ − 1461 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+ − 1462 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+ − 1463 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+ − 1464 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+ − 1465 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+ − 1466 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
+ − 1467 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+ − 1468 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
+ − 1469 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
+ − 1470 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
+ − 1471 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+ − 1472 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+ − 1473 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+ − 1474 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+ − 1475 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+ − 1476 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
+ − 1477 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
+ − 1478 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
+ − 1479
+ − 1480 /****************** Bit definition for ADC_JOFR1 register *******************/
+ − 1481 #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */
+ − 1482
+ − 1483 /****************** Bit definition for ADC_JOFR2 register *******************/
+ − 1484 #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */
+ − 1485
+ − 1486 /****************** Bit definition for ADC_JOFR3 register *******************/
+ − 1487 #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */
+ − 1488
+ − 1489 /****************** Bit definition for ADC_JOFR4 register *******************/
+ − 1490 #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */
+ − 1491
+ − 1492 /******************* Bit definition for ADC_HTR register ********************/
+ − 1493 #define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */
+ − 1494
+ − 1495 /******************* Bit definition for ADC_LTR register ********************/
+ − 1496 #define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */
+ − 1497
+ − 1498 /******************* Bit definition for ADC_SQR1 register *******************/
+ − 1499 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+ − 1500 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+ − 1501 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+ − 1502 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+ − 1503 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+ − 1504 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+ − 1505 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+ − 1506 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+ − 1507 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+ − 1508 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+ − 1509 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+ − 1510 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+ − 1511 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+ − 1512 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+ − 1513 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+ − 1514 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+ − 1515 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+ − 1516 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+ − 1517 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+ − 1518 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+ − 1519 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+ − 1520 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+ − 1521 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+ − 1522 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+ − 1523 #define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
+ − 1524 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+ − 1525 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+ − 1526 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+ − 1527 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+ − 1528
+ − 1529 /******************* Bit definition for ADC_SQR2 register *******************/
+ − 1530 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+ − 1531 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+ − 1532 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+ − 1533 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+ − 1534 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+ − 1535 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+ − 1536 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+ − 1537 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+ − 1538 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+ − 1539 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+ − 1540 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+ − 1541 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+ − 1542 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+ − 1543 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+ − 1544 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+ − 1545 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+ − 1546 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+ − 1547 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+ − 1548 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+ − 1549 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+ − 1550 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+ − 1551 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+ − 1552 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+ − 1553 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+ − 1554 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+ − 1555 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+ − 1556 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+ − 1557 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+ − 1558 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+ − 1559 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
+ − 1560 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+ − 1561 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
+ − 1562 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
+ − 1563 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
+ − 1564 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
+ − 1565 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
+ − 1566
+ − 1567 /******************* Bit definition for ADC_SQR3 register *******************/
+ − 1568 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+ − 1569 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+ − 1570 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+ − 1571 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+ − 1572 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+ − 1573 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+ − 1574 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+ − 1575 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+ − 1576 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+ − 1577 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+ − 1578 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+ − 1579 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+ − 1580 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+ − 1581 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+ − 1582 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+ − 1583 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+ − 1584 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+ − 1585 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+ − 1586 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+ − 1587 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+ − 1588 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+ − 1589 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+ − 1590 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+ − 1591 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+ − 1592 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+ − 1593 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+ − 1594 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+ − 1595 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+ − 1596 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+ − 1597 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
+ − 1598 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+ − 1599 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
+ − 1600 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
+ − 1601 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
+ − 1602 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
+ − 1603 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
+ − 1604
+ − 1605 /******************* Bit definition for ADC_JSQR register *******************/
+ − 1606 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+ − 1607 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+ − 1608 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+ − 1609 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+ − 1610 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+ − 1611 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+ − 1612 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+ − 1613 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+ − 1614 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+ − 1615 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+ − 1616 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+ − 1617 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+ − 1618 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+ − 1619 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+ − 1620 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+ − 1621 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+ − 1622 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+ − 1623 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+ − 1624 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+ − 1625 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+ − 1626 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+ − 1627 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+ − 1628 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+ − 1629 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+ − 1630 #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
+ − 1631 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+ − 1632 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+ − 1633
+ − 1634 /******************* Bit definition for ADC_JDR1 register *******************/
+ − 1635 #define ADC_JDR1_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+ − 1636
+ − 1637 /******************* Bit definition for ADC_JDR2 register *******************/
+ − 1638 #define ADC_JDR2_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+ − 1639
+ − 1640 /******************* Bit definition for ADC_JDR3 register *******************/
+ − 1641 #define ADC_JDR3_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+ − 1642
+ − 1643 /******************* Bit definition for ADC_JDR4 register *******************/
+ − 1644 #define ADC_JDR4_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+ − 1645
+ − 1646 /******************** Bit definition for ADC_DR register ********************/
+ − 1647 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
+ − 1648 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
+ − 1649
+ − 1650 /******************* Bit definition for ADC_CSR register ********************/
+ − 1651 #define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
+ − 1652 #define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
+ − 1653 #define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
+ − 1654 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
+ − 1655 #define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
+ − 1656 #define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
+ − 1657 #define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
+ − 1658 #define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
+ − 1659 #define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
+ − 1660 #define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
+ − 1661 #define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
+ − 1662 #define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
+ − 1663 #define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
+ − 1664 #define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
+ − 1665 #define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
+ − 1666 #define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
+ − 1667 #define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
+ − 1668 #define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
+ − 1669
+ − 1670 /******************* Bit definition for ADC_CCR register ********************/
+ − 1671 #define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+ − 1672 #define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+ − 1673 #define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+ − 1674 #define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+ − 1675 #define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+ − 1676 #define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+ − 1677 #define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+ − 1678 #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+ − 1679 #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+ − 1680 #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+ − 1681 #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+ − 1682 #define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
+ − 1683 #define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+ − 1684 #define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
+ − 1685 #define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
+ − 1686 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
+ − 1687 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+ − 1688 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+ − 1689 #define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
+ − 1690 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
+ − 1691
+ − 1692 /******************* Bit definition for ADC_CDR register ********************/
+ − 1693 #define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
+ − 1694 #define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
+ − 1695
+ − 1696 /******************************************************************************/
+ − 1697 /* */
+ − 1698 /* Controller Area Network */
+ − 1699 /* */
+ − 1700 /******************************************************************************/
+ − 1701 /*!<CAN control and status registers */
+ − 1702 /******************* Bit definition for CAN_MCR register ********************/
+ − 1703 #define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
+ − 1704 #define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
+ − 1705 #define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
+ − 1706 #define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
+ − 1707 #define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
+ − 1708 #define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
+ − 1709 #define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
+ − 1710 #define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
+ − 1711 #define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
+ − 1712 #define CAN_MCR_DBF ((uint32_t)0x00010000) /*!<bxCAN Debug freeze */
+ − 1713 /******************* Bit definition for CAN_MSR register ********************/
+ − 1714 #define CAN_MSR_INAK ((uint32_t)0x0001) /*!<Initialization Acknowledge */
+ − 1715 #define CAN_MSR_SLAK ((uint32_t)0x0002) /*!<Sleep Acknowledge */
+ − 1716 #define CAN_MSR_ERRI ((uint32_t)0x0004) /*!<Error Interrupt */
+ − 1717 #define CAN_MSR_WKUI ((uint32_t)0x0008) /*!<Wakeup Interrupt */
+ − 1718 #define CAN_MSR_SLAKI ((uint32_t)0x0010) /*!<Sleep Acknowledge Interrupt */
+ − 1719 #define CAN_MSR_TXM ((uint32_t)0x0100) /*!<Transmit Mode */
+ − 1720 #define CAN_MSR_RXM ((uint32_t)0x0200) /*!<Receive Mode */
+ − 1721 #define CAN_MSR_SAMP ((uint32_t)0x0400) /*!<Last Sample Point */
+ − 1722 #define CAN_MSR_RX ((uint32_t)0x0800) /*!<CAN Rx Signal */
+ − 1723
+ − 1724 /******************* Bit definition for CAN_TSR register ********************/
+ − 1725 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
+ − 1726 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
+ − 1727 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
+ − 1728 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
+ − 1729 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
+ − 1730 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
+ − 1731 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
+ − 1732 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
+ − 1733 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
+ − 1734 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
+ − 1735 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
+ − 1736 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
+ − 1737 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
+ − 1738 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
+ − 1739 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
+ − 1740 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
+ − 1741
+ − 1742 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
+ − 1743 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
+ − 1744 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
+ − 1745 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
+ − 1746
+ − 1747 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
+ − 1748 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
+ − 1749 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
+ − 1750 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
+ − 1751
+ − 1752 /******************* Bit definition for CAN_RF0R register *******************/
+ − 1753 #define CAN_RF0R_FMP0 ((uint32_t)0x03) /*!<FIFO 0 Message Pending */
+ − 1754 #define CAN_RF0R_FULL0 ((uint32_t)0x08) /*!<FIFO 0 Full */
+ − 1755 #define CAN_RF0R_FOVR0 ((uint32_t)0x10) /*!<FIFO 0 Overrun */
+ − 1756 #define CAN_RF0R_RFOM0 ((uint32_t)0x20) /*!<Release FIFO 0 Output Mailbox */
+ − 1757
+ − 1758 /******************* Bit definition for CAN_RF1R register *******************/
+ − 1759 #define CAN_RF1R_FMP1 ((uint32_t)0x03) /*!<FIFO 1 Message Pending */
+ − 1760 #define CAN_RF1R_FULL1 ((uint32_t)0x08) /*!<FIFO 1 Full */
+ − 1761 #define CAN_RF1R_FOVR1 ((uint32_t)0x10) /*!<FIFO 1 Overrun */
+ − 1762 #define CAN_RF1R_RFOM1 ((uint32_t)0x20) /*!<Release FIFO 1 Output Mailbox */
+ − 1763
+ − 1764 /******************** Bit definition for CAN_IER register *******************/
+ − 1765 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
+ − 1766 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
+ − 1767 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
+ − 1768 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
+ − 1769 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
+ − 1770 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
+ − 1771 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
+ − 1772 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
+ − 1773 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
+ − 1774 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
+ − 1775 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
+ − 1776 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
+ − 1777 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
+ − 1778 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
+ − 1779 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error warning interrupt enable */
+ − 1780 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error passive interrupt enable */
+ − 1781 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-off interrupt enable */
+ − 1782 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last error code interrupt enable */
+ − 1783 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error interrupt enable */
+ − 1784
+ − 1785
+ − 1786 /******************** Bit definition for CAN_ESR register *******************/
+ − 1787 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
+ − 1788 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
+ − 1789 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
+ − 1790
+ − 1791 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
+ − 1792 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+ − 1793 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+ − 1794 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+ − 1795
+ − 1796 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
+ − 1797 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
+ − 1798
+ − 1799 /******************* Bit definition for CAN_BTR register ********************/
+ − 1800 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
+ − 1801 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
+ − 1802 #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+ − 1803 #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+ − 1804 #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+ − 1805 #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+ − 1806 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
+ − 1807 #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+ − 1808 #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+ − 1809 #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+ − 1810 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
+ − 1811 #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+ − 1812 #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+ − 1813 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
+ − 1814 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
+ − 1815
+ − 1816
+ − 1817 /*!<Mailbox registers */
+ − 1818 /****************** Bit definition for CAN_TI0R register ********************/
+ − 1819 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
+ − 1820 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+ − 1821 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+ − 1822 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
+ − 1823 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+ − 1824
+ − 1825 /****************** Bit definition for CAN_TDT0R register *******************/
+ − 1826 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+ − 1827 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
+ − 1828 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+ − 1829
+ − 1830 /****************** Bit definition for CAN_TDL0R register *******************/
+ − 1831 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+ − 1832 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+ − 1833 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+ − 1834 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+ − 1835
+ − 1836 /****************** Bit definition for CAN_TDH0R register *******************/
+ − 1837 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+ − 1838 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+ − 1839 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+ − 1840 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+ − 1841
+ − 1842 /******************* Bit definition for CAN_TI1R register *******************/
+ − 1843 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
+ − 1844 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+ − 1845 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+ − 1846 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
+ − 1847 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+ − 1848
+ − 1849 /******************* Bit definition for CAN_TDT1R register ******************/
+ − 1850 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+ − 1851 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
+ − 1852 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+ − 1853
+ − 1854 /******************* Bit definition for CAN_TDL1R register ******************/
+ − 1855 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+ − 1856 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+ − 1857 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+ − 1858 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+ − 1859
+ − 1860 /******************* Bit definition for CAN_TDH1R register ******************/
+ − 1861 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+ − 1862 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+ − 1863 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+ − 1864 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+ − 1865
+ − 1866 /******************* Bit definition for CAN_TI2R register *******************/
+ − 1867 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
+ − 1868 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+ − 1869 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+ − 1870 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
+ − 1871 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+ − 1872
+ − 1873 /******************* Bit definition for CAN_TDT2R register ******************/
+ − 1874 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+ − 1875 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
+ − 1876 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+ − 1877
+ − 1878 /******************* Bit definition for CAN_TDL2R register ******************/
+ − 1879 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+ − 1880 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+ − 1881 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+ − 1882 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+ − 1883
+ − 1884 /******************* Bit definition for CAN_TDH2R register ******************/
+ − 1885 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+ − 1886 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+ − 1887 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+ − 1888 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+ − 1889
+ − 1890 /******************* Bit definition for CAN_RI0R register *******************/
+ − 1891 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+ − 1892 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+ − 1893 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
+ − 1894 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+ − 1895
+ − 1896 /******************* Bit definition for CAN_RDT0R register ******************/
+ − 1897 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+ − 1898 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
+ − 1899 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+ − 1900
+ − 1901 /******************* Bit definition for CAN_RDL0R register ******************/
+ − 1902 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+ − 1903 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+ − 1904 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+ − 1905 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+ − 1906
+ − 1907 /******************* Bit definition for CAN_RDH0R register ******************/
+ − 1908 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+ − 1909 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+ − 1910 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+ − 1911 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+ − 1912
+ − 1913 /******************* Bit definition for CAN_RI1R register *******************/
+ − 1914 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+ − 1915 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+ − 1916 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
+ − 1917 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+ − 1918
+ − 1919 /******************* Bit definition for CAN_RDT1R register ******************/
+ − 1920 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+ − 1921 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
+ − 1922 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+ − 1923
+ − 1924 /******************* Bit definition for CAN_RDL1R register ******************/
+ − 1925 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+ − 1926 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+ − 1927 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+ − 1928 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+ − 1929
+ − 1930 /******************* Bit definition for CAN_RDH1R register ******************/
+ − 1931 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+ − 1932 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+ − 1933 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+ − 1934 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+ − 1935
+ − 1936 /*!<CAN filter registers */
+ − 1937 /******************* Bit definition for CAN_FMR register ********************/
+ − 1938 #define CAN_FMR_FINIT ((uint32_t)0x01) /*!<Filter Init Mode */
+ − 1939 #define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
+ − 1940
+ − 1941 /******************* Bit definition for CAN_FM1R register *******************/
+ − 1942 #define CAN_FM1R_FBM ((uint32_t)0x0FFFFFFF) /*!<Filter Mode */
+ − 1943 #define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
+ − 1944 #define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
+ − 1945 #define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
+ − 1946 #define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */
+ − 1947 #define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */
+ − 1948 #define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */
+ − 1949 #define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */
+ − 1950 #define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */
+ − 1951 #define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */
+ − 1952 #define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */
+ − 1953 #define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */
+ − 1954 #define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
+ − 1955 #define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
+ − 1956 #define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
+ − 1957 #define CAN_FM1R_FBM14 ((uint32_t)0x00004000) /*!<Filter Init Mode bit 14 */
+ − 1958 #define CAN_FM1R_FBM15 ((uint32_t)0x00008000) /*!<Filter Init Mode bit 15 */
+ − 1959 #define CAN_FM1R_FBM16 ((uint32_t)0x00010000) /*!<Filter Init Mode bit 16 */
+ − 1960 #define CAN_FM1R_FBM17 ((uint32_t)0x00020000) /*!<Filter Init Mode bit 17 */
+ − 1961 #define CAN_FM1R_FBM18 ((uint32_t)0x00040000) /*!<Filter Init Mode bit 18 */
+ − 1962 #define CAN_FM1R_FBM19 ((uint32_t)0x00080000) /*!<Filter Init Mode bit 19 */
+ − 1963 #define CAN_FM1R_FBM20 ((uint32_t)0x00100000) /*!<Filter Init Mode bit 20 */
+ − 1964 #define CAN_FM1R_FBM21 ((uint32_t)0x00200000) /*!<Filter Init Mode bit 21 */
+ − 1965 #define CAN_FM1R_FBM22 ((uint32_t)0x00400000) /*!<Filter Init Mode bit 22 */
+ − 1966 #define CAN_FM1R_FBM23 ((uint32_t)0x00800000) /*!<Filter Init Mode bit 23 */
+ − 1967 #define CAN_FM1R_FBM24 ((uint32_t)0x01000000) /*!<Filter Init Mode bit 24 */
+ − 1968 #define CAN_FM1R_FBM25 ((uint32_t)0x02000000) /*!<Filter Init Mode bit 25 */
+ − 1969 #define CAN_FM1R_FBM26 ((uint32_t)0x04000000) /*!<Filter Init Mode bit 26 */
+ − 1970 #define CAN_FM1R_FBM27 ((uint32_t)0x08000000) /*!<Filter Init Mode bit 27 */
+ − 1971
+ − 1972 /******************* Bit definition for CAN_FS1R register *******************/
+ − 1973 #define CAN_FS1R_FSC ((uint32_t)0x0FFFFFFF) /*!<Filter Scale Configuration */
+ − 1974 #define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
+ − 1975 #define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
+ − 1976 #define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
+ − 1977 #define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
+ − 1978 #define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
+ − 1979 #define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
+ − 1980 #define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
+ − 1981 #define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
+ − 1982 #define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
+ − 1983 #define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
+ − 1984 #define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
+ − 1985 #define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
+ − 1986 #define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
+ − 1987 #define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
+ − 1988 #define CAN_FS1R_FSC14 ((uint32_t)0x00004000) /*!<Filter Scale Configuration bit 14 */
+ − 1989 #define CAN_FS1R_FSC15 ((uint32_t)0x00008000) /*!<Filter Scale Configuration bit 15 */
+ − 1990 #define CAN_FS1R_FSC16 ((uint32_t)0x00010000) /*!<Filter Scale Configuration bit 16 */
+ − 1991 #define CAN_FS1R_FSC17 ((uint32_t)0x00020000) /*!<Filter Scale Configuration bit 17 */
+ − 1992 #define CAN_FS1R_FSC18 ((uint32_t)0x00040000) /*!<Filter Scale Configuration bit 18 */
+ − 1993 #define CAN_FS1R_FSC19 ((uint32_t)0x00080000) /*!<Filter Scale Configuration bit 19 */
+ − 1994 #define CAN_FS1R_FSC20 ((uint32_t)0x00100000) /*!<Filter Scale Configuration bit 20 */
+ − 1995 #define CAN_FS1R_FSC21 ((uint32_t)0x00200000) /*!<Filter Scale Configuration bit 21 */
+ − 1996 #define CAN_FS1R_FSC22 ((uint32_t)0x00400000) /*!<Filter Scale Configuration bit 22 */
+ − 1997 #define CAN_FS1R_FSC23 ((uint32_t)0x00800000) /*!<Filter Scale Configuration bit 23 */
+ − 1998 #define CAN_FS1R_FSC24 ((uint32_t)0x01000000) /*!<Filter Scale Configuration bit 24 */
+ − 1999 #define CAN_FS1R_FSC25 ((uint32_t)0x02000000) /*!<Filter Scale Configuration bit 25 */
+ − 2000 #define CAN_FS1R_FSC26 ((uint32_t)0x04000000) /*!<Filter Scale Configuration bit 26 */
+ − 2001 #define CAN_FS1R_FSC27 ((uint32_t)0x08000000) /*!<Filter Scale Configuration bit 27 */
+ − 2002
+ − 2003 /****************** Bit definition for CAN_FFA1R register *******************/
+ − 2004 #define CAN_FFA1R_FFA ((uint32_t)0x0FFFFFFF) /*!<Filter FIFO Assignment */
+ − 2005 #define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment bit 0 */
+ − 2006 #define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment bit 1 */
+ − 2007 #define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment bit 2 */
+ − 2008 #define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment bit 3 */
+ − 2009 #define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment bit 4 */
+ − 2010 #define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment bit 5 */
+ − 2011 #define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment bit 6 */
+ − 2012 #define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment bit 7 */
+ − 2013 #define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment bit 8 */
+ − 2014 #define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment bit 9 */
+ − 2015 #define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment bit 10 */
+ − 2016 #define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment bit 11 */
+ − 2017 #define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment bit 12 */
+ − 2018 #define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment bit 13 */
+ − 2019 #define CAN_FFA1R_FFA14 ((uint32_t)0x00004000) /*!<Filter FIFO Assignment bit 14 */
+ − 2020 #define CAN_FFA1R_FFA15 ((uint32_t)0x00008000) /*!<Filter FIFO Assignment bit 15 */
+ − 2021 #define CAN_FFA1R_FFA16 ((uint32_t)0x00010000) /*!<Filter FIFO Assignment bit 16 */
+ − 2022 #define CAN_FFA1R_FFA17 ((uint32_t)0x00020000) /*!<Filter FIFO Assignment bit 17 */
+ − 2023 #define CAN_FFA1R_FFA18 ((uint32_t)0x00040000) /*!<Filter FIFO Assignment bit 18 */
+ − 2024 #define CAN_FFA1R_FFA19 ((uint32_t)0x00080000) /*!<Filter FIFO Assignment bit 19 */
+ − 2025 #define CAN_FFA1R_FFA20 ((uint32_t)0x00100000) /*!<Filter FIFO Assignment bit 20 */
+ − 2026 #define CAN_FFA1R_FFA21 ((uint32_t)0x00200000) /*!<Filter FIFO Assignment bit 21 */
+ − 2027 #define CAN_FFA1R_FFA22 ((uint32_t)0x00400000) /*!<Filter FIFO Assignment bit 22 */
+ − 2028 #define CAN_FFA1R_FFA23 ((uint32_t)0x00800000) /*!<Filter FIFO Assignment bit 23 */
+ − 2029 #define CAN_FFA1R_FFA24 ((uint32_t)0x01000000) /*!<Filter FIFO Assignment bit 24 */
+ − 2030 #define CAN_FFA1R_FFA25 ((uint32_t)0x02000000) /*!<Filter FIFO Assignment bit 25 */
+ − 2031 #define CAN_FFA1R_FFA26 ((uint32_t)0x04000000) /*!<Filter FIFO Assignment bit 26 */
+ − 2032 #define CAN_FFA1R_FFA27 ((uint32_t)0x08000000) /*!<Filter FIFO Assignment bit 27 */
+ − 2033
+ − 2034 /******************* Bit definition for CAN_FA1R register *******************/
+ − 2035 #define CAN_FA1R_FACT ((uint32_t)0x0FFFFFFF) /*!<Filter Active */
+ − 2036 #define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter Active bit 0 */
+ − 2037 #define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter Active bit 1 */
+ − 2038 #define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter Active bit 2 */
+ − 2039 #define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter Active bit 3 */
+ − 2040 #define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter Active bit 4 */
+ − 2041 #define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter Active bit 5 */
+ − 2042 #define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter Active bit 6 */
+ − 2043 #define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter Active bit 7 */
+ − 2044 #define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter Active bit 8 */
+ − 2045 #define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter Active bit 9 */
+ − 2046 #define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter Active bit 10 */
+ − 2047 #define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter Active bit 11 */
+ − 2048 #define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter Active bit 12 */
+ − 2049 #define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter Active bit 13 */
+ − 2050 #define CAN_FA1R_FACT14 ((uint32_t)0x00004000) /*!<Filter Active bit 14 */
+ − 2051 #define CAN_FA1R_FACT15 ((uint32_t)0x00008000) /*!<Filter Active bit 15 */
+ − 2052 #define CAN_FA1R_FACT16 ((uint32_t)0x00010000) /*!<Filter Active bit 16 */
+ − 2053 #define CAN_FA1R_FACT17 ((uint32_t)0x00020000) /*!<Filter Active bit 17 */
+ − 2054 #define CAN_FA1R_FACT18 ((uint32_t)0x00040000) /*!<Filter Active bit 18 */
+ − 2055 #define CAN_FA1R_FACT19 ((uint32_t)0x00080000) /*!<Filter Active bit 19 */
+ − 2056 #define CAN_FA1R_FACT20 ((uint32_t)0x00100000) /*!<Filter Active bit 20 */
+ − 2057 #define CAN_FA1R_FACT21 ((uint32_t)0x00200000) /*!<Filter Active bit 21 */
+ − 2058 #define CAN_FA1R_FACT22 ((uint32_t)0x00400000) /*!<Filter Active bit 22 */
+ − 2059 #define CAN_FA1R_FACT23 ((uint32_t)0x00800000) /*!<Filter Active bit 23 */
+ − 2060 #define CAN_FA1R_FACT24 ((uint32_t)0x01000000) /*!<Filter Active bit 24 */
+ − 2061 #define CAN_FA1R_FACT25 ((uint32_t)0x02000000) /*!<Filter Active bit 25 */
+ − 2062 #define CAN_FA1R_FACT26 ((uint32_t)0x04000000) /*!<Filter Active bit 26 */
+ − 2063 #define CAN_FA1R_FACT27 ((uint32_t)0x08000000) /*!<Filter Active bit 27 */
+ − 2064
+ − 2065 /******************* Bit definition for CAN_F0R1 register *******************/
+ − 2066 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+ − 2067 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+ − 2068 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+ − 2069 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+ − 2070 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+ − 2071 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+ − 2072 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+ − 2073 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+ − 2074 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+ − 2075 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+ − 2076 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+ − 2077 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+ − 2078 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+ − 2079 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+ − 2080 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+ − 2081 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+ − 2082 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+ − 2083 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+ − 2084 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+ − 2085 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+ − 2086 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+ − 2087 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+ − 2088 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+ − 2089 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+ − 2090 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+ − 2091 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+ − 2092 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+ − 2093 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+ − 2094 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+ − 2095 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+ − 2096 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+ − 2097 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+ − 2098
+ − 2099 /******************* Bit definition for CAN_F1R1 register *******************/
+ − 2100 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+ − 2101 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+ − 2102 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+ − 2103 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+ − 2104 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+ − 2105 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+ − 2106 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+ − 2107 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+ − 2108 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+ − 2109 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+ − 2110 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+ − 2111 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+ − 2112 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+ − 2113 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+ − 2114 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+ − 2115 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+ − 2116 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+ − 2117 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+ − 2118 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+ − 2119 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+ − 2120 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+ − 2121 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+ − 2122 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+ − 2123 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+ − 2124 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+ − 2125 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+ − 2126 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+ − 2127 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+ − 2128 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+ − 2129 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+ − 2130 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+ − 2131 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+ − 2132
+ − 2133 /******************* Bit definition for CAN_F2R1 register *******************/
+ − 2134 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+ − 2135 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+ − 2136 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+ − 2137 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+ − 2138 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+ − 2139 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+ − 2140 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+ − 2141 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+ − 2142 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+ − 2143 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+ − 2144 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+ − 2145 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+ − 2146 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+ − 2147 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+ − 2148 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+ − 2149 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+ − 2150 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+ − 2151 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+ − 2152 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+ − 2153 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+ − 2154 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+ − 2155 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+ − 2156 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+ − 2157 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+ − 2158 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+ − 2159 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+ − 2160 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+ − 2161 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+ − 2162 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+ − 2163 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+ − 2164 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+ − 2165 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+ − 2166
+ − 2167 /******************* Bit definition for CAN_F3R1 register *******************/
+ − 2168 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+ − 2169 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+ − 2170 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+ − 2171 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+ − 2172 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+ − 2173 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+ − 2174 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+ − 2175 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+ − 2176 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+ − 2177 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+ − 2178 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+ − 2179 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+ − 2180 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+ − 2181 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+ − 2182 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+ − 2183 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+ − 2184 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+ − 2185 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+ − 2186 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+ − 2187 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+ − 2188 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+ − 2189 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+ − 2190 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+ − 2191 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+ − 2192 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+ − 2193 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+ − 2194 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+ − 2195 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+ − 2196 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+ − 2197 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+ − 2198 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+ − 2199 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+ − 2200
+ − 2201 /******************* Bit definition for CAN_F4R1 register *******************/
+ − 2202 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+ − 2203 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+ − 2204 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+ − 2205 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+ − 2206 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+ − 2207 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+ − 2208 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+ − 2209 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+ − 2210 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+ − 2211 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+ − 2212 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+ − 2213 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+ − 2214 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+ − 2215 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+ − 2216 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+ − 2217 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+ − 2218 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+ − 2219 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+ − 2220 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+ − 2221 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+ − 2222 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+ − 2223 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+ − 2224 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+ − 2225 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+ − 2226 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+ − 2227 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+ − 2228 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+ − 2229 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+ − 2230 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+ − 2231 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+ − 2232 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+ − 2233 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+ − 2234
+ − 2235 /******************* Bit definition for CAN_F5R1 register *******************/
+ − 2236 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+ − 2237 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+ − 2238 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+ − 2239 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+ − 2240 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+ − 2241 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+ − 2242 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+ − 2243 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+ − 2244 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+ − 2245 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+ − 2246 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+ − 2247 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+ − 2248 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+ − 2249 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+ − 2250 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+ − 2251 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+ − 2252 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+ − 2253 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+ − 2254 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+ − 2255 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+ − 2256 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+ − 2257 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+ − 2258 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+ − 2259 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+ − 2260 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+ − 2261 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+ − 2262 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+ − 2263 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+ − 2264 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+ − 2265 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+ − 2266 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+ − 2267 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+ − 2268
+ − 2269 /******************* Bit definition for CAN_F6R1 register *******************/
+ − 2270 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+ − 2271 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+ − 2272 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+ − 2273 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+ − 2274 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+ − 2275 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+ − 2276 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+ − 2277 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+ − 2278 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+ − 2279 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+ − 2280 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+ − 2281 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+ − 2282 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+ − 2283 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+ − 2284 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+ − 2285 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+ − 2286 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+ − 2287 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+ − 2288 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+ − 2289 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+ − 2290 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+ − 2291 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+ − 2292 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+ − 2293 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+ − 2294 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+ − 2295 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+ − 2296 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+ − 2297 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+ − 2298 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+ − 2299 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+ − 2300 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+ − 2301 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+ − 2302
+ − 2303 /******************* Bit definition for CAN_F7R1 register *******************/
+ − 2304 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+ − 2305 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+ − 2306 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+ − 2307 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+ − 2308 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+ − 2309 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+ − 2310 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+ − 2311 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+ − 2312 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+ − 2313 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+ − 2314 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+ − 2315 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+ − 2316 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+ − 2317 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+ − 2318 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+ − 2319 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+ − 2320 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+ − 2321 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+ − 2322 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+ − 2323 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+ − 2324 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+ − 2325 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+ − 2326 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+ − 2327 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+ − 2328 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+ − 2329 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+ − 2330 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+ − 2331 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+ − 2332 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+ − 2333 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+ − 2334 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+ − 2335 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+ − 2336
+ − 2337 /******************* Bit definition for CAN_F8R1 register *******************/
+ − 2338 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+ − 2339 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+ − 2340 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+ − 2341 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+ − 2342 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+ − 2343 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+ − 2344 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+ − 2345 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+ − 2346 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+ − 2347 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+ − 2348 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+ − 2349 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+ − 2350 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+ − 2351 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+ − 2352 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+ − 2353 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+ − 2354 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+ − 2355 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+ − 2356 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+ − 2357 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+ − 2358 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+ − 2359 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+ − 2360 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+ − 2361 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+ − 2362 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+ − 2363 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+ − 2364 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+ − 2365 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+ − 2366 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+ − 2367 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+ − 2368 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+ − 2369 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+ − 2370
+ − 2371 /******************* Bit definition for CAN_F9R1 register *******************/
+ − 2372 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+ − 2373 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+ − 2374 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+ − 2375 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+ − 2376 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+ − 2377 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+ − 2378 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+ − 2379 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+ − 2380 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+ − 2381 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+ − 2382 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+ − 2383 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+ − 2384 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+ − 2385 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+ − 2386 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+ − 2387 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+ − 2388 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+ − 2389 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+ − 2390 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+ − 2391 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+ − 2392 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+ − 2393 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+ − 2394 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+ − 2395 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+ − 2396 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+ − 2397 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+ − 2398 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+ − 2399 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+ − 2400 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+ − 2401 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+ − 2402 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+ − 2403 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+ − 2404
+ − 2405 /******************* Bit definition for CAN_F10R1 register ******************/
+ − 2406 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+ − 2407 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+ − 2408 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+ − 2409 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+ − 2410 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+ − 2411 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+ − 2412 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+ − 2413 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+ − 2414 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+ − 2415 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+ − 2416 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+ − 2417 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+ − 2418 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+ − 2419 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+ − 2420 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+ − 2421 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+ − 2422 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+ − 2423 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+ − 2424 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+ − 2425 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+ − 2426 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+ − 2427 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+ − 2428 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+ − 2429 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+ − 2430 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+ − 2431 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+ − 2432 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+ − 2433 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+ − 2434 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+ − 2435 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+ − 2436 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+ − 2437 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+ − 2438
+ − 2439 /******************* Bit definition for CAN_F11R1 register ******************/
+ − 2440 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+ − 2441 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+ − 2442 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+ − 2443 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+ − 2444 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+ − 2445 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+ − 2446 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+ − 2447 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+ − 2448 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+ − 2449 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+ − 2450 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+ − 2451 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+ − 2452 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+ − 2453 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+ − 2454 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+ − 2455 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+ − 2456 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+ − 2457 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+ − 2458 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+ − 2459 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+ − 2460 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+ − 2461 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+ − 2462 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+ − 2463 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+ − 2464 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+ − 2465 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+ − 2466 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+ − 2467 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+ − 2468 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+ − 2469 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+ − 2470 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+ − 2471 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+ − 2472
+ − 2473 /******************* Bit definition for CAN_F12R1 register ******************/
+ − 2474 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+ − 2475 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+ − 2476 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+ − 2477 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+ − 2478 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+ − 2479 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+ − 2480 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+ − 2481 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+ − 2482 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+ − 2483 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+ − 2484 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+ − 2485 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+ − 2486 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+ − 2487 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+ − 2488 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+ − 2489 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+ − 2490 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+ − 2491 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+ − 2492 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+ − 2493 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+ − 2494 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+ − 2495 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+ − 2496 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+ − 2497 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+ − 2498 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+ − 2499 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+ − 2500 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+ − 2501 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+ − 2502 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+ − 2503 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+ − 2504 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+ − 2505 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+ − 2506
+ − 2507 /******************* Bit definition for CAN_F13R1 register ******************/
+ − 2508 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+ − 2509 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+ − 2510 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+ − 2511 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+ − 2512 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+ − 2513 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+ − 2514 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+ − 2515 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+ − 2516 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+ − 2517 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+ − 2518 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+ − 2519 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+ − 2520 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+ − 2521 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+ − 2522 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+ − 2523 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+ − 2524 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+ − 2525 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+ − 2526 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+ − 2527 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+ − 2528 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+ − 2529 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+ − 2530 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+ − 2531 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+ − 2532 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+ − 2533 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+ − 2534 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+ − 2535 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+ − 2536 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+ − 2537 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+ − 2538 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+ − 2539 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+ − 2540
+ − 2541 /******************* Bit definition for CAN_F0R2 register *******************/
+ − 2542 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+ − 2543 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+ − 2544 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+ − 2545 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+ − 2546 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+ − 2547 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+ − 2548 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+ − 2549 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+ − 2550 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+ − 2551 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+ − 2552 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+ − 2553 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+ − 2554 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+ − 2555 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+ − 2556 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+ − 2557 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+ − 2558 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+ − 2559 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+ − 2560 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+ − 2561 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+ − 2562 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+ − 2563 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+ − 2564 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+ − 2565 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+ − 2566 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+ − 2567 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+ − 2568 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+ − 2569 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+ − 2570 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+ − 2571 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+ − 2572 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+ − 2573 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+ − 2574
+ − 2575 /******************* Bit definition for CAN_F1R2 register *******************/
+ − 2576 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+ − 2577 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+ − 2578 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+ − 2579 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+ − 2580 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+ − 2581 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+ − 2582 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+ − 2583 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+ − 2584 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+ − 2585 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+ − 2586 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+ − 2587 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+ − 2588 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+ − 2589 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+ − 2590 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+ − 2591 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+ − 2592 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+ − 2593 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+ − 2594 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+ − 2595 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+ − 2596 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+ − 2597 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+ − 2598 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+ − 2599 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+ − 2600 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+ − 2601 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+ − 2602 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+ − 2603 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+ − 2604 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+ − 2605 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+ − 2606 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+ − 2607 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+ − 2608
+ − 2609 /******************* Bit definition for CAN_F2R2 register *******************/
+ − 2610 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+ − 2611 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+ − 2612 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+ − 2613 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+ − 2614 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+ − 2615 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+ − 2616 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+ − 2617 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+ − 2618 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+ − 2619 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+ − 2620 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+ − 2621 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+ − 2622 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+ − 2623 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+ − 2624 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+ − 2625 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+ − 2626 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+ − 2627 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+ − 2628 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+ − 2629 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+ − 2630 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+ − 2631 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+ − 2632 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+ − 2633 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+ − 2634 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+ − 2635 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+ − 2636 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+ − 2637 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+ − 2638 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+ − 2639 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+ − 2640 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+ − 2641 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+ − 2642
+ − 2643 /******************* Bit definition for CAN_F3R2 register *******************/
+ − 2644 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+ − 2645 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+ − 2646 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+ − 2647 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+ − 2648 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+ − 2649 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+ − 2650 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+ − 2651 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+ − 2652 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+ − 2653 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+ − 2654 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+ − 2655 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+ − 2656 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+ − 2657 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+ − 2658 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+ − 2659 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+ − 2660 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+ − 2661 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+ − 2662 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+ − 2663 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+ − 2664 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+ − 2665 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+ − 2666 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+ − 2667 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+ − 2668 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+ − 2669 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+ − 2670 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+ − 2671 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+ − 2672 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+ − 2673 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+ − 2674 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+ − 2675 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+ − 2676
+ − 2677 /******************* Bit definition for CAN_F4R2 register *******************/
+ − 2678 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+ − 2679 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+ − 2680 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+ − 2681 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+ − 2682 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+ − 2683 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+ − 2684 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+ − 2685 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+ − 2686 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+ − 2687 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+ − 2688 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+ − 2689 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+ − 2690 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+ − 2691 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+ − 2692 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+ − 2693 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+ − 2694 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+ − 2695 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+ − 2696 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+ − 2697 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+ − 2698 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+ − 2699 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+ − 2700 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+ − 2701 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+ − 2702 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+ − 2703 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+ − 2704 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+ − 2705 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+ − 2706 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+ − 2707 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+ − 2708 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+ − 2709 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+ − 2710
+ − 2711 /******************* Bit definition for CAN_F5R2 register *******************/
+ − 2712 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+ − 2713 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+ − 2714 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+ − 2715 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+ − 2716 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+ − 2717 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+ − 2718 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+ − 2719 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+ − 2720 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+ − 2721 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+ − 2722 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+ − 2723 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+ − 2724 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+ − 2725 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+ − 2726 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+ − 2727 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+ − 2728 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+ − 2729 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+ − 2730 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+ − 2731 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+ − 2732 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+ − 2733 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+ − 2734 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+ − 2735 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+ − 2736 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+ − 2737 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+ − 2738 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+ − 2739 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+ − 2740 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+ − 2741 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+ − 2742 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+ − 2743 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+ − 2744
+ − 2745 /******************* Bit definition for CAN_F6R2 register *******************/
+ − 2746 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+ − 2747 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+ − 2748 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+ − 2749 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+ − 2750 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+ − 2751 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+ − 2752 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+ − 2753 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+ − 2754 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+ − 2755 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+ − 2756 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+ − 2757 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+ − 2758 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+ − 2759 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+ − 2760 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+ − 2761 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+ − 2762 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+ − 2763 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+ − 2764 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+ − 2765 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+ − 2766 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+ − 2767 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+ − 2768 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+ − 2769 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+ − 2770 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+ − 2771 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+ − 2772 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+ − 2773 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+ − 2774 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+ − 2775 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+ − 2776 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+ − 2777 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+ − 2778
+ − 2779 /******************* Bit definition for CAN_F7R2 register *******************/
+ − 2780 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+ − 2781 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+ − 2782 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+ − 2783 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+ − 2784 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+ − 2785 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+ − 2786 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+ − 2787 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+ − 2788 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+ − 2789 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+ − 2790 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+ − 2791 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+ − 2792 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+ − 2793 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+ − 2794 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+ − 2795 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+ − 2796 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+ − 2797 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+ − 2798 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+ − 2799 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+ − 2800 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+ − 2801 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+ − 2802 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+ − 2803 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+ − 2804 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+ − 2805 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+ − 2806 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+ − 2807 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+ − 2808 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+ − 2809 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+ − 2810 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+ − 2811 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+ − 2812
+ − 2813 /******************* Bit definition for CAN_F8R2 register *******************/
+ − 2814 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+ − 2815 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+ − 2816 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+ − 2817 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+ − 2818 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+ − 2819 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+ − 2820 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+ − 2821 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+ − 2822 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+ − 2823 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+ − 2824 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+ − 2825 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+ − 2826 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+ − 2827 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+ − 2828 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+ − 2829 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+ − 2830 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+ − 2831 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+ − 2832 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+ − 2833 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+ − 2834 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+ − 2835 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+ − 2836 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+ − 2837 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+ − 2838 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+ − 2839 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+ − 2840 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+ − 2841 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+ − 2842 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+ − 2843 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+ − 2844 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+ − 2845 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+ − 2846
+ − 2847 /******************* Bit definition for CAN_F9R2 register *******************/
+ − 2848 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+ − 2849 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+ − 2850 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+ − 2851 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+ − 2852 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+ − 2853 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+ − 2854 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+ − 2855 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+ − 2856 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+ − 2857 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+ − 2858 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+ − 2859 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+ − 2860 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+ − 2861 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+ − 2862 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+ − 2863 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+ − 2864 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+ − 2865 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+ − 2866 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+ − 2867 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+ − 2868 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+ − 2869 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+ − 2870 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+ − 2871 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+ − 2872 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+ − 2873 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+ − 2874 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+ − 2875 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+ − 2876 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+ − 2877 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+ − 2878 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+ − 2879 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+ − 2880
+ − 2881 /******************* Bit definition for CAN_F10R2 register ******************/
+ − 2882 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+ − 2883 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+ − 2884 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+ − 2885 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+ − 2886 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+ − 2887 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+ − 2888 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+ − 2889 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+ − 2890 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+ − 2891 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+ − 2892 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+ − 2893 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+ − 2894 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+ − 2895 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+ − 2896 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+ − 2897 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+ − 2898 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+ − 2899 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+ − 2900 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+ − 2901 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+ − 2902 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+ − 2903 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+ − 2904 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+ − 2905 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+ − 2906 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+ − 2907 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+ − 2908 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+ − 2909 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+ − 2910 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+ − 2911 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+ − 2912 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+ − 2913 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+ − 2914
+ − 2915 /******************* Bit definition for CAN_F11R2 register ******************/
+ − 2916 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+ − 2917 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+ − 2918 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+ − 2919 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+ − 2920 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+ − 2921 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+ − 2922 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+ − 2923 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+ − 2924 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+ − 2925 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+ − 2926 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+ − 2927 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+ − 2928 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+ − 2929 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+ − 2930 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+ − 2931 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+ − 2932 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+ − 2933 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+ − 2934 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+ − 2935 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+ − 2936 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+ − 2937 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+ − 2938 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+ − 2939 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+ − 2940 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+ − 2941 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+ − 2942 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+ − 2943 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+ − 2944 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+ − 2945 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+ − 2946 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+ − 2947 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+ − 2948
+ − 2949 /******************* Bit definition for CAN_F12R2 register ******************/
+ − 2950 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+ − 2951 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+ − 2952 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+ − 2953 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+ − 2954 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+ − 2955 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+ − 2956 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+ − 2957 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+ − 2958 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+ − 2959 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+ − 2960 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+ − 2961 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+ − 2962 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+ − 2963 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+ − 2964 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+ − 2965 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+ − 2966 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+ − 2967 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+ − 2968 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+ − 2969 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+ − 2970 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+ − 2971 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+ − 2972 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+ − 2973 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+ − 2974 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+ − 2975 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+ − 2976 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+ − 2977 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+ − 2978 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+ − 2979 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+ − 2980 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+ − 2981 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+ − 2982
+ − 2983 /******************* Bit definition for CAN_F13R2 register ******************/
+ − 2984 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+ − 2985 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+ − 2986 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+ − 2987 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+ − 2988 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+ − 2989 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+ − 2990 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+ − 2991 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+ − 2992 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+ − 2993 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+ − 2994 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+ − 2995 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+ − 2996 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+ − 2997 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+ − 2998 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+ − 2999 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+ − 3000 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+ − 3001 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+ − 3002 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+ − 3003 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+ − 3004 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+ − 3005 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+ − 3006 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+ − 3007 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+ − 3008 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+ − 3009 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+ − 3010 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+ − 3011 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+ − 3012 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+ − 3013 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+ − 3014 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+ − 3015 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+ − 3016
+ − 3017 /******************************************************************************/
+ − 3018 /* */
+ − 3019 /* CRC calculation unit */
+ − 3020 /* */
+ − 3021 /******************************************************************************/
+ − 3022 /******************* Bit definition for CRC_DR register *********************/
+ − 3023 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+ − 3024
+ − 3025
+ − 3026 /******************* Bit definition for CRC_IDR register ********************/
+ − 3027 #define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
+ − 3028
+ − 3029
+ − 3030 /******************** Bit definition for CRC_CR register ********************/
+ − 3031 #define CRC_CR_RESET ((uint32_t)0x01) /*!< RESET bit */
+ − 3032
+ − 3033 /******************************************************************************/
+ − 3034 /* */
+ − 3035 /* Digital to Analog Converter */
+ − 3036 /* */
+ − 3037 /******************************************************************************/
+ − 3038 /******************** Bit definition for DAC_CR register ********************/
+ − 3039 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
+ − 3040 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
+ − 3041 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
+ − 3042
+ − 3043 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+ − 3044 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+ − 3045 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+ − 3046 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+ − 3047
+ − 3048 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+ − 3049 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+ − 3050 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+ − 3051
+ − 3052 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+ − 3053 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+ − 3054 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+ − 3055 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+ − 3056 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+ − 3057
+ − 3058 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
+ − 3059 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
+ − 3060 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
+ − 3061 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
+ − 3062
+ − 3063 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+ − 3064 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
+ − 3065 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
+ − 3066 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
+ − 3067
+ − 3068 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+ − 3069 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
+ − 3070 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
+ − 3071
+ − 3072 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+ − 3073 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+ − 3074 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+ − 3075 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+ − 3076 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+ − 3077
+ − 3078 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
+ − 3079
+ − 3080 /***************** Bit definition for DAC_SWTRIGR register ******************/
+ − 3081 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x01) /*!<DAC channel1 software trigger */
+ − 3082 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x02) /*!<DAC channel2 software trigger */
+ − 3083
+ − 3084 /***************** Bit definition for DAC_DHR12R1 register ******************/
+ − 3085 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
+ − 3086
+ − 3087 /***************** Bit definition for DAC_DHR12L1 register ******************/
+ − 3088 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
+ − 3089
+ − 3090 /****************** Bit definition for DAC_DHR8R1 register ******************/
+ − 3091 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
+ − 3092
+ − 3093 /***************** Bit definition for DAC_DHR12R2 register ******************/
+ − 3094 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
+ − 3095
+ − 3096 /***************** Bit definition for DAC_DHR12L2 register ******************/
+ − 3097 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
+ − 3098
+ − 3099 /****************** Bit definition for DAC_DHR8R2 register ******************/
+ − 3100 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
+ − 3101
+ − 3102 /***************** Bit definition for DAC_DHR12RD register ******************/
+ − 3103 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
+ − 3104 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
+ − 3105
+ − 3106 /***************** Bit definition for DAC_DHR12LD register ******************/
+ − 3107 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
+ − 3108 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
+ − 3109
+ − 3110 /****************** Bit definition for DAC_DHR8RD register ******************/
+ − 3111 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
+ − 3112 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
+ − 3113
+ − 3114 /******************* Bit definition for DAC_DOR1 register *******************/
+ − 3115 #define DAC_DOR1_DACC1DOR ((uint32_t)0x0FFF) /*!<DAC channel1 data output */
+ − 3116
+ − 3117 /******************* Bit definition for DAC_DOR2 register *******************/
+ − 3118 #define DAC_DOR2_DACC2DOR ((uint32_t)0x0FFF) /*!<DAC channel2 data output */
+ − 3119
+ − 3120 /******************** Bit definition for DAC_SR register ********************/
+ − 3121 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
+ − 3122 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
+ − 3123
+ − 3124 /******************************************************************************/
+ − 3125 /* */
+ − 3126 /* Debug MCU */
+ − 3127 /* */
+ − 3128 /******************************************************************************/
+ − 3129
+ − 3130 /******************************************************************************/
+ − 3131 /* */
+ − 3132 /* DCMI */
+ − 3133 /* */
+ − 3134 /******************************************************************************/
+ − 3135 /******************** Bits definition for DCMI_CR register ******************/
+ − 3136 #define DCMI_CR_CAPTURE ((uint32_t)0x00000001)
+ − 3137 #define DCMI_CR_CM ((uint32_t)0x00000002)
+ − 3138 #define DCMI_CR_CROP ((uint32_t)0x00000004)
+ − 3139 #define DCMI_CR_JPEG ((uint32_t)0x00000008)
+ − 3140 #define DCMI_CR_ESS ((uint32_t)0x00000010)
+ − 3141 #define DCMI_CR_PCKPOL ((uint32_t)0x00000020)
+ − 3142 #define DCMI_CR_HSPOL ((uint32_t)0x00000040)
+ − 3143 #define DCMI_CR_VSPOL ((uint32_t)0x00000080)
+ − 3144 #define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)
+ − 3145 #define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)
+ − 3146 #define DCMI_CR_EDM_0 ((uint32_t)0x00000400)
+ − 3147 #define DCMI_CR_EDM_1 ((uint32_t)0x00000800)
+ − 3148 #define DCMI_CR_CRE ((uint32_t)0x00001000)
+ − 3149 #define DCMI_CR_ENABLE ((uint32_t)0x00004000)
+ − 3150
+ − 3151 /******************** Bits definition for DCMI_SR register ******************/
+ − 3152 #define DCMI_SR_HSYNC ((uint32_t)0x00000001)
+ − 3153 #define DCMI_SR_VSYNC ((uint32_t)0x00000002)
+ − 3154 #define DCMI_SR_FNE ((uint32_t)0x00000004)
+ − 3155
+ − 3156 /******************** Bits definition for DCMI_RISR register ****************/
+ − 3157 #define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)
+ − 3158 #define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)
+ − 3159 #define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)
+ − 3160 #define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)
+ − 3161 #define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)
+ − 3162
+ − 3163 /******************** Bits definition for DCMI_IER register *****************/
+ − 3164 #define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)
+ − 3165 #define DCMI_IER_OVF_IE ((uint32_t)0x00000002)
+ − 3166 #define DCMI_IER_ERR_IE ((uint32_t)0x00000004)
+ − 3167 #define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)
+ − 3168 #define DCMI_IER_LINE_IE ((uint32_t)0x00000010)
+ − 3169
+ − 3170 /******************** Bits definition for DCMI_MISR register ****************/
+ − 3171 #define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)
+ − 3172 #define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)
+ − 3173 #define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)
+ − 3174 #define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)
+ − 3175 #define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)
+ − 3176
+ − 3177 /******************** Bits definition for DCMI_ICR register *****************/
+ − 3178 #define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)
+ − 3179 #define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)
+ − 3180 #define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)
+ − 3181 #define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)
+ − 3182 #define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)
+ − 3183
+ − 3184 /******************************************************************************/
+ − 3185 /* */
+ − 3186 /* DMA Controller */
+ − 3187 /* */
+ − 3188 /******************************************************************************/
+ − 3189 /******************** Bits definition for DMA_SxCR register *****************/
+ − 3190 #define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
+ − 3191 #define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
+ − 3192 #define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
+ − 3193 #define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
+ − 3194 #define DMA_SxCR_MBURST ((uint32_t)0x01800000)
+ − 3195 #define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
+ − 3196 #define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
+ − 3197 #define DMA_SxCR_PBURST ((uint32_t)0x00600000)
+ − 3198 #define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
+ − 3199 #define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
+ − 3200 #define DMA_SxCR_ACK ((uint32_t)0x00100000)
+ − 3201 #define DMA_SxCR_CT ((uint32_t)0x00080000)
+ − 3202 #define DMA_SxCR_DBM ((uint32_t)0x00040000)
+ − 3203 #define DMA_SxCR_PL ((uint32_t)0x00030000)
+ − 3204 #define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
+ − 3205 #define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
+ − 3206 #define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
+ − 3207 #define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
+ − 3208 #define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
+ − 3209 #define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
+ − 3210 #define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
+ − 3211 #define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
+ − 3212 #define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
+ − 3213 #define DMA_SxCR_MINC ((uint32_t)0x00000400)
+ − 3214 #define DMA_SxCR_PINC ((uint32_t)0x00000200)
+ − 3215 #define DMA_SxCR_CIRC ((uint32_t)0x00000100)
+ − 3216 #define DMA_SxCR_DIR ((uint32_t)0x000000C0)
+ − 3217 #define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
+ − 3218 #define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
+ − 3219 #define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
+ − 3220 #define DMA_SxCR_TCIE ((uint32_t)0x00000010)
+ − 3221 #define DMA_SxCR_HTIE ((uint32_t)0x00000008)
+ − 3222 #define DMA_SxCR_TEIE ((uint32_t)0x00000004)
+ − 3223 #define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
+ − 3224 #define DMA_SxCR_EN ((uint32_t)0x00000001)
+ − 3225
+ − 3226 /******************** Bits definition for DMA_SxCNDTR register **************/
+ − 3227 #define DMA_SxNDT ((uint32_t)0x0000FFFF)
+ − 3228 #define DMA_SxNDT_0 ((uint32_t)0x00000001)
+ − 3229 #define DMA_SxNDT_1 ((uint32_t)0x00000002)
+ − 3230 #define DMA_SxNDT_2 ((uint32_t)0x00000004)
+ − 3231 #define DMA_SxNDT_3 ((uint32_t)0x00000008)
+ − 3232 #define DMA_SxNDT_4 ((uint32_t)0x00000010)
+ − 3233 #define DMA_SxNDT_5 ((uint32_t)0x00000020)
+ − 3234 #define DMA_SxNDT_6 ((uint32_t)0x00000040)
+ − 3235 #define DMA_SxNDT_7 ((uint32_t)0x00000080)
+ − 3236 #define DMA_SxNDT_8 ((uint32_t)0x00000100)
+ − 3237 #define DMA_SxNDT_9 ((uint32_t)0x00000200)
+ − 3238 #define DMA_SxNDT_10 ((uint32_t)0x00000400)
+ − 3239 #define DMA_SxNDT_11 ((uint32_t)0x00000800)
+ − 3240 #define DMA_SxNDT_12 ((uint32_t)0x00001000)
+ − 3241 #define DMA_SxNDT_13 ((uint32_t)0x00002000)
+ − 3242 #define DMA_SxNDT_14 ((uint32_t)0x00004000)
+ − 3243 #define DMA_SxNDT_15 ((uint32_t)0x00008000)
+ − 3244
+ − 3245 /******************** Bits definition for DMA_SxFCR register ****************/
+ − 3246 #define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
+ − 3247 #define DMA_SxFCR_FS ((uint32_t)0x00000038)
+ − 3248 #define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
+ − 3249 #define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
+ − 3250 #define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
+ − 3251 #define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
+ − 3252 #define DMA_SxFCR_FTH ((uint32_t)0x00000003)
+ − 3253 #define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
+ − 3254 #define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
+ − 3255
+ − 3256 /******************** Bits definition for DMA_LISR register *****************/
+ − 3257 #define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
+ − 3258 #define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
+ − 3259 #define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
+ − 3260 #define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
+ − 3261 #define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
+ − 3262 #define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
+ − 3263 #define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
+ − 3264 #define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
+ − 3265 #define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
+ − 3266 #define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
+ − 3267 #define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
+ − 3268 #define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
+ − 3269 #define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
+ − 3270 #define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
+ − 3271 #define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
+ − 3272 #define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
+ − 3273 #define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
+ − 3274 #define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
+ − 3275 #define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
+ − 3276 #define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
+ − 3277
+ − 3278 /******************** Bits definition for DMA_HISR register *****************/
+ − 3279 #define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
+ − 3280 #define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
+ − 3281 #define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
+ − 3282 #define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
+ − 3283 #define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
+ − 3284 #define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
+ − 3285 #define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
+ − 3286 #define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
+ − 3287 #define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
+ − 3288 #define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
+ − 3289 #define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
+ − 3290 #define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
+ − 3291 #define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
+ − 3292 #define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
+ − 3293 #define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
+ − 3294 #define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
+ − 3295 #define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
+ − 3296 #define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
+ − 3297 #define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
+ − 3298 #define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
+ − 3299
+ − 3300 /******************** Bits definition for DMA_LIFCR register ****************/
+ − 3301 #define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
+ − 3302 #define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
+ − 3303 #define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
+ − 3304 #define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
+ − 3305 #define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
+ − 3306 #define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
+ − 3307 #define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
+ − 3308 #define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
+ − 3309 #define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
+ − 3310 #define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
+ − 3311 #define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
+ − 3312 #define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
+ − 3313 #define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
+ − 3314 #define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
+ − 3315 #define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
+ − 3316 #define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
+ − 3317 #define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
+ − 3318 #define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
+ − 3319 #define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
+ − 3320 #define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
+ − 3321
+ − 3322 /******************** Bits definition for DMA_HIFCR register ****************/
+ − 3323 #define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
+ − 3324 #define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
+ − 3325 #define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
+ − 3326 #define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
+ − 3327 #define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
+ − 3328 #define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
+ − 3329 #define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
+ − 3330 #define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
+ − 3331 #define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
+ − 3332 #define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
+ − 3333 #define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
+ − 3334 #define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
+ − 3335 #define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
+ − 3336 #define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
+ − 3337 #define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
+ − 3338 #define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
+ − 3339 #define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
+ − 3340 #define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
+ − 3341 #define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
+ − 3342 #define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
+ − 3343
+ − 3344
+ − 3345 /******************************************************************************/
+ − 3346 /* */
+ − 3347 /* AHB Master DMA2D Controller (DMA2D) */
+ − 3348 /* */
+ − 3349 /******************************************************************************/
+ − 3350
+ − 3351 /******************** Bit definition for DMA2D_CR register ******************/
+ − 3352
+ − 3353 #define DMA2D_CR_START ((uint32_t)0x00000001) /*!< Start transfer */
+ − 3354 #define DMA2D_CR_SUSP ((uint32_t)0x00000002) /*!< Suspend transfer */
+ − 3355 #define DMA2D_CR_ABORT ((uint32_t)0x00000004) /*!< Abort transfer */
+ − 3356 #define DMA2D_CR_TEIE ((uint32_t)0x00000100) /*!< Transfer Error Interrupt Enable */
+ − 3357 #define DMA2D_CR_TCIE ((uint32_t)0x00000200) /*!< Transfer Complete Interrupt Enable */
+ − 3358 #define DMA2D_CR_TWIE ((uint32_t)0x00000400) /*!< Transfer Watermark Interrupt Enable */
+ − 3359 #define DMA2D_CR_CAEIE ((uint32_t)0x00000800) /*!< CLUT Access Error Interrupt Enable */
+ − 3360 #define DMA2D_CR_CTCIE ((uint32_t)0x00001000) /*!< CLUT Transfer Complete Interrupt Enable */
+ − 3361 #define DMA2D_CR_CEIE ((uint32_t)0x00002000) /*!< Configuration Error Interrupt Enable */
+ − 3362 #define DMA2D_CR_MODE ((uint32_t)0x00030000) /*!< DMA2D Mode */
+ − 3363
+ − 3364 /******************** Bit definition for DMA2D_ISR register *****************/
+ − 3365
+ − 3366 #define DMA2D_ISR_TEIF ((uint32_t)0x00000001) /*!< Transfer Error Interrupt Flag */
+ − 3367 #define DMA2D_ISR_TCIF ((uint32_t)0x00000002) /*!< Transfer Complete Interrupt Flag */
+ − 3368 #define DMA2D_ISR_TWIF ((uint32_t)0x00000004) /*!< Transfer Watermark Interrupt Flag */
+ − 3369 #define DMA2D_ISR_CAEIF ((uint32_t)0x00000008) /*!< CLUT Access Error Interrupt Flag */
+ − 3370 #define DMA2D_ISR_CTCIF ((uint32_t)0x00000010) /*!< CLUT Transfer Complete Interrupt Flag */
+ − 3371 #define DMA2D_ISR_CEIF ((uint32_t)0x00000020) /*!< Configuration Error Interrupt Flag */
+ − 3372
+ − 3373 /******************** Bit definition for DMA2D_IFSR register ****************/
+ − 3374
+ − 3375 #define DMA2D_IFSR_CTEIF ((uint32_t)0x00000001) /*!< Clears Transfer Error Interrupt Flag */
+ − 3376 #define DMA2D_IFSR_CTCIF ((uint32_t)0x00000002) /*!< Clears Transfer Complete Interrupt Flag */
+ − 3377 #define DMA2D_IFSR_CTWIF ((uint32_t)0x00000004) /*!< Clears Transfer Watermark Interrupt Flag */
+ − 3378 #define DMA2D_IFSR_CCAEIF ((uint32_t)0x00000008) /*!< Clears CLUT Access Error Interrupt Flag */
+ − 3379 #define DMA2D_IFSR_CCTCIF ((uint32_t)0x00000010) /*!< Clears CLUT Transfer Complete Interrupt Flag */
+ − 3380 #define DMA2D_IFSR_CCEIF ((uint32_t)0x00000020) /*!< Clears Configuration Error Interrupt Flag */
+ − 3381
+ − 3382 /******************** Bit definition for DMA2D_FGMAR register ***************/
+ − 3383
+ − 3384 #define DMA2D_FGMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+ − 3385
+ − 3386 /******************** Bit definition for DMA2D_FGOR register ****************/
+ − 3387
+ − 3388 #define DMA2D_FGOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */
+ − 3389
+ − 3390 /******************** Bit definition for DMA2D_BGMAR register ***************/
+ − 3391
+ − 3392 #define DMA2D_BGMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+ − 3393
+ − 3394 /******************** Bit definition for DMA2D_BGOR register ****************/
+ − 3395
+ − 3396 #define DMA2D_BGOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */
+ − 3397
+ − 3398 /******************** Bit definition for DMA2D_FGPFCCR register *************/
+ − 3399
+ − 3400 #define DMA2D_FGPFCCR_CM ((uint32_t)0x0000000F) /*!< Color mode */
+ − 3401 #define DMA2D_FGPFCCR_CCM ((uint32_t)0x00000010) /*!< CLUT Color mode */
+ − 3402 #define DMA2D_FGPFCCR_START ((uint32_t)0x00000020) /*!< Start */
+ − 3403 #define DMA2D_FGPFCCR_CS ((uint32_t)0x0000FF00) /*!< CLUT size */
+ − 3404 #define DMA2D_FGPFCCR_AM ((uint32_t)0x00030000) /*!< Alpha mode */
+ − 3405 #define DMA2D_FGPFCCR_ALPHA ((uint32_t)0xFF000000) /*!< Alpha value */
+ − 3406
+ − 3407 /******************** Bit definition for DMA2D_FGCOLR register **************/
+ − 3408
+ − 3409 #define DMA2D_FGCOLR_BLUE ((uint32_t)0x000000FF) /*!< Blue Value */
+ − 3410 #define DMA2D_FGCOLR_GREEN ((uint32_t)0x0000FF00) /*!< Green Value */
+ − 3411 #define DMA2D_FGCOLR_RED ((uint32_t)0x00FF0000) /*!< Red Value */
+ − 3412
+ − 3413 /******************** Bit definition for DMA2D_BGPFCCR register *************/
+ − 3414
+ − 3415 #define DMA2D_BGPFCCR_CM ((uint32_t)0x0000000F) /*!< Color mode */
+ − 3416 #define DMA2D_BGPFCCR_CCM ((uint32_t)0x00000010) /*!< CLUT Color mode */
+ − 3417 #define DMA2D_BGPFCCR_START ((uint32_t)0x00000020) /*!< Start */
+ − 3418 #define DMA2D_BGPFCCR_CS ((uint32_t)0x0000FF00) /*!< CLUT size */
+ − 3419 #define DMA2D_BGPFCCR_AM ((uint32_t)0x00030000) /*!< Alpha Mode */
+ − 3420 #define DMA2D_BGPFCCR_ALPHA ((uint32_t)0xFF000000) /*!< Alpha value */
+ − 3421
+ − 3422 /******************** Bit definition for DMA2D_BGCOLR register **************/
+ − 3423
+ − 3424 #define DMA2D_BGCOLR_BLUE ((uint32_t)0x000000FF) /*!< Blue Value */
+ − 3425 #define DMA2D_BGCOLR_GREEN ((uint32_t)0x0000FF00) /*!< Green Value */
+ − 3426 #define DMA2D_BGCOLR_RED ((uint32_t)0x00FF0000) /*!< Red Value */
+ − 3427
+ − 3428 /******************** Bit definition for DMA2D_FGCMAR register **************/
+ − 3429
+ − 3430 #define DMA2D_FGCMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+ − 3431
+ − 3432 /******************** Bit definition for DMA2D_BGCMAR register **************/
+ − 3433
+ − 3434 #define DMA2D_BGCMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+ − 3435
+ − 3436 /******************** Bit definition for DMA2D_OPFCCR register **************/
+ − 3437
+ − 3438 #define DMA2D_OPFCCR_CM ((uint32_t)0x00000007) /*!< Color mode */
+ − 3439
+ − 3440 /******************** Bit definition for DMA2D_OCOLR register ***************/
+ − 3441
+ − 3442 /*!<Mode_ARGB8888/RGB888 */
+ − 3443
+ − 3444 #define DMA2D_OCOLR_BLUE_1 ((uint32_t)0x000000FF) /*!< BLUE Value */
+ − 3445 #define DMA2D_OCOLR_GREEN_1 ((uint32_t)0x0000FF00) /*!< GREEN Value */
+ − 3446 #define DMA2D_OCOLR_RED_1 ((uint32_t)0x00FF0000) /*!< Red Value */
+ − 3447 #define DMA2D_OCOLR_ALPHA_1 ((uint32_t)0xFF000000) /*!< Alpha Channel Value */
+ − 3448
+ − 3449 /*!<Mode_RGB565 */
+ − 3450 #define DMA2D_OCOLR_BLUE_2 ((uint32_t)0x0000001F) /*!< BLUE Value */
+ − 3451 #define DMA2D_OCOLR_GREEN_2 ((uint32_t)0x000007E0) /*!< GREEN Value */
+ − 3452 #define DMA2D_OCOLR_RED_2 ((uint32_t)0x0000F800) /*!< Red Value */
+ − 3453
+ − 3454 /*!<Mode_ARGB1555 */
+ − 3455 #define DMA2D_OCOLR_BLUE_3 ((uint32_t)0x0000001F) /*!< BLUE Value */
+ − 3456 #define DMA2D_OCOLR_GREEN_3 ((uint32_t)0x000003E0) /*!< GREEN Value */
+ − 3457 #define DMA2D_OCOLR_RED_3 ((uint32_t)0x00007C00) /*!< Red Value */
+ − 3458 #define DMA2D_OCOLR_ALPHA_3 ((uint32_t)0x00008000) /*!< Alpha Channel Value */
+ − 3459
+ − 3460 /*!<Mode_ARGB4444 */
+ − 3461 #define DMA2D_OCOLR_BLUE_4 ((uint32_t)0x0000000F) /*!< BLUE Value */
+ − 3462 #define DMA2D_OCOLR_GREEN_4 ((uint32_t)0x000000F0) /*!< GREEN Value */
+ − 3463 #define DMA2D_OCOLR_RED_4 ((uint32_t)0x00000F00) /*!< Red Value */
+ − 3464 #define DMA2D_OCOLR_ALPHA_4 ((uint32_t)0x0000F000) /*!< Alpha Channel Value */
+ − 3465
+ − 3466 /******************** Bit definition for DMA2D_OMAR register ****************/
+ − 3467
+ − 3468 #define DMA2D_OMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+ − 3469
+ − 3470 /******************** Bit definition for DMA2D_OOR register *****************/
+ − 3471
+ − 3472 #define DMA2D_OOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */
+ − 3473
+ − 3474 /******************** Bit definition for DMA2D_NLR register *****************/
+ − 3475
+ − 3476 #define DMA2D_NLR_NL ((uint32_t)0x0000FFFF) /*!< Number of Lines */
+ − 3477 #define DMA2D_NLR_PL ((uint32_t)0x3FFF0000) /*!< Pixel per Lines */
+ − 3478
+ − 3479 /******************** Bit definition for DMA2D_LWR register *****************/
+ − 3480
+ − 3481 #define DMA2D_LWR_LW ((uint32_t)0x0000FFFF) /*!< Line Watermark */
+ − 3482
+ − 3483 /******************** Bit definition for DMA2D_AMTCR register ***************/
+ − 3484
+ − 3485 #define DMA2D_AMTCR_EN ((uint32_t)0x00000001) /*!< Enable */
+ − 3486 #define DMA2D_AMTCR_DT ((uint32_t)0x0000FF00) /*!< Dead Time */
+ − 3487
+ − 3488
+ − 3489 /******************** Bit definition for DMA2D_FGCLUT register **************/
+ − 3490
+ − 3491 /******************** Bit definition for DMA2D_BGCLUT register **************/
+ − 3492
+ − 3493
+ − 3494
+ − 3495 /******************************************************************************/
+ − 3496 /* */
+ − 3497 /* External Interrupt/Event Controller */
+ − 3498 /* */
+ − 3499 /******************************************************************************/
+ − 3500 /******************* Bit definition for EXTI_IMR register *******************/
+ − 3501 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
+ − 3502 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
+ − 3503 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
+ − 3504 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
+ − 3505 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
+ − 3506 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
+ − 3507 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
+ − 3508 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
+ − 3509 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
+ − 3510 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
+ − 3511 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
+ − 3512 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
+ − 3513 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
+ − 3514 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
+ − 3515 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
+ − 3516 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
+ − 3517 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
+ − 3518 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
+ − 3519 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
+ − 3520 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+ − 3521
+ − 3522 /******************* Bit definition for EXTI_EMR register *******************/
+ − 3523 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
+ − 3524 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
+ − 3525 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
+ − 3526 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
+ − 3527 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
+ − 3528 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
+ − 3529 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
+ − 3530 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
+ − 3531 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
+ − 3532 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
+ − 3533 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
+ − 3534 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
+ − 3535 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
+ − 3536 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
+ − 3537 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
+ − 3538 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
+ − 3539 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
+ − 3540 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
+ − 3541 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
+ − 3542 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+ − 3543
+ − 3544 /****************** Bit definition for EXTI_RTSR register *******************/
+ − 3545 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
+ − 3546 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
+ − 3547 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
+ − 3548 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
+ − 3549 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
+ − 3550 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
+ − 3551 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
+ − 3552 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
+ − 3553 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
+ − 3554 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
+ − 3555 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
+ − 3556 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
+ − 3557 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
+ − 3558 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
+ − 3559 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
+ − 3560 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
+ − 3561 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
+ − 3562 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
+ − 3563 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
+ − 3564 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+ − 3565
+ − 3566 /****************** Bit definition for EXTI_FTSR register *******************/
+ − 3567 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
+ − 3568 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
+ − 3569 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
+ − 3570 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
+ − 3571 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
+ − 3572 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
+ − 3573 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
+ − 3574 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
+ − 3575 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
+ − 3576 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
+ − 3577 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
+ − 3578 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
+ − 3579 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
+ − 3580 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
+ − 3581 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
+ − 3582 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
+ − 3583 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
+ − 3584 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
+ − 3585 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
+ − 3586 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+ − 3587
+ − 3588 /****************** Bit definition for EXTI_SWIER register ******************/
+ − 3589 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
+ − 3590 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
+ − 3591 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
+ − 3592 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
+ − 3593 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
+ − 3594 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
+ − 3595 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
+ − 3596 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
+ − 3597 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
+ − 3598 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
+ − 3599 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
+ − 3600 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
+ − 3601 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
+ − 3602 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
+ − 3603 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
+ − 3604 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
+ − 3605 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
+ − 3606 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
+ − 3607 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
+ − 3608 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+ − 3609
+ − 3610 /******************* Bit definition for EXTI_PR register ********************/
+ − 3611 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
+ − 3612 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
+ − 3613 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
+ − 3614 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
+ − 3615 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
+ − 3616 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
+ − 3617 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
+ − 3618 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
+ − 3619 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
+ − 3620 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
+ − 3621 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
+ − 3622 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
+ − 3623 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
+ − 3624 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
+ − 3625 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
+ − 3626 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
+ − 3627 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
+ − 3628 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
+ − 3629 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
+ − 3630 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+ − 3631
+ − 3632 /******************************************************************************/
+ − 3633 /* */
+ − 3634 /* FLASH */
+ − 3635 /* */
+ − 3636 /******************************************************************************/
+ − 3637 /******************* Bits definition for FLASH_ACR register *****************/
+ − 3638 #define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
+ − 3639 #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
+ − 3640 #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
+ − 3641 #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
+ − 3642 #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
+ − 3643 #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
+ − 3644 #define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
+ − 3645 #define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
+ − 3646 #define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
+ − 3647 #define FLASH_ACR_LATENCY_8WS ((uint32_t)0x00000008)
+ − 3648 #define FLASH_ACR_LATENCY_9WS ((uint32_t)0x00000009)
+ − 3649 #define FLASH_ACR_LATENCY_10WS ((uint32_t)0x0000000A)
+ − 3650 #define FLASH_ACR_LATENCY_11WS ((uint32_t)0x0000000B)
+ − 3651 #define FLASH_ACR_LATENCY_12WS ((uint32_t)0x0000000C)
+ − 3652 #define FLASH_ACR_LATENCY_13WS ((uint32_t)0x0000000D)
+ − 3653 #define FLASH_ACR_LATENCY_14WS ((uint32_t)0x0000000E)
+ − 3654 #define FLASH_ACR_LATENCY_15WS ((uint32_t)0x0000000F)
+ − 3655 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
+ − 3656 #define FLASH_ACR_ICEN ((uint32_t)0x00000200)
+ − 3657 #define FLASH_ACR_DCEN ((uint32_t)0x00000400)
+ − 3658 #define FLASH_ACR_ICRST ((uint32_t)0x00000800)
+ − 3659 #define FLASH_ACR_DCRST ((uint32_t)0x00001000)
+ − 3660 #define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
+ − 3661 #define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
+ − 3662
+ − 3663 /******************* Bits definition for FLASH_SR register ******************/
+ − 3664 #define FLASH_SR_EOP ((uint32_t)0x00000001)
+ − 3665 #define FLASH_SR_SOP ((uint32_t)0x00000002)
+ − 3666 #define FLASH_SR_WRPERR ((uint32_t)0x00000010)
+ − 3667 #define FLASH_SR_PGAERR ((uint32_t)0x00000020)
+ − 3668 #define FLASH_SR_PGPERR ((uint32_t)0x00000040)
+ − 3669 #define FLASH_SR_PGSERR ((uint32_t)0x00000080)
+ − 3670 #define FLASH_SR_BSY ((uint32_t)0x00010000)
+ − 3671
+ − 3672 /******************* Bits definition for FLASH_CR register ******************/
+ − 3673 #define FLASH_CR_PG ((uint32_t)0x00000001)
+ − 3674 #define FLASH_CR_SER ((uint32_t)0x00000002)
+ − 3675 #define FLASH_CR_MER ((uint32_t)0x00000004)
+ − 3676 #define FLASH_CR_MER1 FLASH_CR_MER
+ − 3677 #define FLASH_CR_SNB ((uint32_t)0x000000F8)
+ − 3678 #define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
+ − 3679 #define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
+ − 3680 #define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
+ − 3681 #define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
+ − 3682 #define FLASH_CR_SNB_4 ((uint32_t)0x00000080)
+ − 3683 #define FLASH_CR_PSIZE ((uint32_t)0x00000300)
+ − 3684 #define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
+ − 3685 #define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
+ − 3686 #define FLASH_CR_MER2 ((uint32_t)0x00008000)
+ − 3687 #define FLASH_CR_STRT ((uint32_t)0x00010000)
+ − 3688 #define FLASH_CR_EOPIE ((uint32_t)0x01000000)
+ − 3689 #define FLASH_CR_LOCK ((uint32_t)0x80000000)
+ − 3690
+ − 3691 /******************* Bits definition for FLASH_OPTCR register ***************/
+ − 3692 #define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
+ − 3693 #define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
+ − 3694 #define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
+ − 3695 #define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
+ − 3696 #define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
+ − 3697 #define FLASH_OPTCR_BFB2 ((uint32_t)0x00000010)
+ − 3698 #define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
+ − 3699 #define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
+ − 3700 #define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
+ − 3701 #define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
+ − 3702 #define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
+ − 3703 #define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
+ − 3704 #define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
+ − 3705 #define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
+ − 3706 #define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
+ − 3707 #define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
+ − 3708 #define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
+ − 3709 #define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
+ − 3710 #define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)
+ − 3711 #define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
+ − 3712 #define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
+ − 3713 #define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
+ − 3714 #define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
+ − 3715 #define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
+ − 3716 #define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
+ − 3717 #define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
+ − 3718 #define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
+ − 3719 #define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
+ − 3720 #define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
+ − 3721 #define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
+ − 3722 #define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
+ − 3723 #define FLASH_OPTCR_DB1M ((uint32_t)0x40000000)
+ − 3724 #define FLASH_OPTCR_SPRMOD ((uint32_t)0x80000000)
+ − 3725
+ − 3726 /****************** Bits definition for FLASH_OPTCR1 register ***************/
+ − 3727 #define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)
+ − 3728 #define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)
+ − 3729 #define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)
+ − 3730 #define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)
+ − 3731 #define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)
+ − 3732 #define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)
+ − 3733 #define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)
+ − 3734 #define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)
+ − 3735 #define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)
+ − 3736 #define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)
+ − 3737 #define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)
+ − 3738 #define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)
+ − 3739 #define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)
+ − 3740
+ − 3741 /******************************************************************************/
+ − 3742 /* */
+ − 3743 /* Flexible Memory Controller */
+ − 3744 /* */
+ − 3745 /******************************************************************************/
+ − 3746 /****************** Bit definition for FMC_BCR1 register *******************/
+ − 3747 #define FMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
+ − 3748 #define FMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+ − 3749
+ − 3750 #define FMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
+ − 3751 #define FMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+ − 3752 #define FMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+ − 3753
+ − 3754 #define FMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
+ − 3755 #define FMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+ − 3756 #define FMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+ − 3757
+ − 3758 #define FMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
+ − 3759 #define FMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
+ − 3760 #define FMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
+ − 3761 #define FMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
+ − 3762 #define FMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
+ − 3763 #define FMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
+ − 3764 #define FMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
+ − 3765 #define FMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
+ − 3766 #define FMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
+ − 3767 #define FMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+ − 3768 #define FMC_BCR1_CCLKEN ((uint32_t)0x00100000) /*!<Continous clock enable */
+ − 3769
+ − 3770 /****************** Bit definition for FMC_BCR2 register *******************/
+ − 3771 #define FMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
+ − 3772 #define FMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+ − 3773
+ − 3774 #define FMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
+ − 3775 #define FMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+ − 3776 #define FMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+ − 3777
+ − 3778 #define FMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
+ − 3779 #define FMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+ − 3780 #define FMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+ − 3781
+ − 3782 #define FMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
+ − 3783 #define FMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
+ − 3784 #define FMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
+ − 3785 #define FMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
+ − 3786 #define FMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
+ − 3787 #define FMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
+ − 3788 #define FMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
+ − 3789 #define FMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
+ − 3790 #define FMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
+ − 3791 #define FMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+ − 3792
+ − 3793 /****************** Bit definition for FMC_BCR3 register *******************/
+ − 3794 #define FMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
+ − 3795 #define FMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+ − 3796
+ − 3797 #define FMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
+ − 3798 #define FMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+ − 3799 #define FMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+ − 3800
+ − 3801 #define FMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
+ − 3802 #define FMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+ − 3803 #define FMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+ − 3804
+ − 3805 #define FMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
+ − 3806 #define FMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
+ − 3807 #define FMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
+ − 3808 #define FMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
+ − 3809 #define FMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
+ − 3810 #define FMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
+ − 3811 #define FMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
+ − 3812 #define FMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
+ − 3813 #define FMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
+ − 3814 #define FMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+ − 3815
+ − 3816 /****************** Bit definition for FMC_BCR4 register *******************/
+ − 3817 #define FMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
+ − 3818 #define FMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+ − 3819
+ − 3820 #define FMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
+ − 3821 #define FMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+ − 3822 #define FMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+ − 3823
+ − 3824 #define FMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
+ − 3825 #define FMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+ − 3826 #define FMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+ − 3827
+ − 3828 #define FMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
+ − 3829 #define FMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
+ − 3830 #define FMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
+ − 3831 #define FMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
+ − 3832 #define FMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
+ − 3833 #define FMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
+ − 3834 #define FMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
+ − 3835 #define FMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
+ − 3836 #define FMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
+ − 3837 #define FMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+ − 3838
+ − 3839 /****************** Bit definition for FMC_BTR1 register ******************/
+ − 3840 #define FMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+ − 3841 #define FMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+ − 3842 #define FMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+ − 3843 #define FMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+ − 3844 #define FMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+ − 3845
+ − 3846 #define FMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+ − 3847 #define FMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+ − 3848 #define FMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+ − 3849 #define FMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+ − 3850 #define FMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+ − 3851
+ − 3852 #define FMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+ − 3853 #define FMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+ − 3854 #define FMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+ − 3855 #define FMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+ − 3856 #define FMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+ − 3857 #define FMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+ − 3858 #define FMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+ − 3859 #define FMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+ − 3860 #define FMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+ − 3861
+ − 3862 #define FMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+ − 3863 #define FMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+ − 3864 #define FMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+ − 3865 #define FMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+ − 3866 #define FMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+ − 3867
+ − 3868 #define FMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+ − 3869 #define FMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+ − 3870 #define FMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+ − 3871 #define FMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+ − 3872 #define FMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+ − 3873
+ − 3874 #define FMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+ − 3875 #define FMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+ − 3876 #define FMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+ − 3877 #define FMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+ − 3878 #define FMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+ − 3879
+ − 3880 #define FMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+ − 3881 #define FMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+ − 3882 #define FMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+ − 3883
+ − 3884 /****************** Bit definition for FMC_BTR2 register *******************/
+ − 3885 #define FMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+ − 3886 #define FMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+ − 3887 #define FMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+ − 3888 #define FMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+ − 3889 #define FMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+ − 3890
+ − 3891 #define FMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+ − 3892 #define FMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+ − 3893 #define FMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+ − 3894 #define FMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+ − 3895 #define FMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+ − 3896
+ − 3897 #define FMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+ − 3898 #define FMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+ − 3899 #define FMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+ − 3900 #define FMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+ − 3901 #define FMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+ − 3902 #define FMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+ − 3903 #define FMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+ − 3904 #define FMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+ − 3905 #define FMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+ − 3906
+ − 3907 #define FMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+ − 3908 #define FMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+ − 3909 #define FMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+ − 3910 #define FMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+ − 3911 #define FMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+ − 3912
+ − 3913 #define FMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+ − 3914 #define FMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+ − 3915 #define FMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+ − 3916 #define FMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+ − 3917 #define FMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+ − 3918
+ − 3919 #define FMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+ − 3920 #define FMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+ − 3921 #define FMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+ − 3922 #define FMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+ − 3923 #define FMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+ − 3924
+ − 3925 #define FMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+ − 3926 #define FMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+ − 3927 #define FMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+ − 3928
+ − 3929 /******************* Bit definition for FMC_BTR3 register *******************/
+ − 3930 #define FMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+ − 3931 #define FMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+ − 3932 #define FMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+ − 3933 #define FMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+ − 3934 #define FMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+ − 3935
+ − 3936 #define FMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+ − 3937 #define FMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+ − 3938 #define FMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+ − 3939 #define FMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+ − 3940 #define FMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+ − 3941
+ − 3942 #define FMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+ − 3943 #define FMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+ − 3944 #define FMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+ − 3945 #define FMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+ − 3946 #define FMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+ − 3947 #define FMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+ − 3948 #define FMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+ − 3949 #define FMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+ − 3950 #define FMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+ − 3951
+ − 3952 #define FMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+ − 3953 #define FMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+ − 3954 #define FMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+ − 3955 #define FMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+ − 3956 #define FMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+ − 3957
+ − 3958 #define FMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+ − 3959 #define FMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+ − 3960 #define FMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+ − 3961 #define FMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+ − 3962 #define FMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+ − 3963
+ − 3964 #define FMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+ − 3965 #define FMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+ − 3966 #define FMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+ − 3967 #define FMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+ − 3968 #define FMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+ − 3969
+ − 3970 #define FMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+ − 3971 #define FMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+ − 3972 #define FMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+ − 3973
+ − 3974 /****************** Bit definition for FMC_BTR4 register *******************/
+ − 3975 #define FMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+ − 3976 #define FMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+ − 3977 #define FMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+ − 3978 #define FMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+ − 3979 #define FMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+ − 3980
+ − 3981 #define FMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+ − 3982 #define FMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+ − 3983 #define FMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+ − 3984 #define FMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+ − 3985 #define FMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+ − 3986
+ − 3987 #define FMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+ − 3988 #define FMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+ − 3989 #define FMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+ − 3990 #define FMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+ − 3991 #define FMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+ − 3992 #define FMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+ − 3993 #define FMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+ − 3994 #define FMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+ − 3995 #define FMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+ − 3996
+ − 3997 #define FMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+ − 3998 #define FMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+ − 3999 #define FMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+ − 4000 #define FMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+ − 4001 #define FMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+ − 4002
+ − 4003 #define FMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+ − 4004 #define FMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+ − 4005 #define FMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+ − 4006 #define FMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+ − 4007 #define FMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+ − 4008
+ − 4009 #define FMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+ − 4010 #define FMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+ − 4011 #define FMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+ − 4012 #define FMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+ − 4013 #define FMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+ − 4014
+ − 4015 #define FMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+ − 4016 #define FMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+ − 4017 #define FMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+ − 4018
+ − 4019 /****************** Bit definition for FMC_BWTR1 register ******************/
+ − 4020 #define FMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+ − 4021 #define FMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+ − 4022 #define FMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+ − 4023 #define FMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+ − 4024 #define FMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+ − 4025
+ − 4026 #define FMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+ − 4027 #define FMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+ − 4028 #define FMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+ − 4029 #define FMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+ − 4030 #define FMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+ − 4031
+ − 4032 #define FMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+ − 4033 #define FMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+ − 4034 #define FMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+ − 4035 #define FMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+ − 4036 #define FMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+ − 4037 #define FMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+ − 4038 #define FMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+ − 4039 #define FMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+ − 4040 #define FMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+ − 4041
+ − 4042 #define FMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+ − 4043 #define FMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+ − 4044 #define FMC_BWTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+ − 4045 #define FMC_BWTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+ − 4046 #define FMC_BWTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+ − 4047
+ − 4048 #define FMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+ − 4049 #define FMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+ − 4050 #define FMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+ − 4051 #define FMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+ − 4052 #define FMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+ − 4053
+ − 4054 #define FMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+ − 4055 #define FMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+ − 4056 #define FMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+ − 4057 #define FMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+ − 4058 #define FMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+ − 4059
+ − 4060 #define FMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+ − 4061 #define FMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+ − 4062 #define FMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+ − 4063
+ − 4064 /****************** Bit definition for FMC_BWTR2 register ******************/
+ − 4065 #define FMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+ − 4066 #define FMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+ − 4067 #define FMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+ − 4068 #define FMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+ − 4069 #define FMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+ − 4070
+ − 4071 #define FMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+ − 4072 #define FMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+ − 4073 #define FMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+ − 4074 #define FMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+ − 4075 #define FMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+ − 4076
+ − 4077 #define FMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+ − 4078 #define FMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+ − 4079 #define FMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+ − 4080 #define FMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+ − 4081 #define FMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+ − 4082 #define FMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+ − 4083 #define FMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+ − 4084 #define FMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+ − 4085 #define FMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+ − 4086
+ − 4087 #define FMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+ − 4088 #define FMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+ − 4089 #define FMC_BWTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+ − 4090 #define FMC_BWTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+ − 4091 #define FMC_BWTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+ − 4092
+ − 4093 #define FMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+ − 4094 #define FMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+ − 4095 #define FMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/
+ − 4096 #define FMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+ − 4097 #define FMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+ − 4098
+ − 4099 #define FMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+ − 4100 #define FMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+ − 4101 #define FMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+ − 4102 #define FMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+ − 4103 #define FMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+ − 4104
+ − 4105 #define FMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+ − 4106 #define FMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+ − 4107 #define FMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+ − 4108
+ − 4109 /****************** Bit definition for FMC_BWTR3 register ******************/
+ − 4110 #define FMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+ − 4111 #define FMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+ − 4112 #define FMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+ − 4113 #define FMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+ − 4114 #define FMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+ − 4115
+ − 4116 #define FMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+ − 4117 #define FMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+ − 4118 #define FMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+ − 4119 #define FMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+ − 4120 #define FMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+ − 4121
+ − 4122 #define FMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+ − 4123 #define FMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+ − 4124 #define FMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+ − 4125 #define FMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+ − 4126 #define FMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+ − 4127 #define FMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+ − 4128 #define FMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+ − 4129 #define FMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+ − 4130 #define FMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+ − 4131
+ − 4132 #define FMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+ − 4133 #define FMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+ − 4134 #define FMC_BWTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+ − 4135 #define FMC_BWTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+ − 4136 #define FMC_BWTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+ − 4137
+ − 4138 #define FMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+ − 4139 #define FMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+ − 4140 #define FMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+ − 4141 #define FMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+ − 4142 #define FMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+ − 4143
+ − 4144 #define FMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+ − 4145 #define FMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+ − 4146 #define FMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+ − 4147 #define FMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+ − 4148 #define FMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+ − 4149
+ − 4150 #define FMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+ − 4151 #define FMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+ − 4152 #define FMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+ − 4153
+ − 4154 /****************** Bit definition for FMC_BWTR4 register ******************/
+ − 4155 #define FMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+ − 4156 #define FMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+ − 4157 #define FMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+ − 4158 #define FMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+ − 4159 #define FMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+ − 4160
+ − 4161 #define FMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+ − 4162 #define FMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+ − 4163 #define FMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+ − 4164 #define FMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+ − 4165 #define FMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+ − 4166
+ − 4167 #define FMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+ − 4168 #define FMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+ − 4169 #define FMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+ − 4170 #define FMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+ − 4171 #define FMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+ − 4172 #define FMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+ − 4173 #define FMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+ − 4174 #define FMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+ − 4175 #define FMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+ − 4176
+ − 4177 #define FMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+ − 4178 #define FMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+ − 4179 #define FMC_BWTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+ − 4180 #define FMC_BWTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+ − 4181 #define FMC_BWTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+ − 4182
+ − 4183 #define FMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+ − 4184 #define FMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+ − 4185 #define FMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+ − 4186 #define FMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+ − 4187 #define FMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+ − 4188
+ − 4189 #define FMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+ − 4190 #define FMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+ − 4191 #define FMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+ − 4192 #define FMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+ − 4193 #define FMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+ − 4194
+ − 4195 #define FMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+ − 4196 #define FMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+ − 4197 #define FMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+ − 4198
+ − 4199 /****************** Bit definition for FMC_PCR2 register *******************/
+ − 4200 #define FMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
+ − 4201 #define FMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
+ − 4202 #define FMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */
+ − 4203
+ − 4204 #define FMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
+ − 4205 #define FMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+ − 4206 #define FMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+ − 4207
+ − 4208 #define FMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
+ − 4209
+ − 4210 #define FMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
+ − 4211 #define FMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+ − 4212 #define FMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+ − 4213 #define FMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+ − 4214 #define FMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
+ − 4215
+ − 4216 #define FMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
+ − 4217 #define FMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+ − 4218 #define FMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+ − 4219 #define FMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+ − 4220 #define FMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+ − 4221
+ − 4222 #define FMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */
+ − 4223 #define FMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+ − 4224 #define FMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+ − 4225 #define FMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+ − 4226
+ − 4227 /****************** Bit definition for FMC_PCR3 register *******************/
+ − 4228 #define FMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
+ − 4229 #define FMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
+ − 4230 #define FMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */
+ − 4231
+ − 4232 #define FMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
+ − 4233 #define FMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+ − 4234 #define FMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+ − 4235
+ − 4236 #define FMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
+ − 4237
+ − 4238 #define FMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
+ − 4239 #define FMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+ − 4240 #define FMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+ − 4241 #define FMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+ − 4242 #define FMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
+ − 4243
+ − 4244 #define FMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
+ − 4245 #define FMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+ − 4246 #define FMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+ − 4247 #define FMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+ − 4248 #define FMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+ − 4249
+ − 4250 #define FMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
+ − 4251 #define FMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+ − 4252 #define FMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+ − 4253 #define FMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+ − 4254
+ − 4255 /****************** Bit definition for FMC_PCR4 register *******************/
+ − 4256 #define FMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
+ − 4257 #define FMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
+ − 4258 #define FMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */
+ − 4259
+ − 4260 #define FMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
+ − 4261 #define FMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+ − 4262 #define FMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+ − 4263
+ − 4264 #define FMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
+ − 4265
+ − 4266 #define FMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
+ − 4267 #define FMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+ − 4268 #define FMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+ − 4269 #define FMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+ − 4270 #define FMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
+ − 4271
+ − 4272 #define FMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
+ − 4273 #define FMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+ − 4274 #define FMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+ − 4275 #define FMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+ − 4276 #define FMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+ − 4277
+ − 4278 #define FMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
+ − 4279 #define FMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+ − 4280 #define FMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+ − 4281 #define FMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+ − 4282
+ − 4283 /******************* Bit definition for FMC_SR2 register *******************/
+ − 4284 #define FMC_SR2_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
+ − 4285 #define FMC_SR2_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
+ − 4286 #define FMC_SR2_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
+ − 4287 #define FMC_SR2_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
+ − 4288 #define FMC_SR2_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
+ − 4289 #define FMC_SR2_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
+ − 4290 #define FMC_SR2_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
+ − 4291
+ − 4292 /******************* Bit definition for FMC_SR3 register *******************/
+ − 4293 #define FMC_SR3_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
+ − 4294 #define FMC_SR3_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
+ − 4295 #define FMC_SR3_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
+ − 4296 #define FMC_SR3_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
+ − 4297 #define FMC_SR3_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
+ − 4298 #define FMC_SR3_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
+ − 4299 #define FMC_SR3_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
+ − 4300
+ − 4301 /******************* Bit definition for FMC_SR4 register *******************/
+ − 4302 #define FMC_SR4_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
+ − 4303 #define FMC_SR4_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
+ − 4304 #define FMC_SR4_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
+ − 4305 #define FMC_SR4_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
+ − 4306 #define FMC_SR4_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
+ − 4307 #define FMC_SR4_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
+ − 4308 #define FMC_SR4_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
+ − 4309
+ − 4310 /****************** Bit definition for FMC_PMEM2 register ******************/
+ − 4311 #define FMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+ − 4312 #define FMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+ − 4313 #define FMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+ − 4314 #define FMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+ − 4315 #define FMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+ − 4316 #define FMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+ − 4317 #define FMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+ − 4318 #define FMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+ − 4319 #define FMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+ − 4320
+ − 4321 #define FMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+ − 4322 #define FMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+ − 4323 #define FMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+ − 4324 #define FMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+ − 4325 #define FMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+ − 4326 #define FMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+ − 4327 #define FMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+ − 4328 #define FMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+ − 4329 #define FMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+ − 4330
+ − 4331 #define FMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+ − 4332 #define FMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+ − 4333 #define FMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+ − 4334 #define FMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+ − 4335 #define FMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+ − 4336 #define FMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+ − 4337 #define FMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+ − 4338 #define FMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+ − 4339 #define FMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+ − 4340
+ − 4341 #define FMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+ − 4342 #define FMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+ − 4343 #define FMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+ − 4344 #define FMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+ − 4345 #define FMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+ − 4346 #define FMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+ − 4347 #define FMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+ − 4348 #define FMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+ − 4349 #define FMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+ − 4350
+ − 4351 /****************** Bit definition for FMC_PMEM3 register ******************/
+ − 4352 #define FMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
+ − 4353 #define FMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+ − 4354 #define FMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+ − 4355 #define FMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+ − 4356 #define FMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+ − 4357 #define FMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+ − 4358 #define FMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+ − 4359 #define FMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+ − 4360 #define FMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+ − 4361
+ − 4362 #define FMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+ − 4363 #define FMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+ − 4364 #define FMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+ − 4365 #define FMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+ − 4366 #define FMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+ − 4367 #define FMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+ − 4368 #define FMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+ − 4369 #define FMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+ − 4370 #define FMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+ − 4371
+ − 4372 #define FMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+ − 4373 #define FMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+ − 4374 #define FMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+ − 4375 #define FMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+ − 4376 #define FMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+ − 4377 #define FMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+ − 4378 #define FMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+ − 4379 #define FMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+ − 4380 #define FMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+ − 4381
+ − 4382 #define FMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+ − 4383 #define FMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+ − 4384 #define FMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+ − 4385 #define FMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+ − 4386 #define FMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+ − 4387 #define FMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+ − 4388 #define FMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+ − 4389 #define FMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+ − 4390 #define FMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+ − 4391
+ − 4392 /****************** Bit definition for FMC_PMEM4 register ******************/
+ − 4393 #define FMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
+ − 4394 #define FMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+ − 4395 #define FMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+ − 4396 #define FMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+ − 4397 #define FMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+ − 4398 #define FMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+ − 4399 #define FMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+ − 4400 #define FMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+ − 4401 #define FMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+ − 4402
+ − 4403 #define FMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
+ − 4404 #define FMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+ − 4405 #define FMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+ − 4406 #define FMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+ − 4407 #define FMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+ − 4408 #define FMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+ − 4409 #define FMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+ − 4410 #define FMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+ − 4411 #define FMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+ − 4412
+ − 4413 #define FMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
+ − 4414 #define FMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+ − 4415 #define FMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+ − 4416 #define FMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+ − 4417 #define FMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+ − 4418 #define FMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+ − 4419 #define FMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+ − 4420 #define FMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+ − 4421 #define FMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+ − 4422
+ − 4423 #define FMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
+ − 4424 #define FMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+ − 4425 #define FMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+ − 4426 #define FMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+ − 4427 #define FMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+ − 4428 #define FMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+ − 4429 #define FMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+ − 4430 #define FMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+ − 4431 #define FMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+ − 4432
+ − 4433 /****************** Bit definition for FMC_PATT2 register ******************/
+ − 4434 #define FMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+ − 4435 #define FMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+ − 4436 #define FMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+ − 4437 #define FMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+ − 4438 #define FMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+ − 4439 #define FMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+ − 4440 #define FMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+ − 4441 #define FMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+ − 4442 #define FMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+ − 4443
+ − 4444 #define FMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+ − 4445 #define FMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+ − 4446 #define FMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+ − 4447 #define FMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+ − 4448 #define FMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+ − 4449 #define FMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+ − 4450 #define FMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+ − 4451 #define FMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+ − 4452 #define FMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+ − 4453
+ − 4454 #define FMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+ − 4455 #define FMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+ − 4456 #define FMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+ − 4457 #define FMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+ − 4458 #define FMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+ − 4459 #define FMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+ − 4460 #define FMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+ − 4461 #define FMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+ − 4462 #define FMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+ − 4463
+ − 4464 #define FMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+ − 4465 #define FMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+ − 4466 #define FMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+ − 4467 #define FMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+ − 4468 #define FMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+ − 4469 #define FMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+ − 4470 #define FMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+ − 4471 #define FMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+ − 4472 #define FMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+ − 4473
+ − 4474 /****************** Bit definition for FMC_PATT3 register ******************/
+ − 4475 #define FMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+ − 4476 #define FMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+ − 4477 #define FMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+ − 4478 #define FMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+ − 4479 #define FMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+ − 4480 #define FMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+ − 4481 #define FMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+ − 4482 #define FMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+ − 4483 #define FMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+ − 4484
+ − 4485 #define FMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+ − 4486 #define FMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+ − 4487 #define FMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+ − 4488 #define FMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+ − 4489 #define FMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+ − 4490 #define FMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+ − 4491 #define FMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+ − 4492 #define FMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+ − 4493 #define FMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+ − 4494
+ − 4495 #define FMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+ − 4496 #define FMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+ − 4497 #define FMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+ − 4498 #define FMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+ − 4499 #define FMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+ − 4500 #define FMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+ − 4501 #define FMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+ − 4502 #define FMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+ − 4503 #define FMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+ − 4504
+ − 4505 #define FMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+ − 4506 #define FMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+ − 4507 #define FMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+ − 4508 #define FMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+ − 4509 #define FMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+ − 4510 #define FMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+ − 4511 #define FMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+ − 4512 #define FMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+ − 4513 #define FMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+ − 4514
+ − 4515 /****************** Bit definition for FMC_PATT4 register ******************/
+ − 4516 #define FMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
+ − 4517 #define FMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+ − 4518 #define FMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+ − 4519 #define FMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+ − 4520 #define FMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+ − 4521 #define FMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+ − 4522 #define FMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+ − 4523 #define FMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+ − 4524 #define FMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+ − 4525
+ − 4526 #define FMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
+ − 4527 #define FMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+ − 4528 #define FMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+ − 4529 #define FMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+ − 4530 #define FMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+ − 4531 #define FMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+ − 4532 #define FMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+ − 4533 #define FMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+ − 4534 #define FMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+ − 4535
+ − 4536 #define FMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
+ − 4537 #define FMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+ − 4538 #define FMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+ − 4539 #define FMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+ − 4540 #define FMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+ − 4541 #define FMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+ − 4542 #define FMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+ − 4543 #define FMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+ − 4544 #define FMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+ − 4545
+ − 4546 #define FMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
+ − 4547 #define FMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+ − 4548 #define FMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+ − 4549 #define FMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+ − 4550 #define FMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+ − 4551 #define FMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+ − 4552 #define FMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+ − 4553 #define FMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+ − 4554 #define FMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+ − 4555
+ − 4556 /****************** Bit definition for FMC_PIO4 register *******************/
+ − 4557 #define FMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */
+ − 4558 #define FMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+ − 4559 #define FMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+ − 4560 #define FMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+ − 4561 #define FMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+ − 4562 #define FMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+ − 4563 #define FMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+ − 4564 #define FMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+ − 4565 #define FMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+ − 4566
+ − 4567 #define FMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
+ − 4568 #define FMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+ − 4569 #define FMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+ − 4570 #define FMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+ − 4571 #define FMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+ − 4572 #define FMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+ − 4573 #define FMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+ − 4574 #define FMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+ − 4575 #define FMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+ − 4576
+ − 4577 #define FMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
+ − 4578 #define FMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+ − 4579 #define FMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+ − 4580 #define FMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+ − 4581 #define FMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+ − 4582 #define FMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+ − 4583 #define FMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+ − 4584 #define FMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+ − 4585 #define FMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+ − 4586
+ − 4587 #define FMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
+ − 4588 #define FMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+ − 4589 #define FMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+ − 4590 #define FMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+ − 4591 #define FMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+ − 4592 #define FMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+ − 4593 #define FMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+ − 4594 #define FMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+ − 4595 #define FMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+ − 4596
+ − 4597 /****************** Bit definition for FMC_ECCR2 register ******************/
+ − 4598 #define FMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
+ − 4599
+ − 4600 /****************** Bit definition for FMC_ECCR3 register ******************/
+ − 4601 #define FMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
+ − 4602
+ − 4603 /****************** Bit definition for FMC_SDCR1 register ******************/
+ − 4604 #define FMC_SDCR1_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */
+ − 4605 #define FMC_SDCR1_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+ − 4606 #define FMC_SDCR1_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+ − 4607
+ − 4608 #define FMC_SDCR1_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */
+ − 4609 #define FMC_SDCR1_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+ − 4610 #define FMC_SDCR1_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+ − 4611
+ − 4612 #define FMC_SDCR1_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */
+ − 4613 #define FMC_SDCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+ − 4614 #define FMC_SDCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+ − 4615
+ − 4616 #define FMC_SDCR1_NB ((uint32_t)0x00000040) /*!<Number of internal bank */
+ − 4617
+ − 4618 #define FMC_SDCR1_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */
+ − 4619 #define FMC_SDCR1_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */
+ − 4620 #define FMC_SDCR1_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */
+ − 4621
+ − 4622 #define FMC_SDCR1_WP ((uint32_t)0x00000200) /*!<Write protection */
+ − 4623
+ − 4624 #define FMC_SDCR1_SDCLK ((uint32_t)0x00000C00) /*!<SDRAM clock configuration */
+ − 4625 #define FMC_SDCR1_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+ − 4626 #define FMC_SDCR1_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+ − 4627
+ − 4628 #define FMC_SDCR1_RBURST ((uint32_t)0x00001000) /*!<Read burst */
+ − 4629
+ − 4630 #define FMC_SDCR1_RPIPE ((uint32_t)0x00006000) /*!<Write protection */
+ − 4631 #define FMC_SDCR1_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+ − 4632 #define FMC_SDCR1_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+ − 4633
+ − 4634 /****************** Bit definition for FMC_SDCR2 register ******************/
+ − 4635 #define FMC_SDCR2_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */
+ − 4636 #define FMC_SDCR2_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+ − 4637 #define FMC_SDCR2_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+ − 4638
+ − 4639 #define FMC_SDCR2_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */
+ − 4640 #define FMC_SDCR2_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+ − 4641 #define FMC_SDCR2_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+ − 4642
+ − 4643 #define FMC_SDCR2_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */
+ − 4644 #define FMC_SDCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+ − 4645 #define FMC_SDCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+ − 4646
+ − 4647 #define FMC_SDCR2_NB ((uint32_t)0x00000040) /*!<Number of internal bank */
+ − 4648
+ − 4649 #define FMC_SDCR2_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */
+ − 4650 #define FMC_SDCR2_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */
+ − 4651 #define FMC_SDCR2_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */
+ − 4652
+ − 4653 #define FMC_SDCR2_WP ((uint32_t)0x00000200) /*!<Write protection */
+ − 4654
+ − 4655 #define FMC_SDCR2_SDCLK ((uint32_t)0x00000C00) /*!<SDCLK[1:0] (SDRAM clock configuration) */
+ − 4656 #define FMC_SDCR2_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+ − 4657 #define FMC_SDCR2_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+ − 4658
+ − 4659 #define FMC_SDCR2_RBURST ((uint32_t)0x00001000) /*!<Read burst */
+ − 4660
+ − 4661 #define FMC_SDCR2_RPIPE ((uint32_t)0x00006000) /*!<RPIPE[1:0](Read pipe) */
+ − 4662 #define FMC_SDCR2_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+ − 4663 #define FMC_SDCR2_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+ − 4664
+ − 4665 /****************** Bit definition for FMC_SDTR1 register ******************/
+ − 4666 #define FMC_SDTR1_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */
+ − 4667 #define FMC_SDTR1_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+ − 4668 #define FMC_SDTR1_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+ − 4669 #define FMC_SDTR1_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+ − 4670 #define FMC_SDTR1_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+ − 4671
+ − 4672 #define FMC_SDTR1_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */
+ − 4673 #define FMC_SDTR1_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+ − 4674 #define FMC_SDTR1_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+ − 4675 #define FMC_SDTR1_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+ − 4676 #define FMC_SDTR1_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+ − 4677
+ − 4678 #define FMC_SDTR1_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */
+ − 4679 #define FMC_SDTR1_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+ − 4680 #define FMC_SDTR1_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+ − 4681 #define FMC_SDTR1_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+ − 4682 #define FMC_SDTR1_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+ − 4683
+ − 4684 #define FMC_SDTR1_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */
+ − 4685 #define FMC_SDTR1_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+ − 4686 #define FMC_SDTR1_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+ − 4687 #define FMC_SDTR1_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+ − 4688
+ − 4689 #define FMC_SDTR1_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */
+ − 4690 #define FMC_SDTR1_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+ − 4691 #define FMC_SDTR1_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+ − 4692 #define FMC_SDTR1_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+ − 4693
+ − 4694 #define FMC_SDTR1_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */
+ − 4695 #define FMC_SDTR1_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+ − 4696 #define FMC_SDTR1_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+ − 4697 #define FMC_SDTR1_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+ − 4698
+ − 4699 #define FMC_SDTR1_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */
+ − 4700 #define FMC_SDTR1_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+ − 4701 #define FMC_SDTR1_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+ − 4702 #define FMC_SDTR1_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+ − 4703
+ − 4704 /****************** Bit definition for FMC_SDTR2 register ******************/
+ − 4705 #define FMC_SDTR2_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */
+ − 4706 #define FMC_SDTR2_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+ − 4707 #define FMC_SDTR2_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+ − 4708 #define FMC_SDTR2_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+ − 4709 #define FMC_SDTR2_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+ − 4710
+ − 4711 #define FMC_SDTR2_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */
+ − 4712 #define FMC_SDTR2_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+ − 4713 #define FMC_SDTR2_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+ − 4714 #define FMC_SDTR2_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+ − 4715 #define FMC_SDTR2_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+ − 4716
+ − 4717 #define FMC_SDTR2_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */
+ − 4718 #define FMC_SDTR2_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+ − 4719 #define FMC_SDTR2_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+ − 4720 #define FMC_SDTR2_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+ − 4721 #define FMC_SDTR2_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+ − 4722
+ − 4723 #define FMC_SDTR2_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */
+ − 4724 #define FMC_SDTR2_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+ − 4725 #define FMC_SDTR2_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+ − 4726 #define FMC_SDTR2_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+ − 4727
+ − 4728 #define FMC_SDTR2_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */
+ − 4729 #define FMC_SDTR2_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+ − 4730 #define FMC_SDTR2_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+ − 4731 #define FMC_SDTR2_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+ − 4732
+ − 4733 #define FMC_SDTR2_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */
+ − 4734 #define FMC_SDTR2_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+ − 4735 #define FMC_SDTR2_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+ − 4736 #define FMC_SDTR2_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+ − 4737
+ − 4738 #define FMC_SDTR2_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */
+ − 4739 #define FMC_SDTR2_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+ − 4740 #define FMC_SDTR2_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+ − 4741 #define FMC_SDTR2_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+ − 4742
+ − 4743 /****************** Bit definition for FMC_SDCMR register ******************/
+ − 4744 #define FMC_SDCMR_MODE ((uint32_t)0x00000007) /*!<MODE[2:0] bits (Command mode) */
+ − 4745 #define FMC_SDCMR_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+ − 4746 #define FMC_SDCMR_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+ − 4747 #define FMC_SDCMR_MODE_2 ((uint32_t)0x00000003) /*!<Bit 2 */
+ − 4748
+ − 4749 #define FMC_SDCMR_CTB2 ((uint32_t)0x00000008) /*!<Command target 2 */
+ − 4750
+ − 4751 #define FMC_SDCMR_CTB1 ((uint32_t)0x00000010) /*!<Command target 1 */
+ − 4752
+ − 4753 #define FMC_SDCMR_NRFS ((uint32_t)0x000001E0) /*!<NRFS[3:0] bits (Number of auto-refresh) */
+ − 4754 #define FMC_SDCMR_NRFS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+ − 4755 #define FMC_SDCMR_NRFS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+ − 4756 #define FMC_SDCMR_NRFS_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+ − 4757 #define FMC_SDCMR_NRFS_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+ − 4758
+ − 4759 #define FMC_SDCMR_MRD ((uint32_t)0x003FFE00) /*!<MRD[12:0] bits (Mode register definition) */
+ − 4760
+ − 4761 /****************** Bit definition for FMC_SDRTR register ******************/
+ − 4762 #define FMC_SDRTR_CRE ((uint32_t)0x00000001) /*!<Clear refresh error flag */
+ − 4763
+ − 4764 #define FMC_SDRTR_COUNT ((uint32_t)0x00003FFE) /*!<COUNT[12:0] bits (Refresh timer count) */
+ − 4765
+ − 4766 #define FMC_SDRTR_REIE ((uint32_t)0x00004000) /*!<RES interupt enable */
+ − 4767
+ − 4768 /****************** Bit definition for FMC_SDSR register ******************/
+ − 4769 #define FMC_SDSR_RE ((uint32_t)0x00000001) /*!<Refresh error flag */
+ − 4770
+ − 4771 #define FMC_SDSR_MODES1 ((uint32_t)0x00000006) /*!<MODES1[1:0]bits (Status mode for bank 1) */
+ − 4772 #define FMC_SDSR_MODES1_0 ((uint32_t)0x00000002) /*!<Bit 0 */
+ − 4773 #define FMC_SDSR_MODES1_1 ((uint32_t)0x00000004) /*!<Bit 1 */
+ − 4774
+ − 4775 #define FMC_SDSR_MODES2 ((uint32_t)0x00000018) /*!<MODES2[1:0]bits (Status mode for bank 2) */
+ − 4776 #define FMC_SDSR_MODES2_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+ − 4777 #define FMC_SDSR_MODES2_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+ − 4778 #define FMC_SDSR_BUSY ((uint32_t)0x00000020) /*!<Busy status */
+ − 4779
+ − 4780
+ − 4781
+ − 4782 /******************************************************************************/
+ − 4783 /* */
+ − 4784 /* General Purpose I/O */
+ − 4785 /* */
+ − 4786 /******************************************************************************/
+ − 4787 /****************** Bits definition for GPIO_MODER register *****************/
+ − 4788 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
+ − 4789 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
+ − 4790 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
+ − 4791
+ − 4792 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
+ − 4793 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
+ − 4794 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
+ − 4795
+ − 4796 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
+ − 4797 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
+ − 4798 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
+ − 4799
+ − 4800 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
+ − 4801 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
+ − 4802 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
+ − 4803
+ − 4804 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
+ − 4805 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
+ − 4806 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
+ − 4807
+ − 4808 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
+ − 4809 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
+ − 4810 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
+ − 4811
+ − 4812 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
+ − 4813 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
+ − 4814 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
+ − 4815
+ − 4816 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
+ − 4817 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
+ − 4818 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
+ − 4819
+ − 4820 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
+ − 4821 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
+ − 4822 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
+ − 4823
+ − 4824 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
+ − 4825 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
+ − 4826 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
+ − 4827
+ − 4828 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
+ − 4829 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
+ − 4830 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
+ − 4831
+ − 4832 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
+ − 4833 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
+ − 4834 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
+ − 4835
+ − 4836 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
+ − 4837 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
+ − 4838 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
+ − 4839
+ − 4840 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
+ − 4841 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
+ − 4842 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
+ − 4843
+ − 4844 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
+ − 4845 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
+ − 4846 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
+ − 4847
+ − 4848 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
+ − 4849 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
+ − 4850 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
+ − 4851
+ − 4852 /****************** Bits definition for GPIO_OTYPER register ****************/
+ − 4853 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
+ − 4854 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
+ − 4855 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
+ − 4856 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
+ − 4857 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
+ − 4858 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
+ − 4859 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
+ − 4860 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
+ − 4861 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
+ − 4862 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
+ − 4863 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
+ − 4864 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
+ − 4865 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
+ − 4866 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
+ − 4867 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
+ − 4868 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
+ − 4869
+ − 4870 /****************** Bits definition for GPIO_OSPEEDR register ***************/
+ − 4871 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
+ − 4872 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
+ − 4873 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
+ − 4874
+ − 4875 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
+ − 4876 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
+ − 4877 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
+ − 4878
+ − 4879 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
+ − 4880 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
+ − 4881 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
+ − 4882
+ − 4883 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
+ − 4884 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
+ − 4885 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
+ − 4886
+ − 4887 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
+ − 4888 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
+ − 4889 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
+ − 4890
+ − 4891 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
+ − 4892 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
+ − 4893 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
+ − 4894
+ − 4895 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
+ − 4896 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
+ − 4897 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
+ − 4898
+ − 4899 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
+ − 4900 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
+ − 4901 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
+ − 4902
+ − 4903 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
+ − 4904 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
+ − 4905 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
+ − 4906
+ − 4907 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
+ − 4908 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
+ − 4909 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
+ − 4910
+ − 4911 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
+ − 4912 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
+ − 4913 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
+ − 4914
+ − 4915 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
+ − 4916 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
+ − 4917 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
+ − 4918
+ − 4919 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
+ − 4920 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
+ − 4921 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
+ − 4922
+ − 4923 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
+ − 4924 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
+ − 4925 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
+ − 4926
+ − 4927 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
+ − 4928 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
+ − 4929 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
+ − 4930
+ − 4931 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
+ − 4932 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
+ − 4933 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
+ − 4934
+ − 4935 /****************** Bits definition for GPIO_PUPDR register *****************/
+ − 4936 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
+ − 4937 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
+ − 4938 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
+ − 4939
+ − 4940 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
+ − 4941 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
+ − 4942 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
+ − 4943
+ − 4944 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
+ − 4945 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
+ − 4946 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
+ − 4947
+ − 4948 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
+ − 4949 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
+ − 4950 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
+ − 4951
+ − 4952 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
+ − 4953 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
+ − 4954 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
+ − 4955
+ − 4956 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
+ − 4957 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
+ − 4958 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
+ − 4959
+ − 4960 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
+ − 4961 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
+ − 4962 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
+ − 4963
+ − 4964 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
+ − 4965 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
+ − 4966 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
+ − 4967
+ − 4968 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
+ − 4969 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
+ − 4970 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
+ − 4971
+ − 4972 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
+ − 4973 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
+ − 4974 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
+ − 4975
+ − 4976 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
+ − 4977 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
+ − 4978 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
+ − 4979
+ − 4980 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
+ − 4981 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
+ − 4982 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
+ − 4983
+ − 4984 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
+ − 4985 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
+ − 4986 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
+ − 4987
+ − 4988 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
+ − 4989 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
+ − 4990 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
+ − 4991
+ − 4992 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
+ − 4993 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
+ − 4994 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
+ − 4995
+ − 4996 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
+ − 4997 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
+ − 4998 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
+ − 4999
+ − 5000 /****************** Bits definition for GPIO_IDR register *******************/
+ − 5001 #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
+ − 5002 #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
+ − 5003 #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
+ − 5004 #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
+ − 5005 #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
+ − 5006 #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
+ − 5007 #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
+ − 5008 #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
+ − 5009 #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
+ − 5010 #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
+ − 5011 #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
+ − 5012 #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
+ − 5013 #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
+ − 5014 #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
+ − 5015 #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
+ − 5016 #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
+ − 5017 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
+ − 5018 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
+ − 5019 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
+ − 5020 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
+ − 5021 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
+ − 5022 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
+ − 5023 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
+ − 5024 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
+ − 5025 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
+ − 5026 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
+ − 5027 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
+ − 5028 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
+ − 5029 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
+ − 5030 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
+ − 5031 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
+ − 5032 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
+ − 5033 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
+ − 5034
+ − 5035 /****************** Bits definition for GPIO_ODR register *******************/
+ − 5036 #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
+ − 5037 #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
+ − 5038 #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
+ − 5039 #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
+ − 5040 #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
+ − 5041 #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
+ − 5042 #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
+ − 5043 #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
+ − 5044 #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
+ − 5045 #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
+ − 5046 #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
+ − 5047 #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
+ − 5048 #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
+ − 5049 #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
+ − 5050 #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
+ − 5051 #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
+ − 5052 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
+ − 5053 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
+ − 5054 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
+ − 5055 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
+ − 5056 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
+ − 5057 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
+ − 5058 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
+ − 5059 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
+ − 5060 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
+ − 5061 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
+ − 5062 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
+ − 5063 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
+ − 5064 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
+ − 5065 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
+ − 5066 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
+ − 5067 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
+ − 5068 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
+ − 5069
+ − 5070 /****************** Bits definition for GPIO_BSRR register ******************/
+ − 5071 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
+ − 5072 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
+ − 5073 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
+ − 5074 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
+ − 5075 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
+ − 5076 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
+ − 5077 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
+ − 5078 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
+ − 5079 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
+ − 5080 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
+ − 5081 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
+ − 5082 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
+ − 5083 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
+ − 5084 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
+ − 5085 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
+ − 5086 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
+ − 5087 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
+ − 5088 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
+ − 5089 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
+ − 5090 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
+ − 5091 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
+ − 5092 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
+ − 5093 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
+ − 5094 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
+ − 5095 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
+ − 5096 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
+ − 5097 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
+ − 5098 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
+ − 5099 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
+ − 5100 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
+ − 5101 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
+ − 5102 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
+ − 5103
+ − 5104 /****************** Bit definition for GPIO_LCKR register *********************/
+ − 5105 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
+ − 5106 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
+ − 5107 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
+ − 5108 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
+ − 5109 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
+ − 5110 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
+ − 5111 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
+ − 5112 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
+ − 5113 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
+ − 5114 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
+ − 5115 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
+ − 5116 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
+ − 5117 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
+ − 5118 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
+ − 5119 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
+ − 5120 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
+ − 5121 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
+ − 5122
+ − 5123 /******************************************************************************/
+ − 5124 /* */
+ − 5125 /* Inter-integrated Circuit Interface */
+ − 5126 /* */
+ − 5127 /******************************************************************************/
+ − 5128 /******************* Bit definition for I2C_CR1 register ********************/
+ − 5129 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!<Peripheral Enable */
+ − 5130 #define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!<SMBus Mode */
+ − 5131 #define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!<SMBus Type */
+ − 5132 #define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!<ARP Enable */
+ − 5133 #define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!<PEC Enable */
+ − 5134 #define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!<General Call Enable */
+ − 5135 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!<Clock Stretching Disable (Slave mode) */
+ − 5136 #define I2C_CR1_START ((uint32_t)0x00000100) /*!<Start Generation */
+ − 5137 #define I2C_CR1_STOP ((uint32_t)0x00000200) /*!<Stop Generation */
+ − 5138 #define I2C_CR1_ACK ((uint32_t)0x00000400) /*!<Acknowledge Enable */
+ − 5139 #define I2C_CR1_POS ((uint32_t)0x00000800) /*!<Acknowledge/PEC Position (for data reception) */
+ − 5140 #define I2C_CR1_PEC ((uint32_t)0x00001000) /*!<Packet Error Checking */
+ − 5141 #define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!<SMBus Alert */
+ − 5142 #define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!<Software Reset */
+ − 5143
+ − 5144 /******************* Bit definition for I2C_CR2 register ********************/
+ − 5145 #define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+ − 5146 #define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+ − 5147 #define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+ − 5148 #define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+ − 5149 #define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+ − 5150 #define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+ − 5151 #define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+ − 5152
+ − 5153 #define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!<Error Interrupt Enable */
+ − 5154 #define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!<Event Interrupt Enable */
+ − 5155 #define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!<Buffer Interrupt Enable */
+ − 5156 #define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!<DMA Requests Enable */
+ − 5157 #define I2C_CR2_LAST ((uint32_t)0x00001000) /*!<DMA Last Transfer */
+ − 5158
+ − 5159 /******************* Bit definition for I2C_OAR1 register *******************/
+ − 5160 #define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!<Interface Address */
+ − 5161 #define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!<Interface Address */
+ − 5162
+ − 5163 #define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!<Bit 0 */
+ − 5164 #define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!<Bit 1 */
+ − 5165 #define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!<Bit 2 */
+ − 5166 #define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!<Bit 3 */
+ − 5167 #define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!<Bit 4 */
+ − 5168 #define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!<Bit 5 */
+ − 5169 #define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!<Bit 6 */
+ − 5170 #define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!<Bit 7 */
+ − 5171 #define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!<Bit 8 */
+ − 5172 #define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!<Bit 9 */
+ − 5173
+ − 5174 #define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!<Addressing Mode (Slave mode) */
+ − 5175
+ − 5176 /******************* Bit definition for I2C_OAR2 register *******************/
+ − 5177 #define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!<Dual addressing mode enable */
+ − 5178 #define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!<Interface address */
+ − 5179
+ − 5180 /******************** Bit definition for I2C_DR register ********************/
+ − 5181 #define I2C_DR_DR ((uint32_t)0x000000FF) /*!<8-bit Data Register */
+ − 5182
+ − 5183 /******************* Bit definition for I2C_SR1 register ********************/
+ − 5184 #define I2C_SR1_SB ((uint32_t)0x00000001) /*!<Start Bit (Master mode) */
+ − 5185 #define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!<Address sent (master mode)/matched (slave mode) */
+ − 5186 #define I2C_SR1_BTF ((uint32_t)0x00000004) /*!<Byte Transfer Finished */
+ − 5187 #define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!<10-bit header sent (Master mode) */
+ − 5188 #define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!<Stop detection (Slave mode) */
+ − 5189 #define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!<Data Register not Empty (receivers) */
+ − 5190 #define I2C_SR1_TXE ((uint32_t)0x00000080) /*!<Data Register Empty (transmitters) */
+ − 5191 #define I2C_SR1_BERR ((uint32_t)0x00000100) /*!<Bus Error */
+ − 5192 #define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!<Arbitration Lost (master mode) */
+ − 5193 #define I2C_SR1_AF ((uint32_t)0x00000400) /*!<Acknowledge Failure */
+ − 5194 #define I2C_SR1_OVR ((uint32_t)0x00000800) /*!<Overrun/Underrun */
+ − 5195 #define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!<PEC Error in reception */
+ − 5196 #define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!<Timeout or Tlow Error */
+ − 5197 #define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!<SMBus Alert */
+ − 5198
+ − 5199 /******************* Bit definition for I2C_SR2 register ********************/
+ − 5200 #define I2C_SR2_MSL ((uint32_t)0x00000001) /*!<Master/Slave */
+ − 5201 #define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!<Bus Busy */
+ − 5202 #define I2C_SR2_TRA ((uint32_t)0x00000004) /*!<Transmitter/Receiver */
+ − 5203 #define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!<General Call Address (Slave mode) */
+ − 5204 #define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!<SMBus Device Default Address (Slave mode) */
+ − 5205 #define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!<SMBus Host Header (Slave mode) */
+ − 5206 #define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!<Dual Flag (Slave mode) */
+ − 5207 #define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!<Packet Error Checking Register */
+ − 5208
+ − 5209 /******************* Bit definition for I2C_CCR register ********************/
+ − 5210 #define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+ − 5211 #define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!<Fast Mode Duty Cycle */
+ − 5212 #define I2C_CCR_FS ((uint32_t)0x00008000) /*!<I2C Master Mode Selection */
+ − 5213
+ − 5214 /****************** Bit definition for I2C_TRISE register *******************/
+ − 5215 #define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+ − 5216
+ − 5217 /****************** Bit definition for I2C_FLTR register *******************/
+ − 5218 #define I2C_FLTR_DNF ((uint32_t)0x0000000F) /*!<Digital Noise Filter */
+ − 5219 #define I2C_FLTR_ANOFF ((uint32_t)0x00000010) /*!<Analog Noise Filter OFF */
+ − 5220
+ − 5221 /******************************************************************************/
+ − 5222 /* */
+ − 5223 /* Independent WATCHDOG */
+ − 5224 /* */
+ − 5225 /******************************************************************************/
+ − 5226 /******************* Bit definition for IWDG_KR register ********************/
+ − 5227 #define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */
+ − 5228
+ − 5229 /******************* Bit definition for IWDG_PR register ********************/
+ − 5230 #define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */
+ − 5231 #define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */
+ − 5232 #define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */
+ − 5233 #define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */
+ − 5234
+ − 5235 /******************* Bit definition for IWDG_RLR register *******************/
+ − 5236 #define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */
+ − 5237
+ − 5238 /******************* Bit definition for IWDG_SR register ********************/
+ − 5239 #define IWDG_SR_PVU ((uint32_t)0x01) /*!<Watchdog prescaler value update */
+ − 5240 #define IWDG_SR_RVU ((uint32_t)0x02) /*!<Watchdog counter reload value update */
+ − 5241
+ − 5242
+ − 5243 /******************************************************************************/
+ − 5244 /* */
+ − 5245 /* LCD-TFT Display Controller (LTDC) */
+ − 5246 /* */
+ − 5247 /******************************************************************************/
+ − 5248
+ − 5249 /******************** Bit definition for LTDC_SSCR register *****************/
+ − 5250
+ − 5251 #define LTDC_SSCR_VSH ((uint32_t)0x000007FF) /*!< Vertical Synchronization Height */
+ − 5252 #define LTDC_SSCR_HSW ((uint32_t)0x0FFF0000) /*!< Horizontal Synchronization Width */
+ − 5253
+ − 5254 /******************** Bit definition for LTDC_BPCR register *****************/
+ − 5255
+ − 5256 #define LTDC_BPCR_AVBP ((uint32_t)0x000007FF) /*!< Accumulated Vertical Back Porch */
+ − 5257 #define LTDC_BPCR_AHBP ((uint32_t)0x0FFF0000) /*!< Accumulated Horizontal Back Porch */
+ − 5258
+ − 5259 /******************** Bit definition for LTDC_AWCR register *****************/
+ − 5260
+ − 5261 #define LTDC_AWCR_AAH ((uint32_t)0x000007FF) /*!< Accumulated Active heigh */
+ − 5262 #define LTDC_AWCR_AAW ((uint32_t)0x0FFF0000) /*!< Accumulated Active Width */
+ − 5263
+ − 5264 /******************** Bit definition for LTDC_TWCR register *****************/
+ − 5265
+ − 5266 #define LTDC_TWCR_TOTALH ((uint32_t)0x000007FF) /*!< Total Heigh */
+ − 5267 #define LTDC_TWCR_TOTALW ((uint32_t)0x0FFF0000) /*!< Total Width */
+ − 5268
+ − 5269 /******************** Bit definition for LTDC_GCR register ******************/
+ − 5270
+ − 5271 #define LTDC_GCR_LTDCEN ((uint32_t)0x00000001) /*!< LCD-TFT controller enable bit */
+ − 5272 #define LTDC_GCR_DBW ((uint32_t)0x00000070) /*!< Dither Blue Width */
+ − 5273 #define LTDC_GCR_DGW ((uint32_t)0x00000700) /*!< Dither Green Width */
+ − 5274 #define LTDC_GCR_DRW ((uint32_t)0x00007000) /*!< Dither Red Width */
+ − 5275 #define LTDC_GCR_DTEN ((uint32_t)0x00010000) /*!< Dither Enable */
+ − 5276 #define LTDC_GCR_PCPOL ((uint32_t)0x10000000) /*!< Pixel Clock Polarity */
+ − 5277 #define LTDC_GCR_DEPOL ((uint32_t)0x20000000) /*!< Data Enable Polarity */
+ − 5278 #define LTDC_GCR_VSPOL ((uint32_t)0x40000000) /*!< Vertical Synchronization Polarity */
+ − 5279 #define LTDC_GCR_HSPOL ((uint32_t)0x80000000) /*!< Horizontal Synchronization Polarity */
+ − 5280
+ − 5281 /******************** Bit definition for LTDC_SRCR register *****************/
+ − 5282
+ − 5283 #define LTDC_SRCR_IMR ((uint32_t)0x00000001) /*!< Immediate Reload */
+ − 5284 #define LTDC_SRCR_VBR ((uint32_t)0x00000002) /*!< Vertical Blanking Reload */
+ − 5285
+ − 5286 /******************** Bit definition for LTDC_BCCR register *****************/
+ − 5287
+ − 5288 #define LTDC_BCCR_BCBLUE ((uint32_t)0x000000FF) /*!< Background Blue value */
+ − 5289 #define LTDC_BCCR_BCGREEN ((uint32_t)0x0000FF00) /*!< Background Green value */
+ − 5290 #define LTDC_BCCR_BCRED ((uint32_t)0x00FF0000) /*!< Background Red value */
+ − 5291
+ − 5292 /******************** Bit definition for LTDC_IER register ******************/
+ − 5293
+ − 5294 #define LTDC_IER_LIE ((uint32_t)0x00000001) /*!< Line Interrupt Enable */
+ − 5295 #define LTDC_IER_FUIE ((uint32_t)0x00000002) /*!< FIFO Underrun Interrupt Enable */
+ − 5296 #define LTDC_IER_TERRIE ((uint32_t)0x00000004) /*!< Transfer Error Interrupt Enable */
+ − 5297 #define LTDC_IER_RRIE ((uint32_t)0x00000008) /*!< Register Reload interrupt enable */
+ − 5298
+ − 5299 /******************** Bit definition for LTDC_ISR register ******************/
+ − 5300
+ − 5301 #define LTDC_ISR_LIF ((uint32_t)0x00000001) /*!< Line Interrupt Flag */
+ − 5302 #define LTDC_ISR_FUIF ((uint32_t)0x00000002) /*!< FIFO Underrun Interrupt Flag */
+ − 5303 #define LTDC_ISR_TERRIF ((uint32_t)0x00000004) /*!< Transfer Error Interrupt Flag */
+ − 5304 #define LTDC_ISR_RRIF ((uint32_t)0x00000008) /*!< Register Reload interrupt Flag */
+ − 5305
+ − 5306 /******************** Bit definition for LTDC_ICR register ******************/
+ − 5307
+ − 5308 #define LTDC_ICR_CLIF ((uint32_t)0x00000001) /*!< Clears the Line Interrupt Flag */
+ − 5309 #define LTDC_ICR_CFUIF ((uint32_t)0x00000002) /*!< Clears the FIFO Underrun Interrupt Flag */
+ − 5310 #define LTDC_ICR_CTERRIF ((uint32_t)0x00000004) /*!< Clears the Transfer Error Interrupt Flag */
+ − 5311 #define LTDC_ICR_CRRIF ((uint32_t)0x00000008) /*!< Clears Register Reload interrupt Flag */
+ − 5312
+ − 5313 /******************** Bit definition for LTDC_LIPCR register ****************/
+ − 5314
+ − 5315 #define LTDC_LIPCR_LIPOS ((uint32_t)0x000007FF) /*!< Line Interrupt Position */
+ − 5316
+ − 5317 /******************** Bit definition for LTDC_CPSR register *****************/
+ − 5318
+ − 5319 #define LTDC_CPSR_CYPOS ((uint32_t)0x0000FFFF) /*!< Current Y Position */
+ − 5320 #define LTDC_CPSR_CXPOS ((uint32_t)0xFFFF0000) /*!< Current X Position */
+ − 5321
+ − 5322 /******************** Bit definition for LTDC_CDSR register *****************/
+ − 5323
+ − 5324 #define LTDC_CDSR_VDES ((uint32_t)0x00000001) /*!< Vertical Data Enable Status */
+ − 5325 #define LTDC_CDSR_HDES ((uint32_t)0x00000002) /*!< Horizontal Data Enable Status */
+ − 5326 #define LTDC_CDSR_VSYNCS ((uint32_t)0x00000004) /*!< Vertical Synchronization Status */
+ − 5327 #define LTDC_CDSR_HSYNCS ((uint32_t)0x00000008) /*!< Horizontal Synchronization Status */
+ − 5328
+ − 5329 /******************** Bit definition for LTDC_LxCR register *****************/
+ − 5330
+ − 5331 #define LTDC_LxCR_LEN ((uint32_t)0x00000001) /*!< Layer Enable */
+ − 5332 #define LTDC_LxCR_COLKEN ((uint32_t)0x00000002) /*!< Color Keying Enable */
+ − 5333 #define LTDC_LxCR_CLUTEN ((uint32_t)0x00000010) /*!< Color Lockup Table Enable */
+ − 5334
+ − 5335 /******************** Bit definition for LTDC_LxWHPCR register **************/
+ − 5336
+ − 5337 #define LTDC_LxWHPCR_WHSTPOS ((uint32_t)0x00000FFF) /*!< Window Horizontal Start Position */
+ − 5338 #define LTDC_LxWHPCR_WHSPPOS ((uint32_t)0xFFFF0000) /*!< Window Horizontal Stop Position */
+ − 5339
+ − 5340 /******************** Bit definition for LTDC_LxWVPCR register **************/
+ − 5341
+ − 5342 #define LTDC_LxWVPCR_WVSTPOS ((uint32_t)0x00000FFF) /*!< Window Vertical Start Position */
+ − 5343 #define LTDC_LxWVPCR_WVSPPOS ((uint32_t)0xFFFF0000) /*!< Window Vertical Stop Position */
+ − 5344
+ − 5345 /******************** Bit definition for LTDC_LxCKCR register ***************/
+ − 5346
+ − 5347 #define LTDC_LxCKCR_CKBLUE ((uint32_t)0x000000FF) /*!< Color Key Blue value */
+ − 5348 #define LTDC_LxCKCR_CKGREEN ((uint32_t)0x0000FF00) /*!< Color Key Green value */
+ − 5349 #define LTDC_LxCKCR_CKRED ((uint32_t)0x00FF0000) /*!< Color Key Red value */
+ − 5350
+ − 5351 /******************** Bit definition for LTDC_LxPFCR register ***************/
+ − 5352
+ − 5353 #define LTDC_LxPFCR_PF ((uint32_t)0x00000007) /*!< Pixel Format */
+ − 5354
+ − 5355 /******************** Bit definition for LTDC_LxCACR register ***************/
+ − 5356
+ − 5357 #define LTDC_LxCACR_CONSTA ((uint32_t)0x000000FF) /*!< Constant Alpha */
+ − 5358
+ − 5359 /******************** Bit definition for LTDC_LxDCCR register ***************/
+ − 5360
+ − 5361 #define LTDC_LxDCCR_DCBLUE ((uint32_t)0x000000FF) /*!< Default Color Blue */
+ − 5362 #define LTDC_LxDCCR_DCGREEN ((uint32_t)0x0000FF00) /*!< Default Color Green */
+ − 5363 #define LTDC_LxDCCR_DCRED ((uint32_t)0x00FF0000) /*!< Default Color Red */
+ − 5364 #define LTDC_LxDCCR_DCALPHA ((uint32_t)0xFF000000) /*!< Default Color Alpha */
+ − 5365
+ − 5366 /******************** Bit definition for LTDC_LxBFCR register ***************/
+ − 5367
+ − 5368 #define LTDC_LxBFCR_BF2 ((uint32_t)0x00000007) /*!< Blending Factor 2 */
+ − 5369 #define LTDC_LxBFCR_BF1 ((uint32_t)0x00000700) /*!< Blending Factor 1 */
+ − 5370
+ − 5371 /******************** Bit definition for LTDC_LxCFBAR register **************/
+ − 5372
+ − 5373 #define LTDC_LxCFBAR_CFBADD ((uint32_t)0xFFFFFFFF) /*!< Color Frame Buffer Start Address */
+ − 5374
+ − 5375 /******************** Bit definition for LTDC_LxCFBLR register **************/
+ − 5376
+ − 5377 #define LTDC_LxCFBLR_CFBLL ((uint32_t)0x00001FFF) /*!< Color Frame Buffer Line Length */
+ − 5378 #define LTDC_LxCFBLR_CFBP ((uint32_t)0x1FFF0000) /*!< Color Frame Buffer Pitch in bytes */
+ − 5379
+ − 5380 /******************** Bit definition for LTDC_LxCFBLNR register *************/
+ − 5381
+ − 5382 #define LTDC_LxCFBLNR_CFBLNBR ((uint32_t)0x000007FF) /*!< Frame Buffer Line Number */
+ − 5383
+ − 5384 /******************** Bit definition for LTDC_LxCLUTWR register *************/
+ − 5385
+ − 5386 #define LTDC_LxCLUTWR_BLUE ((uint32_t)0x000000FF) /*!< Blue value */
+ − 5387 #define LTDC_LxCLUTWR_GREEN ((uint32_t)0x0000FF00) /*!< Green value */
+ − 5388 #define LTDC_LxCLUTWR_RED ((uint32_t)0x00FF0000) /*!< Red value */
+ − 5389 #define LTDC_LxCLUTWR_CLUTADD ((uint32_t)0xFF000000) /*!< CLUT address */
+ − 5390
+ − 5391
+ − 5392 /******************************************************************************/
+ − 5393 /* */
+ − 5394 /* Power Control */
+ − 5395 /* */
+ − 5396 /******************************************************************************/
+ − 5397 /******************** Bit definition for PWR_CR register ********************/
+ − 5398 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
+ − 5399 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
+ − 5400 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
+ − 5401 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
+ − 5402 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
+ − 5403
+ − 5404 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
+ − 5405 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+ − 5406 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+ − 5407 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+ − 5408
+ − 5409 /*!< PVD level configuration */
+ − 5410 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
+ − 5411 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
+ − 5412 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
+ − 5413 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
+ − 5414 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
+ − 5415 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
+ − 5416 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
+ − 5417 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
+ − 5418 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
+ − 5419 #define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
+ − 5420 #define PWR_CR_LPLVDS ((uint32_t)0x00000400) /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */
+ − 5421 #define PWR_CR_MRLVDS ((uint32_t)0x00000800) /*!< Main regulator Low Voltage Scaling in Stop mode */
+ − 5422 #define PWR_CR_ADCDC1 ((uint32_t)0x00002000) /*!< Refer to AN4073 on how to use this bit */
+ − 5423 #define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+ − 5424 #define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+ − 5425 #define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+ − 5426 #define PWR_CR_ODEN ((uint32_t)0x00010000) /*!< Over Drive enable */
+ − 5427 #define PWR_CR_ODSWEN ((uint32_t)0x00020000) /*!< Over Drive switch enabled */
+ − 5428 #define PWR_CR_UDEN ((uint32_t)0x000C0000) /*!< Under Drive enable in stop mode */
+ − 5429 #define PWR_CR_UDEN_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+ − 5430 #define PWR_CR_UDEN_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+ − 5431
+ − 5432 /* Legacy define */
+ − 5433 #define PWR_CR_PMODE PWR_CR_VOS
+ − 5434 #define PWR_CR_LPUDS PWR_CR_LPLVDS /*!< Low-Power Regulator in deepsleep under-drive mode */
+ − 5435 #define PWR_CR_MRUDS PWR_CR_MRLVDS /*!< Main regulator in deepsleep under-drive mode */
+ − 5436
+ − 5437 /******************* Bit definition for PWR_CSR register ********************/
+ − 5438 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
+ − 5439 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
+ − 5440 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
+ − 5441 #define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
+ − 5442 #define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */
+ − 5443 #define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
+ − 5444 #define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
+ − 5445 #define PWR_CSR_ODRDY ((uint32_t)0x00010000) /*!< Over Drive generator ready */
+ − 5446 #define PWR_CSR_ODSWRDY ((uint32_t)0x00020000) /*!< Over Drive Switch ready */
+ − 5447 #define PWR_CSR_UDSWRDY ((uint32_t)0x000C0000) /*!< Under Drive ready */
+ − 5448
+ − 5449 /* Legacy define */
+ − 5450 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
+ − 5451
+ − 5452 /******************************************************************************/
+ − 5453 /* */
+ − 5454 /* Reset and Clock Control */
+ − 5455 /* */
+ − 5456 /******************************************************************************/
+ − 5457 /******************** Bit definition for RCC_CR register ********************/
+ − 5458 #define RCC_CR_HSION ((uint32_t)0x00000001)
+ − 5459 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
+ − 5460
+ − 5461 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
+ − 5462 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
+ − 5463 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
+ − 5464 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
+ − 5465 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
+ − 5466 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
+ − 5467
+ − 5468 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
+ − 5469 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
+ − 5470 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
+ − 5471 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
+ − 5472 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
+ − 5473 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
+ − 5474 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
+ − 5475 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
+ − 5476 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
+ − 5477
+ − 5478 #define RCC_CR_HSEON ((uint32_t)0x00010000)
+ − 5479 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
+ − 5480 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
+ − 5481 #define RCC_CR_CSSON ((uint32_t)0x00080000)
+ − 5482 #define RCC_CR_PLLON ((uint32_t)0x01000000)
+ − 5483 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
+ − 5484 #define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
+ − 5485 #define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
+ − 5486 #define RCC_CR_PLLSAION ((uint32_t)0x10000000)
+ − 5487 #define RCC_CR_PLLSAIRDY ((uint32_t)0x20000000)
+ − 5488
+ − 5489 /******************** Bit definition for RCC_PLLCFGR register ***************/
+ − 5490 #define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
+ − 5491 #define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
+ − 5492 #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
+ − 5493 #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
+ − 5494 #define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
+ − 5495 #define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
+ − 5496 #define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
+ − 5497
+ − 5498 #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
+ − 5499 #define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
+ − 5500 #define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
+ − 5501 #define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
+ − 5502 #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
+ − 5503 #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
+ − 5504 #define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
+ − 5505 #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
+ − 5506 #define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
+ − 5507 #define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
+ − 5508
+ − 5509 #define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
+ − 5510 #define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
+ − 5511 #define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
+ − 5512
+ − 5513 #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
+ − 5514 #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
+ − 5515 #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
+ − 5516
+ − 5517 #define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
+ − 5518 #define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
+ − 5519 #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
+ − 5520 #define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
+ − 5521 #define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
+ − 5522
+ − 5523 /******************** Bit definition for RCC_CFGR register ******************/
+ − 5524 /*!< SW configuration */
+ − 5525 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
+ − 5526 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+ − 5527 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+ − 5528
+ − 5529 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+ − 5530 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+ − 5531 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+ − 5532
+ − 5533 /*!< SWS configuration */
+ − 5534 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
+ − 5535 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+ − 5536 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+ − 5537
+ − 5538 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+ − 5539 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+ − 5540 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+ − 5541
+ − 5542 /*!< HPRE configuration */
+ − 5543 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
+ − 5544 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+ − 5545 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+ − 5546 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+ − 5547 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+ − 5548
+ − 5549 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+ − 5550 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+ − 5551 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+ − 5552 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+ − 5553 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+ − 5554 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+ − 5555 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+ − 5556 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+ − 5557 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+ − 5558
+ − 5559 /*!< PPRE1 configuration */
+ − 5560 #define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
+ − 5561 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+ − 5562 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+ − 5563 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+ − 5564
+ − 5565 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+ − 5566 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
+ − 5567 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
+ − 5568 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
+ − 5569 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
+ − 5570
+ − 5571 /*!< PPRE2 configuration */
+ − 5572 #define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
+ − 5573 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+ − 5574 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+ − 5575 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+ − 5576
+ − 5577 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+ − 5578 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
+ − 5579 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
+ − 5580 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
+ − 5581 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
+ − 5582
+ − 5583 /*!< RTCPRE configuration */
+ − 5584 #define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
+ − 5585 #define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
+ − 5586 #define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
+ − 5587 #define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
+ − 5588 #define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
+ − 5589 #define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
+ − 5590
+ − 5591 /*!< MCO1 configuration */
+ − 5592 #define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
+ − 5593 #define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
+ − 5594 #define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
+ − 5595
+ − 5596 #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
+ − 5597
+ − 5598 #define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
+ − 5599 #define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
+ − 5600 #define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
+ − 5601 #define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
+ − 5602
+ − 5603 #define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
+ − 5604 #define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
+ − 5605 #define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
+ − 5606 #define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
+ − 5607
+ − 5608 #define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
+ − 5609 #define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
+ − 5610 #define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
+ − 5611
+ − 5612 /******************** Bit definition for RCC_CIR register *******************/
+ − 5613 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
+ − 5614 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
+ − 5615 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
+ − 5616 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
+ − 5617 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
+ − 5618 #define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
+ − 5619 #define RCC_CIR_PLLSAIRDYF ((uint32_t)0x00000040)
+ − 5620 #define RCC_CIR_CSSF ((uint32_t)0x00000080)
+ − 5621 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
+ − 5622 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
+ − 5623 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
+ − 5624 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
+ − 5625 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
+ − 5626 #define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
+ − 5627 #define RCC_CIR_PLLSAIRDYIE ((uint32_t)0x00004000)
+ − 5628 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
+ − 5629 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
+ − 5630 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
+ − 5631 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
+ − 5632 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
+ − 5633 #define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
+ − 5634 #define RCC_CIR_PLLSAIRDYC ((uint32_t)0x00400000)
+ − 5635 #define RCC_CIR_CSSC ((uint32_t)0x00800000)
+ − 5636
+ − 5637 /******************** Bit definition for RCC_AHB1RSTR register **************/
+ − 5638 #define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
+ − 5639 #define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
+ − 5640 #define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
+ − 5641 #define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
+ − 5642 #define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
+ − 5643 #define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
+ − 5644 #define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)
+ − 5645 #define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
+ − 5646 #define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)
+ − 5647 #define RCC_AHB1RSTR_GPIOJRST ((uint32_t)0x00000200)
+ − 5648 #define RCC_AHB1RSTR_GPIOKRST ((uint32_t)0x00000400)
+ − 5649 #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
+ − 5650 #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
+ − 5651 #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
+ − 5652 #define RCC_AHB1RSTR_DMA2DRST ((uint32_t)0x00800000)
+ − 5653 #define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
+ − 5654 #define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)
+ − 5655
+ − 5656 /******************** Bit definition for RCC_AHB2RSTR register **************/
+ − 5657 #define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
+ − 5658 #define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
+ − 5659 #define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
+ − 5660
+ − 5661 /******************** Bit definition for RCC_AHB3RSTR register **************/
+ − 5662 #define RCC_AHB3RSTR_FMCRST ((uint32_t)0x00000001)
+ − 5663
+ − 5664 /******************** Bit definition for RCC_APB1RSTR register **************/
+ − 5665 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
+ − 5666 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
+ − 5667 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
+ − 5668 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
+ − 5669 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
+ − 5670 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
+ − 5671 #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
+ − 5672 #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
+ − 5673 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
+ − 5674 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
+ − 5675 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
+ − 5676 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
+ − 5677 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
+ − 5678 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
+ − 5679 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
+ − 5680 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
+ − 5681 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
+ − 5682 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
+ − 5683 #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
+ − 5684 #define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
+ − 5685 #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
+ − 5686 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
+ − 5687 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
+ − 5688 #define RCC_APB1RSTR_UART7RST ((uint32_t)0x40000000)
+ − 5689 #define RCC_APB1RSTR_UART8RST ((uint32_t)0x80000000)
+ − 5690
+ − 5691 /******************** Bit definition for RCC_APB2RSTR register **************/
+ − 5692 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
+ − 5693 #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)
+ − 5694 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
+ − 5695 #define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
+ − 5696 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
+ − 5697 #define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
+ − 5698 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
+ − 5699 #define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)
+ − 5700 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
+ − 5701 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
+ − 5702 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
+ − 5703 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
+ − 5704 #define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000)
+ − 5705 #define RCC_APB2RSTR_SPI6RST ((uint32_t)0x00200000)
+ − 5706 #define RCC_APB2RSTR_SAI1RST ((uint32_t)0x00400000)
+ − 5707 #define RCC_APB2RSTR_LTDCRST ((uint32_t)0x04000000)
+ − 5708
+ − 5709 /* Old SPI1RST bit definition, maintained for legacy purpose */
+ − 5710 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
+ − 5711
+ − 5712 /******************** Bit definition for RCC_AHB1ENR register ***************/
+ − 5713 #define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
+ − 5714 #define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
+ − 5715 #define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
+ − 5716 #define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
+ − 5717 #define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
+ − 5718 #define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)
+ − 5719 #define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)
+ − 5720 #define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
+ − 5721 #define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)
+ − 5722 #define RCC_AHB1ENR_GPIOJEN ((uint32_t)0x00000200)
+ − 5723 #define RCC_AHB1ENR_GPIOKEN ((uint32_t)0x00000400)
+ − 5724
+ − 5725 #define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
+ − 5726 #define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
+ − 5727 #define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
+ − 5728 #define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
+ − 5729 #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
+ − 5730 #define RCC_AHB1ENR_DMA2DEN ((uint32_t)0x00800000)
+ − 5731
+ − 5732 #define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)
+ − 5733 #define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)
+ − 5734 #define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)
+ − 5735 #define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)
+ − 5736 #define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)
+ − 5737 #define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)
+ − 5738
+ − 5739 /******************** Bit definition for RCC_AHB2ENR register ***************/
+ − 5740 #define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)
+ − 5741 #define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
+ − 5742 #define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
+ − 5743
+ − 5744 /******************** Bit definition for RCC_AHB3ENR register ***************/
+ − 5745 #define RCC_AHB3ENR_FMCEN ((uint32_t)0x00000001)
+ − 5746
+ − 5747 /******************** Bit definition for RCC_APB1ENR register ***************/
+ − 5748 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
+ − 5749 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
+ − 5750 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
+ − 5751 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
+ − 5752 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
+ − 5753 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
+ − 5754 #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
+ − 5755 #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
+ − 5756 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
+ − 5757 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
+ − 5758 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
+ − 5759 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
+ − 5760 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
+ − 5761 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
+ − 5762 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
+ − 5763 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
+ − 5764 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
+ − 5765 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
+ − 5766 #define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
+ − 5767 #define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
+ − 5768 #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
+ − 5769 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
+ − 5770 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
+ − 5771 #define RCC_APB1ENR_UART7EN ((uint32_t)0x40000000)
+ − 5772 #define RCC_APB1ENR_UART8EN ((uint32_t)0x80000000)
+ − 5773
+ − 5774 /******************** Bit definition for RCC_APB2ENR register ***************/
+ − 5775 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
+ − 5776 #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
+ − 5777 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
+ − 5778 #define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
+ − 5779 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
+ − 5780 #define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)
+ − 5781 #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
+ − 5782 #define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
+ − 5783 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
+ − 5784 #define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)
+ − 5785 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
+ − 5786 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
+ − 5787 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
+ − 5788 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
+ − 5789 #define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)
+ − 5790 #define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000)
+ − 5791 #define RCC_APB2ENR_SAI1EN ((uint32_t)0x00400000)
+ − 5792 #define RCC_APB2ENR_LTDCEN ((uint32_t)0x04000000)
+ − 5793
+ − 5794 /******************** Bit definition for RCC_AHB1LPENR register *************/
+ − 5795 #define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
+ − 5796 #define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
+ − 5797 #define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
+ − 5798 #define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
+ − 5799 #define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
+ − 5800 #define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)
+ − 5801 #define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)
+ − 5802 #define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
+ − 5803 #define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)
+ − 5804 #define RCC_AHB1LPENR_GPIOJLPEN ((uint32_t)0x00000200)
+ − 5805 #define RCC_AHB1LPENR_GPIOKLPEN ((uint32_t)0x00000400)
+ − 5806
+ − 5807 #define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
+ − 5808 #define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
+ − 5809 #define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
+ − 5810 #define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
+ − 5811 #define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
+ − 5812 #define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
+ − 5813 #define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
+ − 5814 #define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
+ − 5815 #define RCC_AHB1LPENR_DMA2DLPEN ((uint32_t)0x00800000)
+ − 5816
+ − 5817 #define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)
+ − 5818 #define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)
+ − 5819 #define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)
+ − 5820 #define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)
+ − 5821 #define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
+ − 5822 #define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)
+ − 5823
+ − 5824 /******************** Bit definition for RCC_AHB2LPENR register *************/
+ − 5825 #define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)
+ − 5826 #define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
+ − 5827 #define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
+ − 5828
+ − 5829 /******************** Bit definition for RCC_AHB3LPENR register *************/
+ − 5830 #define RCC_AHB3LPENR_FMCLPEN ((uint32_t)0x00000001)
+ − 5831
+ − 5832 /******************** Bit definition for RCC_APB1LPENR register *************/
+ − 5833 #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
+ − 5834 #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
+ − 5835 #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
+ − 5836 #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
+ − 5837 #define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
+ − 5838 #define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
+ − 5839 #define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)
+ − 5840 #define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
+ − 5841 #define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)
+ − 5842 #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
+ − 5843 #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
+ − 5844 #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
+ − 5845 #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
+ − 5846 #define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
+ − 5847 #define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)
+ − 5848 #define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)
+ − 5849 #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
+ − 5850 #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
+ − 5851 #define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
+ − 5852 #define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)
+ − 5853 #define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)
+ − 5854 #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
+ − 5855 #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
+ − 5856 #define RCC_APB1LPENR_UART7LPEN ((uint32_t)0x40000000)
+ − 5857 #define RCC_APB1LPENR_UART8LPEN ((uint32_t)0x80000000)
+ − 5858
+ − 5859 /******************** Bit definition for RCC_APB2LPENR register *************/
+ − 5860 #define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
+ − 5861 #define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
+ − 5862 #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
+ − 5863 #define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
+ − 5864 #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
+ − 5865 #define RCC_APB2LPENR_ADC2LPEN ((uint32_t)0x00000200)
+ − 5866 #define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
+ − 5867 #define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
+ − 5868 #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
+ − 5869 #define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)
+ − 5870 #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
+ − 5871 #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
+ − 5872 #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
+ − 5873 #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
+ − 5874 #define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000)
+ − 5875 #define RCC_APB2LPENR_SPI6LPEN ((uint32_t)0x00200000)
+ − 5876 #define RCC_APB2LPENR_SAI1LPEN ((uint32_t)0x00400000)
+ − 5877 #define RCC_APB2LPENR_LTDCLPEN ((uint32_t)0x04000000)
+ − 5878
+ − 5879 /******************** Bit definition for RCC_BDCR register ******************/
+ − 5880 #define RCC_BDCR_LSEON ((uint32_t)0x00000001)
+ − 5881 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
+ − 5882 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
+ − 5883
+ − 5884 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
+ − 5885 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
+ − 5886 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
+ − 5887
+ − 5888 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
+ − 5889 #define RCC_BDCR_BDRST ((uint32_t)0x00010000)
+ − 5890
+ − 5891 /******************** Bit definition for RCC_CSR register *******************/
+ − 5892 #define RCC_CSR_LSION ((uint32_t)0x00000001)
+ − 5893 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
+ − 5894 #define RCC_CSR_RMVF ((uint32_t)0x01000000)
+ − 5895 #define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
+ − 5896 #define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
+ − 5897 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
+ − 5898 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
+ − 5899 #define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
+ − 5900 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
+ − 5901 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
+ − 5902
+ − 5903 /******************** Bit definition for RCC_SSCGR register *****************/
+ − 5904 #define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
+ − 5905 #define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
+ − 5906 #define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
+ − 5907 #define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
+ − 5908
+ − 5909 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
+ − 5910 #define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
+ − 5911 #define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040)
+ − 5912 #define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080)
+ − 5913 #define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)
+ − 5914 #define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)
+ − 5915 #define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)
+ − 5916 #define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)
+ − 5917 #define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)
+ − 5918 #define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)
+ − 5919 #define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)
+ − 5920
+ − 5921 #define RCC_PLLI2SCFGR_PLLI2SQ ((uint32_t)0x0F000000)
+ − 5922 #define RCC_PLLI2SCFGR_PLLI2SQ_0 ((uint32_t)0x01000000)
+ − 5923 #define RCC_PLLI2SCFGR_PLLI2SQ_1 ((uint32_t)0x02000000)
+ − 5924 #define RCC_PLLI2SCFGR_PLLI2SQ_2 ((uint32_t)0x04000000)
+ − 5925 #define RCC_PLLI2SCFGR_PLLI2SQ_3 ((uint32_t)0x08000000)
+ − 5926
+ − 5927 #define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
+ − 5928 #define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)
+ − 5929 #define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)
+ − 5930 #define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)
+ − 5931
+ − 5932
+ − 5933 /******************** Bit definition for RCC_PLLSAICFGR register ************/
+ − 5934 #define RCC_PLLSAICFGR_PLLSAIN ((uint32_t)0x00007FC0)
+ − 5935 #define RCC_PLLSAICFGR_PLLSAIN_0 ((uint32_t)0x00000040)
+ − 5936 #define RCC_PLLSAICFGR_PLLSAIN_1 ((uint32_t)0x00000080)
+ − 5937 #define RCC_PLLSAICFGR_PLLSAIN_2 ((uint32_t)0x00000100)
+ − 5938 #define RCC_PLLSAICFGR_PLLSAIN_3 ((uint32_t)0x00000200)
+ − 5939 #define RCC_PLLSAICFGR_PLLSAIN_4 ((uint32_t)0x00000400)
+ − 5940 #define RCC_PLLSAICFGR_PLLSAIN_5 ((uint32_t)0x00000800)
+ − 5941 #define RCC_PLLSAICFGR_PLLSAIN_6 ((uint32_t)0x00001000)
+ − 5942 #define RCC_PLLSAICFGR_PLLSAIN_7 ((uint32_t)0x00002000)
+ − 5943 #define RCC_PLLSAICFGR_PLLSAIN_8 ((uint32_t)0x00004000)
+ − 5944
+ − 5945 #define RCC_PLLSAICFGR_PLLSAIQ ((uint32_t)0x0F000000)
+ − 5946 #define RCC_PLLSAICFGR_PLLSAIQ_0 ((uint32_t)0x01000000)
+ − 5947 #define RCC_PLLSAICFGR_PLLSAIQ_1 ((uint32_t)0x02000000)
+ − 5948 #define RCC_PLLSAICFGR_PLLSAIQ_2 ((uint32_t)0x04000000)
+ − 5949 #define RCC_PLLSAICFGR_PLLSAIQ_3 ((uint32_t)0x08000000)
+ − 5950
+ − 5951 #define RCC_PLLSAICFGR_PLLSAIR ((uint32_t)0x70000000)
+ − 5952 #define RCC_PLLSAICFGR_PLLSAIR_0 ((uint32_t)0x10000000)
+ − 5953 #define RCC_PLLSAICFGR_PLLSAIR_1 ((uint32_t)0x20000000)
+ − 5954 #define RCC_PLLSAICFGR_PLLSAIR_2 ((uint32_t)0x40000000)
+ − 5955
+ − 5956 /******************** Bit definition for RCC_DCKCFGR register ***************/
+ − 5957 #define RCC_DCKCFGR_PLLI2SDIVQ ((uint32_t)0x0000001F)
+ − 5958 #define RCC_DCKCFGR_PLLSAIDIVQ ((uint32_t)0x00001F00)
+ − 5959 #define RCC_DCKCFGR_PLLSAIDIVR ((uint32_t)0x00030000)
+ − 5960 #define RCC_DCKCFGR_SAI1ASRC ((uint32_t)0x00300000)
+ − 5961 #define RCC_DCKCFGR_SAI1BSRC ((uint32_t)0x00C00000)
+ − 5962 #define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000)
+ − 5963
+ − 5964
+ − 5965 /******************************************************************************/
+ − 5966 /* */
+ − 5967 /* RNG */
+ − 5968 /* */
+ − 5969 /******************************************************************************/
+ − 5970 /******************** Bits definition for RNG_CR register *******************/
+ − 5971 #define RNG_CR_RNGEN ((uint32_t)0x00000004)
+ − 5972 #define RNG_CR_IE ((uint32_t)0x00000008)
+ − 5973
+ − 5974 /******************** Bits definition for RNG_SR register *******************/
+ − 5975 #define RNG_SR_DRDY ((uint32_t)0x00000001)
+ − 5976 #define RNG_SR_CECS ((uint32_t)0x00000002)
+ − 5977 #define RNG_SR_SECS ((uint32_t)0x00000004)
+ − 5978 #define RNG_SR_CEIS ((uint32_t)0x00000020)
+ − 5979 #define RNG_SR_SEIS ((uint32_t)0x00000040)
+ − 5980
+ − 5981 /******************************************************************************/
+ − 5982 /* */
+ − 5983 /* Real-Time Clock (RTC) */
+ − 5984 /* */
+ − 5985 /******************************************************************************/
+ − 5986 /******************** Bits definition for RTC_TR register *******************/
+ − 5987 #define RTC_TR_PM ((uint32_t)0x00400000)
+ − 5988 #define RTC_TR_HT ((uint32_t)0x00300000)
+ − 5989 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
+ − 5990 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
+ − 5991 #define RTC_TR_HU ((uint32_t)0x000F0000)
+ − 5992 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
+ − 5993 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
+ − 5994 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
+ − 5995 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
+ − 5996 #define RTC_TR_MNT ((uint32_t)0x00007000)
+ − 5997 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
+ − 5998 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
+ − 5999 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
+ − 6000 #define RTC_TR_MNU ((uint32_t)0x00000F00)
+ − 6001 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
+ − 6002 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
+ − 6003 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
+ − 6004 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
+ − 6005 #define RTC_TR_ST ((uint32_t)0x00000070)
+ − 6006 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
+ − 6007 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
+ − 6008 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
+ − 6009 #define RTC_TR_SU ((uint32_t)0x0000000F)
+ − 6010 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
+ − 6011 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
+ − 6012 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
+ − 6013 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
+ − 6014
+ − 6015 /******************** Bits definition for RTC_DR register *******************/
+ − 6016 #define RTC_DR_YT ((uint32_t)0x00F00000)
+ − 6017 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
+ − 6018 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
+ − 6019 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
+ − 6020 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
+ − 6021 #define RTC_DR_YU ((uint32_t)0x000F0000)
+ − 6022 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
+ − 6023 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
+ − 6024 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
+ − 6025 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
+ − 6026 #define RTC_DR_WDU ((uint32_t)0x0000E000)
+ − 6027 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
+ − 6028 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
+ − 6029 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
+ − 6030 #define RTC_DR_MT ((uint32_t)0x00001000)
+ − 6031 #define RTC_DR_MU ((uint32_t)0x00000F00)
+ − 6032 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
+ − 6033 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
+ − 6034 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
+ − 6035 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
+ − 6036 #define RTC_DR_DT ((uint32_t)0x00000030)
+ − 6037 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
+ − 6038 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
+ − 6039 #define RTC_DR_DU ((uint32_t)0x0000000F)
+ − 6040 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
+ − 6041 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
+ − 6042 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
+ − 6043 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
+ − 6044
+ − 6045 /******************** Bits definition for RTC_CR register *******************/
+ − 6046 #define RTC_CR_COE ((uint32_t)0x00800000)
+ − 6047 #define RTC_CR_OSEL ((uint32_t)0x00600000)
+ − 6048 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
+ − 6049 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
+ − 6050 #define RTC_CR_POL ((uint32_t)0x00100000)
+ − 6051 #define RTC_CR_COSEL ((uint32_t)0x00080000)
+ − 6052 #define RTC_CR_BCK ((uint32_t)0x00040000)
+ − 6053 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
+ − 6054 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
+ − 6055 #define RTC_CR_TSIE ((uint32_t)0x00008000)
+ − 6056 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
+ − 6057 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
+ − 6058 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
+ − 6059 #define RTC_CR_TSE ((uint32_t)0x00000800)
+ − 6060 #define RTC_CR_WUTE ((uint32_t)0x00000400)
+ − 6061 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
+ − 6062 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
+ − 6063 #define RTC_CR_DCE ((uint32_t)0x00000080)
+ − 6064 #define RTC_CR_FMT ((uint32_t)0x00000040)
+ − 6065 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
+ − 6066 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
+ − 6067 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
+ − 6068 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
+ − 6069 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
+ − 6070 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
+ − 6071 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
+ − 6072
+ − 6073 /******************** Bits definition for RTC_ISR register ******************/
+ − 6074 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
+ − 6075 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
+ − 6076 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
+ − 6077 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
+ − 6078 #define RTC_ISR_TSF ((uint32_t)0x00000800)
+ − 6079 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
+ − 6080 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
+ − 6081 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
+ − 6082 #define RTC_ISR_INIT ((uint32_t)0x00000080)
+ − 6083 #define RTC_ISR_INITF ((uint32_t)0x00000040)
+ − 6084 #define RTC_ISR_RSF ((uint32_t)0x00000020)
+ − 6085 #define RTC_ISR_INITS ((uint32_t)0x00000010)
+ − 6086 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
+ − 6087 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
+ − 6088 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
+ − 6089 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
+ − 6090
+ − 6091 /******************** Bits definition for RTC_PRER register *****************/
+ − 6092 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
+ − 6093 #define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
+ − 6094
+ − 6095 /******************** Bits definition for RTC_WUTR register *****************/
+ − 6096 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
+ − 6097
+ − 6098 /******************** Bits definition for RTC_CALIBR register ***************/
+ − 6099 #define RTC_CALIBR_DCS ((uint32_t)0x00000080)
+ − 6100 #define RTC_CALIBR_DC ((uint32_t)0x0000001F)
+ − 6101
+ − 6102 /******************** Bits definition for RTC_ALRMAR register ***************/
+ − 6103 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
+ − 6104 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
+ − 6105 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
+ − 6106 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
+ − 6107 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
+ − 6108 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
+ − 6109 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
+ − 6110 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
+ − 6111 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
+ − 6112 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
+ − 6113 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
+ − 6114 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
+ − 6115 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
+ − 6116 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
+ − 6117 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
+ − 6118 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
+ − 6119 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
+ − 6120 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
+ − 6121 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
+ − 6122 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
+ − 6123 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
+ − 6124 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
+ − 6125 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
+ − 6126 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
+ − 6127 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
+ − 6128 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
+ − 6129 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
+ − 6130 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
+ − 6131 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
+ − 6132 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
+ − 6133 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
+ − 6134 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
+ − 6135 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
+ − 6136 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
+ − 6137 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
+ − 6138 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
+ − 6139 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
+ − 6140 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
+ − 6141 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
+ − 6142 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
+ − 6143
+ − 6144 /******************** Bits definition for RTC_ALRMBR register ***************/
+ − 6145 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
+ − 6146 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
+ − 6147 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
+ − 6148 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
+ − 6149 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
+ − 6150 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
+ − 6151 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
+ − 6152 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
+ − 6153 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
+ − 6154 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
+ − 6155 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
+ − 6156 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
+ − 6157 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
+ − 6158 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
+ − 6159 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
+ − 6160 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
+ − 6161 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
+ − 6162 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
+ − 6163 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
+ − 6164 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
+ − 6165 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
+ − 6166 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
+ − 6167 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
+ − 6168 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
+ − 6169 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
+ − 6170 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
+ − 6171 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
+ − 6172 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
+ − 6173 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
+ − 6174 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
+ − 6175 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
+ − 6176 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
+ − 6177 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
+ − 6178 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
+ − 6179 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
+ − 6180 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
+ − 6181 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
+ − 6182 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
+ − 6183 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
+ − 6184 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
+ − 6185
+ − 6186 /******************** Bits definition for RTC_WPR register ******************/
+ − 6187 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
+ − 6188
+ − 6189 /******************** Bits definition for RTC_SSR register ******************/
+ − 6190 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
+ − 6191
+ − 6192 /******************** Bits definition for RTC_SHIFTR register ***************/
+ − 6193 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
+ − 6194 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
+ − 6195
+ − 6196 /******************** Bits definition for RTC_TSTR register *****************/
+ − 6197 #define RTC_TSTR_PM ((uint32_t)0x00400000)
+ − 6198 #define RTC_TSTR_HT ((uint32_t)0x00300000)
+ − 6199 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
+ − 6200 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
+ − 6201 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
+ − 6202 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
+ − 6203 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
+ − 6204 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
+ − 6205 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
+ − 6206 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
+ − 6207 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
+ − 6208 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
+ − 6209 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
+ − 6210 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
+ − 6211 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
+ − 6212 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
+ − 6213 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
+ − 6214 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
+ − 6215 #define RTC_TSTR_ST ((uint32_t)0x00000070)
+ − 6216 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
+ − 6217 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
+ − 6218 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
+ − 6219 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
+ − 6220 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
+ − 6221 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
+ − 6222 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
+ − 6223 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
+ − 6224
+ − 6225 /******************** Bits definition for RTC_TSDR register *****************/
+ − 6226 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
+ − 6227 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
+ − 6228 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
+ − 6229 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
+ − 6230 #define RTC_TSDR_MT ((uint32_t)0x00001000)
+ − 6231 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
+ − 6232 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
+ − 6233 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
+ − 6234 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
+ − 6235 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
+ − 6236 #define RTC_TSDR_DT ((uint32_t)0x00000030)
+ − 6237 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
+ − 6238 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
+ − 6239 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
+ − 6240 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
+ − 6241 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
+ − 6242 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
+ − 6243 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
+ − 6244
+ − 6245 /******************** Bits definition for RTC_TSSSR register ****************/
+ − 6246 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
+ − 6247
+ − 6248 /******************** Bits definition for RTC_CAL register *****************/
+ − 6249 #define RTC_CALR_CALP ((uint32_t)0x00008000)
+ − 6250 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
+ − 6251 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
+ − 6252 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
+ − 6253 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
+ − 6254 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
+ − 6255 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
+ − 6256 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
+ − 6257 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
+ − 6258 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
+ − 6259 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
+ − 6260 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
+ − 6261 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
+ − 6262
+ − 6263 /******************** Bits definition for RTC_TAFCR register ****************/
+ − 6264 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
+ − 6265 #define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
+ − 6266 #define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
+ − 6267 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
+ − 6268 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
+ − 6269 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
+ − 6270 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
+ − 6271 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
+ − 6272 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
+ − 6273 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
+ − 6274 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
+ − 6275 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
+ − 6276 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
+ − 6277 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
+ − 6278 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
+ − 6279 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
+ − 6280 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
+ − 6281 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
+ − 6282 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
+ − 6283 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
+ − 6284
+ − 6285 /******************** Bits definition for RTC_ALRMASSR register *************/
+ − 6286 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
+ − 6287 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
+ − 6288 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
+ − 6289 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
+ − 6290 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
+ − 6291 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
+ − 6292
+ − 6293 /******************** Bits definition for RTC_ALRMBSSR register *************/
+ − 6294 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
+ − 6295 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
+ − 6296 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
+ − 6297 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
+ − 6298 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
+ − 6299 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
+ − 6300
+ − 6301 /******************** Bits definition for RTC_BKP0R register ****************/
+ − 6302 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
+ − 6303
+ − 6304 /******************** Bits definition for RTC_BKP1R register ****************/
+ − 6305 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
+ − 6306
+ − 6307 /******************** Bits definition for RTC_BKP2R register ****************/
+ − 6308 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
+ − 6309
+ − 6310 /******************** Bits definition for RTC_BKP3R register ****************/
+ − 6311 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
+ − 6312
+ − 6313 /******************** Bits definition for RTC_BKP4R register ****************/
+ − 6314 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
+ − 6315
+ − 6316 /******************** Bits definition for RTC_BKP5R register ****************/
+ − 6317 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
+ − 6318
+ − 6319 /******************** Bits definition for RTC_BKP6R register ****************/
+ − 6320 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
+ − 6321
+ − 6322 /******************** Bits definition for RTC_BKP7R register ****************/
+ − 6323 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
+ − 6324
+ − 6325 /******************** Bits definition for RTC_BKP8R register ****************/
+ − 6326 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
+ − 6327
+ − 6328 /******************** Bits definition for RTC_BKP9R register ****************/
+ − 6329 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
+ − 6330
+ − 6331 /******************** Bits definition for RTC_BKP10R register ***************/
+ − 6332 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
+ − 6333
+ − 6334 /******************** Bits definition for RTC_BKP11R register ***************/
+ − 6335 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
+ − 6336
+ − 6337 /******************** Bits definition for RTC_BKP12R register ***************/
+ − 6338 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
+ − 6339
+ − 6340 /******************** Bits definition for RTC_BKP13R register ***************/
+ − 6341 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
+ − 6342
+ − 6343 /******************** Bits definition for RTC_BKP14R register ***************/
+ − 6344 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
+ − 6345
+ − 6346 /******************** Bits definition for RTC_BKP15R register ***************/
+ − 6347 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
+ − 6348
+ − 6349 /******************** Bits definition for RTC_BKP16R register ***************/
+ − 6350 #define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
+ − 6351
+ − 6352 /******************** Bits definition for RTC_BKP17R register ***************/
+ − 6353 #define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
+ − 6354
+ − 6355 /******************** Bits definition for RTC_BKP18R register ***************/
+ − 6356 #define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
+ − 6357
+ − 6358 /******************** Bits definition for RTC_BKP19R register ***************/
+ − 6359 #define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
+ − 6360
+ − 6361 /******************************************************************************/
+ − 6362 /* */
+ − 6363 /* Serial Audio Interface */
+ − 6364 /* */
+ − 6365 /******************************************************************************/
+ − 6366 /******************** Bit definition for SAI_GCR register *******************/
+ − 6367 #define SAI_GCR_SYNCIN ((uint32_t)0x00000003) /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
+ − 6368 #define SAI_GCR_SYNCIN_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+ − 6369 #define SAI_GCR_SYNCIN_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+ − 6370
+ − 6371 #define SAI_GCR_SYNCOUT ((uint32_t)0x00000030) /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+ − 6372 #define SAI_GCR_SYNCOUT_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+ − 6373 #define SAI_GCR_SYNCOUT_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+ − 6374
+ − 6375 /******************* Bit definition for SAI_xCR1 register *******************/
+ − 6376 #define SAI_xCR1_MODE ((uint32_t)0x00000003) /*!<MODE[1:0] bits (Audio Block Mode) */
+ − 6377 #define SAI_xCR1_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+ − 6378 #define SAI_xCR1_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+ − 6379
+ − 6380 #define SAI_xCR1_PRTCFG ((uint32_t)0x0000000C) /*!<PRTCFG[1:0] bits (Protocol Configuration) */
+ − 6381 #define SAI_xCR1_PRTCFG_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+ − 6382 #define SAI_xCR1_PRTCFG_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+ − 6383
+ − 6384 #define SAI_xCR1_DS ((uint32_t)0x000000E0) /*!<DS[1:0] bits (Data Size) */
+ − 6385 #define SAI_xCR1_DS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+ − 6386 #define SAI_xCR1_DS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+ − 6387 #define SAI_xCR1_DS_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+ − 6388
+ − 6389 #define SAI_xCR1_LSBFIRST ((uint32_t)0x00000100) /*!<LSB First Configuration */
+ − 6390 #define SAI_xCR1_CKSTR ((uint32_t)0x00000200) /*!<ClocK STRobing edge */
+ − 6391
+ − 6392 #define SAI_xCR1_SYNCEN ((uint32_t)0x00000C00) /*!<SYNCEN[1:0](SYNChronization ENable) */
+ − 6393 #define SAI_xCR1_SYNCEN_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+ − 6394 #define SAI_xCR1_SYNCEN_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+ − 6395
+ − 6396 #define SAI_xCR1_MONO ((uint32_t)0x00001000) /*!<Mono mode */
+ − 6397 #define SAI_xCR1_OUTDRIV ((uint32_t)0x00002000) /*!<Output Drive */
+ − 6398 #define SAI_xCR1_SAIEN ((uint32_t)0x00010000) /*!<Audio Block enable */
+ − 6399 #define SAI_xCR1_DMAEN ((uint32_t)0x00020000) /*!<DMA enable */
+ − 6400 #define SAI_xCR1_NODIV ((uint32_t)0x00080000) /*!<No Divider Configuration */
+ − 6401
+ − 6402 #define SAI_xCR1_MCKDIV ((uint32_t)0x00780000) /*!<MCKDIV[3:0] (Master ClocK Divider) */
+ − 6403 #define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00080000) /*!<Bit 0 */
+ − 6404 #define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00100000) /*!<Bit 1 */
+ − 6405 #define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00200000) /*!<Bit 2 */
+ − 6406 #define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00400000) /*!<Bit 3 */
+ − 6407
+ − 6408 /******************* Bit definition for SAI_xCR2 register *******************/
+ − 6409 #define SAI_xCR2_FTH ((uint32_t)0x00000003) /*!<FTH[1:0](Fifo THreshold) */
+ − 6410 #define SAI_xCR2_FTH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+ − 6411 #define SAI_xCR2_FTH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+ − 6412
+ − 6413 #define SAI_xCR2_FFLUSH ((uint32_t)0x00000008) /*!<Fifo FLUSH */
+ − 6414 #define SAI_xCR2_TRIS ((uint32_t)0x00000010) /*!<TRIState Management on data line */
+ − 6415 #define SAI_xCR2_MUTE ((uint32_t)0x00000020) /*!<Mute mode */
+ − 6416 #define SAI_xCR2_MUTEVAL ((uint32_t)0x00000040) /*!<Muate value */
+ − 6417
+ − 6418 #define SAI_xCR2_MUTECNT ((uint32_t)0x00001F80) /*!<MUTECNT[5:0] (MUTE counter) */
+ − 6419 #define SAI_xCR2_MUTECNT_0 ((uint32_t)0x00000080) /*!<Bit 0 */
+ − 6420 #define SAI_xCR2_MUTECNT_1 ((uint32_t)0x00000100) /*!<Bit 1 */
+ − 6421 #define SAI_xCR2_MUTECNT_2 ((uint32_t)0x00000200) /*!<Bit 2 */
+ − 6422 #define SAI_xCR2_MUTECNT_3 ((uint32_t)0x00000400) /*!<Bit 3 */
+ − 6423 #define SAI_xCR2_MUTECNT_4 ((uint32_t)0x00000800) /*!<Bit 4 */
+ − 6424 #define SAI_xCR2_MUTECNT_5 ((uint32_t)0x00001000) /*!<Bit 5 */
+ − 6425
+ − 6426 #define SAI_xCR2_CPL ((uint32_t)0x00080000) /*!< Complement Bit */
+ − 6427
+ − 6428 #define SAI_xCR2_COMP ((uint32_t)0x0000C000) /*!<COMP[1:0] (Companding mode) */
+ − 6429 #define SAI_xCR2_COMP_0 ((uint32_t)0x00004000) /*!<Bit 0 */
+ − 6430 #define SAI_xCR2_COMP_1 ((uint32_t)0x00008000) /*!<Bit 1 */
+ − 6431
+ − 6432 /****************** Bit definition for SAI_xFRCR register *******************/
+ − 6433 #define SAI_xFRCR_FRL ((uint32_t)0x000000FF) /*!<FRL[1:0](Frame length) */
+ − 6434 #define SAI_xFRCR_FRL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+ − 6435 #define SAI_xFRCR_FRL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+ − 6436 #define SAI_xFRCR_FRL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+ − 6437 #define SAI_xFRCR_FRL_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+ − 6438 #define SAI_xFRCR_FRL_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+ − 6439 #define SAI_xFRCR_FRL_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+ − 6440 #define SAI_xFRCR_FRL_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+ − 6441 #define SAI_xFRCR_FRL_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+ − 6442
+ − 6443 #define SAI_xFRCR_FSALL ((uint32_t)0x00007F00) /*!<FRL[1:0] (Frame synchronization active level length) */
+ − 6444 #define SAI_xFRCR_FSALL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+ − 6445 #define SAI_xFRCR_FSALL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+ − 6446 #define SAI_xFRCR_FSALL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+ − 6447 #define SAI_xFRCR_FSALL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+ − 6448 #define SAI_xFRCR_FSALL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+ − 6449 #define SAI_xFRCR_FSALL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+ − 6450 #define SAI_xFRCR_FSALL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+ − 6451
+ − 6452 #define SAI_xFRCR_FSDEF ((uint32_t)0x00010000) /*!< Frame Synchronization Definition */
+ − 6453 #define SAI_xFRCR_FSPO ((uint32_t)0x00020000) /*!<Frame Synchronization POLarity */
+ − 6454 #define SAI_xFRCR_FSOFF ((uint32_t)0x00040000) /*!<Frame Synchronization OFFset */
+ − 6455
+ − 6456 /****************** Bit definition for SAI_xSLOTR register *******************/
+ − 6457 #define SAI_xSLOTR_FBOFF ((uint32_t)0x0000001F) /*!<FRL[4:0](First Bit Offset) */
+ − 6458 #define SAI_xSLOTR_FBOFF_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+ − 6459 #define SAI_xSLOTR_FBOFF_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+ − 6460 #define SAI_xSLOTR_FBOFF_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+ − 6461 #define SAI_xSLOTR_FBOFF_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+ − 6462 #define SAI_xSLOTR_FBOFF_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+ − 6463
+ − 6464 #define SAI_xSLOTR_SLOTSZ ((uint32_t)0x000000C0) /*!<SLOTSZ[1:0] (Slot size) */
+ − 6465 #define SAI_xSLOTR_SLOTSZ_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+ − 6466 #define SAI_xSLOTR_SLOTSZ_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+ − 6467
+ − 6468 #define SAI_xSLOTR_NBSLOT ((uint32_t)0x00000F00) /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
+ − 6469 #define SAI_xSLOTR_NBSLOT_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+ − 6470 #define SAI_xSLOTR_NBSLOT_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+ − 6471 #define SAI_xSLOTR_NBSLOT_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+ − 6472 #define SAI_xSLOTR_NBSLOT_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+ − 6473
+ − 6474 #define SAI_xSLOTR_SLOTEN ((uint32_t)0xFFFF0000) /*!<SLOTEN[15:0] (Slot Enable) */
+ − 6475
+ − 6476 /******************* Bit definition for SAI_xIMR register *******************/
+ − 6477 #define SAI_xIMR_OVRUDRIE ((uint32_t)0x00000001) /*!<Overrun underrun interrupt enable */
+ − 6478 #define SAI_xIMR_MUTEDETIE ((uint32_t)0x00000002) /*!<Mute detection interrupt enable */
+ − 6479 #define SAI_xIMR_WCKCFGIE ((uint32_t)0x00000004) /*!<Wrong Clock Configuration interrupt enable */
+ − 6480 #define SAI_xIMR_FREQIE ((uint32_t)0x00000008) /*!<FIFO request interrupt enable */
+ − 6481 #define SAI_xIMR_CNRDYIE ((uint32_t)0x00000010) /*!<Codec not ready interrupt enable */
+ − 6482 #define SAI_xIMR_AFSDETIE ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection interrupt enable */
+ − 6483 #define SAI_xIMR_LFSDETIE ((uint32_t)0x00000040) /*!<Late frame synchronization detection interrupt enable */
+ − 6484
+ − 6485 /******************** Bit definition for SAI_xSR register *******************/
+ − 6486 #define SAI_xSR_OVRUDR ((uint32_t)0x00000001) /*!<Overrun underrun */
+ − 6487 #define SAI_xSR_MUTEDET ((uint32_t)0x00000002) /*!<Mute detection */
+ − 6488 #define SAI_xSR_WCKCFG ((uint32_t)0x00000004) /*!<Wrong Clock Configuration */
+ − 6489 #define SAI_xSR_FREQ ((uint32_t)0x00000008) /*!<FIFO request */
+ − 6490 #define SAI_xSR_CNRDY ((uint32_t)0x00000010) /*!<Codec not ready */
+ − 6491 #define SAI_xSR_AFSDET ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection */
+ − 6492 #define SAI_xSR_LFSDET ((uint32_t)0x00000040) /*!<Late frame synchronization detection */
+ − 6493
+ − 6494 #define SAI_xSR_FLVL ((uint32_t)0x00070000) /*!<FLVL[2:0] (FIFO Level Threshold) */
+ − 6495 #define SAI_xSR_FLVL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+ − 6496 #define SAI_xSR_FLVL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+ − 6497 #define SAI_xSR_FLVL_2 ((uint32_t)0x00030000) /*!<Bit 2 */
+ − 6498
+ − 6499 /****************** Bit definition for SAI_xCLRFR register ******************/
+ − 6500 #define SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001) /*!<Clear Overrun underrun */
+ − 6501 #define SAI_xCLRFR_CMUTEDET ((uint32_t)0x00000002) /*!<Clear Mute detection */
+ − 6502 #define SAI_xCLRFR_CWCKCFG ((uint32_t)0x00000004) /*!<Clear Wrong Clock Configuration */
+ − 6503 #define SAI_xCLRFR_CFREQ ((uint32_t)0x00000008) /*!<Clear FIFO request */
+ − 6504 #define SAI_xCLRFR_CCNRDY ((uint32_t)0x00000010) /*!<Clear Codec not ready */
+ − 6505 #define SAI_xCLRFR_CAFSDET ((uint32_t)0x00000020) /*!<Clear Anticipated frame synchronization detection */
+ − 6506 #define SAI_xCLRFR_CLFSDET ((uint32_t)0x00000040) /*!<Clear Late frame synchronization detection */
+ − 6507
+ − 6508 /****************** Bit definition for SAI_xDR register ******************/
+ − 6509 #define SAI_xDR_DATA ((uint32_t)0xFFFFFFFF)
+ − 6510
+ − 6511
+ − 6512 /******************************************************************************/
+ − 6513 /* */
+ − 6514 /* SD host Interface */
+ − 6515 /* */
+ − 6516 /******************************************************************************/
+ − 6517 /****************** Bit definition for SDIO_POWER register ******************/
+ − 6518 #define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+ − 6519 #define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!<Bit 0 */
+ − 6520 #define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!<Bit 1 */
+ − 6521
+ − 6522 /****************** Bit definition for SDIO_CLKCR register ******************/
+ − 6523 #define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!<Clock divide factor */
+ − 6524 #define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /*!<Clock enable bit */
+ − 6525 #define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /*!<Power saving configuration bit */
+ − 6526 #define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /*!<Clock divider bypass enable bit */
+ − 6527
+ − 6528 #define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+ − 6529 #define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!<Bit 0 */
+ − 6530 #define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!<Bit 1 */
+ − 6531
+ − 6532 #define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!<SDIO_CK dephasing selection bit */
+ − 6533 #define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!<HW Flow Control enable */
+ − 6534
+ − 6535 /******************* Bit definition for SDIO_ARG register *******************/
+ − 6536 #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
+ − 6537
+ − 6538 /******************* Bit definition for SDIO_CMD register *******************/
+ − 6539 #define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /*!<Command Index */
+ − 6540
+ − 6541 #define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
+ − 6542 #define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */
+ − 6543 #define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */
+ − 6544
+ − 6545 #define SDIO_CMD_WAITINT ((uint32_t)0x0100) /*!<CPSM Waits for Interrupt Request */
+ − 6546 #define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+ − 6547 #define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
+ − 6548 #define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!<SD I/O suspend command */
+ − 6549 #define SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) /*!<Enable CMD completion */
+ − 6550 #define SDIO_CMD_NIEN ((uint32_t)0x2000) /*!<Not Interrupt Enable */
+ − 6551 #define SDIO_CMD_CEATACMD ((uint32_t)0x4000) /*!<CE-ATA command */
+ − 6552
+ − 6553 /***************** Bit definition for SDIO_RESPCMD register *****************/
+ − 6554 #define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!<Response command index */
+ − 6555
+ − 6556 /****************** Bit definition for SDIO_RESP0 register ******************/
+ − 6557 #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+ − 6558
+ − 6559 /****************** Bit definition for SDIO_RESP1 register ******************/
+ − 6560 #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+ − 6561
+ − 6562 /****************** Bit definition for SDIO_RESP2 register ******************/
+ − 6563 #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+ − 6564
+ − 6565 /****************** Bit definition for SDIO_RESP3 register ******************/
+ − 6566 #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+ − 6567
+ − 6568 /****************** Bit definition for SDIO_RESP4 register ******************/
+ − 6569 #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+ − 6570
+ − 6571 /****************** Bit definition for SDIO_DTIMER register *****************/
+ − 6572 #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
+ − 6573
+ − 6574 /****************** Bit definition for SDIO_DLEN register *******************/
+ − 6575 #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
+ − 6576
+ − 6577 /****************** Bit definition for SDIO_DCTRL register ******************/
+ − 6578 #define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /*!<Data transfer enabled bit */
+ − 6579 #define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /*!<Data transfer direction selection */
+ − 6580 #define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /*!<Data transfer mode selection */
+ − 6581 #define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /*!<DMA enabled bit */
+ − 6582
+ − 6583 #define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+ − 6584 #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!<Bit 0 */
+ − 6585 #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!<Bit 1 */
+ − 6586 #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!<Bit 2 */
+ − 6587 #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!<Bit 3 */
+ − 6588
+ − 6589 #define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /*!<Read wait start */
+ − 6590 #define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /*!<Read wait stop */
+ − 6591 #define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /*!<Read wait mode */
+ − 6592 #define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /*!<SD I/O enable functions */
+ − 6593
+ − 6594 /****************** Bit definition for SDIO_DCOUNT register *****************/
+ − 6595 #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
+ − 6596
+ − 6597 /****************** Bit definition for SDIO_STA register ********************/
+ − 6598 #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
+ − 6599 #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
+ − 6600 #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
+ − 6601 #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
+ − 6602 #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
+ − 6603 #define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
+ − 6604 #define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
+ − 6605 #define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
+ − 6606 #define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
+ − 6607 #define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */
+ − 6608 #define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
+ − 6609 #define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
+ − 6610 #define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
+ − 6611 #define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
+ − 6612 #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+ − 6613 #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+ − 6614 #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
+ − 6615 #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
+ − 6616 #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
+ − 6617 #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
+ − 6618 #define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
+ − 6619 #define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
+ − 6620 #define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
+ − 6621 #define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */
+ − 6622
+ − 6623 /******************* Bit definition for SDIO_ICR register *******************/
+ − 6624 #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
+ − 6625 #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
+ − 6626 #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
+ − 6627 #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
+ − 6628 #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
+ − 6629 #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
+ − 6630 #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
+ − 6631 #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
+ − 6632 #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
+ − 6633 #define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */
+ − 6634 #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
+ − 6635 #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
+ − 6636 #define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */
+ − 6637
+ − 6638 /****************** Bit definition for SDIO_MASK register *******************/
+ − 6639 #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
+ − 6640 #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
+ − 6641 #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
+ − 6642 #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
+ − 6643 #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
+ − 6644 #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
+ − 6645 #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
+ − 6646 #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
+ − 6647 #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
+ − 6648 #define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */
+ − 6649 #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
+ − 6650 #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
+ − 6651 #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
+ − 6652 #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
+ − 6653 #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
+ − 6654 #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
+ − 6655 #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
+ − 6656 #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
+ − 6657 #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
+ − 6658 #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
+ − 6659 #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
+ − 6660 #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
+ − 6661 #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
+ − 6662 #define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */
+ − 6663
+ − 6664 /***************** Bit definition for SDIO_FIFOCNT register *****************/
+ − 6665 #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
+ − 6666
+ − 6667 /****************** Bit definition for SDIO_FIFO register *******************/
+ − 6668 #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
+ − 6669
+ − 6670 /******************************************************************************/
+ − 6671 /* */
+ − 6672 /* Serial Peripheral Interface */
+ − 6673 /* */
+ − 6674 /******************************************************************************/
+ − 6675 /******************* Bit definition for SPI_CR1 register ********************/
+ − 6676 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!<Clock Phase */
+ − 6677 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!<Clock Polarity */
+ − 6678 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!<Master Selection */
+ − 6679
+ − 6680 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!<BR[2:0] bits (Baud Rate Control) */
+ − 6681 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+ − 6682 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+ − 6683 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+ − 6684
+ − 6685 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!<SPI Enable */
+ − 6686 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!<Frame Format */
+ − 6687 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!<Internal slave select */
+ − 6688 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!<Software slave management */
+ − 6689 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!<Receive only */
+ − 6690 #define SPI_CR1_DFF ((uint32_t)0x00000800) /*!<Data Frame Format */
+ − 6691 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!<Transmit CRC next */
+ − 6692 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!<Hardware CRC calculation enable */
+ − 6693 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!<Output enable in bidirectional mode */
+ − 6694 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!<Bidirectional data mode enable */
+ − 6695
+ − 6696 /******************* Bit definition for SPI_CR2 register ********************/
+ − 6697 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!<Rx Buffer DMA Enable */
+ − 6698 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!<Tx Buffer DMA Enable */
+ − 6699 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!<SS Output Enable */
+ − 6700 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!<Frame Format */
+ − 6701 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!<Error Interrupt Enable */
+ − 6702 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!<RX buffer Not Empty Interrupt Enable */
+ − 6703 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!<Tx buffer Empty Interrupt Enable */
+ − 6704
+ − 6705 /******************** Bit definition for SPI_SR register ********************/
+ − 6706 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!<Receive buffer Not Empty */
+ − 6707 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!<Transmit buffer Empty */
+ − 6708 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!<Channel side */
+ − 6709 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!<Underrun flag */
+ − 6710 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!<CRC Error flag */
+ − 6711 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!<Mode fault */
+ − 6712 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!<Overrun flag */
+ − 6713 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!<Busy flag */
+ − 6714 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!<Frame format error flag */
+ − 6715
+ − 6716 /******************** Bit definition for SPI_DR register ********************/
+ − 6717 #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!<Data Register */
+ − 6718
+ − 6719 /******************* Bit definition for SPI_CRCPR register ******************/
+ − 6720 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!<CRC polynomial register */
+ − 6721
+ − 6722 /****************** Bit definition for SPI_RXCRCR register ******************/
+ − 6723 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!<Rx CRC Register */
+ − 6724
+ − 6725 /****************** Bit definition for SPI_TXCRCR register ******************/
+ − 6726 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!<Tx CRC Register */
+ − 6727
+ − 6728 /****************** Bit definition for SPI_I2SCFGR register *****************/
+ − 6729 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
+ − 6730
+ − 6731 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
+ − 6732 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
+ − 6733 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
+ − 6734
+ − 6735 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
+ − 6736
+ − 6737 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
+ − 6738 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+ − 6739 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+ − 6740
+ − 6741 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
+ − 6742
+ − 6743 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+ − 6744 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+ − 6745 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+ − 6746
+ − 6747 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
+ − 6748 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
+ − 6749
+ − 6750 /****************** Bit definition for SPI_I2SPR register *******************/
+ − 6751 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
+ − 6752 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
+ − 6753 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
+ − 6754
+ − 6755 /******************************************************************************/
+ − 6756 /* */
+ − 6757 /* SYSCFG */
+ − 6758 /* */
+ − 6759 /******************************************************************************/
+ − 6760 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
+ − 6761 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
+ − 6762 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
+ − 6763 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
+ − 6764 #define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
+ − 6765
+ − 6766 #define SYSCFG_MEMRMP_UFB_MODE ((uint32_t)0x00000100) /*!< User Flash Bank mode */
+ − 6767 #define SYSCFG_SWP_FMC ((uint32_t)0x00000C00) /*!< FMC memory mapping swap */
+ − 6768
+ − 6769 /****************** Bit definition for SYSCFG_PMC register ******************/
+ − 6770 #define SYSCFG_PMC_ADCxDC2 ((uint32_t)0x00070000) /*!< Refer to AN4073 on how to use this bit */
+ − 6771 #define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit */
+ − 6772 #define SYSCFG_PMC_ADC2DC2 ((uint32_t)0x00020000) /*!< Refer to AN4073 on how to use this bit */
+ − 6773 #define SYSCFG_PMC_ADC3DC2 ((uint32_t)0x00040000) /*!< Refer to AN4073 on how to use this bit */
+ − 6774
+ − 6775 #define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */
+ − 6776 /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
+ − 6777 #define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
+ − 6778
+ − 6779 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+ − 6780 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */
+ − 6781 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
+ − 6782 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
+ − 6783 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */
+ − 6784 /**
+ − 6785 * @brief EXTI0 configuration
+ − 6786 */
+ − 6787 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */
+ − 6788 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */
+ − 6789 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */
+ − 6790 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x0003) /*!<PD[0] pin */
+ − 6791 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x0004) /*!<PE[0] pin */
+ − 6792 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x0005) /*!<PF[0] pin */
+ − 6793 #define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x0006) /*!<PG[0] pin */
+ − 6794 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */
+ − 6795 #define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x0008) /*!<PI[0] pin */
+ − 6796 #define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x0009) /*!<PJ[0] pin */
+ − 6797 #define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x000A) /*!<PK[0] pin */
+ − 6798
+ − 6799 /**
+ − 6800 * @brief EXTI1 configuration
+ − 6801 */
+ − 6802 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */
+ − 6803 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */
+ − 6804 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */
+ − 6805 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x0030) /*!<PD[1] pin */
+ − 6806 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x0040) /*!<PE[1] pin */
+ − 6807 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x0050) /*!<PF[1] pin */
+ − 6808 #define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x0060) /*!<PG[1] pin */
+ − 6809 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */
+ − 6810 #define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x0080) /*!<PI[1] pin */
+ − 6811 #define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x0090) /*!<PJ[1] pin */
+ − 6812 #define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x00A0) /*!<PK[1] pin */
+ − 6813
+ − 6814
+ − 6815 /**
+ − 6816 * @brief EXTI2 configuration
+ − 6817 */
+ − 6818 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */
+ − 6819 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */
+ − 6820 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */
+ − 6821 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x0300) /*!<PD[2] pin */
+ − 6822 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x0400) /*!<PE[2] pin */
+ − 6823 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x0500) /*!<PF[2] pin */
+ − 6824 #define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x0600) /*!<PG[2] pin */
+ − 6825 #define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */
+ − 6826 #define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x0800) /*!<PI[2] pin */
+ − 6827 #define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x0900) /*!<PJ[2] pin */
+ − 6828 #define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x0A00) /*!<PK[2] pin */
+ − 6829
+ − 6830
+ − 6831 /**
+ − 6832 * @brief EXTI3 configuration
+ − 6833 */
+ − 6834 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */
+ − 6835 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */
+ − 6836 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */
+ − 6837 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x3000) /*!<PD[3] pin */
+ − 6838 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x4000) /*!<PE[3] pin */
+ − 6839 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x5000) /*!<PF[3] pin */
+ − 6840 #define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x6000) /*!<PG[3] pin */
+ − 6841 #define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */
+ − 6842 #define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x8000) /*!<PI[3] pin */
+ − 6843 #define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x9000) /*!<PJ[3] pin */
+ − 6844 #define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0xA000) /*!<PK[3] pin */
+ − 6845
+ − 6846
+ − 6847 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+ − 6848 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */
+ − 6849 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
+ − 6850 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
+ − 6851 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */
+ − 6852 /**
+ − 6853 * @brief EXTI4 configuration
+ − 6854 */
+ − 6855 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */
+ − 6856 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */
+ − 6857 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */
+ − 6858 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x0003) /*!<PD[4] pin */
+ − 6859 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x0004) /*!<PE[4] pin */
+ − 6860 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x0005) /*!<PF[4] pin */
+ − 6861 #define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x0006) /*!<PG[4] pin */
+ − 6862 #define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */
+ − 6863 #define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x0008) /*!<PI[4] pin */
+ − 6864 #define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x0009) /*!<PJ[4] pin */
+ − 6865 #define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x000A) /*!<PK[4] pin */
+ − 6866
+ − 6867 /**
+ − 6868 * @brief EXTI5 configuration
+ − 6869 */
+ − 6870 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */
+ − 6871 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */
+ − 6872 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */
+ − 6873 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x0030) /*!<PD[5] pin */
+ − 6874 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x0040) /*!<PE[5] pin */
+ − 6875 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x0050) /*!<PF[5] pin */
+ − 6876 #define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x0060) /*!<PG[5] pin */
+ − 6877 #define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */
+ − 6878 #define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x0080) /*!<PI[5] pin */
+ − 6879 #define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x0090) /*!<PJ[5] pin */
+ − 6880 #define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x00A0) /*!<PK[5] pin */
+ − 6881
+ − 6882 /**
+ − 6883 * @brief EXTI6 configuration
+ − 6884 */
+ − 6885 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */
+ − 6886 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */
+ − 6887 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */
+ − 6888 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x0300) /*!<PD[6] pin */
+ − 6889 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x0400) /*!<PE[6] pin */
+ − 6890 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x0500) /*!<PF[6] pin */
+ − 6891 #define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x0600) /*!<PG[6] pin */
+ − 6892 #define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */
+ − 6893 #define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x0800) /*!<PI[6] pin */
+ − 6894 #define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x0900) /*!<PJ[6] pin */
+ − 6895 #define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x0A00) /*!<PK[6] pin */
+ − 6896
+ − 6897
+ − 6898 /**
+ − 6899 * @brief EXTI7 configuration
+ − 6900 */
+ − 6901 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */
+ − 6902 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */
+ − 6903 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */
+ − 6904 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x3000) /*!<PD[7] pin */
+ − 6905 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x4000) /*!<PE[7] pin */
+ − 6906 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x5000) /*!<PF[7] pin */
+ − 6907 #define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x6000) /*!<PG[7] pin */
+ − 6908 #define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */
+ − 6909 #define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x8000) /*!<PI[7] pin */
+ − 6910 #define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x9000) /*!<PJ[7] pin */
+ − 6911 #define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0xA000) /*!<PK[7] pin */
+ − 6912
+ − 6913 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+ − 6914 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */
+ − 6915 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
+ − 6916 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
+ − 6917 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */
+ − 6918
+ − 6919 /**
+ − 6920 * @brief EXTI8 configuration
+ − 6921 */
+ − 6922 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */
+ − 6923 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */
+ − 6924 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */
+ − 6925 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x0003) /*!<PD[8] pin */
+ − 6926 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x0004) /*!<PE[8] pin */
+ − 6927 #define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x0005) /*!<PF[8] pin */
+ − 6928 #define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x0006) /*!<PG[8] pin */
+ − 6929 #define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */
+ − 6930 #define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x0008) /*!<PI[8] pin */
+ − 6931 #define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x0009) /*!<PJ[8] pin */
+ − 6932
+ − 6933 /**
+ − 6934 * @brief EXTI9 configuration
+ − 6935 */
+ − 6936 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */
+ − 6937 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */
+ − 6938 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */
+ − 6939 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x0030) /*!<PD[9] pin */
+ − 6940 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x0040) /*!<PE[9] pin */
+ − 6941 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x0050) /*!<PF[9] pin */
+ − 6942 #define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x0060) /*!<PG[9] pin */
+ − 6943 #define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */
+ − 6944 #define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x0080) /*!<PI[9] pin */
+ − 6945 #define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x0090) /*!<PJ[9] pin */
+ − 6946
+ − 6947
+ − 6948 /**
+ − 6949 * @brief EXTI10 configuration
+ − 6950 */
+ − 6951 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */
+ − 6952 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */
+ − 6953 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */
+ − 6954 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x0300) /*!<PD[10] pin */
+ − 6955 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x0400) /*!<PE[10] pin */
+ − 6956 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x0500) /*!<PF[10] pin */
+ − 6957 #define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x0600) /*!<PG[10] pin */
+ − 6958 #define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */
+ − 6959 #define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x0800) /*!<PI[10] pin */
+ − 6960 #define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x0900) /*!<PJ[10] pin */
+ − 6961
+ − 6962
+ − 6963 /**
+ − 6964 * @brief EXTI11 configuration
+ − 6965 */
+ − 6966 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */
+ − 6967 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */
+ − 6968 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */
+ − 6969 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x3000) /*!<PD[11] pin */
+ − 6970 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x4000) /*!<PE[11] pin */
+ − 6971 #define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x5000) /*!<PF[11] pin */
+ − 6972 #define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x6000) /*!<PG[11] pin */
+ − 6973 #define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */
+ − 6974 #define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x8000) /*!<PI[11] pin */
+ − 6975 #define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x9000) /*!<PJ[11] pin */
+ − 6976
+ − 6977
+ − 6978 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+ − 6979 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */
+ − 6980 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
+ − 6981 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
+ − 6982 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */
+ − 6983 /**
+ − 6984 * @brief EXTI12 configuration
+ − 6985 */
+ − 6986 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */
+ − 6987 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */
+ − 6988 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */
+ − 6989 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x0003) /*!<PD[12] pin */
+ − 6990 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x0004) /*!<PE[12] pin */
+ − 6991 #define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x0005) /*!<PF[12] pin */
+ − 6992 #define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x0006) /*!<PG[12] pin */
+ − 6993 #define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */
+ − 6994 #define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x0008) /*!<PI[12] pin */
+ − 6995 #define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x0009) /*!<PJ[12] pin */
+ − 6996
+ − 6997
+ − 6998 /**
+ − 6999 * @brief EXTI13 configuration
+ − 7000 */
+ − 7001 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */
+ − 7002 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */
+ − 7003 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */
+ − 7004 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x0030) /*!<PD[13] pin */
+ − 7005 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x0040) /*!<PE[13] pin */
+ − 7006 #define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x0050) /*!<PF[13] pin */
+ − 7007 #define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x0060) /*!<PG[13] pin */
+ − 7008 #define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */
+ − 7009 #define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x0008) /*!<PI[13] pin */
+ − 7010 #define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x0009) /*!<PJ[13] pin */
+ − 7011
+ − 7012
+ − 7013 /**
+ − 7014 * @brief EXTI14 configuration
+ − 7015 */
+ − 7016 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */
+ − 7017 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */
+ − 7018 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */
+ − 7019 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x0300) /*!<PD[14] pin */
+ − 7020 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x0400) /*!<PE[14] pin */
+ − 7021 #define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x0500) /*!<PF[14] pin */
+ − 7022 #define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x0600) /*!<PG[14] pin */
+ − 7023 #define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */
+ − 7024 #define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x0800) /*!<PI[14] pin */
+ − 7025 #define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x0900) /*!<PJ[14] pin */
+ − 7026
+ − 7027
+ − 7028 /**
+ − 7029 * @brief EXTI15 configuration
+ − 7030 */
+ − 7031 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */
+ − 7032 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */
+ − 7033 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */
+ − 7034 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x3000) /*!<PD[15] pin */
+ − 7035 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x4000) /*!<PE[15] pin */
+ − 7036 #define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x5000) /*!<PF[15] pin */
+ − 7037 #define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x6000) /*!<PG[15] pin */
+ − 7038 #define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */
+ − 7039 #define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x8000) /*!<PI[15] pin */
+ − 7040 #define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x9000) /*!<PJ[15] pin */
+ − 7041
+ − 7042 /****************** Bit definition for SYSCFG_CMPCR register ****************/
+ − 7043 #define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
+ − 7044 #define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */
+ − 7045
+ − 7046 /******************************************************************************/
+ − 7047 /* */
+ − 7048 /* TIM */
+ − 7049 /* */
+ − 7050 /******************************************************************************/
+ − 7051 /******************* Bit definition for TIM_CR1 register ********************/
+ − 7052 #define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */
+ − 7053 #define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */
+ − 7054 #define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */
+ − 7055 #define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */
+ − 7056 #define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */
+ − 7057
+ − 7058 #define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
+ − 7059 #define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */
+ − 7060 #define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */
+ − 7061
+ − 7062 #define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */
+ − 7063
+ − 7064 #define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */
+ − 7065 #define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */
+ − 7066 #define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */
+ − 7067
+ − 7068 /******************* Bit definition for TIM_CR2 register ********************/
+ − 7069 #define TIM_CR2_CCPC ((uint32_t)0x0001) /*!<Capture/Compare Preloaded Control */
+ − 7070 #define TIM_CR2_CCUS ((uint32_t)0x0004) /*!<Capture/Compare Control Update Selection */
+ − 7071 #define TIM_CR2_CCDS ((uint32_t)0x0008) /*!<Capture/Compare DMA Selection */
+ − 7072
+ − 7073 #define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
+ − 7074 #define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */
+ − 7075 #define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */
+ − 7076 #define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */
+ − 7077
+ − 7078 #define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */
+ − 7079 #define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
+ − 7080 #define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
+ − 7081 #define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
+ − 7082 #define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
+ − 7083 #define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
+ − 7084 #define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
+ − 7085 #define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
+ − 7086
+ − 7087 /******************* Bit definition for TIM_SMCR register *******************/
+ − 7088 #define TIM_SMCR_SMS ((uint32_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
+ − 7089 #define TIM_SMCR_SMS_0 ((uint32_t)0x0001) /*!<Bit 0 */
+ − 7090 #define TIM_SMCR_SMS_1 ((uint32_t)0x0002) /*!<Bit 1 */
+ − 7091 #define TIM_SMCR_SMS_2 ((uint32_t)0x0004) /*!<Bit 2 */
+ − 7092
+ − 7093 #define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
+ − 7094 #define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */
+ − 7095 #define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */
+ − 7096 #define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */
+ − 7097
+ − 7098 #define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */
+ − 7099
+ − 7100 #define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
+ − 7101 #define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */
+ − 7102 #define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */
+ − 7103 #define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */
+ − 7104 #define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */
+ − 7105
+ − 7106 #define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
+ − 7107 #define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */
+ − 7108 #define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */
+ − 7109
+ − 7110 #define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */
+ − 7111 #define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */
+ − 7112
+ − 7113 /******************* Bit definition for TIM_DIER register *******************/
+ − 7114 #define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */
+ − 7115 #define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
+ − 7116 #define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
+ − 7117 #define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
+ − 7118 #define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
+ − 7119 #define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */
+ − 7120 #define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */
+ − 7121 #define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */
+ − 7122 #define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */
+ − 7123 #define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
+ − 7124 #define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
+ − 7125 #define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
+ − 7126 #define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
+ − 7127 #define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */
+ − 7128 #define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */
+ − 7129
+ − 7130 /******************** Bit definition for TIM_SR register ********************/
+ − 7131 #define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */
+ − 7132 #define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
+ − 7133 #define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
+ − 7134 #define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
+ − 7135 #define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
+ − 7136 #define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */
+ − 7137 #define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */
+ − 7138 #define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */
+ − 7139 #define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
+ − 7140 #define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
+ − 7141 #define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
+ − 7142 #define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
+ − 7143
+ − 7144 /******************* Bit definition for TIM_EGR register ********************/
+ − 7145 #define TIM_EGR_UG ((uint32_t)0x01) /*!<Update Generation */
+ − 7146 #define TIM_EGR_CC1G ((uint32_t)0x02) /*!<Capture/Compare 1 Generation */
+ − 7147 #define TIM_EGR_CC2G ((uint32_t)0x04) /*!<Capture/Compare 2 Generation */
+ − 7148 #define TIM_EGR_CC3G ((uint32_t)0x08) /*!<Capture/Compare 3 Generation */
+ − 7149 #define TIM_EGR_CC4G ((uint32_t)0x10) /*!<Capture/Compare 4 Generation */
+ − 7150 #define TIM_EGR_COMG ((uint32_t)0x20) /*!<Capture/Compare Control Update Generation */
+ − 7151 #define TIM_EGR_TG ((uint32_t)0x40) /*!<Trigger Generation */
+ − 7152 #define TIM_EGR_BG ((uint32_t)0x80) /*!<Break Generation */
+ − 7153
+ − 7154 /****************** Bit definition for TIM_CCMR1 register *******************/
+ − 7155 #define TIM_CCMR1_CC1S ((uint32_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+ − 7156 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x0001) /*!<Bit 0 */
+ − 7157 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x0002) /*!<Bit 1 */
+ − 7158
+ − 7159 #define TIM_CCMR1_OC1FE ((uint32_t)0x0004) /*!<Output Compare 1 Fast enable */
+ − 7160 #define TIM_CCMR1_OC1PE ((uint32_t)0x0008) /*!<Output Compare 1 Preload enable */
+ − 7161
+ − 7162 #define TIM_CCMR1_OC1M ((uint32_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+ − 7163 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x0010) /*!<Bit 0 */
+ − 7164 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x0020) /*!<Bit 1 */
+ − 7165 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x0040) /*!<Bit 2 */
+ − 7166
+ − 7167 #define TIM_CCMR1_OC1CE ((uint32_t)0x0080) /*!<Output Compare 1Clear Enable */
+ − 7168
+ − 7169 #define TIM_CCMR1_CC2S ((uint32_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+ − 7170 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x0100) /*!<Bit 0 */
+ − 7171 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x0200) /*!<Bit 1 */
+ − 7172
+ − 7173 #define TIM_CCMR1_OC2FE ((uint32_t)0x0400) /*!<Output Compare 2 Fast enable */
+ − 7174 #define TIM_CCMR1_OC2PE ((uint32_t)0x0800) /*!<Output Compare 2 Preload enable */
+ − 7175
+ − 7176 #define TIM_CCMR1_OC2M ((uint32_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+ − 7177 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x1000) /*!<Bit 0 */
+ − 7178 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x2000) /*!<Bit 1 */
+ − 7179 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x4000) /*!<Bit 2 */
+ − 7180
+ − 7181 #define TIM_CCMR1_OC2CE ((uint32_t)0x8000) /*!<Output Compare 2 Clear Enable */
+ − 7182
+ − 7183 /*----------------------------------------------------------------------------*/
+ − 7184
+ − 7185 #define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+ − 7186 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
+ − 7187 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
+ − 7188
+ − 7189 #define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+ − 7190 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */
+ − 7191 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */
+ − 7192 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */
+ − 7193 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */
+ − 7194
+ − 7195 #define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+ − 7196 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
+ − 7197 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
+ − 7198
+ − 7199 #define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+ − 7200 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */
+ − 7201 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */
+ − 7202 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */
+ − 7203 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */
+ − 7204
+ − 7205 /****************** Bit definition for TIM_CCMR2 register *******************/
+ − 7206 #define TIM_CCMR2_CC3S ((uint32_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+ − 7207 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x0001) /*!<Bit 0 */
+ − 7208 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x0002) /*!<Bit 1 */
+ − 7209
+ − 7210 #define TIM_CCMR2_OC3FE ((uint32_t)0x0004) /*!<Output Compare 3 Fast enable */
+ − 7211 #define TIM_CCMR2_OC3PE ((uint32_t)0x0008) /*!<Output Compare 3 Preload enable */
+ − 7212
+ − 7213 #define TIM_CCMR2_OC3M ((uint32_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+ − 7214 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x0010) /*!<Bit 0 */
+ − 7215 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x0020) /*!<Bit 1 */
+ − 7216 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x0040) /*!<Bit 2 */
+ − 7217
+ − 7218 #define TIM_CCMR2_OC3CE ((uint32_t)0x0080) /*!<Output Compare 3 Clear Enable */
+ − 7219
+ − 7220 #define TIM_CCMR2_CC4S ((uint32_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+ − 7221 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x0100) /*!<Bit 0 */
+ − 7222 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x0200) /*!<Bit 1 */
+ − 7223
+ − 7224 #define TIM_CCMR2_OC4FE ((uint32_t)0x0400) /*!<Output Compare 4 Fast enable */
+ − 7225 #define TIM_CCMR2_OC4PE ((uint32_t)0x0800) /*!<Output Compare 4 Preload enable */
+ − 7226
+ − 7227 #define TIM_CCMR2_OC4M ((uint32_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+ − 7228 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x1000) /*!<Bit 0 */
+ − 7229 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x2000) /*!<Bit 1 */
+ − 7230 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x4000) /*!<Bit 2 */
+ − 7231
+ − 7232 #define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */
+ − 7233
+ − 7234 /*----------------------------------------------------------------------------*/
+ − 7235
+ − 7236 #define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+ − 7237 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
+ − 7238 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
+ − 7239
+ − 7240 #define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+ − 7241 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */
+ − 7242 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */
+ − 7243 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */
+ − 7244 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */
+ − 7245
+ − 7246 #define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+ − 7247 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
+ − 7248 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
+ − 7249
+ − 7250 #define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+ − 7251 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */
+ − 7252 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */
+ − 7253 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */
+ − 7254 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */
+ − 7255
+ − 7256 /******************* Bit definition for TIM_CCER register *******************/
+ − 7257 #define TIM_CCER_CC1E ((uint32_t)0x0001) /*!<Capture/Compare 1 output enable */
+ − 7258 #define TIM_CCER_CC1P ((uint32_t)0x0002) /*!<Capture/Compare 1 output Polarity */
+ − 7259 #define TIM_CCER_CC1NE ((uint32_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
+ − 7260 #define TIM_CCER_CC1NP ((uint32_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
+ − 7261 #define TIM_CCER_CC2E ((uint32_t)0x0010) /*!<Capture/Compare 2 output enable */
+ − 7262 #define TIM_CCER_CC2P ((uint32_t)0x0020) /*!<Capture/Compare 2 output Polarity */
+ − 7263 #define TIM_CCER_CC2NE ((uint32_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
+ − 7264 #define TIM_CCER_CC2NP ((uint32_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
+ − 7265 #define TIM_CCER_CC3E ((uint32_t)0x0100) /*!<Capture/Compare 3 output enable */
+ − 7266 #define TIM_CCER_CC3P ((uint32_t)0x0200) /*!<Capture/Compare 3 output Polarity */
+ − 7267 #define TIM_CCER_CC3NE ((uint32_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
+ − 7268 #define TIM_CCER_CC3NP ((uint32_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
+ − 7269 #define TIM_CCER_CC4E ((uint32_t)0x1000) /*!<Capture/Compare 4 output enable */
+ − 7270 #define TIM_CCER_CC4P ((uint32_t)0x2000) /*!<Capture/Compare 4 output Polarity */
+ − 7271 #define TIM_CCER_CC4NP ((uint32_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
+ − 7272
+ − 7273 /******************* Bit definition for TIM_CNT register ********************/
+ − 7274 #define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */
+ − 7275
+ − 7276 /******************* Bit definition for TIM_PSC register ********************/
+ − 7277 #define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */
+ − 7278
+ − 7279 /******************* Bit definition for TIM_ARR register ********************/
+ − 7280 #define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */
+ − 7281
+ − 7282 /******************* Bit definition for TIM_RCR register ********************/
+ − 7283 #define TIM_RCR_REP ((uint32_t)0xFF) /*!<Repetition Counter Value */
+ − 7284
+ − 7285 /******************* Bit definition for TIM_CCR1 register *******************/
+ − 7286 #define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */
+ − 7287
+ − 7288 /******************* Bit definition for TIM_CCR2 register *******************/
+ − 7289 #define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */
+ − 7290
+ − 7291 /******************* Bit definition for TIM_CCR3 register *******************/
+ − 7292 #define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */
+ − 7293
+ − 7294 /******************* Bit definition for TIM_CCR4 register *******************/
+ − 7295 #define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */
+ − 7296
+ − 7297 /******************* Bit definition for TIM_BDTR register *******************/
+ − 7298 #define TIM_BDTR_DTG ((uint32_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+ − 7299 #define TIM_BDTR_DTG_0 ((uint32_t)0x0001) /*!<Bit 0 */
+ − 7300 #define TIM_BDTR_DTG_1 ((uint32_t)0x0002) /*!<Bit 1 */
+ − 7301 #define TIM_BDTR_DTG_2 ((uint32_t)0x0004) /*!<Bit 2 */
+ − 7302 #define TIM_BDTR_DTG_3 ((uint32_t)0x0008) /*!<Bit 3 */
+ − 7303 #define TIM_BDTR_DTG_4 ((uint32_t)0x0010) /*!<Bit 4 */
+ − 7304 #define TIM_BDTR_DTG_5 ((uint32_t)0x0020) /*!<Bit 5 */
+ − 7305 #define TIM_BDTR_DTG_6 ((uint32_t)0x0040) /*!<Bit 6 */
+ − 7306 #define TIM_BDTR_DTG_7 ((uint32_t)0x0080) /*!<Bit 7 */
+ − 7307
+ − 7308 #define TIM_BDTR_LOCK ((uint32_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
+ − 7309 #define TIM_BDTR_LOCK_0 ((uint32_t)0x0100) /*!<Bit 0 */
+ − 7310 #define TIM_BDTR_LOCK_1 ((uint32_t)0x0200) /*!<Bit 1 */
+ − 7311
+ − 7312 #define TIM_BDTR_OSSI ((uint32_t)0x0400) /*!<Off-State Selection for Idle mode */
+ − 7313 #define TIM_BDTR_OSSR ((uint32_t)0x0800) /*!<Off-State Selection for Run mode */
+ − 7314 #define TIM_BDTR_BKE ((uint32_t)0x1000) /*!<Break enable */
+ − 7315 #define TIM_BDTR_BKP ((uint32_t)0x2000) /*!<Break Polarity */
+ − 7316 #define TIM_BDTR_AOE ((uint32_t)0x4000) /*!<Automatic Output enable */
+ − 7317 #define TIM_BDTR_MOE ((uint32_t)0x8000) /*!<Main Output enable */
+ − 7318
+ − 7319 /******************* Bit definition for TIM_DCR register ********************/
+ − 7320 #define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
+ − 7321 #define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */
+ − 7322 #define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */
+ − 7323 #define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */
+ − 7324 #define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */
+ − 7325 #define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */
+ − 7326
+ − 7327 #define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
+ − 7328 #define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */
+ − 7329 #define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */
+ − 7330 #define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */
+ − 7331 #define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */
+ − 7332 #define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */
+ − 7333
+ − 7334 /******************* Bit definition for TIM_DMAR register *******************/
+ − 7335 #define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */
+ − 7336
+ − 7337 /******************* Bit definition for TIM_OR register *********************/
+ − 7338 #define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+ − 7339 #define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */
+ − 7340 #define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */
+ − 7341 #define TIM_OR_ITR1_RMP ((uint32_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+ − 7342 #define TIM_OR_ITR1_RMP_0 ((uint32_t)0x0400) /*!<Bit 0 */
+ − 7343 #define TIM_OR_ITR1_RMP_1 ((uint32_t)0x0800) /*!<Bit 1 */
+ − 7344
+ − 7345
+ − 7346 /******************************************************************************/
+ − 7347 /* */
+ − 7348 /* Universal Synchronous Asynchronous Receiver Transmitter */
+ − 7349 /* */
+ − 7350 /******************************************************************************/
+ − 7351 /******************* Bit definition for USART_SR register *******************/
+ − 7352 #define USART_SR_PE ((uint32_t)0x0001) /*!<Parity Error */
+ − 7353 #define USART_SR_FE ((uint32_t)0x0002) /*!<Framing Error */
+ − 7354 #define USART_SR_NE ((uint32_t)0x0004) /*!<Noise Error Flag */
+ − 7355 #define USART_SR_ORE ((uint32_t)0x0008) /*!<OverRun Error */
+ − 7356 #define USART_SR_IDLE ((uint32_t)0x0010) /*!<IDLE line detected */
+ − 7357 #define USART_SR_RXNE ((uint32_t)0x0020) /*!<Read Data Register Not Empty */
+ − 7358 #define USART_SR_TC ((uint32_t)0x0040) /*!<Transmission Complete */
+ − 7359 #define USART_SR_TXE ((uint32_t)0x0080) /*!<Transmit Data Register Empty */
+ − 7360 #define USART_SR_LBD ((uint32_t)0x0100) /*!<LIN Break Detection Flag */
+ − 7361 #define USART_SR_CTS ((uint32_t)0x0200) /*!<CTS Flag */
+ − 7362
+ − 7363 /******************* Bit definition for USART_DR register *******************/
+ − 7364 #define USART_DR_DR ((uint32_t)0x01FF) /*!<Data value */
+ − 7365
+ − 7366 /****************** Bit definition for USART_BRR register *******************/
+ − 7367 #define USART_BRR_DIV_Fraction ((uint32_t)0x000F) /*!<Fraction of USARTDIV */
+ − 7368 #define USART_BRR_DIV_Mantissa ((uint32_t)0xFFF0) /*!<Mantissa of USARTDIV */
+ − 7369
+ − 7370 /****************** Bit definition for USART_CR1 register *******************/
+ − 7371 #define USART_CR1_SBK ((uint32_t)0x0001) /*!<Send Break */
+ − 7372 #define USART_CR1_RWU ((uint32_t)0x0002) /*!<Receiver wakeup */
+ − 7373 #define USART_CR1_RE ((uint32_t)0x0004) /*!<Receiver Enable */
+ − 7374 #define USART_CR1_TE ((uint32_t)0x0008) /*!<Transmitter Enable */
+ − 7375 #define USART_CR1_IDLEIE ((uint32_t)0x0010) /*!<IDLE Interrupt Enable */
+ − 7376 #define USART_CR1_RXNEIE ((uint32_t)0x0020) /*!<RXNE Interrupt Enable */
+ − 7377 #define USART_CR1_TCIE ((uint32_t)0x0040) /*!<Transmission Complete Interrupt Enable */
+ − 7378 #define USART_CR1_TXEIE ((uint32_t)0x0080) /*!<PE Interrupt Enable */
+ − 7379 #define USART_CR1_PEIE ((uint32_t)0x0100) /*!<PE Interrupt Enable */
+ − 7380 #define USART_CR1_PS ((uint32_t)0x0200) /*!<Parity Selection */
+ − 7381 #define USART_CR1_PCE ((uint32_t)0x0400) /*!<Parity Control Enable */
+ − 7382 #define USART_CR1_WAKE ((uint32_t)0x0800) /*!<Wakeup method */
+ − 7383 #define USART_CR1_M ((uint32_t)0x1000) /*!<Word length */
+ − 7384 #define USART_CR1_UE ((uint32_t)0x2000) /*!<USART Enable */
+ − 7385 #define USART_CR1_OVER8 ((uint32_t)0x8000) /*!<USART Oversampling by 8 enable */
+ − 7386
+ − 7387 /****************** Bit definition for USART_CR2 register *******************/
+ − 7388 #define USART_CR2_ADD ((uint32_t)0x000F) /*!<Address of the USART node */
+ − 7389 #define USART_CR2_LBDL ((uint32_t)0x0020) /*!<LIN Break Detection Length */
+ − 7390 #define USART_CR2_LBDIE ((uint32_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
+ − 7391 #define USART_CR2_LBCL ((uint32_t)0x0100) /*!<Last Bit Clock pulse */
+ − 7392 #define USART_CR2_CPHA ((uint32_t)0x0200) /*!<Clock Phase */
+ − 7393 #define USART_CR2_CPOL ((uint32_t)0x0400) /*!<Clock Polarity */
+ − 7394 #define USART_CR2_CLKEN ((uint32_t)0x0800) /*!<Clock Enable */
+ − 7395
+ − 7396 #define USART_CR2_STOP ((uint32_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
+ − 7397 #define USART_CR2_STOP_0 ((uint32_t)0x1000) /*!<Bit 0 */
+ − 7398 #define USART_CR2_STOP_1 ((uint32_t)0x2000) /*!<Bit 1 */
+ − 7399
+ − 7400 #define USART_CR2_LINEN ((uint32_t)0x4000) /*!<LIN mode enable */
+ − 7401
+ − 7402 /****************** Bit definition for USART_CR3 register *******************/
+ − 7403 #define USART_CR3_EIE ((uint32_t)0x0001) /*!<Error Interrupt Enable */
+ − 7404 #define USART_CR3_IREN ((uint32_t)0x0002) /*!<IrDA mode Enable */
+ − 7405 #define USART_CR3_IRLP ((uint32_t)0x0004) /*!<IrDA Low-Power */
+ − 7406 #define USART_CR3_HDSEL ((uint32_t)0x0008) /*!<Half-Duplex Selection */
+ − 7407 #define USART_CR3_NACK ((uint32_t)0x0010) /*!<Smartcard NACK enable */
+ − 7408 #define USART_CR3_SCEN ((uint32_t)0x0020) /*!<Smartcard mode enable */
+ − 7409 #define USART_CR3_DMAR ((uint32_t)0x0040) /*!<DMA Enable Receiver */
+ − 7410 #define USART_CR3_DMAT ((uint32_t)0x0080) /*!<DMA Enable Transmitter */
+ − 7411 #define USART_CR3_RTSE ((uint32_t)0x0100) /*!<RTS Enable */
+ − 7412 #define USART_CR3_CTSE ((uint32_t)0x0200) /*!<CTS Enable */
+ − 7413 #define USART_CR3_CTSIE ((uint32_t)0x0400) /*!<CTS Interrupt Enable */
+ − 7414 #define USART_CR3_ONEBIT ((uint32_t)0x0800) /*!<USART One bit method enable */
+ − 7415
+ − 7416 /****************** Bit definition for USART_GTPR register ******************/
+ − 7417 #define USART_GTPR_PSC ((uint32_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
+ − 7418 #define USART_GTPR_PSC_0 ((uint32_t)0x0001) /*!<Bit 0 */
+ − 7419 #define USART_GTPR_PSC_1 ((uint32_t)0x0002) /*!<Bit 1 */
+ − 7420 #define USART_GTPR_PSC_2 ((uint32_t)0x0004) /*!<Bit 2 */
+ − 7421 #define USART_GTPR_PSC_3 ((uint32_t)0x0008) /*!<Bit 3 */
+ − 7422 #define USART_GTPR_PSC_4 ((uint32_t)0x0010) /*!<Bit 4 */
+ − 7423 #define USART_GTPR_PSC_5 ((uint32_t)0x0020) /*!<Bit 5 */
+ − 7424 #define USART_GTPR_PSC_6 ((uint32_t)0x0040) /*!<Bit 6 */
+ − 7425 #define USART_GTPR_PSC_7 ((uint32_t)0x0080) /*!<Bit 7 */
+ − 7426
+ − 7427 #define USART_GTPR_GT ((uint32_t)0xFF00) /*!<Guard time value */
+ − 7428
+ − 7429 /******************************************************************************/
+ − 7430 /* */
+ − 7431 /* Window WATCHDOG */
+ − 7432 /* */
+ − 7433 /******************************************************************************/
+ − 7434 /******************* Bit definition for WWDG_CR register ********************/
+ − 7435 #define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+ − 7436 #define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
+ − 7437 #define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
+ − 7438 #define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
+ − 7439 #define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
+ − 7440 #define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
+ − 7441 #define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
+ − 7442 #define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
+ − 7443
+ − 7444 #define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
+ − 7445
+ − 7446 /******************* Bit definition for WWDG_CFR register *******************/
+ − 7447 #define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
+ − 7448 #define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
+ − 7449 #define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
+ − 7450 #define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
+ − 7451 #define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
+ − 7452 #define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
+ − 7453 #define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
+ − 7454 #define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
+ − 7455
+ − 7456 #define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
+ − 7457 #define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
+ − 7458 #define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
+ − 7459
+ − 7460 #define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
+ − 7461
+ − 7462 /******************* Bit definition for WWDG_SR register ********************/
+ − 7463 #define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
+ − 7464
+ − 7465
+ − 7466 /******************************************************************************/
+ − 7467 /* */
+ − 7468 /* DBG */
+ − 7469 /* */
+ − 7470 /******************************************************************************/
+ − 7471 /******************** Bit definition for DBGMCU_IDCODE register *************/
+ − 7472 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
+ − 7473 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
+ − 7474
+ − 7475 /******************** Bit definition for DBGMCU_CR register *****************/
+ − 7476 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
+ − 7477 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
+ − 7478 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
+ − 7479 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
+ − 7480
+ − 7481 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
+ − 7482 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
+ − 7483 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
+ − 7484
+ − 7485 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
+ − 7486 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
+ − 7487 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
+ − 7488 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
+ − 7489 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
+ − 7490 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
+ − 7491 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
+ − 7492 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
+ − 7493 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
+ − 7494 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
+ − 7495 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
+ − 7496 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
+ − 7497 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
+ − 7498 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
+ − 7499 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
+ − 7500 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
+ − 7501 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
+ − 7502 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
+ − 7503 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
+ − 7504 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
+ − 7505
+ − 7506 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
+ − 7507 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
+ − 7508 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
+ − 7509 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
+ − 7510 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
+ − 7511 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
+ − 7512
+ − 7513 /******************************************************************************/
+ − 7514 /* */
+ − 7515 /* Ethernet MAC Registers bits definitions */
+ − 7516 /* */
+ − 7517 /******************************************************************************/
+ − 7518 /* Bit definition for Ethernet MAC Control Register register */
+ − 7519 #define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
+ − 7520 #define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
+ − 7521 #define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
+ − 7522 #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
+ − 7523 #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
+ − 7524 #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
+ − 7525 #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
+ − 7526 #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
+ − 7527 #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
+ − 7528 #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
+ − 7529 #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
+ − 7530 #define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
+ − 7531 #define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
+ − 7532 #define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
+ − 7533 #define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
+ − 7534 #define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
+ − 7535 #define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
+ − 7536 #define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
+ − 7537 #define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
+ − 7538 #define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
+ − 7539 a transmission attempt during retries after a collision: 0 =< r <2^k */
+ − 7540 #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
+ − 7541 #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
+ − 7542 #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
+ − 7543 #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
+ − 7544 #define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
+ − 7545 #define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
+ − 7546 #define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
+ − 7547
+ − 7548 /* Bit definition for Ethernet MAC Frame Filter Register */
+ − 7549 #define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
+ − 7550 #define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
+ − 7551 #define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
+ − 7552 #define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
+ − 7553 #define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
+ − 7554 #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
+ − 7555 #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
+ − 7556 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
+ − 7557 #define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
+ − 7558 #define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
+ − 7559 #define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
+ − 7560 #define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
+ − 7561 #define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
+ − 7562 #define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
+ − 7563
+ − 7564 /* Bit definition for Ethernet MAC Hash Table High Register */
+ − 7565 #define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
+ − 7566
+ − 7567 /* Bit definition for Ethernet MAC Hash Table Low Register */
+ − 7568 #define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
+ − 7569
+ − 7570 /* Bit definition for Ethernet MAC MII Address Register */
+ − 7571 #define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
+ − 7572 #define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
+ − 7573 #define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
+ − 7574 #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
+ − 7575 #define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
+ − 7576 #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
+ − 7577 #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
+ − 7578 #define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
+ − 7579 #define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
+ − 7580 #define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
+ − 7581
+ − 7582 /* Bit definition for Ethernet MAC MII Data Register */
+ − 7583 #define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
+ − 7584
+ − 7585 /* Bit definition for Ethernet MAC Flow Control Register */
+ − 7586 #define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
+ − 7587 #define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
+ − 7588 #define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
+ − 7589 #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
+ − 7590 #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
+ − 7591 #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
+ − 7592 #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
+ − 7593 #define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
+ − 7594 #define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
+ − 7595 #define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
+ − 7596 #define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
+ − 7597
+ − 7598 /* Bit definition for Ethernet MAC VLAN Tag Register */
+ − 7599 #define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
+ − 7600 #define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
+ − 7601
+ − 7602 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
+ − 7603 #define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
+ − 7604 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
+ − 7605 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
+ − 7606 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
+ − 7607 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
+ − 7608 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
+ − 7609 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
+ − 7610 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
+ − 7611 RSVD - Filter1 Command - RSVD - Filter0 Command
+ − 7612 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
+ − 7613 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
+ − 7614 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
+ − 7615
+ − 7616 /* Bit definition for Ethernet MAC PMT Control and Status Register */
+ − 7617 #define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
+ − 7618 #define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
+ − 7619 #define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
+ − 7620 #define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
+ − 7621 #define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
+ − 7622 #define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
+ − 7623 #define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
+ − 7624
+ − 7625 /* Bit definition for Ethernet MAC Status Register */
+ − 7626 #define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
+ − 7627 #define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
+ − 7628 #define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
+ − 7629 #define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
+ − 7630 #define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
+ − 7631
+ − 7632 /* Bit definition for Ethernet MAC Interrupt Mask Register */
+ − 7633 #define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
+ − 7634 #define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
+ − 7635
+ − 7636 /* Bit definition for Ethernet MAC Address0 High Register */
+ − 7637 #define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
+ − 7638
+ − 7639 /* Bit definition for Ethernet MAC Address0 Low Register */
+ − 7640 #define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
+ − 7641
+ − 7642 /* Bit definition for Ethernet MAC Address1 High Register */
+ − 7643 #define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
+ − 7644 #define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
+ − 7645 #define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+ − 7646 #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
+ − 7647 #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
+ − 7648 #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
+ − 7649 #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
+ − 7650 #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
+ − 7651 #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
+ − 7652 #define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
+ − 7653
+ − 7654 /* Bit definition for Ethernet MAC Address1 Low Register */
+ − 7655 #define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
+ − 7656
+ − 7657 /* Bit definition for Ethernet MAC Address2 High Register */
+ − 7658 #define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
+ − 7659 #define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
+ − 7660 #define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
+ − 7661 #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
+ − 7662 #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
+ − 7663 #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
+ − 7664 #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
+ − 7665 #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
+ − 7666 #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
+ − 7667 #define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
+ − 7668
+ − 7669 /* Bit definition for Ethernet MAC Address2 Low Register */
+ − 7670 #define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
+ − 7671
+ − 7672 /* Bit definition for Ethernet MAC Address3 High Register */
+ − 7673 #define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
+ − 7674 #define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
+ − 7675 #define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
+ − 7676 #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
+ − 7677 #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
+ − 7678 #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
+ − 7679 #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
+ − 7680 #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
+ − 7681 #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
+ − 7682 #define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
+ − 7683
+ − 7684 /* Bit definition for Ethernet MAC Address3 Low Register */
+ − 7685 #define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
+ − 7686
+ − 7687 /******************************************************************************/
+ − 7688 /* Ethernet MMC Registers bits definition */
+ − 7689 /******************************************************************************/
+ − 7690
+ − 7691 /* Bit definition for Ethernet MMC Contol Register */
+ − 7692 #define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */
+ − 7693 #define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */
+ − 7694 #define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
+ − 7695 #define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
+ − 7696 #define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
+ − 7697 #define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
+ − 7698
+ − 7699 /* Bit definition for Ethernet MMC Receive Interrupt Register */
+ − 7700 #define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
+ − 7701 #define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
+ − 7702 #define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
+ − 7703
+ − 7704 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
+ − 7705 #define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
+ − 7706 #define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
+ − 7707 #define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
+ − 7708
+ − 7709 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
+ − 7710 #define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
+ − 7711 #define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+ − 7712 #define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
+ − 7713
+ − 7714 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
+ − 7715 #define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
+ − 7716 #define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
+ − 7717 #define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
+ − 7718
+ − 7719 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
+ − 7720 #define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
+ − 7721
+ − 7722 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
+ − 7723 #define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
+ − 7724
+ − 7725 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
+ − 7726 #define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
+ − 7727
+ − 7728 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
+ − 7729 #define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
+ − 7730
+ − 7731 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
+ − 7732 #define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
+ − 7733
+ − 7734 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
+ − 7735 #define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
+ − 7736
+ − 7737 /******************************************************************************/
+ − 7738 /* Ethernet PTP Registers bits definition */
+ − 7739 /******************************************************************************/
+ − 7740
+ − 7741 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
+ − 7742 #define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */
+ − 7743 #define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */
+ − 7744 #define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */
+ − 7745 #define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */
+ − 7746 #define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */
+ − 7747 #define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */
+ − 7748 #define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */
+ − 7749 #define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */
+ − 7750 #define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */
+ − 7751
+ − 7752 #define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
+ − 7753 #define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
+ − 7754 #define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
+ − 7755 #define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
+ − 7756 #define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
+ − 7757 #define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
+ − 7758
+ − 7759 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
+ − 7760 #define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
+ − 7761
+ − 7762 /* Bit definition for Ethernet PTP Time Stamp High Register */
+ − 7763 #define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
+ − 7764
+ − 7765 /* Bit definition for Ethernet PTP Time Stamp Low Register */
+ − 7766 #define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
+ − 7767 #define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
+ − 7768
+ − 7769 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
+ − 7770 #define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
+ − 7771
+ − 7772 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
+ − 7773 #define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
+ − 7774 #define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
+ − 7775
+ − 7776 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
+ − 7777 #define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
+ − 7778
+ − 7779 /* Bit definition for Ethernet PTP Target Time High Register */
+ − 7780 #define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
+ − 7781
+ − 7782 /* Bit definition for Ethernet PTP Target Time Low Register */
+ − 7783 #define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
+ − 7784
+ − 7785 /* Bit definition for Ethernet PTP Time Stamp Status Register */
+ − 7786 #define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */
+ − 7787 #define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */
+ − 7788
+ − 7789 /******************************************************************************/
+ − 7790 /* Ethernet DMA Registers bits definition */
+ − 7791 /******************************************************************************/
+ − 7792
+ − 7793 /* Bit definition for Ethernet DMA Bus Mode Register */
+ − 7794 #define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
+ − 7795 #define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
+ − 7796 #define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
+ − 7797 #define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
+ − 7798 #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+ − 7799 #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+ − 7800 #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+ − 7801 #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+ − 7802 #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+ − 7803 #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+ − 7804 #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+ − 7805 #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+ − 7806 #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+ − 7807 #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+ − 7808 #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+ − 7809 #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
+ − 7810 #define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
+ − 7811 #define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
+ − 7812 #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
+ − 7813 #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
+ − 7814 #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
+ − 7815 #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
+ − 7816 #define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
+ − 7817 #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+ − 7818 #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+ − 7819 #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+ − 7820 #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+ − 7821 #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+ − 7822 #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+ − 7823 #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+ − 7824 #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+ − 7825 #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+ − 7826 #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+ − 7827 #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+ − 7828 #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+ − 7829 #define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */
+ − 7830 #define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
+ − 7831 #define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
+ − 7832 #define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
+ − 7833
+ − 7834 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
+ − 7835 #define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
+ − 7836
+ − 7837 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
+ − 7838 #define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
+ − 7839
+ − 7840 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
+ − 7841 #define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
+ − 7842
+ − 7843 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
+ − 7844 #define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
+ − 7845
+ − 7846 /* Bit definition for Ethernet DMA Status Register */
+ − 7847 #define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
+ − 7848 #define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
+ − 7849 #define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
+ − 7850 #define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
+ − 7851 /* combination with EBS[2:0] for GetFlagStatus function */
+ − 7852 #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
+ − 7853 #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
+ − 7854 #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
+ − 7855 #define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
+ − 7856 #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
+ − 7857 #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
+ − 7858 #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
+ − 7859 #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
+ − 7860 #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
+ − 7861 #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
+ − 7862 #define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
+ − 7863 #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
+ − 7864 #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
+ − 7865 #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
+ − 7866 #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
+ − 7867 #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
+ − 7868 #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
+ − 7869 #define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
+ − 7870 #define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
+ − 7871 #define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
+ − 7872 #define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
+ − 7873 #define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
+ − 7874 #define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
+ − 7875 #define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
+ − 7876 #define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
+ − 7877 #define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
+ − 7878 #define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
+ − 7879 #define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
+ − 7880 #define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
+ − 7881 #define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
+ − 7882 #define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
+ − 7883 #define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
+ − 7884
+ − 7885 /* Bit definition for Ethernet DMA Operation Mode Register */
+ − 7886 #define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
+ − 7887 #define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
+ − 7888 #define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
+ − 7889 #define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
+ − 7890 #define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
+ − 7891 #define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
+ − 7892 #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+ − 7893 #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+ − 7894 #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+ − 7895 #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+ − 7896 #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+ − 7897 #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+ − 7898 #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+ − 7899 #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+ − 7900 #define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
+ − 7901 #define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
+ − 7902 #define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
+ − 7903 #define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
+ − 7904 #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
+ − 7905 #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
+ − 7906 #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
+ − 7907 #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
+ − 7908 #define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
+ − 7909 #define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
+ − 7910
+ − 7911 /* Bit definition for Ethernet DMA Interrupt Enable Register */
+ − 7912 #define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
+ − 7913 #define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
+ − 7914 #define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
+ − 7915 #define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
+ − 7916 #define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
+ − 7917 #define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
+ − 7918 #define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
+ − 7919 #define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
+ − 7920 #define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
+ − 7921 #define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
+ − 7922 #define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
+ − 7923 #define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
+ − 7924 #define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
+ − 7925 #define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
+ − 7926 #define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
+ − 7927
+ − 7928 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
+ − 7929 #define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
+ − 7930 #define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
+ − 7931 #define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
+ − 7932 #define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
+ − 7933
+ − 7934 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
+ − 7935 #define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
+ − 7936
+ − 7937 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
+ − 7938 #define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
+ − 7939
+ − 7940 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
+ − 7941 #define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
+ − 7942
+ − 7943 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
+ − 7944 #define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
+ − 7945
+ − 7946 /******************************************************************************/
+ − 7947 /* */
+ − 7948 /* USB_OTG */
+ − 7949 /* */
+ − 7950 /******************************************************************************/
+ − 7951 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
+ − 7952 #define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */
+ − 7953 #define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */
+ − 7954 #define USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) /*!< Host negotiation success */
+ − 7955 #define USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) /*!< HNP request */
+ − 7956 #define USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) /*!< Host set HNP enable */
+ − 7957 #define USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) /*!< Device HNP enabled */
+ − 7958 #define USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) /*!< Connector ID status */
+ − 7959 #define USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) /*!< Long/short debounce time */
+ − 7960 #define USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) /*!< A-session valid */
+ − 7961 #define USB_OTG_GOTGCTL_BSVLD ((uint32_t)0x00080000) /*!< B-session valid */
+ − 7962
+ − 7963 /******************** Bit definition forUSB_OTG_HCFG register ********************/
+ − 7964
+ − 7965 #define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */
+ − 7966 #define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+ − 7967 #define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+ − 7968 #define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /*!< FS- and LS-only support */
+ − 7969
+ − 7970 /******************** Bit definition forUSB_OTG_DCFG register ********************/
+ − 7971
+ − 7972 #define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /*!< Device speed */
+ − 7973 #define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+ − 7974 #define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+ − 7975 #define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /*!< Nonzero-length status OUT handshake */
+ − 7976
+ − 7977 #define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /*!< Device address */
+ − 7978 #define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+ − 7979 #define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+ − 7980 #define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+ − 7981 #define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+ − 7982 #define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /*!<Bit 4 */
+ − 7983 #define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /*!<Bit 5 */
+ − 7984 #define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /*!<Bit 6 */
+ − 7985
+ − 7986 #define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /*!< Periodic (micro)frame interval */
+ − 7987 #define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /*!<Bit 0 */
+ − 7988 #define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /*!<Bit 1 */
+ − 7989
+ − 7990 #define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /*!< Periodic scheduling interval */
+ − 7991 #define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+ − 7992 #define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+ − 7993
+ − 7994 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
+ − 7995 #define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /*!< Stop PHY clock */
+ − 7996 #define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /*!< Gate HCLK */
+ − 7997 #define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /*!< PHY suspended */
+ − 7998
+ − 7999 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
+ − 8000 #define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /*!< Session end detected */
+ − 8001 #define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /*!< Session request success status change */
+ − 8002 #define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /*!< Host negotiation success status change */
+ − 8003 #define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /*!< Host negotiation detected */
+ − 8004 #define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /*!< A-device timeout change */
+ − 8005 #define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /*!< Debounce done */
+ − 8006
+ − 8007 /******************** Bit definition forUSB_OTG_DCTL register ********************/
+ − 8008 #define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /*!< Remote wakeup signaling */
+ − 8009 #define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /*!< Soft disconnect */
+ − 8010 #define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /*!< Global IN NAK status */
+ − 8011 #define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /*!< Global OUT NAK status */
+ − 8012
+ − 8013 #define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /*!< Test control */
+ − 8014 #define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+ − 8015 #define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+ − 8016 #define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+ − 8017 #define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /*!< Set global IN NAK */
+ − 8018 #define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /*!< Clear global IN NAK */
+ − 8019 #define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /*!< Set global OUT NAK */
+ − 8020 #define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /*!< Clear global OUT NAK */
+ − 8021 #define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /*!< Power-on programming done */
+ − 8022
+ − 8023 /******************** Bit definition forUSB_OTG_HFIR register ********************/
+ − 8024 #define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /*!< Frame interval */
+ − 8025
+ − 8026 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
+ − 8027 #define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /*!< Frame number */
+ − 8028 #define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /*!< Frame time remaining */
+ − 8029
+ − 8030 /******************** Bit definition forUSB_OTG_DSTS register ********************/
+ − 8031 #define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /*!< Suspend status */
+ − 8032
+ − 8033 #define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /*!< Enumerated speed */
+ − 8034 #define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /*!<Bit 0 */
+ − 8035 #define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /*!<Bit 1 */
+ − 8036 #define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /*!< Erratic error */
+ − 8037 #define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /*!< Frame number of the received SOF */
+ − 8038
+ − 8039 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
+ − 8040 #define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /*!< Global interrupt mask */
+ − 8041
+ − 8042 #define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /*!< Burst length/type */
+ − 8043 #define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
+ − 8044 #define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
+ − 8045 #define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /*!<Bit 2 */
+ − 8046 #define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /*!<Bit 3 */
+ − 8047 #define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /*!< DMA enable */
+ − 8048 #define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /*!< TxFIFO empty level */
+ − 8049 #define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /*!< Periodic TxFIFO empty level */
+ − 8050
+ − 8051 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
+ − 8052
+ − 8053 #define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /*!< FS timeout calibration */
+ − 8054 #define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+ − 8055 #define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+ − 8056 #define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+ − 8057 #define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+ − 8058 #define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /*!< SRP-capable */
+ − 8059 #define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /*!< HNP-capable */
+ − 8060
+ − 8061 #define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /*!< USB turnaround time */
+ − 8062 #define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+ − 8063 #define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+ − 8064 #define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+ − 8065 #define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+ − 8066 #define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /*!< PHY Low-power clock select */
+ − 8067 #define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /*!< ULPI FS/LS select */
+ − 8068 #define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /*!< ULPI Auto-resume */
+ − 8069 #define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /*!< ULPI Clock SuspendM */
+ − 8070 #define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /*!< ULPI External VBUS Drive */
+ − 8071 #define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /*!< ULPI external VBUS indicator */
+ − 8072 #define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /*!< TermSel DLine pulsing selection */
+ − 8073 #define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /*!< Indicator complement */
+ − 8074 #define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /*!< Indicator pass through */
+ − 8075 #define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /*!< ULPI interface protect disable */
+ − 8076 #define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /*!< Forced host mode */
+ − 8077 #define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /*!< Forced peripheral mode */
+ − 8078 #define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /*!< Corrupt Tx packet */
+ − 8079
+ − 8080 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
+ − 8081 #define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /*!< Core soft reset */
+ − 8082 #define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /*!< HCLK soft reset */
+ − 8083 #define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /*!< Host frame counter reset */
+ − 8084 #define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /*!< RxFIFO flush */
+ − 8085 #define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /*!< TxFIFO flush */
+ − 8086
+ − 8087 #define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /*!< TxFIFO number */
+ − 8088 #define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+ − 8089 #define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+ − 8090 #define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /*!<Bit 2 */
+ − 8091 #define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /*!<Bit 3 */
+ − 8092 #define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /*!<Bit 4 */
+ − 8093 #define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /*!< DMA request signal */
+ − 8094 #define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /*!< AHB master idle */
+ − 8095
+ − 8096 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
+ − 8097 #define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
+ − 8098 #define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
+ − 8099 #define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
+ − 8100 #define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
+ − 8101 #define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
+ − 8102 #define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
+ − 8103 #define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
+ − 8104 #define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
+ − 8105
+ − 8106 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
+ − 8107 #define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /*!< Periodic transmit data FIFO space available */
+ − 8108
+ − 8109 #define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /*!< Periodic transmit request queue space available */
+ − 8110 #define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+ − 8111 #define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+ − 8112 #define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+ − 8113 #define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+ − 8114 #define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+ − 8115 #define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+ − 8116 #define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+ − 8117 #define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+ − 8118
+ − 8119 #define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /*!< Top of the periodic transmit request queue */
+ − 8120 #define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+ − 8121 #define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+ − 8122 #define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+ − 8123 #define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+ − 8124 #define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+ − 8125 #define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+ − 8126 #define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+ − 8127 #define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+ − 8128
+ − 8129 /******************** Bit definition forUSB_OTG_HAINT register ********************/
+ − 8130 #define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /*!< Channel interrupts */
+ − 8131
+ − 8132 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
+ − 8133 #define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
+ − 8134 #define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
+ − 8135 #define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */
+ − 8136 #define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled mask */
+ − 8137 #define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received mask */
+ − 8138 #define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */
+ − 8139 #define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
+ − 8140
+ − 8141 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
+ − 8142 #define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /*!< Current mode of operation */
+ − 8143 #define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /*!< Mode mismatch interrupt */
+ − 8144 #define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt */
+ − 8145 #define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /*!< Start of frame */
+ − 8146 #define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /*!< RxFIFO nonempty */
+ − 8147 #define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty */
+ − 8148 #define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /*!< Global IN nonperiodic NAK effective */
+ − 8149 #define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /*!< Global OUT NAK effective */
+ − 8150 #define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /*!< Early suspend */
+ − 8151 #define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /*!< USB suspend */
+ − 8152 #define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /*!< USB reset */
+ − 8153 #define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /*!< Enumeration done */
+ − 8154 #define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt */
+ − 8155 #define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /*!< End of periodic frame interrupt */
+ − 8156 #define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /*!< IN endpoint interrupt */
+ − 8157 #define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoint interrupt */
+ − 8158 #define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer */
+ − 8159 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /*!< Incomplete periodic transfer */
+ − 8160 #define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /*!< Data fetch suspended */
+ − 8161 #define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /*!< Host port interrupt */
+ − 8162 #define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /*!< Host channels interrupt */
+ − 8163 #define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty */
+ − 8164 #define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /*!< Connector ID status change */
+ − 8165 #define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt */
+ − 8166 #define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt */
+ − 8167 #define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt */
+ − 8168
+ − 8169 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
+ − 8170 #define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /*!< Mode mismatch interrupt mask */
+ − 8171 #define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt mask */
+ − 8172 #define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /*!< Start of frame mask */
+ − 8173 #define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /*!< Receive FIFO nonempty mask */
+ − 8174 #define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty mask */
+ − 8175 #define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /*!< Global nonperiodic IN NAK effective mask */
+ − 8176 #define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /*!< Global OUT NAK effective mask */
+ − 8177 #define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /*!< Early suspend mask */
+ − 8178 #define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /*!< USB suspend mask */
+ − 8179 #define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /*!< USB reset mask */
+ − 8180 #define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /*!< Enumeration done mask */
+ − 8181 #define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt mask */
+ − 8182 #define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /*!< End of periodic frame interrupt mask */
+ − 8183 #define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /*!< Endpoint mismatch interrupt mask */
+ − 8184 #define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /*!< IN endpoints interrupt mask */
+ − 8185 #define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoints interrupt mask */
+ − 8186 #define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer mask */
+ − 8187 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /*!< Incomplete periodic transfer mask */
+ − 8188 #define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /*!< Data fetch suspended mask */
+ − 8189 #define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /*!< Host port interrupt mask */
+ − 8190 #define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /*!< Host channels interrupt mask */
+ − 8191 #define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty mask */
+ − 8192 #define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /*!< Connector ID status change mask */
+ − 8193 #define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt mask */
+ − 8194 #define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt mask */
+ − 8195 #define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt mask */
+ − 8196
+ − 8197 /******************** Bit definition forUSB_OTG_DAINT register ********************/
+ − 8198 #define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /*!< IN endpoint interrupt bits */
+ − 8199 #define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /*!< OUT endpoint interrupt bits */
+ − 8200
+ − 8201 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
+ − 8202 #define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /*!< Channel interrupt mask */
+ − 8203
+ − 8204 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
+ − 8205 #define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /*!< IN EP interrupt mask bits */
+ − 8206 #define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< OUT EP interrupt mask bits */
+ − 8207 #define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< OUT EP interrupt mask bits */
+ − 8208 #define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< OUT EP interrupt mask bits */
+ − 8209
+ − 8210 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
+ − 8211 #define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /*!< IN EP interrupt mask bits */
+ − 8212 #define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /*!< OUT EP interrupt mask bits */
+ − 8213
+ − 8214 /******************** Bit definition for OTG register ********************/
+ − 8215
+ − 8216 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
+ − 8217 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+ − 8218 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+ − 8219 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+ − 8220 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+ − 8221 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
+ − 8222
+ − 8223 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
+ − 8224 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+ − 8225 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+ − 8226
+ − 8227 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
+ − 8228 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+ − 8229 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+ − 8230 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+ − 8231 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
+ − 8232
+ − 8233 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
+ − 8234 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+ − 8235 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+ − 8236 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+ − 8237 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+ − 8238
+ − 8239 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
+ − 8240 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
+ − 8241 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
+ − 8242 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
+ − 8243 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
+ − 8244
+ − 8245 /******************** Bit definition for OTG register ********************/
+ − 8246
+ − 8247 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
+ − 8248 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+ − 8249 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+ − 8250 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+ − 8251 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+ − 8252 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
+ − 8253
+ − 8254 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
+ − 8255 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+ − 8256 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+ − 8257
+ − 8258 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
+ − 8259 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+ − 8260 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+ − 8261 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+ − 8262 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
+ − 8263
+ − 8264 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
+ − 8265 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+ − 8266 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+ − 8267 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+ − 8268 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+ − 8269
+ − 8270 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
+ − 8271 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
+ − 8272 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
+ − 8273 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
+ − 8274 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
+ − 8275
+ − 8276 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
+ − 8277 #define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /*!< RxFIFO depth */
+ − 8278
+ − 8279 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
+ − 8280 #define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /*!< Device VBUS discharge time */
+ − 8281
+ − 8282 /******************** Bit definition for OTG register ********************/
+ − 8283 #define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /*!< Nonperiodic transmit RAM start address */
+ − 8284 #define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /*!< Nonperiodic TxFIFO depth */
+ − 8285 #define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /*!< Endpoint 0 transmit RAM start address */
+ − 8286 #define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /*!< Endpoint 0 TxFIFO depth */
+ − 8287
+ − 8288 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
+ − 8289 #define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /*!< Device VBUS pulsing time */
+ − 8290
+ − 8291 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
+ − 8292 #define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /*!< Nonperiodic TxFIFO space available */
+ − 8293
+ − 8294 #define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /*!< Nonperiodic transmit request queue space available */
+ − 8295 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+ − 8296 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+ − 8297 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+ − 8298 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+ − 8299 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+ − 8300 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+ − 8301 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+ − 8302 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+ − 8303
+ − 8304 #define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /*!< Top of the nonperiodic transmit request queue */
+ − 8305 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+ − 8306 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+ − 8307 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+ − 8308 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+ − 8309 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+ − 8310 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+ − 8311 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+ − 8312
+ − 8313 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
+ − 8314 #define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /*!< Nonisochronous IN endpoints threshold enable */
+ − 8315 #define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /*!< ISO IN endpoint threshold enable */
+ − 8316
+ − 8317 #define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /*!< Transmit threshold length */
+ − 8318 #define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+ − 8319 #define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+ − 8320 #define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /*!<Bit 2 */
+ − 8321 #define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /*!<Bit 3 */
+ − 8322 #define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /*!<Bit 4 */
+ − 8323 #define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /*!<Bit 5 */
+ − 8324 #define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /*!<Bit 6 */
+ − 8325 #define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /*!<Bit 7 */
+ − 8326 #define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /*!<Bit 8 */
+ − 8327 #define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /*!< Receive threshold enable */
+ − 8328
+ − 8329 #define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /*!< Receive threshold length */
+ − 8330 #define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+ − 8331 #define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+ − 8332 #define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+ − 8333 #define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /*!<Bit 3 */
+ − 8334 #define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /*!<Bit 4 */
+ − 8335 #define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /*!<Bit 5 */
+ − 8336 #define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /*!<Bit 6 */
+ − 8337 #define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /*!<Bit 7 */
+ − 8338 #define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /*!<Bit 8 */
+ − 8339 #define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /*!< Arbiter parking enable */
+ − 8340
+ − 8341 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
+ − 8342 #define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /*!< IN EP Tx FIFO empty interrupt mask bits */
+ − 8343
+ − 8344 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
+ − 8345 #define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /*!< IN endpoint 1interrupt bit */
+ − 8346 #define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /*!< OUT endpoint 1 interrupt bit */
+ − 8347
+ − 8348 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
+ − 8349 #define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /*!< Power down */
+ − 8350 #define USB_OTG_GCCFG_I2CPADEN ((uint32_t)0x00020000) /*!< Enable I2C bus connection for the external I2C PHY interface */
+ − 8351 #define USB_OTG_GCCFG_VBUSASEN ((uint32_t)0x00040000) /*!< Enable the VBUS sensing device */
+ − 8352 #define USB_OTG_GCCFG_VBUSBSEN ((uint32_t)0x00080000) /*!< Enable the VBUS sensing device */
+ − 8353 #define USB_OTG_GCCFG_SOFOUTEN ((uint32_t)0x00100000) /*!< SOF output enable */
+ − 8354 #define USB_OTG_GCCFG_NOVBUSSENS ((uint32_t)0x00200000) /*!< VBUS sensing disable option */
+ − 8355
+ − 8356 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
+ − 8357 #define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /*!< IN Endpoint 1 interrupt mask bit */
+ − 8358 #define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /*!< OUT Endpoint 1 interrupt mask bit */
+ − 8359
+ − 8360 /******************** Bit definition forUSB_OTG_CID register ********************/
+ − 8361 #define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /*!< Product ID field */
+ − 8362
+ − 8363 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
+ − 8364 #define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
+ − 8365 #define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
+ − 8366 #define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
+ − 8367 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
+ − 8368 #define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
+ − 8369 #define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
+ − 8370 #define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
+ − 8371 #define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
+ − 8372 #define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
+ − 8373
+ − 8374 /******************** Bit definition forUSB_OTG_HPRT register ********************/
+ − 8375 #define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /*!< Port connect status */
+ − 8376 #define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /*!< Port connect detected */
+ − 8377 #define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /*!< Port enable */
+ − 8378 #define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /*!< Port enable/disable change */
+ − 8379 #define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /*!< Port overcurrent active */
+ − 8380 #define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /*!< Port overcurrent change */
+ − 8381 #define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /*!< Port resume */
+ − 8382 #define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /*!< Port suspend */
+ − 8383 #define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /*!< Port reset */
+ − 8384
+ − 8385 #define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /*!< Port line status */
+ − 8386 #define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+ − 8387 #define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+ − 8388 #define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /*!< Port power */
+ − 8389
+ − 8390 #define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /*!< Port test control */
+ − 8391 #define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+ − 8392 #define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+ − 8393 #define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+ − 8394 #define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+ − 8395
+ − 8396 #define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /*!< Port speed */
+ − 8397 #define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+ − 8398 #define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+ − 8399
+ − 8400 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
+ − 8401 #define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
+ − 8402 #define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
+ − 8403 #define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask */
+ − 8404 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
+ − 8405 #define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
+ − 8406 #define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
+ − 8407 #define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< OUT packet error mask */
+ − 8408 #define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
+ − 8409 #define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /*!< Bubble error interrupt mask */
+ − 8410 #define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
+ − 8411 #define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /*!< NYET interrupt mask */
+ − 8412
+ − 8413 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
+ − 8414 #define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /*!< Host periodic TxFIFO start address */
+ − 8415 #define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /*!< Host periodic TxFIFO depth */
+ − 8416
+ − 8417 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
+ − 8418 #define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
+ − 8419 #define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
+ − 8420 #define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /*!< Even/odd frame */
+ − 8421 #define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
+ − 8422
+ − 8423 #define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
+ − 8424 #define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+ − 8425 #define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+ − 8426 #define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
+ − 8427
+ − 8428 #define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /*!< TxFIFO number */
+ − 8429 #define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /*!<Bit 0 */
+ − 8430 #define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /*!<Bit 1 */
+ − 8431 #define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /*!<Bit 2 */
+ − 8432 #define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /*!<Bit 3 */
+ − 8433 #define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
+ − 8434 #define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
+ − 8435 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
+ − 8436 #define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
+ − 8437 #define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
+ − 8438 #define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
+ − 8439
+ − 8440 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
+ − 8441 #define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
+ − 8442
+ − 8443 #define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /*!< Endpoint number */
+ − 8444 #define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /*!<Bit 0 */
+ − 8445 #define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /*!<Bit 1 */
+ − 8446 #define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /*!<Bit 2 */
+ − 8447 #define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /*!<Bit 3 */
+ − 8448 #define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /*!< Endpoint direction */
+ − 8449 #define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /*!< Low-speed device */
+ − 8450
+ − 8451 #define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
+ − 8452 #define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+ − 8453 #define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+ − 8454
+ − 8455 #define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< Multi Count (MC) / Error Count (EC) */
+ − 8456 #define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+ − 8457 #define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+ − 8458
+ − 8459 #define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /*!< Device address */
+ − 8460 #define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /*!<Bit 0 */
+ − 8461 #define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /*!<Bit 1 */
+ − 8462 #define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /*!<Bit 2 */
+ − 8463 #define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /*!<Bit 3 */
+ − 8464 #define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /*!<Bit 4 */
+ − 8465 #define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /*!<Bit 5 */
+ − 8466 #define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /*!<Bit 6 */
+ − 8467 #define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< Odd frame */
+ − 8468 #define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< Channel disable */
+ − 8469 #define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< Channel enable */
+ − 8470
+ − 8471 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
+ − 8472
+ − 8473 #define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /*!< Port address */
+ − 8474 #define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+ − 8475 #define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+ − 8476 #define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+ − 8477 #define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+ − 8478 #define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+ − 8479 #define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+ − 8480 #define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+ − 8481
+ − 8482 #define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /*!< Hub address */
+ − 8483 #define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /*!<Bit 0 */
+ − 8484 #define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /*!<Bit 1 */
+ − 8485 #define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /*!<Bit 2 */
+ − 8486 #define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /*!<Bit 3 */
+ − 8487 #define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /*!<Bit 4 */
+ − 8488 #define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /*!<Bit 5 */
+ − 8489 #define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /*!<Bit 6 */
+ − 8490
+ − 8491 #define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /*!< XACTPOS */
+ − 8492 #define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /*!<Bit 0 */
+ − 8493 #define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /*!<Bit 1 */
+ − 8494 #define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /*!< Do complete split */
+ − 8495 #define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /*!< Split enable */
+ − 8496
+ − 8497 /******************** Bit definition forUSB_OTG_HCINT register ********************/
+ − 8498 #define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed */
+ − 8499 #define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /*!< Channel halted */
+ − 8500 #define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
+ − 8501 #define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /*!< STALL response received interrupt */
+ − 8502 #define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /*!< NAK response received interrupt */
+ − 8503 #define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt */
+ − 8504 #define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /*!< Response received interrupt */
+ − 8505 #define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /*!< Transaction error */
+ − 8506 #define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /*!< Babble error */
+ − 8507 #define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /*!< Frame overrun */
+ − 8508 #define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /*!< Data toggle error */
+ − 8509
+ − 8510 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
+ − 8511 #define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
+ − 8512 #define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
+ − 8513 #define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /*!< Timeout condition */
+ − 8514 #define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /*!< IN token received when TxFIFO is empty */
+ − 8515 #define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /*!< IN endpoint NAK effective */
+ − 8516 #define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /*!< Transmit FIFO empty */
+ − 8517 #define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /*!< Transmit Fifo Underrun */
+ − 8518 #define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /*!< Buffer not available interrupt */
+ − 8519 #define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /*!< Packet dropped status */
+ − 8520 #define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /*!< Babble error interrupt */
+ − 8521 #define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /*!< NAK interrupt */
+ − 8522
+ − 8523 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
+ − 8524 #define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed mask */
+ − 8525 #define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /*!< Channel halted mask */
+ − 8526 #define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
+ − 8527 #define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /*!< STALL response received interrupt mask */
+ − 8528 #define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /*!< NAK response received interrupt mask */
+ − 8529 #define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt mask */
+ − 8530 #define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /*!< response received interrupt mask */
+ − 8531 #define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /*!< Transaction error mask */
+ − 8532 #define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /*!< Babble error mask */
+ − 8533 #define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /*!< Frame overrun mask */
+ − 8534 #define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /*!< Data toggle error mask */
+ − 8535
+ − 8536 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
+ − 8537
+ − 8538 #define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
+ − 8539 #define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
+ − 8540 #define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /*!< Packet count */
+ − 8541 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
+ − 8542 #define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
+ − 8543 #define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
+ − 8544 #define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /*!< Do PING */
+ − 8545 #define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /*!< Data PID */
+ − 8546 #define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /*!<Bit 0 */
+ − 8547 #define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /*!<Bit 1 */
+ − 8548
+ − 8549 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
+ − 8550 #define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
+ − 8551
+ − 8552 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
+ − 8553 #define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
+ − 8554
+ − 8555 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
+ − 8556 #define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< IN endpoint TxFIFO space available */
+ − 8557
+ − 8558 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
+ − 8559 #define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /*!< IN endpoint FIFOx transmit RAM start address */
+ − 8560 #define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /*!< IN endpoint TxFIFO depth */
+ − 8561
+ − 8562 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
+ − 8563
+ − 8564 #define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ /*!<Bit 1 */
+ − 8565 #define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
+ − 8566 #define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
+ − 8567 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
+ − 8568 #define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
+ − 8569 #define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
+ − 8570 #define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+ − 8571 #define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+ − 8572 #define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /*!< Snoop mode */
+ − 8573 #define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
+ − 8574 #define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
+ − 8575 #define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
+ − 8576 #define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
+ − 8577 #define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
+ − 8578
+ − 8579 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
+ − 8580 #define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
+ − 8581 #define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
+ − 8582 #define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */
+ − 8583 #define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled */
+ − 8584 #define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */
+ − 8585 #define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */
+ − 8586
+ − 8587 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
+ − 8588
+ − 8589 #define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
+ − 8590 #define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
+ − 8591
+ − 8592 #define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /*!< SETUP packet count */
+ − 8593 #define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /*!<Bit 0 */
+ − 8594 #define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /*!<Bit 1 */
+ − 8595
+ − 8596 /******************** Bit definition for PCGCCTL register ********************/
+ − 8597 #define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /*!< SETUP packet count */
+ − 8598 #define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /*!<Bit 0 */
+ − 8599 #define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /*!<Bit 1 */
+ − 8600
+ − 8601
+ − 8602 /**
+ − 8603 * @}
+ − 8604 */
+ − 8605
+ − 8606 /**
+ − 8607 * @}
+ − 8608 */
+ − 8609
+ − 8610 /** @addtogroup Exported_macros
+ − 8611 * @{
+ − 8612 */
+ − 8613
+ − 8614 /******************************* ADC Instances ********************************/
+ − 8615 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+ − 8616 ((INSTANCE) == ADC2) || \
+ − 8617 ((INSTANCE) == ADC3))
+ − 8618
+ − 8619 /******************************* CAN Instances ********************************/
+ − 8620 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
+ − 8621 ((INSTANCE) == CAN2))
+ − 8622
+ − 8623 /******************************* CRC Instances ********************************/
+ − 8624 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+ − 8625
+ − 8626 /******************************* DAC Instances ********************************/
+ − 8627 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+ − 8628
+ − 8629 /******************************* DCMI Instances *******************************/
+ − 8630 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
+ − 8631
+ − 8632 /******************************* DMA2D Instances *******************************/
+ − 8633 #define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
+ − 8634
+ − 8635 /******************************** DMA Instances *******************************/
+ − 8636 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ − 8637 ((INSTANCE) == DMA1_Stream1) || \
+ − 8638 ((INSTANCE) == DMA1_Stream2) || \
+ − 8639 ((INSTANCE) == DMA1_Stream3) || \
+ − 8640 ((INSTANCE) == DMA1_Stream4) || \
+ − 8641 ((INSTANCE) == DMA1_Stream5) || \
+ − 8642 ((INSTANCE) == DMA1_Stream6) || \
+ − 8643 ((INSTANCE) == DMA1_Stream7) || \
+ − 8644 ((INSTANCE) == DMA2_Stream0) || \
+ − 8645 ((INSTANCE) == DMA2_Stream1) || \
+ − 8646 ((INSTANCE) == DMA2_Stream2) || \
+ − 8647 ((INSTANCE) == DMA2_Stream3) || \
+ − 8648 ((INSTANCE) == DMA2_Stream4) || \
+ − 8649 ((INSTANCE) == DMA2_Stream5) || \
+ − 8650 ((INSTANCE) == DMA2_Stream6) || \
+ − 8651 ((INSTANCE) == DMA2_Stream7))
+ − 8652
+ − 8653 /******************************* GPIO Instances *******************************/
+ − 8654 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ − 8655 ((INSTANCE) == GPIOB) || \
+ − 8656 ((INSTANCE) == GPIOC) || \
+ − 8657 ((INSTANCE) == GPIOD) || \
+ − 8658 ((INSTANCE) == GPIOE) || \
+ − 8659 ((INSTANCE) == GPIOF) || \
+ − 8660 ((INSTANCE) == GPIOG) || \
+ − 8661 ((INSTANCE) == GPIOH) || \
+ − 8662 ((INSTANCE) == GPIOI) || \
+ − 8663 ((INSTANCE) == GPIOJ) || \
+ − 8664 ((INSTANCE) == GPIOK))
+ − 8665
+ − 8666 /******************************** I2C Instances *******************************/
+ − 8667 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ − 8668 ((INSTANCE) == I2C2) || \
+ − 8669 ((INSTANCE) == I2C3))
+ − 8670
+ − 8671 /******************************** I2S Instances *******************************/
+ − 8672 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ − 8673 ((INSTANCE) == SPI3))
+ − 8674
+ − 8675 /*************************** I2S Extended Instances ***************************/
+ − 8676 #define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
+ − 8677 ((INSTANCE) == SPI3) || \
+ − 8678 ((INSTANCE) == I2S2ext) || \
+ − 8679 ((INSTANCE) == I2S3ext))
+ − 8680
+ − 8681 /****************************** LTDC Instances ********************************/
+ − 8682 #define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
+ − 8683
+ − 8684 /******************************* RNG Instances ********************************/
+ − 8685 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
+ − 8686
+ − 8687 /****************************** RTC Instances *********************************/
+ − 8688 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+ − 8689
+ − 8690 /******************************* SAI Instances ********************************/
+ − 8691 #define IS_SAI_BLOCK_PERIPH(PERIPH) (((PERIPH) == SAI1_Block_A) || \
+ − 8692 ((PERIPH) == SAI1_Block_B))
+ − 8693
+ − 8694 /******************************** SPI Instances *******************************/
+ − 8695 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ − 8696 ((INSTANCE) == SPI2) || \
+ − 8697 ((INSTANCE) == SPI3) || \
+ − 8698 ((INSTANCE) == SPI4) || \
+ − 8699 ((INSTANCE) == SPI5) || \
+ − 8700 ((INSTANCE) == SPI6))
+ − 8701
+ − 8702 /*************************** SPI Extended Instances ***************************/
+ − 8703 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
+ − 8704 ((INSTANCE) == SPI2) || \
+ − 8705 ((INSTANCE) == SPI3) || \
+ − 8706 ((INSTANCE) == SPI4) || \
+ − 8707 ((INSTANCE) == SPI5) || \
+ − 8708 ((INSTANCE) == SPI6) || \
+ − 8709 ((INSTANCE) == I2S2ext) || \
+ − 8710 ((INSTANCE) == I2S3ext))
+ − 8711
+ − 8712 /****************** TIM Instances : All supported instances *******************/
+ − 8713 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ − 8714 ((INSTANCE) == TIM2) || \
+ − 8715 ((INSTANCE) == TIM3) || \
+ − 8716 ((INSTANCE) == TIM4) || \
+ − 8717 ((INSTANCE) == TIM5) || \
+ − 8718 ((INSTANCE) == TIM6) || \
+ − 8719 ((INSTANCE) == TIM7) || \
+ − 8720 ((INSTANCE) == TIM8) || \
+ − 8721 ((INSTANCE) == TIM9) || \
+ − 8722 ((INSTANCE) == TIM10) || \
+ − 8723 ((INSTANCE) == TIM11) || \
+ − 8724 ((INSTANCE) == TIM12) || \
+ − 8725 ((INSTANCE) == TIM13) || \
+ − 8726 ((INSTANCE) == TIM14))
+ − 8727
+ − 8728 /************* TIM Instances : at least 1 capture/compare channel *************/
+ − 8729 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ − 8730 ((INSTANCE) == TIM2) || \
+ − 8731 ((INSTANCE) == TIM3) || \
+ − 8732 ((INSTANCE) == TIM4) || \
+ − 8733 ((INSTANCE) == TIM5) || \
+ − 8734 ((INSTANCE) == TIM8) || \
+ − 8735 ((INSTANCE) == TIM9) || \
+ − 8736 ((INSTANCE) == TIM10) || \
+ − 8737 ((INSTANCE) == TIM11) || \
+ − 8738 ((INSTANCE) == TIM12) || \
+ − 8739 ((INSTANCE) == TIM13) || \
+ − 8740 ((INSTANCE) == TIM14))
+ − 8741
+ − 8742 /************ TIM Instances : at least 2 capture/compare channels *************/
+ − 8743 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ − 8744 ((INSTANCE) == TIM2) || \
+ − 8745 ((INSTANCE) == TIM3) || \
+ − 8746 ((INSTANCE) == TIM4) || \
+ − 8747 ((INSTANCE) == TIM5) || \
+ − 8748 ((INSTANCE) == TIM8) || \
+ − 8749 ((INSTANCE) == TIM9) || \
+ − 8750 ((INSTANCE) == TIM12))
+ − 8751
+ − 8752 /************ TIM Instances : at least 3 capture/compare channels *************/
+ − 8753 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ − 8754 ((INSTANCE) == TIM2) || \
+ − 8755 ((INSTANCE) == TIM3) || \
+ − 8756 ((INSTANCE) == TIM4) || \
+ − 8757 ((INSTANCE) == TIM5) || \
+ − 8758 ((INSTANCE) == TIM8))
+ − 8759
+ − 8760 /************ TIM Instances : at least 4 capture/compare channels *************/
+ − 8761 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ − 8762 ((INSTANCE) == TIM2) || \
+ − 8763 ((INSTANCE) == TIM3) || \
+ − 8764 ((INSTANCE) == TIM4) || \
+ − 8765 ((INSTANCE) == TIM5) || \
+ − 8766 ((INSTANCE) == TIM8))
+ − 8767
+ − 8768 /******************** TIM Instances : Advanced-control timers *****************/
+ − 8769 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ − 8770 ((INSTANCE) == TIM8))
+ − 8771
+ − 8772 /******************* TIM Instances : Timer input XOR function *****************/
+ − 8773 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ − 8774 ((INSTANCE) == TIM2) || \
+ − 8775 ((INSTANCE) == TIM3) || \
+ − 8776 ((INSTANCE) == TIM4) || \
+ − 8777 ((INSTANCE) == TIM5) || \
+ − 8778 ((INSTANCE) == TIM8))
+ − 8779
+ − 8780 /****************** TIM Instances : DMA requests generation (UDE) *************/
+ − 8781 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ − 8782 ((INSTANCE) == TIM2) || \
+ − 8783 ((INSTANCE) == TIM3) || \
+ − 8784 ((INSTANCE) == TIM4) || \
+ − 8785 ((INSTANCE) == TIM5) || \
+ − 8786 ((INSTANCE) == TIM6) || \
+ − 8787 ((INSTANCE) == TIM7) || \
+ − 8788 ((INSTANCE) == TIM8))
+ − 8789
+ − 8790 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
+ − 8791 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ − 8792 ((INSTANCE) == TIM2) || \
+ − 8793 ((INSTANCE) == TIM3) || \
+ − 8794 ((INSTANCE) == TIM4) || \
+ − 8795 ((INSTANCE) == TIM5) || \
+ − 8796 ((INSTANCE) == TIM8))
+ − 8797
+ − 8798 /************ TIM Instances : DMA requests generation (COMDE) *****************/
+ − 8799 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ − 8800 ((INSTANCE) == TIM2) || \
+ − 8801 ((INSTANCE) == TIM3) || \
+ − 8802 ((INSTANCE) == TIM4) || \
+ − 8803 ((INSTANCE) == TIM5) || \
+ − 8804 ((INSTANCE) == TIM8))
+ − 8805
+ − 8806 /******************** TIM Instances : DMA burst feature ***********************/
+ − 8807 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ − 8808 ((INSTANCE) == TIM2) || \
+ − 8809 ((INSTANCE) == TIM3) || \
+ − 8810 ((INSTANCE) == TIM4) || \
+ − 8811 ((INSTANCE) == TIM5) || \
+ − 8812 ((INSTANCE) == TIM8))
+ − 8813
+ − 8814 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+ − 8815 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ − 8816 ((INSTANCE) == TIM2) || \
+ − 8817 ((INSTANCE) == TIM3) || \
+ − 8818 ((INSTANCE) == TIM4) || \
+ − 8819 ((INSTANCE) == TIM5) || \
+ − 8820 ((INSTANCE) == TIM6) || \
+ − 8821 ((INSTANCE) == TIM7) || \
+ − 8822 ((INSTANCE) == TIM8) || \
+ − 8823 ((INSTANCE) == TIM9) || \
+ − 8824 ((INSTANCE) == TIM12))
+ − 8825
+ − 8826 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+ − 8827 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ − 8828 ((INSTANCE) == TIM2) || \
+ − 8829 ((INSTANCE) == TIM3) || \
+ − 8830 ((INSTANCE) == TIM4) || \
+ − 8831 ((INSTANCE) == TIM5) || \
+ − 8832 ((INSTANCE) == TIM8) || \
+ − 8833 ((INSTANCE) == TIM9) || \
+ − 8834 ((INSTANCE) == TIM12))
+ − 8835
+ − 8836 /********************** TIM Instances : 32 bit Counter ************************/
+ − 8837 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+ − 8838 ((INSTANCE) == TIM5))
+ − 8839
+ − 8840 /***************** TIM Instances : external trigger input availabe ************/
+ − 8841 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ − 8842 ((INSTANCE) == TIM2) || \
+ − 8843 ((INSTANCE) == TIM3) || \
+ − 8844 ((INSTANCE) == TIM4) || \
+ − 8845 ((INSTANCE) == TIM5) || \
+ − 8846 ((INSTANCE) == TIM8))
+ − 8847
+ − 8848 /****************** TIM Instances : remapping capability **********************/
+ − 8849 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ − 8850 ((INSTANCE) == TIM5) || \
+ − 8851 ((INSTANCE) == TIM11))
+ − 8852
+ − 8853 /******************* TIM Instances : output(s) available **********************/
+ − 8854 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ − 8855 ((((INSTANCE) == TIM1) && \
+ − 8856 (((CHANNEL) == TIM_CHANNEL_1) || \
+ − 8857 ((CHANNEL) == TIM_CHANNEL_2) || \
+ − 8858 ((CHANNEL) == TIM_CHANNEL_3) || \
+ − 8859 ((CHANNEL) == TIM_CHANNEL_4))) \
+ − 8860 || \
+ − 8861 (((INSTANCE) == TIM2) && \
+ − 8862 (((CHANNEL) == TIM_CHANNEL_1) || \
+ − 8863 ((CHANNEL) == TIM_CHANNEL_2) || \
+ − 8864 ((CHANNEL) == TIM_CHANNEL_3) || \
+ − 8865 ((CHANNEL) == TIM_CHANNEL_4))) \
+ − 8866 || \
+ − 8867 (((INSTANCE) == TIM3) && \
+ − 8868 (((CHANNEL) == TIM_CHANNEL_1) || \
+ − 8869 ((CHANNEL) == TIM_CHANNEL_2) || \
+ − 8870 ((CHANNEL) == TIM_CHANNEL_3) || \
+ − 8871 ((CHANNEL) == TIM_CHANNEL_4))) \
+ − 8872 || \
+ − 8873 (((INSTANCE) == TIM4) && \
+ − 8874 (((CHANNEL) == TIM_CHANNEL_1) || \
+ − 8875 ((CHANNEL) == TIM_CHANNEL_2) || \
+ − 8876 ((CHANNEL) == TIM_CHANNEL_3) || \
+ − 8877 ((CHANNEL) == TIM_CHANNEL_4))) \
+ − 8878 || \
+ − 8879 (((INSTANCE) == TIM5) && \
+ − 8880 (((CHANNEL) == TIM_CHANNEL_1) || \
+ − 8881 ((CHANNEL) == TIM_CHANNEL_2) || \
+ − 8882 ((CHANNEL) == TIM_CHANNEL_3) || \
+ − 8883 ((CHANNEL) == TIM_CHANNEL_4))) \
+ − 8884 || \
+ − 8885 (((INSTANCE) == TIM8) && \
+ − 8886 (((CHANNEL) == TIM_CHANNEL_1) || \
+ − 8887 ((CHANNEL) == TIM_CHANNEL_2) || \
+ − 8888 ((CHANNEL) == TIM_CHANNEL_3) || \
+ − 8889 ((CHANNEL) == TIM_CHANNEL_4))) \
+ − 8890 || \
+ − 8891 (((INSTANCE) == TIM9) && \
+ − 8892 (((CHANNEL) == TIM_CHANNEL_1) || \
+ − 8893 ((CHANNEL) == TIM_CHANNEL_2))) \
+ − 8894 || \
+ − 8895 (((INSTANCE) == TIM10) && \
+ − 8896 (((CHANNEL) == TIM_CHANNEL_1))) \
+ − 8897 || \
+ − 8898 (((INSTANCE) == TIM11) && \
+ − 8899 (((CHANNEL) == TIM_CHANNEL_1))) \
+ − 8900 || \
+ − 8901 (((INSTANCE) == TIM12) && \
+ − 8902 (((CHANNEL) == TIM_CHANNEL_1) || \
+ − 8903 ((CHANNEL) == TIM_CHANNEL_2))) \
+ − 8904 || \
+ − 8905 (((INSTANCE) == TIM13) && \
+ − 8906 (((CHANNEL) == TIM_CHANNEL_1))) \
+ − 8907 || \
+ − 8908 (((INSTANCE) == TIM14) && \
+ − 8909 (((CHANNEL) == TIM_CHANNEL_1))))
+ − 8910
+ − 8911 /************ TIM Instances : complementary output(s) available ***************/
+ − 8912 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ − 8913 ((((INSTANCE) == TIM1) && \
+ − 8914 (((CHANNEL) == TIM_CHANNEL_1) || \
+ − 8915 ((CHANNEL) == TIM_CHANNEL_2) || \
+ − 8916 ((CHANNEL) == TIM_CHANNEL_3))) \
+ − 8917 || \
+ − 8918 (((INSTANCE) == TIM8) && \
+ − 8919 (((CHANNEL) == TIM_CHANNEL_1) || \
+ − 8920 ((CHANNEL) == TIM_CHANNEL_2) || \
+ − 8921 ((CHANNEL) == TIM_CHANNEL_3))))
+ − 8922
+ − 8923 /******************** USART Instances : Synchronous mode **********************/
+ − 8924 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ − 8925 ((INSTANCE) == USART2) || \
+ − 8926 ((INSTANCE) == USART3) || \
+ − 8927 ((INSTANCE) == USART6))
+ − 8928
+ − 8929 /******************** UART Instances : Asynchronous mode **********************/
+ − 8930 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ − 8931 ((INSTANCE) == USART2) || \
+ − 8932 ((INSTANCE) == USART3) || \
+ − 8933 ((INSTANCE) == UART4) || \
+ − 8934 ((INSTANCE) == UART5) || \
+ − 8935 ((INSTANCE) == USART6) || \
+ − 8936 ((INSTANCE) == UART7) || \
+ − 8937 ((INSTANCE) == UART8))
+ − 8938
+ − 8939 /****************** UART Instances : Hardware Flow control ********************/
+ − 8940 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ − 8941 ((INSTANCE) == USART2) || \
+ − 8942 ((INSTANCE) == USART3) || \
+ − 8943 ((INSTANCE) == USART6))
+ − 8944
+ − 8945 /********************* UART Instances : Smard card mode ***********************/
+ − 8946 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ − 8947 ((INSTANCE) == USART2) || \
+ − 8948 ((INSTANCE) == USART3) || \
+ − 8949 ((INSTANCE) == USART6))
+ − 8950
+ − 8951 /*********************** UART Instances : IRDA mode ***************************/
+ − 8952 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ − 8953 ((INSTANCE) == USART2) || \
+ − 8954 ((INSTANCE) == USART3) || \
+ − 8955 ((INSTANCE) == UART4) || \
+ − 8956 ((INSTANCE) == UART5) || \
+ − 8957 ((INSTANCE) == USART6) || \
+ − 8958 ((INSTANCE) == UART7) || \
+ − 8959 ((INSTANCE) == UART8))
+ − 8960
+ − 8961 /****************************** IWDG Instances ********************************/
+ − 8962 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+ − 8963
+ − 8964 /****************************** WWDG Instances ********************************/
+ − 8965 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+ − 8966
+ − 8967 /****************************** SDIO Instances ********************************/
+ − 8968 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+ − 8969
+ − 8970 /****************************** USB Exported Constants ************************/
+ − 8971 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8
+ − 8972 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4 /* Including EP0 */
+ − 8973 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4 /* Including EP0 */
+ − 8974 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */
+ − 8975
+ − 8976 #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12
+ − 8977 #define USB_OTG_HS_MAX_IN_ENDPOINTS 6 /* Including EP0 */
+ − 8978 #define USB_OTG_HS_MAX_IN_ENDPOINTS 6 /* Including EP0 */
+ − 8979 #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096 /* in Bytes */
+ − 8980
+ − 8981 /******************************************************************************/
+ − 8982 /* For a painless codes migration between the STM32F4xx device product */
+ − 8983 /* lines, the aliases defined below are put in place to overcome the */
+ − 8984 /* differences in the interrupt handlers and IRQn definitions. */
+ − 8985 /* No need to update developed interrupt code when moving across */
+ − 8986 /* product lines within the same STM32F4 Family */
+ − 8987 /******************************************************************************/
+ − 8988
+ − 8989 /* Aliases for __IRQn */
+ − 8990 #define FSMC_IRQn FMC_IRQn
+ − 8991
+ − 8992 /* Aliases for __IRQHandler */
+ − 8993 #define FSMC_IRQHandler FMC_IRQHandler
+ − 8994
+ − 8995 /**
+ − 8996 * @}
+ − 8997 */
+ − 8998
+ − 8999 /**
+ − 9000 * @}
+ − 9001 */
+ − 9002
+ − 9003 /**
+ − 9004 * @}
+ − 9005 */
+ − 9006
+ − 9007 #ifdef __cplusplus
+ − 9008 }
+ − 9009 #endif /* __cplusplus */
+ − 9010
+ − 9011 #endif /* __STM32F429xx_H */
+ − 9012
+ − 9013
+ − 9014
+ − 9015 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/