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annotate Common/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cec.h @ 335:c11ce8c885d3 PressureMeasure_Improvment

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Use average calculation for pressure: precondition was that pressure values jittered +- 10 HPa from one capture (once a second) to the other. Basically pressure is measured several times a second => using these values in an additional history calculation reduces the jitter down to +-1 per second Additionaly a similar function has been added to the surface pressure capture to further reduce the jitter in long therm measurements (once a minute)
author ideenmodellierer
date Tue, 13 Aug 2019 21:46:26 +0200
parents c78bcbd5deda
children
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128
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1 /**
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2 ******************************************************************************
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3 * @file stm32f4xx_hal_cec.h
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4 * @author MCD Application Team
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5 * @brief Header file of CEC HAL module.
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6 ******************************************************************************
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7 * @attention
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8 *
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9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
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10 *
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11 * Redistribution and use in source and binary forms, with or without modification,
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12 * are permitted provided that the following conditions are met:
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13 * 1. Redistributions of source code must retain the above copyright notice,
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14 * this list of conditions and the following disclaimer.
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15 * 2. Redistributions in binary form must reproduce the above copyright notice,
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16 * this list of conditions and the following disclaimer in the documentation
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17 * and/or other materials provided with the distribution.
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18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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19 * may be used to endorse or promote products derived from this software
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20 * without specific prior written permission.
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21 *
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22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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32 *
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33 ******************************************************************************
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34 */
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35
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36 /* Define to prevent recursive inclusion -------------------------------------*/
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37 #ifndef __STM32F4xx_HAL_CEC_H
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38 #define __STM32F4xx_HAL_CEC_H
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39
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40 #ifdef __cplusplus
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41 extern "C" {
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42 #endif
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43
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44 #if defined(STM32F446xx)
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45 /* Includes ------------------------------------------------------------------*/
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46 #include "stm32f4xx_hal_def.h"
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47
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48 /** @addtogroup STM32F4xx_HAL_Driver
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49 * @{
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50 */
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51
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52 /** @addtogroup CEC
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53 * @{
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54 */
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55
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56 /* Exported types ------------------------------------------------------------*/
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57 /** @defgroup CEC_Exported_Types CEC Exported Types
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58 * @{
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59 */
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60
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61 /**
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62 * @brief CEC Init Structure definition
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63 */
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64 typedef struct
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65 {
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66 uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time.
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67 It can be one of @ref CEC_Signal_Free_Time
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68 and belongs to the set {0,...,7} where
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69 0x0 is the default configuration
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70 else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */
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71
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72 uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,
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73 it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE
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74 or CEC_EXTENDED_TOLERANCE */
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75
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76 uint32_t BRERxStop; /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception.
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77 CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
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78 CEC_RX_STOP_ON_BRE: reception is stopped. */
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79
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80 uint32_t BREErrorBitGen; /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the
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81 CEC line upon Bit Rising Error detection.
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82 CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.
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83 CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */
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84
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85 uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the
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86 CEC line upon Long Bit Period Error detection.
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87 CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation.
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88 CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */
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89
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90 uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line
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91 upon an error detected on a broadcast message.
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92
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93 It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:
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94
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95 1) CEC_BROADCASTERROR_ERRORBIT_GENERATION.
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96 a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE
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97 and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
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98 b) LBPE detection: error-bit generation on the CEC line
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99 if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.
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100
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101 2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.
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102 no error-bit generation in case neither a) nor b) are satisfied. Additionally,
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103 there is no error-bit generation in case of Short Bit Period Error detection in
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104 a broadcast message while LSTN bit is set. */
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105
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106 uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.
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107 CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software.
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108 CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */
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109
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110 uint32_t ListenMode; /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:
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111
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112 CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its
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113 own address (OAR). Messages addressed to different destination are ignored.
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114 Broadcast messages are always received.
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115
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116 CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own
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117 address (OAR) with positive acknowledge. Messages addressed to different destination
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118 are received, but without interfering with the CEC bus: no acknowledge sent. */
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119
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120 uint16_t OwnAddress; /*!< Own addresses configuration
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121 This parameter can be a value of @ref CEC_OWN_ADDRESS */
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122
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123 uint8_t *RxBuffer; /*!< CEC Rx buffer pointeur */
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124
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125
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126 }CEC_InitTypeDef;
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127
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128 /**
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129 * @brief HAL CEC State structures definition
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130 * @note HAL CEC State value is a combination of 2 different substates: gState and RxState.
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131 * - gState contains CEC state information related to global Handle management
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132 * and also information related to Tx operations.
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133 * gState value coding follow below described bitmap :
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134 * b7 (not used)
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135 * x : Should be set to 0
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136 * b6 Error information
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137 * 0 : No Error
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138 * 1 : Error
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139 * b5 IP initilisation status
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140 * 0 : Reset (IP not initialized)
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141 * 1 : Init done (IP initialized. HAL CEC Init function already called)
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142 * b4-b3 (not used)
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143 * xx : Should be set to 00
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144 * b2 Intrinsic process state
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145 * 0 : Ready
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146 * 1 : Busy (IP busy with some configuration or internal operations)
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147 * b1 (not used)
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148 * x : Should be set to 0
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149 * b0 Tx state
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150 * 0 : Ready (no Tx operation ongoing)
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151 * 1 : Busy (Tx operation ongoing)
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152 * - RxState contains information related to Rx operations.
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153 * RxState value coding follow below described bitmap :
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154 * b7-b6 (not used)
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155 * xx : Should be set to 00
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156 * b5 IP initilisation status
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157 * 0 : Reset (IP not initialized)
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158 * 1 : Init done (IP initialized)
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159 * b4-b2 (not used)
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160 * xxx : Should be set to 000
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161 * b1 Rx state
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162 * 0 : Ready (no Rx operation ongoing)
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163 * 1 : Busy (Rx operation ongoing)
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164 * b0 (not used)
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165 * x : Should be set to 0.
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166 */
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167 typedef enum
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168 {
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169 HAL_CEC_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
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170 Value is allowed for gState and RxState */
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171 HAL_CEC_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
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172 Value is allowed for gState and RxState */
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173 HAL_CEC_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
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174 Value is allowed for gState only */
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175 HAL_CEC_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
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176 Value is allowed for RxState only */
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177 HAL_CEC_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
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178 Value is allowed for gState only */
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179 HAL_CEC_STATE_ERROR = 0x60U /*!< Error Value is allowed for gState only */
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180 }HAL_CEC_StateTypeDef;
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181
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182 /**
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183 * @brief CEC handle Structure definition
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184 */
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185 typedef struct
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186 {
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187 CEC_TypeDef *Instance; /*!< CEC registers base address */
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188
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189 CEC_InitTypeDef Init; /*!< CEC communication parameters */
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190
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191 uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */
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192
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193 uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */
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194
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195 uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */
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196
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197 HAL_LockTypeDef Lock; /*!< Locking object */
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198
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199 HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management
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200 and also related to Tx operations.
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201 This parameter can be a value of @ref HAL_CEC_StateTypeDef */
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202
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203 HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations.
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204 This parameter can be a value of @ref HAL_CEC_StateTypeDef */
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205
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206 uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register
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207 in case error is reported */
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208 }CEC_HandleTypeDef;
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209 /**
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210 * @}
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211 */
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212
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213 /* Exported constants --------------------------------------------------------*/
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214 /** @defgroup CEC_Exported_Constants CEC Exported Constants
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215 * @{
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216 */
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217
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218 /** @defgroup CEC_Error_Code CEC Error Code
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219 * @{
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220 */
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221 #define HAL_CEC_ERROR_NONE 0x00000000U /*!< no error */
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222 #define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR /*!< CEC Rx-Overrun */
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223 #define HAL_CEC_ERROR_BRE CEC_ISR_BRE /*!< CEC Rx Bit Rising Error */
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224 #define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE /*!< CEC Rx Short Bit period Error */
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225 #define HAL_CEC_ERROR_LBPE CEC_ISR_LBPE /*!< CEC Rx Long Bit period Error */
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226 #define HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE /*!< CEC Rx Missing Acknowledge */
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227 #define HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST /*!< CEC Arbitration Lost */
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228 #define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR /*!< CEC Tx-Buffer Underrun */
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229 #define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR /*!< CEC Tx-Error */
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230 #define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE /*!< CEC Tx Missing Acknowledge */
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231 /**
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232 * @}
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233 */
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234
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235 /** @defgroup CEC_Signal_Free_Time CEC Signal Free Time setting parameter
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236 * @{
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237 */
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238 #define CEC_DEFAULT_SFT 0x00000000U
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239 #define CEC_0_5_BITPERIOD_SFT 0x00000001U
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240 #define CEC_1_5_BITPERIOD_SFT 0x00000002U
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241 #define CEC_2_5_BITPERIOD_SFT 0x00000003U
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242 #define CEC_3_5_BITPERIOD_SFT 0x00000004U
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243 #define CEC_4_5_BITPERIOD_SFT 0x00000005U
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244 #define CEC_5_5_BITPERIOD_SFT 0x00000006U
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245 #define CEC_6_5_BITPERIOD_SFT 0x00000007U
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246 /**
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247 * @}
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248 */
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249
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250 /** @defgroup CEC_Tolerance CEC Receiver Tolerance
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251 * @{
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252 */
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253 #define CEC_STANDARD_TOLERANCE 0x00000000U
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254 #define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)
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255 /**
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256 * @}
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257 */
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258
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259 /** @defgroup CEC_BRERxStop CEC Reception Stop on Error
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260 * @{
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261 */
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262 #define CEC_NO_RX_STOP_ON_BRE 0x00000000U
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263 #define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)
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264 /**
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265 * @}
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266 */
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267
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268 /** @defgroup CEC_BREErrorBitGen CEC Error Bit Generation if Bit Rise Error reported
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269 * @{
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270 */
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271 #define CEC_BRE_ERRORBIT_NO_GENERATION 0x00000000U
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272 #define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)
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273 /**
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274 * @}
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275 */
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276
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277 /** @defgroup CEC_LBPEErrorBitGen CEC Error Bit Generation if Long Bit Period Error reported
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278 * @{
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279 */
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280 #define CEC_LBPE_ERRORBIT_NO_GENERATION 0x00000000U
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281 #define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)
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282 /**
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283 * @}
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284 */
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285
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286 /** @defgroup CEC_BroadCastMsgErrorBitGen CEC Error Bit Generation on Broadcast message
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287 * @{
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288 */
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289 #define CEC_BROADCASTERROR_ERRORBIT_GENERATION 0x00000000U
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290 #define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)
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291 /**
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292 * @}
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293 */
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294
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295 /** @defgroup CEC_SFT_Option CEC Signal Free Time start option
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296 * @{
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297 */
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298 #define CEC_SFT_START_ON_TXSOM 0x00000000U
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299 #define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)
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300 /**
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301 * @}
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302 */
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303
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304 /** @defgroup CEC_Listening_Mode CEC Listening mode option
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305 * @{
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306 */
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307 #define CEC_REDUCED_LISTENING_MODE 0x00000000U
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308 #define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)
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309 /**
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310 * @}
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311 */
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312
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313 /** @defgroup CEC_OAR_Position CEC Device Own Address position in CEC CFGR register
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314 * @{
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315 */
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316 #define CEC_CFGR_OAR_LSB_POS 16U
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317 /**
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318 * @}
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319 */
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320
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321 /** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header
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322 * @{
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323 */
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324 #define CEC_INITIATOR_LSB_POS 4U
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325 /**
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326 * @}
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327 */
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328
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329 /** @defgroup CEC_OWN_ADDRESS CEC Own Address
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330 * @{
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331 */
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332 #define CEC_OWN_ADDRESS_NONE ((uint16_t)0x0000) /* Reset value */
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333 #define CEC_OWN_ADDRESS_0 ((uint16_t)0x0001) /* Logical Address 0 */
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334 #define CEC_OWN_ADDRESS_1 ((uint16_t)0x0002) /* Logical Address 1 */
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335 #define CEC_OWN_ADDRESS_2 ((uint16_t)0x0004) /* Logical Address 2 */
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336 #define CEC_OWN_ADDRESS_3 ((uint16_t)0x0008) /* Logical Address 3 */
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337 #define CEC_OWN_ADDRESS_4 ((uint16_t)0x0010) /* Logical Address 4 */
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338 #define CEC_OWN_ADDRESS_5 ((uint16_t)0x0020) /* Logical Address 5 */
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339 #define CEC_OWN_ADDRESS_6 ((uint16_t)0x0040) /* Logical Address 6 */
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340 #define CEC_OWN_ADDRESS_7 ((uint16_t)0x0080) /* Logical Address 7 */
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341 #define CEC_OWN_ADDRESS_8 ((uint16_t)0x0100) /* Logical Address 9 */
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342 #define CEC_OWN_ADDRESS_9 ((uint16_t)0x0200) /* Logical Address 10 */
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343 #define CEC_OWN_ADDRESS_10 ((uint16_t)0x0400) /* Logical Address 11 */
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344 #define CEC_OWN_ADDRESS_11 ((uint16_t)0x0800) /* Logical Address 12 */
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345 #define CEC_OWN_ADDRESS_12 ((uint16_t)0x1000) /* Logical Address 13 */
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346 #define CEC_OWN_ADDRESS_13 ((uint16_t)0x2000) /* Logical Address 14 */
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347 #define CEC_OWN_ADDRESS_14 ((uint16_t)0x4000) /* Logical Address 15 */
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348 /**
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349 * @}
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350 */
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351
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352 /** @defgroup CEC_Interrupts_Definitions CEC Interrupts definition
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353 * @{
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354 */
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355 #define CEC_IT_TXACKE CEC_IER_TXACKEIE
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356 #define CEC_IT_TXERR CEC_IER_TXERRIE
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357 #define CEC_IT_TXUDR CEC_IER_TXUDRIE
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358 #define CEC_IT_TXEND CEC_IER_TXENDIE
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359 #define CEC_IT_TXBR CEC_IER_TXBRIE
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360 #define CEC_IT_ARBLST CEC_IER_ARBLSTIE
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361 #define CEC_IT_RXACKE CEC_IER_RXACKEIE
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362 #define CEC_IT_LBPE CEC_IER_LBPEIE
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363 #define CEC_IT_SBPE CEC_IER_SBPEIE
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364 #define CEC_IT_BRE CEC_IER_BREIE
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365 #define CEC_IT_RXOVR CEC_IER_RXOVRIE
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366 #define CEC_IT_RXEND CEC_IER_RXENDIE
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367 #define CEC_IT_RXBR CEC_IER_RXBRIE
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368 /**
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369 * @}
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370 */
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371
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372 /** @defgroup CEC_Flags_Definitions CEC Flags definition
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373 * @{
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374 */
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375 #define CEC_FLAG_TXACKE CEC_ISR_TXACKE
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376 #define CEC_FLAG_TXERR CEC_ISR_TXERR
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377 #define CEC_FLAG_TXUDR CEC_ISR_TXUDR
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378 #define CEC_FLAG_TXEND CEC_ISR_TXEND
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379 #define CEC_FLAG_TXBR CEC_ISR_TXBR
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380 #define CEC_FLAG_ARBLST CEC_ISR_ARBLST
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381 #define CEC_FLAG_RXACKE CEC_ISR_RXACKE
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382 #define CEC_FLAG_LBPE CEC_ISR_LBPE
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383 #define CEC_FLAG_SBPE CEC_ISR_SBPE
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384 #define CEC_FLAG_BRE CEC_ISR_BRE
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385 #define CEC_FLAG_RXOVR CEC_ISR_RXOVR
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386 #define CEC_FLAG_RXEND CEC_ISR_RXEND
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387 #define CEC_FLAG_RXBR CEC_ISR_RXBR
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388 /**
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389 * @}
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390 */
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391
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392 /** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags
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393 * @{
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394 */
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395 #define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
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396 CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
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397 /**
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398 * @}
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399 */
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400
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401 /** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag
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402 * @{
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403 */
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404 #define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
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405 /**
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406 * @}
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407 */
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408
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409 /** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag
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410 * @{
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411 */
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412 #define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
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413 /**
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414 * @}
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415 */
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416
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417 /**
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418 * @}
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419 */
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420
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421 /* Exported macros -----------------------------------------------------------*/
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422 /** @defgroup CEC_Exported_Macros CEC Exported Macros
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423 * @{
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424 */
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425
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426 /** @brief Reset CEC handle gstate & RxState
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427 * @param __HANDLE__ CEC handle.
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428 * @retval None
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429 */
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430 #define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
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431 (__HANDLE__)->gState = HAL_CEC_STATE_RESET; \
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432 (__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \
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433 } while(0)
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434
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435 /** @brief Checks whether or not the specified CEC interrupt flag is set.
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436 * @param __HANDLE__ specifies the CEC Handle.
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437 * @param __FLAG__ specifies the flag to check.
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438 * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
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439 * @arg CEC_FLAG_TXERR: Tx Error.
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440 * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
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441 * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
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442 * @arg CEC_FLAG_TXBR: Tx-Byte Request.
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443 * @arg CEC_FLAG_ARBLST: Arbitration Lost
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444 * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
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445 * @arg CEC_FLAG_LBPE: Rx Long period Error
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446 * @arg CEC_FLAG_SBPE: Rx Short period Error
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447 * @arg CEC_FLAG_BRE: Rx Bit Rising Error
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448 * @arg CEC_FLAG_RXOVR: Rx Overrun.
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449 * @arg CEC_FLAG_RXEND: End Of Reception.
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450 * @arg CEC_FLAG_RXBR: Rx-Byte Received.
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451 * @retval ITStatus
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452 */
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453 #define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
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454
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455 /** @brief Clears the interrupt or status flag when raised (write at 1)
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456 * @param __HANDLE__ specifies the CEC Handle.
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457 * @param __FLAG__ specifies the interrupt/status flag to clear.
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458 * This parameter can be one of the following values:
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459 * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
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460 * @arg CEC_FLAG_TXERR: Tx Error.
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461 * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
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462 * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
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463 * @arg CEC_FLAG_TXBR: Tx-Byte Request.
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464 * @arg CEC_FLAG_ARBLST: Arbitration Lost
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465 * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
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466 * @arg CEC_FLAG_LBPE: Rx Long period Error
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467 * @arg CEC_FLAG_SBPE: Rx Short period Error
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468 * @arg CEC_FLAG_BRE: Rx Bit Rising Error
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469 * @arg CEC_FLAG_RXOVR: Rx Overrun.
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470 * @arg CEC_FLAG_RXEND: End Of Reception.
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471 * @arg CEC_FLAG_RXBR: Rx-Byte Received.
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472 * @retval none
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473 */
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474 #define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__))
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475
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476 /** @brief Enables the specified CEC interrupt.
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477 * @param __HANDLE__ specifies the CEC Handle.
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478 * @param __INTERRUPT__ specifies the CEC interrupt to enable.
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479 * This parameter can be one of the following values:
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480 * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
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481 * @arg CEC_IT_TXERR: Tx Error IT Enable
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482 * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
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483 * @arg CEC_IT_TXEND: End of transmission IT Enable
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484 * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
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485 * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
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486 * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
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487 * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
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488 * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
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489 * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
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490 * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
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491 * @arg CEC_IT_RXEND: End Of Reception IT Enable
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492 * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
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493 * @retval none
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494 */
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495 #define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
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496
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497 /** @brief Disables the specified CEC interrupt.
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498 * @param __HANDLE__ specifies the CEC Handle.
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499 * @param __INTERRUPT__ specifies the CEC interrupt to disable.
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500 * This parameter can be one of the following values:
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501 * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
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502 * @arg CEC_IT_TXERR: Tx Error IT Enable
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503 * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
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504 * @arg CEC_IT_TXEND: End of transmission IT Enable
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505 * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
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506 * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
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507 * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
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508 * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
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509 * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
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510 * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
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511 * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
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512 * @arg CEC_IT_RXEND: End Of Reception IT Enable
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513 * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
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514 * @retval none
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515 */
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516 #define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
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517
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518 /** @brief Checks whether or not the specified CEC interrupt is enabled.
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519 * @param __HANDLE__ specifies the CEC Handle.
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520 * @param __INTERRUPT__ specifies the CEC interrupt to check.
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521 * This parameter can be one of the following values:
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522 * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
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523 * @arg CEC_IT_TXERR: Tx Error IT Enable
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524 * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
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525 * @arg CEC_IT_TXEND: End of transmission IT Enable
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526 * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
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527 * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
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528 * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
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529 * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
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530 * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
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531 * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
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532 * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
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533 * @arg CEC_IT_RXEND: End Of Reception IT Enable
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534 * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
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535 * @retval FlagStatus
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536 */
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537 #define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
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538
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539 /** @brief Enables the CEC device
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540 * @param __HANDLE__ specifies the CEC Handle.
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541 * @retval none
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542 */
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543 #define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)
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544
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545 /** @brief Disables the CEC device
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546 * @param __HANDLE__ specifies the CEC Handle.
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547 * @retval none
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548 */
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549 #define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)
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550
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551 /** @brief Set Transmission Start flag
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552 * @param __HANDLE__ specifies the CEC Handle.
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553 * @retval none
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554 */
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555 #define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)
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556
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557 /** @brief Set Transmission End flag
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558 * @param __HANDLE__ specifies the CEC Handle.
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559 * @retval none
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560 * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.
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561 */
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562 #define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)
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563
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564 /** @brief Get Transmission Start flag
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565 * @param __HANDLE__ specifies the CEC Handle.
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566 * @retval FlagStatus
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567 */
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568 #define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
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569
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570 /** @brief Get Transmission End flag
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571 * @param __HANDLE__ specifies the CEC Handle.
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572 * @retval FlagStatus
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573 */
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574 #define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
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575
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576 /** @brief Clear OAR register
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577 * @param __HANDLE__ specifies the CEC Handle.
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578 * @retval none
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579 */
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580 #define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
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581
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582 /** @brief Set OAR register (without resetting previously set address in case of multi-address mode)
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583 * To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand
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584 * @param __HANDLE__ specifies the CEC Handle.
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585 * @param __ADDRESS__ Own Address value (CEC logical address is identified by bit position)
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586 * @retval none
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587 */
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588 #define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
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589
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590 /**
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591 * @}
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592 */
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593
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594 /* Exported functions --------------------------------------------------------*/
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595 /** @addtogroup CEC_Exported_Functions
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596 * @{
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597 */
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598
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599 /** @addtogroup CEC_Exported_Functions_Group1
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600 * @{
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601 */
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602 /* Initialization and de-initialization functions ****************************/
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603 HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
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604 HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
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605 HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress);
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606 void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
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607 void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
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608 /**
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609 * @}
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610 */
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611
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612 /** @addtogroup CEC_Exported_Functions_Group2
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613 * @{
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614 */
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615 /* I/O operation functions ***************************************************/
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616 HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
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617 uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec);
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618 void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer);
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619 void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
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620 void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
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621 void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize);
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622 void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
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623 /**
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624 * @}
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625 */
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626
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627 /** @addtogroup CEC_Exported_Functions_Group3
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628 * @{
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629 */
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630 /* Peripheral State functions ************************************************/
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631 HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
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632 uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
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633 /**
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634 * @}
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635 */
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636
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637 /**
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638 * @}
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639 */
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640
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641 /* Private types -------------------------------------------------------------*/
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642 /** @defgroup CEC_Private_Types CEC Private Types
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643 * @{
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644 */
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645
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646 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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647 * @}
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648 */
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649
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650 /* Private variables ---------------------------------------------------------*/
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651 /** @defgroup CEC_Private_Variables CEC Private Variables
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652 * @{
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653 */
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654
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655 /**
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656 * @}
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657 */
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658
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659 /* Private constants ---------------------------------------------------------*/
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660 /** @defgroup CEC_Private_Constants CEC Private Constants
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661 * @{
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662 */
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663
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664 /**
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665 * @}
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666 */
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667
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668 /* Private macros ------------------------------------------------------------*/
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669 /** @defgroup CEC_Private_Macros CEC Private Macros
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670 * @{
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671 */
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672
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673 #define IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT)
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674
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675 #define IS_CEC_TOLERANCE(__RXTOL__) (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \
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676 ((__RXTOL__) == CEC_EXTENDED_TOLERANCE))
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677
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678 #define IS_CEC_BRERXSTOP(__BRERXSTOP__) (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \
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679 ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))
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680
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681 #define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \
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682 ((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION))
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683
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684 #define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
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685 ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))
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686
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687 #define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
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688 ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
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689
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690 #define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \
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691 ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))
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692
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693 #define IS_CEC_LISTENING_MODE(__MODE__) (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \
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694 ((__MODE__) == CEC_FULL_LISTENING_MODE))
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695
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696 /** @brief Check CEC message size.
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697 * The message size is the payload size: without counting the header,
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698 * it varies from 0 byte (ping operation, one header only, no payload) to
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699 * 15 bytes (1 opcode and up to 14 operands following the header).
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700 * @param __SIZE__ CEC message size.
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701 * @retval Test result (TRUE or FALSE).
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702 */
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703 #define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)
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704
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705 /** @brief Check CEC device Own Address Register (OAR) setting.
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706 * OAR address is written in a 15-bit field within CEC_CFGR register.
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707 * @param __ADDRESS__ CEC own address.
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708 * @retval Test result (TRUE or FALSE).
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709 */
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710 #define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU)
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711
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712 /** @brief Check CEC initiator or destination logical address setting.
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713 * Initiator and destination addresses are coded over 4 bits.
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714 * @param __ADDRESS__ CEC initiator or logical address.
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715 * @retval Test result (TRUE or FALSE).
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716 */
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717 #define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0FU)
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718 /**
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719 * @}
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720 */
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721 /* Private functions ---------------------------------------------------------*/
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722 /** @defgroup CEC_Private_Functions CEC Private Functions
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723 * @{
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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724 */
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725
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726 /**
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727 * @}
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728 */
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729
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730 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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731 * @}
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732 */
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733
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734 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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735 * @}
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736 */
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737 #endif /* STM32F446xx */
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738
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739 #ifdef __cplusplus
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740 }
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741 #endif
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742
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743 #endif /* __STM32F4xx_HAL_CEC_H */
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744
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745 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/