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38
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1 /**
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2 ******************************************************************************
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3 * @file compass_LSM303D.h
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4 * @author heinrichs weikamp gmbh, based on PX4 lsm303d.cpp
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5 * @date 15-March-2016
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6 * @version V0.1.0
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7 * @since 15-March-2016
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8 * @brief STMicroelectronics LSM303D accelerometer & magnetometer driver
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9 *
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10 @verbatim
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11 ==============================================================================
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12 ##### How to use #####
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13 ==============================================================================
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14 @endverbatim
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15 ******************************************************************************
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16 * @attention
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17 *
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18 * <h2><center>© COPYRIGHT(c) 2016 heinrichs weikamp</center></h2>
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19 *
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20 ******************************************************************************
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21 */
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22
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23 /* Define to prevent recursive inclusion -------------------------------------*/
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24 #ifndef COMPASS_LSM303D_H
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25 #define COMPASS_LSM303D_H
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26
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27 /* Exported constants --------------------------------------------------------*/
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28
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29 #define WHO_AM_I 0x0F // device identification register - default value
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30 #define WHOIAM_VALUE (0x49) // Who Am I default value
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31
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32 #define ADDR_OUT_TEMP_L 0x05
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33 #define ADDR_OUT_TEMP_H 0x06
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34 #define ADDR_STATUS_M 0x07
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35 #define ADDR_OUT_X_L_M 0x08
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36 #define ADDR_OUT_X_H_M 0x09
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37 #define ADDR_OUT_Y_L_M 0x0A
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38 #define ADDR_OUT_Y_H_M 0x0B
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39 #define ADDR_OUT_Z_L_M 0x0C
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40 #define ADDR_OUT_Z_H_M 0x0D
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41
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42 #define ADDR_INT_CTRL_M 0x12
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43 #define ADDR_INT_SRC_M 0x13
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44
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45 #define ADDR_INT_THS_L_M 0x14
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46 #define ADDR_INT_THS_H_M 0x15
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47
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48 #define ADDR_OFFSET_X_L_M 0x16
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49 #define ADDR_OFFSET_X_H_M 0x17
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50 #define ADDR_OFFSET_Y_L_M 0x18
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51 #define ADDR_OFFSET_Y_H_M 0x19
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52 #define ADDR_OFFSET_Z_L_M 0x1a
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53 #define ADDR_OFFSET_Z_H_M 0x1b
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54
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55 #define ADDR_REFERENCE_X 0x1c
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56 #define ADDR_REFERENCE_Y 0x1d
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57 #define ADDR_REFERENCE_Z 0x1e
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58
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59 #define ADDR_STATUS_A 0x27
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60 #define ADDR_OUT_X_L_A 0x28
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61 #define ADDR_OUT_X_H_A 0x29
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62 #define ADDR_OUT_Y_L_A 0x2A
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63 #define ADDR_OUT_Y_H_A 0x2B
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64 #define ADDR_OUT_Z_L_A 0x2C
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65 #define ADDR_OUT_Z_H_A 0x2D
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66
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67 #define ADDR_CTRL_REG0 0x1F
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68 #define ADDR_CTRL_REG1 0x20
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69 #define ADDR_CTRL_REG2 0x21
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70 #define ADDR_CTRL_REG3 0x22
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71 #define ADDR_CTRL_REG4 0x23
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72 #define ADDR_CTRL_REG5 0x24
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73 #define ADDR_CTRL_REG6 0x25
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74 #define ADDR_CTRL_REG7 0x26
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75
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76 #define ADDR_FIFO_CTRL 0x2e
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77 #define ADDR_FIFO_SRC 0x2f
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78
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79 #define ADDR_IG_CFG1 0x30
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80 #define ADDR_IG_SRC1 0x31
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81 #define ADDR_IG_THS1 0x32
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82 #define ADDR_IG_DUR1 0x33
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83 #define ADDR_IG_CFG2 0x34
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84 #define ADDR_IG_SRC2 0x35
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85 #define ADDR_IG_THS2 0x36
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86 #define ADDR_IG_DUR2 0x37
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87 #define ADDR_CLICK_CFG 0x38
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88 #define ADDR_CLICK_SRC 0x39
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89 #define ADDR_CLICK_THS 0x3a
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90 #define ADDR_TIME_LIMIT 0x3b
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91 #define ADDR_TIME_LATENCY 0x3c
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92 #define ADDR_TIME_WINDOW 0x3d
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93 #define ADDR_ACT_THS 0x3e
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94 #define ADDR_ACT_DUR 0x3f
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95
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96 #define REG1_RATE_BITS_A ((1<<7) | (1<<6) | (1<<5) | (1<<4))
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97 #define REG1_POWERDOWN_A ((0<<7) | (0<<6) | (0<<5) | (0<<4))
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98 #define REG1_RATE_3_125HZ_A ((0<<7) | (0<<6) | (0<<5) | (1<<4))
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99 #define REG1_RATE_6_25HZ_A ((0<<7) | (0<<6) | (1<<5) | (0<<4))
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100 #define REG1_RATE_12_5HZ_A ((0<<7) | (0<<6) | (1<<5) | (1<<4))
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101 #define REG1_RATE_25HZ_A ((0<<7) | (1<<6) | (0<<5) | (0<<4))
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102 #define REG1_RATE_50HZ_A ((0<<7) | (1<<6) | (0<<5) | (1<<4))
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103 #define REG1_RATE_100HZ_A ((0<<7) | (1<<6) | (1<<5) | (0<<4))
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104 #define REG1_RATE_200HZ_A ((0<<7) | (1<<6) | (1<<5) | (1<<4))
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105 #define REG1_RATE_400HZ_A ((1<<7) | (0<<6) | (0<<5) | (0<<4))
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106 #define REG1_RATE_800HZ_A ((1<<7) | (0<<6) | (0<<5) | (1<<4))
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107 #define REG1_RATE_1600HZ_A ((1<<7) | (0<<6) | (1<<5) | (0<<4))
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108
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109 #define REG1_BDU_UPDATE (1<<3)
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110 #define REG1_Z_ENABLE_A (1<<2)
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111 #define REG1_Y_ENABLE_A (1<<1)
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112 #define REG1_X_ENABLE_A (1<<0)
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113
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114 #define REG2_ANTIALIAS_FILTER_BW_BITS_A ((1<<7) | (1<<6))
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115 #define REG2_AA_FILTER_BW_773HZ_A ((0<<7) | (0<<6))
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116 #define REG2_AA_FILTER_BW_194HZ_A ((0<<7) | (1<<6))
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117 #define REG2_AA_FILTER_BW_362HZ_A ((1<<7) | (0<<6))
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118 #define REG2_AA_FILTER_BW_50HZ_A ((1<<7) | (1<<6))
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119
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120 #define REG2_FULL_SCALE_BITS_A ((1<<5) | (1<<4) | (1<<3))
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121 #define REG2_FULL_SCALE_2G_A ((0<<5) | (0<<4) | (0<<3))
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122 #define REG2_FULL_SCALE_4G_A ((0<<5) | (0<<4) | (1<<3))
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123 #define REG2_FULL_SCALE_6G_A ((0<<5) | (1<<4) | (0<<3))
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124 #define REG2_FULL_SCALE_8G_A ((0<<5) | (1<<4) | (1<<3))
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125 #define REG2_FULL_SCALE_16G_A ((1<<5) | (0<<4) | (0<<3))
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126
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127 #define REG5_ENABLE_T (1<<7)
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128
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129 #define REG5_RES_HIGH_M ((1<<6) | (1<<5))
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130 #define REG5_RES_LOW_M ((0<<6) | (0<<5))
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131
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132 #define REG5_RATE_BITS_M ((1<<4) | (1<<3) | (1<<2))
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133 #define REG5_RATE_3_125HZ_M ((0<<4) | (0<<3) | (0<<2))
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134 #define REG5_RATE_6_25HZ_M ((0<<4) | (0<<3) | (1<<2))
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135 #define REG5_RATE_12_5HZ_M ((0<<4) | (1<<3) | (0<<2))
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136 #define REG5_RATE_25HZ_M ((0<<4) | (1<<3) | (1<<2))
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137 #define REG5_RATE_50HZ_M ((1<<4) | (0<<3) | (0<<2))
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138 #define REG5_RATE_100HZ_M ((1<<4) | (0<<3) | (1<<2))
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139 #define REG5_RATE_DO_NOT_USE_M ((1<<4) | (1<<3) | (0<<2))
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140
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141 #define REG6_FULL_SCALE_BITS_M ((1<<6) | (1<<5))
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142 #define REG6_FULL_SCALE_2GA_M ((0<<6) | (0<<5))
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143 #define REG6_FULL_SCALE_4GA_M ((0<<6) | (1<<5))
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144 #define REG6_FULL_SCALE_8GA_M ((1<<6) | (0<<5))
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145 #define REG6_FULL_SCALE_12GA_M ((1<<6) | (1<<5))
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146
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147 #define REG7_CONT_MODE_M ((0<<1) | (0<<0))
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148
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149 #define REG_STATUS_A_NEW_ZYXADA 0x08
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150
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151 #define INT_CTRL_M 0x12
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152 #define INT_SRC_M 0x13
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153
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154 /* default values for this device */
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155 #define LSM303D_ACCEL_DEFAULT_RANGE_G 2
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156 #define LSM303D_ACCEL_DEFAULT_RATE 10
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157
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158 #define LSM303D_ACCEL_DEFAULT_ONCHIP_FILTER_FREQ 50
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159 #define LSM303D_ACCEL_DEFAULT_DRIVER_FILTER_FREQ 30
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160 #define LSM303D_ACCEL_MAX_OUTPUT_RATE 280
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161
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162 #define LSM303D_MAG_DEFAULT_RANGE_GA 12
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163 #define LSM303D_MAG_DEFAULT_RATE 10
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164
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165 #define LSM303D_ONE_G 9.80665f
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166
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167
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168 #endif /* COMPASS_LSM303D_H */
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169
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170 /******************* (C) COPYRIGHT 2016 heinrichs weikamp *****END OF FILE****/
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