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38
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1 /**
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2 ******************************************************************************
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3 * @file startup_stm32f415xx.s
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4 * @author MCD Application Team
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5 * @version V2.2.0
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6 * @date 15-December-2014
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7 * @brief STM32F415xx Devices vector table for Atollic TrueSTUDIO toolchain.
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8 * This module performs:
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9 * - Set the initial SP
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10 * - Set the initial PC == Reset_Handler,
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11 * - Set the vector table entries with the exceptions ISR address
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12 * - Branches to main in the C library (which eventually
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13 * calls main()).
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14 * After Reset the Cortex-M4 processor is in Thread mode,
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15 * priority is Privileged, and the Stack is set to Main.
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16 ******************************************************************************
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17 * @attention
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18 *
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19 * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
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20 *
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21 * Redistribution and use in source and binary forms, with or without modification,
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22 * are permitted provided that the following conditions are met:
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23 * 1. Redistributions of source code must retain the above copyright notice,
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24 * this list of conditions and the following disclaimer.
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25 * 2. Redistributions in binary form must reproduce the above copyright notice,
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26 * this list of conditions and the following disclaimer in the documentation
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27 * and/or other materials provided with the distribution.
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28 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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29 * may be used to endorse or promote products derived from this software
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30 * without specific prior written permission.
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31 *
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32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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33 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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35 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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38 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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39 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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40 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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42 *
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43 ******************************************************************************
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44 */
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45
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46 .syntax unified
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47 .cpu cortex-m4
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48 .fpu softvfp
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49 .thumb
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50
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51 .global g_pfnVectors
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52 .global Default_Handler
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53
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54 /* start address for the initialization values of the .data section.
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55 defined in linker script */
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56 .word _sidata
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57 /* start address for the .data section. defined in linker script */
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58 .word _sdata
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59 /* end address for the .data section. defined in linker script */
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60 .word _edata
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61 /* start address for the .bss section. defined in linker script */
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62 .word _sbss
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63 /* end address for the .bss section. defined in linker script */
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64 .word _ebss
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65 /* stack used for SystemInit_ExtMemCtl; always internal RAM used */
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66
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67 /**
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68 * @brief This is the code that gets called when the processor first
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69 * starts execution following a reset event. Only the absolutely
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70 * necessary set is performed, after which the application
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71 * supplied main() routine is called.
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72 * @param None
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73 * @retval : None
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74 */
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75
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76 .section .text.Reset_Handler
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77 .weak Reset_Handler
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78 .type Reset_Handler, %function
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79 Reset_Handler:
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80 ldr sp, =_estack /* set stack pointer */
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81
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82 /* Copy the data segment initializers from flash to SRAM */
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83 movs r1, #0
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84 b LoopCopyDataInit
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85
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86 CopyDataInit:
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87 ldr r3, =_sidata
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88 ldr r3, [r3, r1]
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89 str r3, [r0, r1]
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90 adds r1, r1, #4
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91
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92 LoopCopyDataInit:
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93 ldr r0, =_sdata
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94 ldr r3, =_edata
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95 adds r2, r0, r1
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96 cmp r2, r3
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97 bcc CopyDataInit
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98 ldr r2, =_sbss
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99 b LoopFillZerobss
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100 /* Zero fill the bss segment. */
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101 FillZerobss:
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102 movs r3, #0
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103 str r3, [r2], #4
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104
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105 LoopFillZerobss:
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106 ldr r3, = _ebss
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107 cmp r2, r3
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108 bcc FillZerobss
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109
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110 /* Call the clock system intitialization function.*/
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111 bl SystemInit
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112 /* Call static constructors */
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113 bl __libc_init_array
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114 /* Call the application's entry point.*/
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115 bl main
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116 bx lr
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117 .size Reset_Handler, .-Reset_Handler
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118
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119 /**
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120 * @brief This is the code that gets called when the processor receives an
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121 * unexpected interrupt. This simply enters an infinite loop, preserving
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122 * the system state for examination by a debugger.
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123 * @param None
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124 * @retval None
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125 */
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126 .section .text.Default_Handler,"ax",%progbits
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127 Default_Handler:
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128 Infinite_Loop:
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129 b Infinite_Loop
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130 .size Default_Handler, .-Default_Handler
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131 /******************************************************************************
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132 *
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133 * The minimal vector table for a Cortex M3. Note that the proper constructs
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134 * must be placed on this to ensure that it ends up at physical address
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135 * 0x0000.0000.
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136 *
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137 *******************************************************************************/
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138 .section .isr_vector,"a",%progbits
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139 .type g_pfnVectors, %object
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140 .size g_pfnVectors, .-g_pfnVectors
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141
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142 g_pfnVectors:
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143 .word _estack
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144 .word Reset_Handler
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145
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146 .word NMI_Handler
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147 .word HardFault_Handler
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148 .word MemManage_Handler
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149 .word BusFault_Handler
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150 .word UsageFault_Handler
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151 .word 0
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152 .word 0
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153 .word 0
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154 .word 0
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155 .word SVC_Handler
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156 .word DebugMon_Handler
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157 .word 0
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158 .word PendSV_Handler
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159 .word SysTick_Handler
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160
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161 /* External Interrupts */
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162 .word WWDG_IRQHandler /* Window WatchDog */
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163 .word PVD_IRQHandler /* PVD through EXTI Line detection */
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164 .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
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165 .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
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166 .word FLASH_IRQHandler /* FLASH */
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167 .word RCC_IRQHandler /* RCC */
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168 .word EXTI0_IRQHandler /* EXTI Line0 */
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169 .word EXTI1_IRQHandler /* EXTI Line1 */
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170 .word EXTI2_IRQHandler /* EXTI Line2 */
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171 .word EXTI3_IRQHandler /* EXTI Line3 */
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172 .word EXTI4_IRQHandler /* EXTI Line4 */
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173 .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
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174 .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
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175 .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
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176 .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
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177 .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
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178 .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
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179 .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
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180 .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
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181 .word CAN1_TX_IRQHandler /* CAN1 TX */
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182 .word CAN1_RX0_IRQHandler /* CAN1 RX0 */
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183 .word CAN1_RX1_IRQHandler /* CAN1 RX1 */
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184 .word CAN1_SCE_IRQHandler /* CAN1 SCE */
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185 .word EXTI9_5_IRQHandler /* External Line[9:5]s */
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186 .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
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187 .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
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188 .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
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189 .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
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190 .word TIM2_IRQHandler /* TIM2 */
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191 .word TIM3_IRQHandler /* TIM3 */
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192 .word TIM4_IRQHandler /* TIM4 */
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193 .word I2C1_EV_IRQHandler /* I2C1 Event */
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194 .word I2C1_ER_IRQHandler /* I2C1 Error */
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195 .word I2C2_EV_IRQHandler /* I2C2 Event */
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196 .word I2C2_ER_IRQHandler /* I2C2 Error */
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197 .word SPI1_IRQHandler /* SPI1 */
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198 .word SPI2_IRQHandler /* SPI2 */
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199 .word USART1_IRQHandler /* USART1 */
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200 .word USART2_IRQHandler /* USART2 */
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201 .word USART3_IRQHandler /* USART3 */
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202 .word EXTI15_10_IRQHandler /* External Line[15:10]s */
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203 .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
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204 .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
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205 .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
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206 .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
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207 .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
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208 .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
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209 .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
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210 .word FSMC_IRQHandler /* FSMC */
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211 .word SDIO_IRQHandler /* SDIO */
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212 .word TIM5_IRQHandler /* TIM5 */
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213 .word SPI3_IRQHandler /* SPI3 */
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214 .word UART4_IRQHandler /* UART4 */
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215 .word UART5_IRQHandler /* UART5 */
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216 .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
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217 .word TIM7_IRQHandler /* TIM7 */
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218 .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
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219 .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
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220 .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
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221 .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
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222 .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
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223 .word 0 /* Reserved */
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224 .word 0 /* Reserved */
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225 .word CAN2_TX_IRQHandler /* CAN2 TX */
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226 .word CAN2_RX0_IRQHandler /* CAN2 RX0 */
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227 .word CAN2_RX1_IRQHandler /* CAN2 RX1 */
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228 .word CAN2_SCE_IRQHandler /* CAN2 SCE */
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229 .word OTG_FS_IRQHandler /* USB OTG FS */
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230 .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
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231 .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
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232 .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
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233 .word USART6_IRQHandler /* USART6 */
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234 .word I2C3_EV_IRQHandler /* I2C3 event */
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235 .word I2C3_ER_IRQHandler /* I2C3 error */
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236 .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
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237 .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
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238 .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
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239 .word OTG_HS_IRQHandler /* USB OTG HS */
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240 .word 0 /* Reserved */
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241 .word CRYP_IRQHandler /* CRYP crypto */
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242 .word HASH_RNG_IRQHandler /* Hash and Rng */
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243 .word FPU_IRQHandler /* FPU */
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244
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245
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246 /*******************************************************************************
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247 *
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248 * Provide weak aliases for each Exception handler to the Default_Handler.
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249 * As they are weak aliases, any function with the same name will override
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250 * this definition.
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251 *
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252 *******************************************************************************/
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253 .weak NMI_Handler
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254 .thumb_set NMI_Handler,Default_Handler
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255
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256 .weak HardFault_Handler
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257 .thumb_set HardFault_Handler,Default_Handler
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258
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259 .weak MemManage_Handler
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260 .thumb_set MemManage_Handler,Default_Handler
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261
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262 .weak BusFault_Handler
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263 .thumb_set BusFault_Handler,Default_Handler
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264
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265 .weak UsageFault_Handler
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266 .thumb_set UsageFault_Handler,Default_Handler
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267
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268 .weak SVC_Handler
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269 .thumb_set SVC_Handler,Default_Handler
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270
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271 .weak DebugMon_Handler
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272 .thumb_set DebugMon_Handler,Default_Handler
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273
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274 .weak PendSV_Handler
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275 .thumb_set PendSV_Handler,Default_Handler
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276
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277 .weak SysTick_Handler
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278 .thumb_set SysTick_Handler,Default_Handler
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279
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280 .weak WWDG_IRQHandler
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281 .thumb_set WWDG_IRQHandler,Default_Handler
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282
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283 .weak PVD_IRQHandler
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284 .thumb_set PVD_IRQHandler,Default_Handler
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285
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286 .weak TAMP_STAMP_IRQHandler
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287 .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
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288
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289 .weak RTC_WKUP_IRQHandler
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290 .thumb_set RTC_WKUP_IRQHandler,Default_Handler
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291
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292 .weak FLASH_IRQHandler
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293 .thumb_set FLASH_IRQHandler,Default_Handler
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294
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295 .weak RCC_IRQHandler
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296 .thumb_set RCC_IRQHandler,Default_Handler
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297
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298 .weak EXTI0_IRQHandler
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299 .thumb_set EXTI0_IRQHandler,Default_Handler
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300
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301 .weak EXTI1_IRQHandler
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302 .thumb_set EXTI1_IRQHandler,Default_Handler
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303
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304 .weak EXTI2_IRQHandler
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305 .thumb_set EXTI2_IRQHandler,Default_Handler
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306
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307 .weak EXTI3_IRQHandler
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308 .thumb_set EXTI3_IRQHandler,Default_Handler
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309
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310 .weak EXTI4_IRQHandler
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311 .thumb_set EXTI4_IRQHandler,Default_Handler
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312
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313 .weak DMA1_Stream0_IRQHandler
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314 .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
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315
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316 .weak DMA1_Stream1_IRQHandler
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317 .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
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318
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319 .weak DMA1_Stream2_IRQHandler
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320 .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
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321
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322 .weak DMA1_Stream3_IRQHandler
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323 .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
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324
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325 .weak DMA1_Stream4_IRQHandler
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326 .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
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327
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328 .weak DMA1_Stream5_IRQHandler
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329 .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
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330
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331 .weak DMA1_Stream6_IRQHandler
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332 .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
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333
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334 .weak ADC_IRQHandler
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335 .thumb_set ADC_IRQHandler,Default_Handler
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336
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337 .weak CAN1_TX_IRQHandler
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338 .thumb_set CAN1_TX_IRQHandler,Default_Handler
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339
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340 .weak CAN1_RX0_IRQHandler
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341 .thumb_set CAN1_RX0_IRQHandler,Default_Handler
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342
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343 .weak CAN1_RX1_IRQHandler
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344 .thumb_set CAN1_RX1_IRQHandler,Default_Handler
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345
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346 .weak CAN1_SCE_IRQHandler
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347 .thumb_set CAN1_SCE_IRQHandler,Default_Handler
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348
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349 .weak EXTI9_5_IRQHandler
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350 .thumb_set EXTI9_5_IRQHandler,Default_Handler
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351
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352 .weak TIM1_BRK_TIM9_IRQHandler
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353 .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
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354
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355 .weak TIM1_UP_TIM10_IRQHandler
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356 .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
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357
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358 .weak TIM1_TRG_COM_TIM11_IRQHandler
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359 .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
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360
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361 .weak TIM1_CC_IRQHandler
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362 .thumb_set TIM1_CC_IRQHandler,Default_Handler
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363
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364 .weak TIM2_IRQHandler
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365 .thumb_set TIM2_IRQHandler,Default_Handler
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366
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367 .weak TIM3_IRQHandler
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368 .thumb_set TIM3_IRQHandler,Default_Handler
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369
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370 .weak TIM4_IRQHandler
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371 .thumb_set TIM4_IRQHandler,Default_Handler
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372
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373 .weak I2C1_EV_IRQHandler
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374 .thumb_set I2C1_EV_IRQHandler,Default_Handler
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375
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376 .weak I2C1_ER_IRQHandler
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377 .thumb_set I2C1_ER_IRQHandler,Default_Handler
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378
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379 .weak I2C2_EV_IRQHandler
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380 .thumb_set I2C2_EV_IRQHandler,Default_Handler
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381
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382 .weak I2C2_ER_IRQHandler
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383 .thumb_set I2C2_ER_IRQHandler,Default_Handler
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384
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385 .weak SPI1_IRQHandler
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386 .thumb_set SPI1_IRQHandler,Default_Handler
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387
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388 .weak SPI2_IRQHandler
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389 .thumb_set SPI2_IRQHandler,Default_Handler
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390
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391 .weak USART1_IRQHandler
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392 .thumb_set USART1_IRQHandler,Default_Handler
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393
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394 .weak USART2_IRQHandler
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395 .thumb_set USART2_IRQHandler,Default_Handler
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396
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397 .weak USART3_IRQHandler
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398 .thumb_set USART3_IRQHandler,Default_Handler
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399
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400 .weak EXTI15_10_IRQHandler
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401 .thumb_set EXTI15_10_IRQHandler,Default_Handler
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402
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403 .weak RTC_Alarm_IRQHandler
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404 .thumb_set RTC_Alarm_IRQHandler,Default_Handler
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405
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406 .weak OTG_FS_WKUP_IRQHandler
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407 .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
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408
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409 .weak TIM8_BRK_TIM12_IRQHandler
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410 .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
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411
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412 .weak TIM8_UP_TIM13_IRQHandler
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413 .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
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414
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415 .weak TIM8_TRG_COM_TIM14_IRQHandler
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416 .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
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417
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418 .weak TIM8_CC_IRQHandler
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419 .thumb_set TIM8_CC_IRQHandler,Default_Handler
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420
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421 .weak DMA1_Stream7_IRQHandler
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422 .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
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423
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424 .weak FSMC_IRQHandler
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425 .thumb_set FSMC_IRQHandler,Default_Handler
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426
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427 .weak SDIO_IRQHandler
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428 .thumb_set SDIO_IRQHandler,Default_Handler
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429
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430 .weak TIM5_IRQHandler
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431 .thumb_set TIM5_IRQHandler,Default_Handler
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432
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433 .weak SPI3_IRQHandler
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434 .thumb_set SPI3_IRQHandler,Default_Handler
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435
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436 .weak UART4_IRQHandler
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437 .thumb_set UART4_IRQHandler,Default_Handler
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438
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439 .weak UART5_IRQHandler
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440 .thumb_set UART5_IRQHandler,Default_Handler
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441
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442 .weak TIM6_DAC_IRQHandler
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443 .thumb_set TIM6_DAC_IRQHandler,Default_Handler
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444
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445 .weak TIM7_IRQHandler
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446 .thumb_set TIM7_IRQHandler,Default_Handler
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447
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448 .weak DMA2_Stream0_IRQHandler
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449 .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
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450
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451 .weak DMA2_Stream1_IRQHandler
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452 .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
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453
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454 .weak DMA2_Stream2_IRQHandler
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455 .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
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456
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457 .weak DMA2_Stream3_IRQHandler
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458 .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
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459
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460 .weak DMA2_Stream4_IRQHandler
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461 .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
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462
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463 .weak CAN2_TX_IRQHandler
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464 .thumb_set CAN2_TX_IRQHandler,Default_Handler
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465
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466 .weak CAN2_RX0_IRQHandler
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467 .thumb_set CAN2_RX0_IRQHandler,Default_Handler
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468
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469 .weak CAN2_RX1_IRQHandler
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470 .thumb_set CAN2_RX1_IRQHandler,Default_Handler
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471
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472 .weak CAN2_SCE_IRQHandler
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473 .thumb_set CAN2_SCE_IRQHandler,Default_Handler
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474
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475 .weak OTG_FS_IRQHandler
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|
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476 .thumb_set OTG_FS_IRQHandler,Default_Handler
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477
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478 .weak DMA2_Stream5_IRQHandler
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479 .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
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480
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481 .weak DMA2_Stream6_IRQHandler
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482 .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
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483
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484 .weak DMA2_Stream7_IRQHandler
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|
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485 .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
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486
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|
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487 .weak USART6_IRQHandler
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|
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488 .thumb_set USART6_IRQHandler,Default_Handler
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489
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490 .weak I2C3_EV_IRQHandler
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491 .thumb_set I2C3_EV_IRQHandler,Default_Handler
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492
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493 .weak I2C3_ER_IRQHandler
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494 .thumb_set I2C3_ER_IRQHandler,Default_Handler
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495
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496 .weak OTG_HS_EP1_OUT_IRQHandler
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497 .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
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498
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499 .weak OTG_HS_EP1_IN_IRQHandler
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500 .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
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501
|
|
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502 .weak OTG_HS_WKUP_IRQHandler
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|
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503 .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
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504
|
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505 .weak OTG_HS_IRQHandler
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506 .thumb_set OTG_HS_IRQHandler,Default_Handler
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507
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508 .weak CRYP_IRQHandler
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509 .thumb_set CRYP_IRQHandler,Default_Handler
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510
|
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511 .weak HASH_RNG_IRQHandler
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512 .thumb_set HASH_RNG_IRQHandler,Default_Handler
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513
|
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514 .weak FPU_IRQHandler
|
|
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515 .thumb_set FPU_IRQHandler,Default_Handler
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516
|
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517 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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518
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519
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520 |
