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38
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1 /**
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2 ******************************************************************************
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3 * @file stm32f439xx.h
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4 * @author MCD Application Team
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5 * @version V2.2.0
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6 * @date 15-December-2014
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7 * @brief CMSIS STM32F439xx Device Peripheral Access Layer Header File.
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8 *
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9 * This file contains:
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10 * - Data structures and the address mapping for all peripherals
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11 * - Peripheral's registers declarations and bits definition
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12 * - Macros to access peripheral’s registers hardware
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13 *
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14 ******************************************************************************
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15 * @attention
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16 *
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17 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
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18 *
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19 * Redistribution and use in source and binary forms, with or without modification,
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20 * are permitted provided that the following conditions are met:
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21 * 1. Redistributions of source code must retain the above copyright notice,
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22 * this list of conditions and the following disclaimer.
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23 * 2. Redistributions in binary form must reproduce the above copyright notice,
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24 * this list of conditions and the following disclaimer in the documentation
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25 * and/or other materials provided with the distribution.
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26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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27 * may be used to endorse or promote products derived from this software
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28 * without specific prior written permission.
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29 *
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30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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40 *
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41 ******************************************************************************
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42 */
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43
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44 /** @addtogroup CMSIS_Device
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45 * @{
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46 */
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47
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48 /** @addtogroup stm32f439xx
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49 * @{
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50 */
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51
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52 #ifndef __STM32F439xx_H
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53 #define __STM32F439xx_H
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54
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55 #ifdef __cplusplus
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56 extern "C" {
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57 #endif /* __cplusplus */
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58
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59 /** @addtogroup Configuration_section_for_CMSIS
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60 * @{
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61 */
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62
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63 /**
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64 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
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65 */
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66 #define __CM4_REV 0x0001 /*!< Core revision r0p1 */
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67 #define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
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68 #define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
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69 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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70 #define __FPU_PRESENT 1 /*!< FPU present */
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71
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72 /**
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73 * @}
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74 */
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75
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76 /** @addtogroup Peripheral_interrupt_number_definition
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77 * @{
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78 */
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79
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80 /**
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81 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
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82 * in @ref Library_configuration_section
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83 */
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84 typedef enum
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85 {
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86 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
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87 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
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88 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
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89 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
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90 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
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91 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
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92 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
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93 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
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94 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
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95 /****** STM32 specific Interrupt Numbers **********************************************************************/
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96 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
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97 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
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98 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
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99 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
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100 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
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101 RCC_IRQn = 5, /*!< RCC global Interrupt */
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102 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
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103 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
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104 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
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105 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
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106 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
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107 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
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108 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
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109 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
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110 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
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111 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
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112 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
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113 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
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114 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
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115 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
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116 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
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117 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
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118 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
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119 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
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120 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
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121 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
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122 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
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123 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
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124 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
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125 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
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126 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
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127 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
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128 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
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129 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
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130 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
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131 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
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132 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
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133 USART1_IRQn = 37, /*!< USART1 global Interrupt */
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134 USART2_IRQn = 38, /*!< USART2 global Interrupt */
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135 USART3_IRQn = 39, /*!< USART3 global Interrupt */
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136 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
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137 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
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138 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
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139 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
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140 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
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141 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
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142 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
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143 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
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144 FMC_IRQn = 48, /*!< FMC global Interrupt */
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145 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
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146 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
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147 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
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148 UART4_IRQn = 52, /*!< UART4 global Interrupt */
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149 UART5_IRQn = 53, /*!< UART5 global Interrupt */
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150 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
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151 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
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152 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
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153 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
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154 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
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155 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
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156 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
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157 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
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158 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
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159 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
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160 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
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161 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
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162 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
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163 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
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164 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
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165 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
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166 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
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167 USART6_IRQn = 71, /*!< USART6 global interrupt */
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168 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
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169 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
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170 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
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171 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
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172 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
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173 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
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174 DCMI_IRQn = 78, /*!< DCMI global interrupt */
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175 CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
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176 HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
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177 FPU_IRQn = 81, /*!< FPU global interrupt */
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178 UART7_IRQn = 82, /*!< UART7 global interrupt */
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179 UART8_IRQn = 83, /*!< UART8 global interrupt */
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180 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
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181 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
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182 SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
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183 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
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184 LTDC_IRQn = 88, /*!< LTDC global Interrupt */
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185 LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
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186 DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */
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187 } IRQn_Type;
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188
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189 /**
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190 * @}
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191 */
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192
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193 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
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194 #include "system_stm32f4xx.h"
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195 #include <stdint.h>
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196
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197 /** @addtogroup Peripheral_registers_structures
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198 * @{
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199 */
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200
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201 /**
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202 * @brief Analog to Digital Converter
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203 */
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204
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205 typedef struct
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206 {
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207 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
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208 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
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209 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
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210 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
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211 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
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212 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
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213 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
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214 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
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215 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
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216 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
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217 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
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218 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
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219 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
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220 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
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221 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
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222 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
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223 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
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224 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
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225 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
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226 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
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227 } ADC_TypeDef;
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228
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229 typedef struct
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230 {
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231 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
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232 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
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233 __IO uint32_t CDR; /*!< ADC common regular data register for dual
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234 AND triple modes, Address offset: ADC1 base address + 0x308 */
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235 } ADC_Common_TypeDef;
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236
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237
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238 /**
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239 * @brief Controller Area Network TxMailBox
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240 */
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241
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242 typedef struct
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243 {
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244 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
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245 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
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246 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
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247 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
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248 } CAN_TxMailBox_TypeDef;
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249
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250 /**
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251 * @brief Controller Area Network FIFOMailBox
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252 */
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253
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254 typedef struct
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255 {
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256 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
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257 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
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258 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
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259 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
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260 } CAN_FIFOMailBox_TypeDef;
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261
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262 /**
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263 * @brief Controller Area Network FilterRegister
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264 */
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265
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266 typedef struct
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267 {
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268 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
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269 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
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270 } CAN_FilterRegister_TypeDef;
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271
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272 /**
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273 * @brief Controller Area Network
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274 */
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275
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276 typedef struct
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277 {
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278 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
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279 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
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280 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
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281 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
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282 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
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283 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
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284 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
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285 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
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286 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
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287 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
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288 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
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289 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
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290 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
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291 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
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292 uint32_t RESERVED2; /*!< Reserved, 0x208 */
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293 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
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294 uint32_t RESERVED3; /*!< Reserved, 0x210 */
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295 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
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296 uint32_t RESERVED4; /*!< Reserved, 0x218 */
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297 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
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298 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
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299 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
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300 } CAN_TypeDef;
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301
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302 /**
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303 * @brief CRC calculation unit
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304 */
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305
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306 typedef struct
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307 {
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308 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
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309 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
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310 uint8_t RESERVED0; /*!< Reserved, 0x05 */
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311 uint16_t RESERVED1; /*!< Reserved, 0x06 */
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312 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
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313 } CRC_TypeDef;
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314
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315 /**
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316 * @brief Digital to Analog Converter
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317 */
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318
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319 typedef struct
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320 {
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321 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
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322 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
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323 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
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324 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
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325 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
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326 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
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327 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
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328 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
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329 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
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330 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
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331 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
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332 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
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333 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
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334 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
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335 } DAC_TypeDef;
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336
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337 /**
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338 * @brief Debug MCU
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339 */
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340
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341 typedef struct
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342 {
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343 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
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344 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
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345 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
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346 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
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347 }DBGMCU_TypeDef;
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348
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349 /**
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350 * @brief DCMI
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351 */
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352
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353 typedef struct
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354 {
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355 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
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356 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
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357 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
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358 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
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359 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
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360 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
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361 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
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362 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
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363 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
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364 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
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365 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
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366 } DCMI_TypeDef;
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367
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368 /**
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369 * @brief DMA Controller
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370 */
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371
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372 typedef struct
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373 {
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374 __IO uint32_t CR; /*!< DMA stream x configuration register */
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375 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
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376 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
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377 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
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378 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
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379 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
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380 } DMA_Stream_TypeDef;
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381
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382 typedef struct
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383 {
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384 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
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385 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
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386 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
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387 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
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|
388 } DMA_TypeDef;
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389
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390 /**
|
|
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391 * @brief DMA2D Controller
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392 */
|
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393
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394 typedef struct
|
|
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395 {
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396 __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
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|
397 __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
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|
398 __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
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|
399 __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
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|
|
400 __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
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401 __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
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|
402 __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
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|
403 __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
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|
|
404 __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
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|
|
405 __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
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|
|
406 __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
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|
|
407 __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
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|
|
408 __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
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|
|
409 __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
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|
|
410 __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
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|
|
411 __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
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|
|
412 __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
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|
413 __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
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|
414 __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
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415 __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
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|
|
416 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
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|
|
417 __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
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|
|
418 __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
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|
|
419 } DMA2D_TypeDef;
|
|
|
420
|
|
|
421 /**
|
|
|
422 * @brief Ethernet MAC
|
|
|
423 */
|
|
|
424
|
|
|
425 typedef struct
|
|
|
426 {
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|
|
427 __IO uint32_t MACCR;
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|
|
428 __IO uint32_t MACFFR;
|
|
|
429 __IO uint32_t MACHTHR;
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|
|
430 __IO uint32_t MACHTLR;
|
|
|
431 __IO uint32_t MACMIIAR;
|
|
|
432 __IO uint32_t MACMIIDR;
|
|
|
433 __IO uint32_t MACFCR;
|
|
|
434 __IO uint32_t MACVLANTR; /* 8 */
|
|
|
435 uint32_t RESERVED0[2];
|
|
|
436 __IO uint32_t MACRWUFFR; /* 11 */
|
|
|
437 __IO uint32_t MACPMTCSR;
|
|
|
438 uint32_t RESERVED1[2];
|
|
|
439 __IO uint32_t MACSR; /* 15 */
|
|
|
440 __IO uint32_t MACIMR;
|
|
|
441 __IO uint32_t MACA0HR;
|
|
|
442 __IO uint32_t MACA0LR;
|
|
|
443 __IO uint32_t MACA1HR;
|
|
|
444 __IO uint32_t MACA1LR;
|
|
|
445 __IO uint32_t MACA2HR;
|
|
|
446 __IO uint32_t MACA2LR;
|
|
|
447 __IO uint32_t MACA3HR;
|
|
|
448 __IO uint32_t MACA3LR; /* 24 */
|
|
|
449 uint32_t RESERVED2[40];
|
|
|
450 __IO uint32_t MMCCR; /* 65 */
|
|
|
451 __IO uint32_t MMCRIR;
|
|
|
452 __IO uint32_t MMCTIR;
|
|
|
453 __IO uint32_t MMCRIMR;
|
|
|
454 __IO uint32_t MMCTIMR; /* 69 */
|
|
|
455 uint32_t RESERVED3[14];
|
|
|
456 __IO uint32_t MMCTGFSCCR; /* 84 */
|
|
|
457 __IO uint32_t MMCTGFMSCCR;
|
|
|
458 uint32_t RESERVED4[5];
|
|
|
459 __IO uint32_t MMCTGFCR;
|
|
|
460 uint32_t RESERVED5[10];
|
|
|
461 __IO uint32_t MMCRFCECR;
|
|
|
462 __IO uint32_t MMCRFAECR;
|
|
|
463 uint32_t RESERVED6[10];
|
|
|
464 __IO uint32_t MMCRGUFCR;
|
|
|
465 uint32_t RESERVED7[334];
|
|
|
466 __IO uint32_t PTPTSCR;
|
|
|
467 __IO uint32_t PTPSSIR;
|
|
|
468 __IO uint32_t PTPTSHR;
|
|
|
469 __IO uint32_t PTPTSLR;
|
|
|
470 __IO uint32_t PTPTSHUR;
|
|
|
471 __IO uint32_t PTPTSLUR;
|
|
|
472 __IO uint32_t PTPTSAR;
|
|
|
473 __IO uint32_t PTPTTHR;
|
|
|
474 __IO uint32_t PTPTTLR;
|
|
|
475 __IO uint32_t RESERVED8;
|
|
|
476 __IO uint32_t PTPTSSR;
|
|
|
477 uint32_t RESERVED9[565];
|
|
|
478 __IO uint32_t DMABMR;
|
|
|
479 __IO uint32_t DMATPDR;
|
|
|
480 __IO uint32_t DMARPDR;
|
|
|
481 __IO uint32_t DMARDLAR;
|
|
|
482 __IO uint32_t DMATDLAR;
|
|
|
483 __IO uint32_t DMASR;
|
|
|
484 __IO uint32_t DMAOMR;
|
|
|
485 __IO uint32_t DMAIER;
|
|
|
486 __IO uint32_t DMAMFBOCR;
|
|
|
487 __IO uint32_t DMARSWTR;
|
|
|
488 uint32_t RESERVED10[8];
|
|
|
489 __IO uint32_t DMACHTDR;
|
|
|
490 __IO uint32_t DMACHRDR;
|
|
|
491 __IO uint32_t DMACHTBAR;
|
|
|
492 __IO uint32_t DMACHRBAR;
|
|
|
493 } ETH_TypeDef;
|
|
|
494
|
|
|
495 /**
|
|
|
496 * @brief External Interrupt/Event Controller
|
|
|
497 */
|
|
|
498
|
|
|
499 typedef struct
|
|
|
500 {
|
|
|
501 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
|
|
|
502 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
|
|
|
503 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
|
|
|
504 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
|
|
|
505 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
|
|
|
506 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
|
|
|
507 } EXTI_TypeDef;
|
|
|
508
|
|
|
509 /**
|
|
|
510 * @brief FLASH Registers
|
|
|
511 */
|
|
|
512
|
|
|
513 typedef struct
|
|
|
514 {
|
|
|
515 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
|
|
|
516 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
|
|
|
517 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
|
|
|
518 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
|
|
|
519 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
|
|
|
520 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
|
|
|
521 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
|
|
|
522 } FLASH_TypeDef;
|
|
|
523
|
|
|
524 /**
|
|
|
525 * @brief Flexible Memory Controller
|
|
|
526 */
|
|
|
527
|
|
|
528 typedef struct
|
|
|
529 {
|
|
|
530 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
|
|
|
531 } FMC_Bank1_TypeDef;
|
|
|
532
|
|
|
533 /**
|
|
|
534 * @brief Flexible Memory Controller Bank1E
|
|
|
535 */
|
|
|
536
|
|
|
537 typedef struct
|
|
|
538 {
|
|
|
539 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
|
|
|
540 } FMC_Bank1E_TypeDef;
|
|
|
541
|
|
|
542 /**
|
|
|
543 * @brief Flexible Memory Controller Bank2
|
|
|
544 */
|
|
|
545
|
|
|
546 typedef struct
|
|
|
547 {
|
|
|
548 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
|
|
|
549 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
|
|
|
550 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
|
|
|
551 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
|
|
|
552 uint32_t RESERVED0; /*!< Reserved, 0x70 */
|
|
|
553 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
|
|
|
554 uint32_t RESERVED1; /*!< Reserved, 0x78 */
|
|
|
555 uint32_t RESERVED2; /*!< Reserved, 0x7C */
|
|
|
556 __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
|
|
|
557 __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
|
|
|
558 __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
|
|
|
559 __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
|
|
|
560 uint32_t RESERVED3; /*!< Reserved, 0x90 */
|
|
|
561 __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
|
|
|
562 } FMC_Bank2_3_TypeDef;
|
|
|
563
|
|
|
564 /**
|
|
|
565 * @brief Flexible Memory Controller Bank4
|
|
|
566 */
|
|
|
567
|
|
|
568 typedef struct
|
|
|
569 {
|
|
|
570 __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
|
|
|
571 __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
|
|
|
572 __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
|
|
|
573 __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
|
|
|
574 __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
|
|
|
575 } FMC_Bank4_TypeDef;
|
|
|
576
|
|
|
577 /**
|
|
|
578 * @brief Flexible Memory Controller Bank5_6
|
|
|
579 */
|
|
|
580
|
|
|
581 typedef struct
|
|
|
582 {
|
|
|
583 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
|
|
|
584 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
|
|
|
585 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
|
|
|
586 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
|
|
|
587 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
|
|
|
588 } FMC_Bank5_6_TypeDef;
|
|
|
589
|
|
|
590 /**
|
|
|
591 * @brief General Purpose I/O
|
|
|
592 */
|
|
|
593
|
|
|
594 typedef struct
|
|
|
595 {
|
|
|
596 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
|
|
|
597 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
|
|
|
598 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
|
|
|
599 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
|
|
|
600 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
|
|
|
601 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
|
|
|
602 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
|
|
|
603 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
|
|
|
604 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
|
|
|
605 } GPIO_TypeDef;
|
|
|
606
|
|
|
607 /**
|
|
|
608 * @brief System configuration controller
|
|
|
609 */
|
|
|
610
|
|
|
611 typedef struct
|
|
|
612 {
|
|
|
613 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
|
|
|
614 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
|
|
|
615 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
|
|
|
616 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
|
|
|
617 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
|
|
|
618 } SYSCFG_TypeDef;
|
|
|
619
|
|
|
620 /**
|
|
|
621 * @brief Inter-integrated Circuit Interface
|
|
|
622 */
|
|
|
623
|
|
|
624 typedef struct
|
|
|
625 {
|
|
|
626 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
|
|
|
627 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
|
|
|
628 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
|
|
|
629 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
|
|
|
630 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
|
|
|
631 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
|
|
|
632 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
|
|
|
633 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
|
|
|
634 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
|
|
|
635 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
|
|
|
636 } I2C_TypeDef;
|
|
|
637
|
|
|
638 /**
|
|
|
639 * @brief Independent WATCHDOG
|
|
|
640 */
|
|
|
641
|
|
|
642 typedef struct
|
|
|
643 {
|
|
|
644 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
|
|
|
645 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
|
|
|
646 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
|
|
|
647 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
|
|
|
648 } IWDG_TypeDef;
|
|
|
649
|
|
|
650 /**
|
|
|
651 * @brief LCD-TFT Display Controller
|
|
|
652 */
|
|
|
653
|
|
|
654 typedef struct
|
|
|
655 {
|
|
|
656 uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
|
|
|
657 __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
|
|
|
658 __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
|
|
|
659 __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
|
|
|
660 __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
|
|
|
661 __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
|
|
|
662 uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
|
|
|
663 __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
|
|
|
664 uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
|
|
|
665 __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
|
|
|
666 uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
|
|
|
667 __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
|
|
|
668 __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
|
|
|
669 __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
|
|
|
670 __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
|
|
|
671 __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
|
|
|
672 __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
|
|
|
673 } LTDC_TypeDef;
|
|
|
674
|
|
|
675 /**
|
|
|
676 * @brief LCD-TFT Display layer x Controller
|
|
|
677 */
|
|
|
678
|
|
|
679 typedef struct
|
|
|
680 {
|
|
|
681 __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
|
|
|
682 __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
|
|
|
683 __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
|
|
|
684 __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
|
|
|
685 __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
|
|
|
686 __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
|
|
|
687 __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
|
|
|
688 __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
|
|
|
689 uint32_t RESERVED0[2]; /*!< Reserved */
|
|
|
690 __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
|
|
|
691 __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
|
|
|
692 __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
|
|
|
693 uint32_t RESERVED1[3]; /*!< Reserved */
|
|
|
694 __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
|
|
|
695
|
|
|
696 } LTDC_Layer_TypeDef;
|
|
|
697
|
|
|
698 /**
|
|
|
699 * @brief Power Control
|
|
|
700 */
|
|
|
701
|
|
|
702 typedef struct
|
|
|
703 {
|
|
|
704 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
|
|
|
705 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
|
|
|
706 } PWR_TypeDef;
|
|
|
707
|
|
|
708 /**
|
|
|
709 * @brief Reset and Clock Control
|
|
|
710 */
|
|
|
711
|
|
|
712 typedef struct
|
|
|
713 {
|
|
|
714 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
|
|
|
715 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
|
|
|
716 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
|
|
|
717 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
|
|
|
718 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
|
|
|
719 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
|
|
|
720 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
|
|
|
721 uint32_t RESERVED0; /*!< Reserved, 0x1C */
|
|
|
722 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
|
|
|
723 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
|
|
|
724 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
|
|
|
725 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
|
|
|
726 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
|
|
|
727 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
|
|
|
728 uint32_t RESERVED2; /*!< Reserved, 0x3C */
|
|
|
729 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
|
|
|
730 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
|
|
|
731 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
|
|
|
732 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
|
|
|
733 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
|
|
|
734 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
|
|
|
735 uint32_t RESERVED4; /*!< Reserved, 0x5C */
|
|
|
736 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
|
|
|
737 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
|
|
|
738 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
|
|
|
739 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
|
|
|
740 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
|
|
|
741 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
|
|
|
742 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
|
|
|
743 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
|
|
|
744 __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
|
|
|
745 __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
|
|
|
746
|
|
|
747 } RCC_TypeDef;
|
|
|
748
|
|
|
749 /**
|
|
|
750 * @brief Real-Time Clock
|
|
|
751 */
|
|
|
752
|
|
|
753 typedef struct
|
|
|
754 {
|
|
|
755 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
|
|
|
756 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
|
|
|
757 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
|
|
|
758 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
|
|
|
759 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
|
|
|
760 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
|
|
|
761 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
|
|
|
762 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
|
|
|
763 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
|
|
|
764 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
|
|
|
765 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
|
|
|
766 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
|
|
|
767 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
|
|
|
768 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
|
|
|
769 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
|
|
|
770 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
|
|
|
771 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
|
|
|
772 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
|
|
|
773 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
|
|
|
774 uint32_t RESERVED7; /*!< Reserved, 0x4C */
|
|
|
775 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
|
|
|
776 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
|
|
|
777 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
|
|
|
778 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
|
|
|
779 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
|
|
|
780 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
|
|
|
781 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
|
|
|
782 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
|
|
|
783 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
|
|
|
784 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
|
|
|
785 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
|
|
|
786 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
|
|
|
787 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
|
|
|
788 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
|
|
|
789 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
|
|
|
790 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
|
|
|
791 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
|
|
|
792 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
|
|
|
793 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
|
|
|
794 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
|
|
|
795 } RTC_TypeDef;
|
|
|
796
|
|
|
797 /**
|
|
|
798 * @brief Serial Audio Interface
|
|
|
799 */
|
|
|
800
|
|
|
801 typedef struct
|
|
|
802 {
|
|
|
803 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
|
|
|
804 } SAI_TypeDef;
|
|
|
805
|
|
|
806 typedef struct
|
|
|
807 {
|
|
|
808 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
|
|
|
809 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
|
|
|
810 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
|
|
|
811 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
|
|
|
812 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
|
|
|
813 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
|
|
|
814 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
|
|
|
815 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
|
|
|
816 } SAI_Block_TypeDef;
|
|
|
817
|
|
|
818 /**
|
|
|
819 * @brief SD host Interface
|
|
|
820 */
|
|
|
821
|
|
|
822 typedef struct
|
|
|
823 {
|
|
|
824 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
|
|
|
825 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
|
|
|
826 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
|
|
|
827 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
|
|
|
828 __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
|
|
|
829 __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
|
|
|
830 __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
|
|
|
831 __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
|
|
|
832 __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
|
|
|
833 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
|
|
|
834 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
|
|
|
835 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
|
|
|
836 __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
|
|
|
837 __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
|
|
|
838 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
|
|
|
839 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
|
|
|
840 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
|
|
|
841 __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
|
|
|
842 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
|
|
|
843 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
|
|
|
844 } SDIO_TypeDef;
|
|
|
845
|
|
|
846 /**
|
|
|
847 * @brief Serial Peripheral Interface
|
|
|
848 */
|
|
|
849
|
|
|
850 typedef struct
|
|
|
851 {
|
|
|
852 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
|
|
|
853 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
|
|
|
854 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
|
|
|
855 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
|
|
|
856 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
|
|
|
857 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
|
|
|
858 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
|
|
|
859 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
|
|
|
860 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
|
|
|
861 } SPI_TypeDef;
|
|
|
862
|
|
|
863 /**
|
|
|
864 * @brief TIM
|
|
|
865 */
|
|
|
866
|
|
|
867 typedef struct
|
|
|
868 {
|
|
|
869 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
|
|
|
870 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
|
|
|
871 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
|
|
|
872 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
|
|
|
873 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
|
|
|
874 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
|
|
|
875 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
|
|
|
876 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
|
|
|
877 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
|
|
|
878 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
|
|
|
879 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
|
|
|
880 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
|
|
|
881 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
|
|
|
882 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
|
|
|
883 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
|
|
|
884 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
|
|
|
885 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
|
|
|
886 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
|
|
|
887 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
|
|
|
888 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
|
|
|
889 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
|
|
|
890 } TIM_TypeDef;
|
|
|
891
|
|
|
892 /**
|
|
|
893 * @brief Universal Synchronous Asynchronous Receiver Transmitter
|
|
|
894 */
|
|
|
895
|
|
|
896 typedef struct
|
|
|
897 {
|
|
|
898 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
|
|
|
899 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
|
|
|
900 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
|
|
|
901 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
|
|
|
902 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
|
|
|
903 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
|
|
|
904 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
|
|
|
905 } USART_TypeDef;
|
|
|
906
|
|
|
907 /**
|
|
|
908 * @brief Window WATCHDOG
|
|
|
909 */
|
|
|
910
|
|
|
911 typedef struct
|
|
|
912 {
|
|
|
913 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
|
|
|
914 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
|
|
|
915 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
|
|
|
916 } WWDG_TypeDef;
|
|
|
917
|
|
|
918 /**
|
|
|
919 * @brief Crypto Processor
|
|
|
920 */
|
|
|
921
|
|
|
922 typedef struct
|
|
|
923 {
|
|
|
924 __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */
|
|
|
925 __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */
|
|
|
926 __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */
|
|
|
927 __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */
|
|
|
928 __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */
|
|
|
929 __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */
|
|
|
930 __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */
|
|
|
931 __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */
|
|
|
932 __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */
|
|
|
933 __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */
|
|
|
934 __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */
|
|
|
935 __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */
|
|
|
936 __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */
|
|
|
937 __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */
|
|
|
938 __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */
|
|
|
939 __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */
|
|
|
940 __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */
|
|
|
941 __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
|
|
|
942 __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */
|
|
|
943 __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
|
|
|
944 __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */
|
|
|
945 __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */
|
|
|
946 __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */
|
|
|
947 __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */
|
|
|
948 __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */
|
|
|
949 __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */
|
|
|
950 __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */
|
|
|
951 __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */
|
|
|
952 __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */
|
|
|
953 __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */
|
|
|
954 __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */
|
|
|
955 __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */
|
|
|
956 __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */
|
|
|
957 __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */
|
|
|
958 __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */
|
|
|
959 __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */
|
|
|
960 } CRYP_TypeDef;
|
|
|
961
|
|
|
962 /**
|
|
|
963 * @brief HASH
|
|
|
964 */
|
|
|
965
|
|
|
966 typedef struct
|
|
|
967 {
|
|
|
968 __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
|
|
|
969 __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
|
|
|
970 __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
|
|
|
971 __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
|
|
|
972 __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
|
|
|
973 __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
|
|
|
974 uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
|
|
|
975 __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
|
|
|
976 } HASH_TypeDef;
|
|
|
977
|
|
|
978 /**
|
|
|
979 * @brief HASH_DIGEST
|
|
|
980 */
|
|
|
981
|
|
|
982 typedef struct
|
|
|
983 {
|
|
|
984 __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
|
|
|
985 } HASH_DIGEST_TypeDef;
|
|
|
986
|
|
|
987 /**
|
|
|
988 * @brief RNG
|
|
|
989 */
|
|
|
990
|
|
|
991 typedef struct
|
|
|
992 {
|
|
|
993 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
|
|
|
994 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
|
|
|
995 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
|
|
|
996 } RNG_TypeDef;
|
|
|
997
|
|
|
998
|
|
|
999 /**
|
|
|
1000 * @brief __USB_OTG_Core_register
|
|
|
1001 */
|
|
|
1002 typedef struct
|
|
|
1003 {
|
|
|
1004 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
|
|
|
1005 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
|
|
|
1006 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
|
|
|
1007 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
|
|
|
1008 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
|
|
|
1009 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
|
|
|
1010 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
|
|
|
1011 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
|
|
|
1012 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
|
|
|
1013 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h */
|
|
|
1014 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/
|
|
|
1015 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
|
|
|
1016 uint32_t Reserved30[2]; /* Reserved 030h*/
|
|
|
1017 __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
|
|
|
1018 __IO uint32_t CID; /* User ID Register 03Ch*/
|
|
|
1019 uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/
|
|
|
1020 __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
|
|
|
1021 __IO uint32_t DIEPTXF[0x0F];/* dev Periodic Transmit FIFO */
|
|
|
1022 }
|
|
|
1023 USB_OTG_GlobalTypeDef;
|
|
|
1024
|
|
|
1025
|
|
|
1026 /**
|
|
|
1027 * @brief __device_Registers
|
|
|
1028 */
|
|
|
1029 typedef struct
|
|
|
1030 {
|
|
|
1031 __IO uint32_t DCFG; /* dev Configuration Register 800h*/
|
|
|
1032 __IO uint32_t DCTL; /* dev Control Register 804h*/
|
|
|
1033 __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
|
|
|
1034 uint32_t Reserved0C; /* Reserved 80Ch*/
|
|
|
1035 __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
|
|
|
1036 __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
|
|
|
1037 __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
|
|
|
1038 __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
|
|
|
1039 uint32_t Reserved20; /* Reserved 820h*/
|
|
|
1040 uint32_t Reserved9; /* Reserved 824h*/
|
|
|
1041 __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
|
|
|
1042 __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
|
|
|
1043 __IO uint32_t DTHRCTL; /* dev thr 830h*/
|
|
|
1044 __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
|
|
|
1045 __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/
|
|
|
1046 __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/
|
|
|
1047 uint32_t Reserved40; /* dedicated EP mask 840h*/
|
|
|
1048 __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/
|
|
|
1049 uint32_t Reserved44[15]; /* Reserved 844-87Ch*/
|
|
|
1050 __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/
|
|
|
1051 }
|
|
|
1052 USB_OTG_DeviceTypeDef;
|
|
|
1053
|
|
|
1054
|
|
|
1055 /**
|
|
|
1056 * @brief __IN_Endpoint-Specific_Register
|
|
|
1057 */
|
|
|
1058 typedef struct
|
|
|
1059 {
|
|
|
1060 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
|
|
|
1061 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
|
|
|
1062 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
|
|
|
1063 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
|
|
|
1064 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
|
|
|
1065 __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
|
|
|
1066 __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
|
|
|
1067 uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
|
|
|
1068 }
|
|
|
1069 USB_OTG_INEndpointTypeDef;
|
|
|
1070
|
|
|
1071
|
|
|
1072 /**
|
|
|
1073 * @brief __OUT_Endpoint-Specific_Registers
|
|
|
1074 */
|
|
|
1075 typedef struct
|
|
|
1076 {
|
|
|
1077 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
|
|
|
1078 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
|
|
|
1079 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
|
|
|
1080 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
|
|
|
1081 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
|
|
|
1082 __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
|
|
|
1083 uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
|
|
|
1084 }
|
|
|
1085 USB_OTG_OUTEndpointTypeDef;
|
|
|
1086
|
|
|
1087
|
|
|
1088 /**
|
|
|
1089 * @brief __Host_Mode_Register_Structures
|
|
|
1090 */
|
|
|
1091 typedef struct
|
|
|
1092 {
|
|
|
1093 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
|
|
|
1094 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
|
|
|
1095 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
|
|
|
1096 uint32_t Reserved40C; /* Reserved 40Ch*/
|
|
|
1097 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
|
|
|
1098 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
|
|
|
1099 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
|
|
|
1100 }
|
|
|
1101 USB_OTG_HostTypeDef;
|
|
|
1102
|
|
|
1103 /**
|
|
|
1104 * @brief __Host_Channel_Specific_Registers
|
|
|
1105 */
|
|
|
1106 typedef struct
|
|
|
1107 {
|
|
|
1108 __IO uint32_t HCCHAR;
|
|
|
1109 __IO uint32_t HCSPLT;
|
|
|
1110 __IO uint32_t HCINT;
|
|
|
1111 __IO uint32_t HCINTMSK;
|
|
|
1112 __IO uint32_t HCTSIZ;
|
|
|
1113 __IO uint32_t HCDMA;
|
|
|
1114 uint32_t Reserved[2];
|
|
|
1115 }
|
|
|
1116 USB_OTG_HostChannelTypeDef;
|
|
|
1117 /**
|
|
|
1118 * @}
|
|
|
1119 */
|
|
|
1120
|
|
|
1121 /** @addtogroup Peripheral_memory_map
|
|
|
1122 * @{
|
|
|
1123 */
|
|
|
1124 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 2 MB) base address in the alias region */
|
|
|
1125 #define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
|
|
|
1126 #define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
|
|
|
1127 #define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
|
|
|
1128 #define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
|
|
|
1129 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
|
|
|
1130 #define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
|
|
|
1131 #define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */
|
|
|
1132 #define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
|
|
|
1133 #define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
|
|
|
1134 #define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
|
|
|
1135 #define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
|
|
|
1136 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
|
|
|
1137 #define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
|
|
|
1138 #define FLASH_END ((uint32_t)0x081FFFFF) /*!< FLASH end address */
|
|
|
1139 #define CCMDATARAM_END ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */
|
|
|
1140
|
|
|
1141 /* Legacy defines */
|
|
|
1142 #define SRAM_BASE SRAM1_BASE
|
|
|
1143 #define SRAM_BB_BASE SRAM1_BB_BASE
|
|
|
1144
|
|
|
1145
|
|
|
1146 /*!< Peripheral memory map */
|
|
|
1147 #define APB1PERIPH_BASE PERIPH_BASE
|
|
|
1148 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
|
|
|
1149 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
|
|
|
1150 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
|
|
|
1151
|
|
|
1152 /*!< APB1 peripherals */
|
|
|
1153 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
|
|
|
1154 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
|
|
|
1155 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
|
|
|
1156 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
|
|
|
1157 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
|
|
|
1158 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
|
|
|
1159 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
|
|
|
1160 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
|
|
|
1161 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
|
|
|
1162 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
|
|
|
1163 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
|
|
|
1164 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
|
|
|
1165 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
|
|
|
1166 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
|
|
|
1167 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
|
|
|
1168 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
|
|
|
1169 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
|
|
|
1170 #define USART3_BASE (APB1PERIPH_BASE + 0x4800)
|
|
|
1171 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
|
|
|
1172 #define UART5_BASE (APB1PERIPH_BASE + 0x5000)
|
|
|
1173 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
|
|
|
1174 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
|
|
|
1175 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
|
|
|
1176 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
|
|
|
1177 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
|
|
|
1178 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
|
|
|
1179 #define DAC_BASE (APB1PERIPH_BASE + 0x7400)
|
|
|
1180 #define UART7_BASE (APB1PERIPH_BASE + 0x7800)
|
|
|
1181 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00)
|
|
|
1182
|
|
|
1183 /*!< APB2 peripherals */
|
|
|
1184 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
|
|
|
1185 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
|
|
|
1186 #define USART1_BASE (APB2PERIPH_BASE + 0x1000)
|
|
|
1187 #define USART6_BASE (APB2PERIPH_BASE + 0x1400)
|
|
|
1188 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
|
|
|
1189 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
|
|
|
1190 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
|
|
|
1191 #define ADC_BASE (APB2PERIPH_BASE + 0x2300)
|
|
|
1192 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
|
|
|
1193 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
|
|
|
1194 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
|
|
|
1195 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
|
|
|
1196 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
|
|
|
1197 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
|
|
|
1198 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
|
|
|
1199 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
|
|
|
1200 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000)
|
|
|
1201 #define SPI6_BASE (APB2PERIPH_BASE + 0x5400)
|
|
|
1202 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800)
|
|
|
1203 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
|
|
|
1204 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
|
|
|
1205 #define LTDC_BASE (APB2PERIPH_BASE + 0x6800)
|
|
|
1206 #define LTDC_Layer1_BASE (LTDC_BASE + 0x84)
|
|
|
1207 #define LTDC_Layer2_BASE (LTDC_BASE + 0x104)
|
|
|
1208
|
|
|
1209 /*!< AHB1 peripherals */
|
|
|
1210 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
|
|
|
1211 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
|
|
|
1212 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
|
|
|
1213 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
|
|
|
1214 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
|
|
|
1215 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
|
|
|
1216 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
|
|
|
1217 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
|
|
|
1218 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
|
|
|
1219 #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400)
|
|
|
1220 #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800)
|
|
|
1221 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
|
|
|
1222 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
|
|
|
1223 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
|
|
|
1224 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
|
|
|
1225 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
|
|
|
1226 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
|
|
|
1227 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
|
|
|
1228 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
|
|
|
1229 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
|
|
|
1230 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
|
|
|
1231 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
|
|
|
1232 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
|
|
|
1233 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
|
|
|
1234 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
|
|
|
1235 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
|
|
|
1236 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
|
|
|
1237 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
|
|
|
1238 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
|
|
|
1239 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
|
|
|
1240 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
|
|
|
1241 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
|
|
|
1242 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000)
|
|
|
1243 #define ETH_MAC_BASE (ETH_BASE)
|
|
|
1244 #define ETH_MMC_BASE (ETH_BASE + 0x0100)
|
|
|
1245 #define ETH_PTP_BASE (ETH_BASE + 0x0700)
|
|
|
1246 #define ETH_DMA_BASE (ETH_BASE + 0x1000)
|
|
|
1247 #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000)
|
|
|
1248
|
|
|
1249 /*!< AHB2 peripherals */
|
|
|
1250 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
|
|
|
1251 #define CRYP_BASE (AHB2PERIPH_BASE + 0x60000)
|
|
|
1252 #define HASH_BASE (AHB2PERIPH_BASE + 0x60400)
|
|
|
1253 #define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710)
|
|
|
1254 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
|
|
|
1255
|
|
|
1256 /*!< FMC Bankx registers base address */
|
|
|
1257 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
|
|
|
1258 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
|
|
|
1259 #define FMC_Bank2_3_R_BASE (FMC_R_BASE + 0x0060)
|
|
|
1260 #define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0)
|
|
|
1261 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140)
|
|
|
1262
|
|
|
1263 /* Debug MCU registers base address */
|
|
|
1264 #define DBGMCU_BASE ((uint32_t )0xE0042000)
|
|
|
1265
|
|
|
1266 /*!< USB registers base address */
|
|
|
1267 #define USB_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000)
|
|
|
1268 #define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
|
|
|
1269
|
|
|
1270 #define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
|
|
|
1271 #define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
|
|
|
1272 #define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
|
|
|
1273 #define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
|
|
|
1274 #define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
|
|
|
1275 #define USB_OTG_HOST_BASE ((uint32_t )0x400)
|
|
|
1276 #define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
|
|
|
1277 #define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
|
|
|
1278 #define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
|
|
|
1279 #define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
|
|
|
1280 #define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
|
|
|
1281 #define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
|
|
|
1282
|
|
|
1283 /**
|
|
|
1284 * @}
|
|
|
1285 */
|
|
|
1286
|
|
|
1287 /** @addtogroup Peripheral_declaration
|
|
|
1288 * @{
|
|
|
1289 */
|
|
|
1290 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
|
|
|
1291 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
|
|
|
1292 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
|
|
|
1293 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
|
|
|
1294 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
|
|
|
1295 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
|
|
|
1296 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
|
|
|
1297 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
|
|
|
1298 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
|
|
|
1299 #define RTC ((RTC_TypeDef *) RTC_BASE)
|
|
|
1300 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
|
|
|
1301 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
|
|
|
1302 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
|
|
|
1303 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
|
|
|
1304 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
|
|
|
1305 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
|
|
|
1306 #define USART2 ((USART_TypeDef *) USART2_BASE)
|
|
|
1307 #define USART3 ((USART_TypeDef *) USART3_BASE)
|
|
|
1308 #define UART4 ((USART_TypeDef *) UART4_BASE)
|
|
|
1309 #define UART5 ((USART_TypeDef *) UART5_BASE)
|
|
|
1310 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
|
|
|
1311 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
|
|
|
1312 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
|
|
|
1313 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
|
|
|
1314 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
|
|
|
1315 #define PWR ((PWR_TypeDef *) PWR_BASE)
|
|
|
1316 #define DAC ((DAC_TypeDef *) DAC_BASE)
|
|
|
1317 #define UART7 ((USART_TypeDef *) UART7_BASE)
|
|
|
1318 #define UART8 ((USART_TypeDef *) UART8_BASE)
|
|
|
1319 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
|
|
|
1320 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
|
|
|
1321 #define USART1 ((USART_TypeDef *) USART1_BASE)
|
|
|
1322 #define USART6 ((USART_TypeDef *) USART6_BASE)
|
|
|
1323 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
|
|
|
1324 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
|
|
|
1325 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
|
|
|
1326 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
|
|
|
1327 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
|
|
|
1328 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
|
|
|
1329 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
|
|
|
1330 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
|
|
|
1331 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
|
|
|
1332 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
|
|
|
1333 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
|
|
|
1334 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
|
|
|
1335 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
|
|
|
1336 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
|
|
|
1337 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
|
|
|
1338 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
|
|
|
1339 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
|
|
|
1340 #define LTDC ((LTDC_TypeDef *)LTDC_BASE)
|
|
|
1341 #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
|
|
|
1342 #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
|
|
|
1343
|
|
|
1344 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
|
|
|
1345 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
|
|
|
1346 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
|
|
|
1347 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
|
|
|
1348 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
|
|
|
1349 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
|
|
|
1350 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
|
|
|
1351 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
|
|
|
1352 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
|
|
|
1353 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
|
|
|
1354 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
|
|
|
1355 #define CRC ((CRC_TypeDef *) CRC_BASE)
|
|
|
1356 #define RCC ((RCC_TypeDef *) RCC_BASE)
|
|
|
1357 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
|
|
|
1358 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
|
|
|
1359 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
|
|
|
1360 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
|
|
|
1361 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
|
|
|
1362 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
|
|
|
1363 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
|
|
|
1364 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
|
|
|
1365 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
|
|
|
1366 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
|
|
|
1367 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
|
|
|
1368 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
|
|
|
1369 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
|
|
|
1370 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
|
|
|
1371 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
|
|
|
1372 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
|
|
|
1373 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
|
|
|
1374 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
|
|
|
1375 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
|
|
|
1376 #define ETH ((ETH_TypeDef *) ETH_BASE)
|
|
|
1377 #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
|
|
|
1378 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
|
|
|
1379 #define CRYP ((CRYP_TypeDef *) CRYP_BASE)
|
|
|
1380 #define HASH ((HASH_TypeDef *) HASH_BASE)
|
|
|
1381 #define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
|
|
|
1382 #define RNG ((RNG_TypeDef *) RNG_BASE)
|
|
|
1383 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
|
|
|
1384 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
|
|
|
1385 #define FMC_Bank2_3 ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
|
|
|
1386 #define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
|
|
|
1387 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
|
|
|
1388
|
|
|
1389 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
|
|
|
1390
|
|
|
1391 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
|
|
|
1392 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
|
|
|
1393
|
|
|
1394 /**
|
|
|
1395 * @}
|
|
|
1396 */
|
|
|
1397
|
|
|
1398 /** @addtogroup Exported_constants
|
|
|
1399 * @{
|
|
|
1400 */
|
|
|
1401
|
|
|
1402 /** @addtogroup Peripheral_Registers_Bits_Definition
|
|
|
1403 * @{
|
|
|
1404 */
|
|
|
1405
|
|
|
1406 /******************************************************************************/
|
|
|
1407 /* Peripheral Registers_Bits_Definition */
|
|
|
1408 /******************************************************************************/
|
|
|
1409
|
|
|
1410 /******************************************************************************/
|
|
|
1411 /* */
|
|
|
1412 /* Analog to Digital Converter */
|
|
|
1413 /* */
|
|
|
1414 /******************************************************************************/
|
|
|
1415 /******************** Bit definition for ADC_SR register ********************/
|
|
|
1416 #define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */
|
|
|
1417 #define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */
|
|
|
1418 #define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */
|
|
|
1419 #define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */
|
|
|
1420 #define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */
|
|
|
1421 #define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */
|
|
|
1422
|
|
|
1423 /******************* Bit definition for ADC_CR1 register ********************/
|
|
|
1424 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
|
|
|
1425 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
1426 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
1427 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
1428 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
1429 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
|
|
1430 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
|
|
|
1431 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
|
|
|
1432 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
|
|
|
1433 #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
|
|
|
1434 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
|
|
|
1435 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
|
|
|
1436 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
|
|
|
1437 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
|
|
|
1438 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
|
|
|
1439 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
|
|
|
1440 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
|
|
|
1441 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
|
|
|
1442 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
|
|
|
1443 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
|
|
|
1444 #define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
|
|
|
1445 #define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
1446 #define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
1447 #define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
|
|
|
1448
|
|
|
1449 /******************* Bit definition for ADC_CR2 register ********************/
|
|
|
1450 #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
|
|
|
1451 #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
|
|
|
1452 #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
|
|
|
1453 #define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
|
|
|
1454 #define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
|
|
|
1455 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
|
|
|
1456 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
|
|
|
1457 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
1458 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
1459 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
|
|
1460 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
|
|
1461 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
|
|
|
1462 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
|
|
1463 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
|
|
1464 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
|
|
|
1465 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
|
|
|
1466 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
1467 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
1468 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
1469 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
|
|
1470 #define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
|
|
|
1471 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
|
|
|
1472 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
|
|
|
1473 #define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
|
|
|
1474
|
|
|
1475 /****************** Bit definition for ADC_SMPR1 register *******************/
|
|
|
1476 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
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|
|
1477 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
1478 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
1479 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
1480 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
|
|
|
1481 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
|
|
|
1482 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
|
|
|
1483 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
|
|
|
1484 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
|
|
|
1485 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
|
|
|
1486 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
|
|
|
1487 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
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1488 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
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|
1489 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
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|
|
1490 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
|
|
|
1491 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
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1492 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
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|
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1493 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
|
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1494 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
|
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1495 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
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1496 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
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1497 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
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|
1498 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
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1499 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
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1500 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
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1501 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
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1502 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
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1503 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
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1504 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
|
|
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1505 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
|
|
|
1506 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
|
|
|
1507 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
|
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|
1508 #define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
|
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|
1509 #define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
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|
1510 #define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
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|
1511 #define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
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|
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1512
|
|
|
1513 /****************** Bit definition for ADC_SMPR2 register *******************/
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1514 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
|
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|
1515 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
1516 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
1517 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
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1518 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
|
|
|
1519 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
|
|
|
1520 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
|
|
|
1521 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
|
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1522 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
|
|
|
1523 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
|
|
|
1524 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
|
|
|
1525 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
|
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1526 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
|
|
|
1527 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
|
|
|
1528 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
|
|
|
1529 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
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1530 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
|
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|
1531 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
|
|
|
1532 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
|
|
|
1533 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
|
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|
1534 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
|
|
|
1535 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
|
|
|
1536 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
|
|
|
1537 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
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|
1538 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
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|
1539 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
|
|
|
1540 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
|
|
|
1541 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
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|
1542 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
|
|
|
1543 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
|
|
|
1544 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
|
|
|
1545 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
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1546 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
|
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|
1547 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
1548 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
1549 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
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1550 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
|
|
|
1551 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
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|
|
1552 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
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|
1553 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
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1554
|
|
|
1555 /****************** Bit definition for ADC_JOFR1 register *******************/
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1556 #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */
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1557
|
|
|
1558 /****************** Bit definition for ADC_JOFR2 register *******************/
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1559 #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */
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1560
|
|
|
1561 /****************** Bit definition for ADC_JOFR3 register *******************/
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1562 #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */
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1563
|
|
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1564 /****************** Bit definition for ADC_JOFR4 register *******************/
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1565 #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */
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1566
|
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|
1567 /******************* Bit definition for ADC_HTR register ********************/
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1568 #define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */
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1569
|
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|
1570 /******************* Bit definition for ADC_LTR register ********************/
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1571 #define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */
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1572
|
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|
1573 /******************* Bit definition for ADC_SQR1 register *******************/
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1574 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
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1575 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
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1576 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
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1577 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
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1578 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
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1579 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
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1580 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
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1581 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
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1582 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
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1583 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
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1584 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
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1585 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
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1586 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
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1587 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
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1588 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
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1589 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
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1590 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
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1591 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
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1592 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
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1593 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
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1594 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
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1595 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
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1596 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
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1597 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
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1598 #define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
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1599 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
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1600 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
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1601 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
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1602 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
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1603
|
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1604 /******************* Bit definition for ADC_SQR2 register *******************/
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1605 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
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1606 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
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|
1607 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
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1608 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
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1609 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
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1610 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
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1611 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
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1612 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
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1613 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
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1614 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
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1615 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
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1616 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
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1617 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
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1618 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
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|
1619 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
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|
1620 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
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1621 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
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|
1622 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
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1623 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
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|
1624 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
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|
1625 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
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|
1626 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
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|
1627 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
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|
1628 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
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1629 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
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|
1630 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
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|
|
1631 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
|
|
1632 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
|
|
|
1633 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
|
|
|
1634 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
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|
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1635 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
|
|
|
1636 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
|
|
|
1637 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
|
|
|
1638 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
|
|
|
1639 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
|
|
|
1640 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
|
|
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1641
|
|
|
1642 /******************* Bit definition for ADC_SQR3 register *******************/
|
|
|
1643 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
|
|
|
1644 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
1645 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
1646 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
1647 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
1648 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
|
|
1649 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
|
|
|
1650 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
|
|
|
1651 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
|
|
|
1652 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
|
|
|
1653 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
|
|
|
1654 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
|
|
|
1655 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
|
|
|
1656 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
|
|
|
1657 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
|
|
|
1658 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
|
|
|
1659 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
|
|
|
1660 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
|
|
|
1661 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
|
|
|
1662 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
|
|
|
1663 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
|
|
|
1664 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
|
|
|
1665 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
|
|
|
1666 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
|
|
|
1667 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
|
|
|
1668 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
|
|
1669 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
|
|
1670 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
|
|
|
1671 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
|
|
|
1672 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
|
|
|
1673 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
|
|
|
1674 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
|
|
|
1675 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
|
|
|
1676 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
|
|
|
1677 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
|
|
|
1678 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
|
|
|
1679
|
|
|
1680 /******************* Bit definition for ADC_JSQR register *******************/
|
|
|
1681 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
|
|
|
1682 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
1683 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
1684 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
1685 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
1686 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
|
|
1687 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
|
|
|
1688 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
|
|
|
1689 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
|
|
|
1690 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
|
|
|
1691 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
|
|
|
1692 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
|
|
|
1693 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
|
|
|
1694 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
|
|
|
1695 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
|
|
|
1696 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
|
|
|
1697 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
|
|
|
1698 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
|
|
|
1699 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
|
|
|
1700 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
|
|
|
1701 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
|
|
|
1702 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
|
|
|
1703 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
|
|
|
1704 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
|
|
|
1705 #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
|
|
|
1706 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
|
|
1707 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
|
|
1708
|
|
|
1709 /******************* Bit definition for ADC_JDR1 register *******************/
|
|
|
1710 #define ADC_JDR1_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
|
|
|
1711
|
|
|
1712 /******************* Bit definition for ADC_JDR2 register *******************/
|
|
|
1713 #define ADC_JDR2_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
|
|
|
1714
|
|
|
1715 /******************* Bit definition for ADC_JDR3 register *******************/
|
|
|
1716 #define ADC_JDR3_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
|
|
|
1717
|
|
|
1718 /******************* Bit definition for ADC_JDR4 register *******************/
|
|
|
1719 #define ADC_JDR4_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
|
|
|
1720
|
|
|
1721 /******************** Bit definition for ADC_DR register ********************/
|
|
|
1722 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
|
|
|
1723 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
|
|
|
1724
|
|
|
1725 /******************* Bit definition for ADC_CSR register ********************/
|
|
|
1726 #define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
|
|
|
1727 #define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
|
|
|
1728 #define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
|
|
|
1729 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
|
|
|
1730 #define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
|
|
|
1731 #define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
|
|
|
1732 #define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
|
|
|
1733 #define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
|
|
|
1734 #define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
|
|
|
1735 #define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
|
|
|
1736 #define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
|
|
|
1737 #define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
|
|
|
1738 #define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
|
|
|
1739 #define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
|
|
|
1740 #define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
|
|
|
1741 #define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
|
|
|
1742 #define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
|
|
|
1743 #define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
|
|
|
1744
|
|
|
1745 /******************* Bit definition for ADC_CCR register ********************/
|
|
|
1746 #define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
|
|
|
1747 #define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
1748 #define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
1749 #define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
1750 #define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
1751 #define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
|
|
1752 #define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
|
|
|
1753 #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
|
|
1754 #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
|
|
1755 #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
|
|
1756 #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
|
|
1757 #define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
|
|
|
1758 #define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
|
|
|
1759 #define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
|
|
|
1760 #define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
|
|
|
1761 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
|
|
|
1762 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
1763 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
1764 #define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
|
|
|
1765 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
|
|
|
1766
|
|
|
1767 /******************* Bit definition for ADC_CDR register ********************/
|
|
|
1768 #define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
|
|
|
1769 #define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
|
|
|
1770
|
|
|
1771 /******************************************************************************/
|
|
|
1772 /* */
|
|
|
1773 /* Controller Area Network */
|
|
|
1774 /* */
|
|
|
1775 /******************************************************************************/
|
|
|
1776 /*!<CAN control and status registers */
|
|
|
1777 /******************* Bit definition for CAN_MCR register ********************/
|
|
|
1778 #define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
|
|
|
1779 #define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
|
|
|
1780 #define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
|
|
|
1781 #define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
|
|
|
1782 #define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
|
|
|
1783 #define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
|
|
|
1784 #define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
|
|
|
1785 #define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
|
|
|
1786 #define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
|
|
|
1787 #define CAN_MCR_DBF ((uint32_t)0x00010000) /*!<bxCAN Debug freeze */
|
|
|
1788 /******************* Bit definition for CAN_MSR register ********************/
|
|
|
1789 #define CAN_MSR_INAK ((uint32_t)0x0001) /*!<Initialization Acknowledge */
|
|
|
1790 #define CAN_MSR_SLAK ((uint32_t)0x0002) /*!<Sleep Acknowledge */
|
|
|
1791 #define CAN_MSR_ERRI ((uint32_t)0x0004) /*!<Error Interrupt */
|
|
|
1792 #define CAN_MSR_WKUI ((uint32_t)0x0008) /*!<Wakeup Interrupt */
|
|
|
1793 #define CAN_MSR_SLAKI ((uint32_t)0x0010) /*!<Sleep Acknowledge Interrupt */
|
|
|
1794 #define CAN_MSR_TXM ((uint32_t)0x0100) /*!<Transmit Mode */
|
|
|
1795 #define CAN_MSR_RXM ((uint32_t)0x0200) /*!<Receive Mode */
|
|
|
1796 #define CAN_MSR_SAMP ((uint32_t)0x0400) /*!<Last Sample Point */
|
|
|
1797 #define CAN_MSR_RX ((uint32_t)0x0800) /*!<CAN Rx Signal */
|
|
|
1798
|
|
|
1799 /******************* Bit definition for CAN_TSR register ********************/
|
|
|
1800 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
|
|
|
1801 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
|
|
|
1802 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
|
|
|
1803 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
|
|
|
1804 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
|
|
|
1805 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
|
|
|
1806 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
|
|
|
1807 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
|
|
|
1808 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
|
|
|
1809 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
|
|
|
1810 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
|
|
|
1811 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
|
|
|
1812 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
|
|
|
1813 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
|
|
|
1814 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
|
|
|
1815 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
|
|
|
1816
|
|
|
1817 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
|
|
|
1818 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
|
|
|
1819 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
|
|
|
1820 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
|
|
|
1821
|
|
|
1822 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
|
|
|
1823 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
|
|
|
1824 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
|
|
|
1825 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
|
|
|
1826
|
|
|
1827 /******************* Bit definition for CAN_RF0R register *******************/
|
|
|
1828 #define CAN_RF0R_FMP0 ((uint32_t)0x03) /*!<FIFO 0 Message Pending */
|
|
|
1829 #define CAN_RF0R_FULL0 ((uint32_t)0x08) /*!<FIFO 0 Full */
|
|
|
1830 #define CAN_RF0R_FOVR0 ((uint32_t)0x10) /*!<FIFO 0 Overrun */
|
|
|
1831 #define CAN_RF0R_RFOM0 ((uint32_t)0x20) /*!<Release FIFO 0 Output Mailbox */
|
|
|
1832
|
|
|
1833 /******************* Bit definition for CAN_RF1R register *******************/
|
|
|
1834 #define CAN_RF1R_FMP1 ((uint32_t)0x03) /*!<FIFO 1 Message Pending */
|
|
|
1835 #define CAN_RF1R_FULL1 ((uint32_t)0x08) /*!<FIFO 1 Full */
|
|
|
1836 #define CAN_RF1R_FOVR1 ((uint32_t)0x10) /*!<FIFO 1 Overrun */
|
|
|
1837 #define CAN_RF1R_RFOM1 ((uint32_t)0x20) /*!<Release FIFO 1 Output Mailbox */
|
|
|
1838
|
|
|
1839 /******************** Bit definition for CAN_IER register *******************/
|
|
|
1840 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
|
|
|
1841 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
|
|
|
1842 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
|
|
|
1843 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
|
|
|
1844 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
|
|
|
1845 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
|
|
|
1846 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
|
|
|
1847 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
|
|
|
1848 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
|
|
|
1849 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
|
|
|
1850 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
|
|
|
1851 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
|
|
|
1852 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
|
|
|
1853 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
|
|
|
1854 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error warning interrupt enable */
|
|
|
1855 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error passive interrupt enable */
|
|
|
1856 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-off interrupt enable */
|
|
|
1857 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last error code interrupt enable */
|
|
|
1858 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error interrupt enable */
|
|
|
1859
|
|
|
1860
|
|
|
1861 /******************** Bit definition for CAN_ESR register *******************/
|
|
|
1862 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
|
|
|
1863 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
|
|
|
1864 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
|
|
|
1865
|
|
|
1866 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
|
|
|
1867 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
1868 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
1869 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
|
|
1870
|
|
|
1871 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
|
|
|
1872 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
|
|
|
1873
|
|
|
1874 /******************* Bit definition for CAN_BTR register ********************/
|
|
|
1875 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
|
|
|
1876 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
|
|
|
1877 #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
1878 #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
1879 #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
|
|
1880 #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
|
|
1881 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
|
|
|
1882 #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
|
|
1883 #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
|
|
1884 #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
|
|
|
1885 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
|
|
|
1886 #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
1887 #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
1888 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
|
|
|
1889 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
|
|
|
1890
|
|
|
1891
|
|
|
1892 /*!<Mailbox registers */
|
|
|
1893 /****************** Bit definition for CAN_TI0R register ********************/
|
|
|
1894 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
|
|
|
1895 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
|
|
|
1896 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
|
|
|
1897 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
|
|
|
1898 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
|
|
|
1899
|
|
|
1900 /****************** Bit definition for CAN_TDT0R register *******************/
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|
|
1901 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
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|
|
1902 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
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|
|
1903 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
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|
1904
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1905 /****************** Bit definition for CAN_TDL0R register *******************/
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|
|
1906 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
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|
1907 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
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|
|
1908 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
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|
|
1909 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
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|
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1910
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|
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1911 /****************** Bit definition for CAN_TDH0R register *******************/
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|
|
1912 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
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|
1913 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
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|
1914 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
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|
1915 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
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|
|
1916
|
|
|
1917 /******************* Bit definition for CAN_TI1R register *******************/
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1918 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
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|
|
1919 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
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|
1920 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
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|
1921 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
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|
1922 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
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|
|
1923
|
|
|
1924 /******************* Bit definition for CAN_TDT1R register ******************/
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|
|
1925 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
|
|
|
1926 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
|
|
|
1927 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
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|
|
1928
|
|
|
1929 /******************* Bit definition for CAN_TDL1R register ******************/
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|
|
1930 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
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|
|
1931 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
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|
1932 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
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|
1933 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
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|
|
1934
|
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1935 /******************* Bit definition for CAN_TDH1R register ******************/
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|
1936 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
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|
1937 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
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|
|
1938 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
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|
1939 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
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|
|
1940
|
|
|
1941 /******************* Bit definition for CAN_TI2R register *******************/
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|
|
1942 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
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|
|
1943 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
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|
|
1944 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
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|
|
1945 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
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|
|
1946 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
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|
|
1947
|
|
|
1948 /******************* Bit definition for CAN_TDT2R register ******************/
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|
|
1949 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
|
|
|
1950 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
|
|
|
1951 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
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|
|
1952
|
|
|
1953 /******************* Bit definition for CAN_TDL2R register ******************/
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|
|
1954 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
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|
|
1955 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
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|
|
1956 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
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|
1957 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
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|
|
1958
|
|
|
1959 /******************* Bit definition for CAN_TDH2R register ******************/
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|
|
1960 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
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|
|
1961 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
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|
|
1962 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
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|
|
1963 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
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|
|
1964
|
|
|
1965 /******************* Bit definition for CAN_RI0R register *******************/
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|
1966 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
|
|
|
1967 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
|
|
|
1968 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
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|
|
1969 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
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|
|
1970
|
|
|
1971 /******************* Bit definition for CAN_RDT0R register ******************/
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|
|
1972 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
|
|
|
1973 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
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|
|
1974 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
|
|
|
1975
|
|
|
1976 /******************* Bit definition for CAN_RDL0R register ******************/
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|
|
1977 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
|
|
|
1978 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
|
|
|
1979 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
|
|
|
1980 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
|
|
|
1981
|
|
|
1982 /******************* Bit definition for CAN_RDH0R register ******************/
|
|
|
1983 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
|
|
|
1984 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
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|
|
1985 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
|
|
|
1986 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
|
|
|
1987
|
|
|
1988 /******************* Bit definition for CAN_RI1R register *******************/
|
|
|
1989 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
|
|
|
1990 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
|
|
|
1991 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
|
|
|
1992 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
|
|
|
1993
|
|
|
1994 /******************* Bit definition for CAN_RDT1R register ******************/
|
|
|
1995 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
|
|
|
1996 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
|
|
|
1997 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
|
|
|
1998
|
|
|
1999 /******************* Bit definition for CAN_RDL1R register ******************/
|
|
|
2000 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
|
|
|
2001 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
|
|
|
2002 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
|
|
|
2003 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
|
|
|
2004
|
|
|
2005 /******************* Bit definition for CAN_RDH1R register ******************/
|
|
|
2006 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
|
|
|
2007 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
|
|
|
2008 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
|
|
|
2009 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
|
|
|
2010
|
|
|
2011 /*!<CAN filter registers */
|
|
|
2012 /******************* Bit definition for CAN_FMR register ********************/
|
|
|
2013 #define CAN_FMR_FINIT ((uint32_t)0x01) /*!<Filter Init Mode */
|
|
|
2014 #define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
|
|
|
2015
|
|
|
2016 /******************* Bit definition for CAN_FM1R register *******************/
|
|
|
2017 #define CAN_FM1R_FBM ((uint32_t)0x0FFFFFFF) /*!<Filter Mode */
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|
2018 #define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
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|
2019 #define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
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|
2020 #define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
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|
|
2021 #define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */
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|
|
2022 #define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */
|
|
|
2023 #define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */
|
|
|
2024 #define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */
|
|
|
2025 #define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */
|
|
|
2026 #define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */
|
|
|
2027 #define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */
|
|
|
2028 #define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */
|
|
|
2029 #define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
|
|
|
2030 #define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
|
|
|
2031 #define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
|
|
|
2032 #define CAN_FM1R_FBM14 ((uint32_t)0x00004000) /*!<Filter Init Mode bit 14 */
|
|
|
2033 #define CAN_FM1R_FBM15 ((uint32_t)0x00008000) /*!<Filter Init Mode bit 15 */
|
|
|
2034 #define CAN_FM1R_FBM16 ((uint32_t)0x00010000) /*!<Filter Init Mode bit 16 */
|
|
|
2035 #define CAN_FM1R_FBM17 ((uint32_t)0x00020000) /*!<Filter Init Mode bit 17 */
|
|
|
2036 #define CAN_FM1R_FBM18 ((uint32_t)0x00040000) /*!<Filter Init Mode bit 18 */
|
|
|
2037 #define CAN_FM1R_FBM19 ((uint32_t)0x00080000) /*!<Filter Init Mode bit 19 */
|
|
|
2038 #define CAN_FM1R_FBM20 ((uint32_t)0x00100000) /*!<Filter Init Mode bit 20 */
|
|
|
2039 #define CAN_FM1R_FBM21 ((uint32_t)0x00200000) /*!<Filter Init Mode bit 21 */
|
|
|
2040 #define CAN_FM1R_FBM22 ((uint32_t)0x00400000) /*!<Filter Init Mode bit 22 */
|
|
|
2041 #define CAN_FM1R_FBM23 ((uint32_t)0x00800000) /*!<Filter Init Mode bit 23 */
|
|
|
2042 #define CAN_FM1R_FBM24 ((uint32_t)0x01000000) /*!<Filter Init Mode bit 24 */
|
|
|
2043 #define CAN_FM1R_FBM25 ((uint32_t)0x02000000) /*!<Filter Init Mode bit 25 */
|
|
|
2044 #define CAN_FM1R_FBM26 ((uint32_t)0x04000000) /*!<Filter Init Mode bit 26 */
|
|
|
2045 #define CAN_FM1R_FBM27 ((uint32_t)0x08000000) /*!<Filter Init Mode bit 27 */
|
|
|
2046
|
|
|
2047 /******************* Bit definition for CAN_FS1R register *******************/
|
|
|
2048 #define CAN_FS1R_FSC ((uint32_t)0x0FFFFFFF) /*!<Filter Scale Configuration */
|
|
|
2049 #define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
|
|
|
2050 #define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
|
|
|
2051 #define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
|
|
|
2052 #define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
|
|
|
2053 #define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
|
|
|
2054 #define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
|
|
|
2055 #define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
|
|
|
2056 #define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
|
|
|
2057 #define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
|
|
|
2058 #define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
|
|
|
2059 #define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
|
|
|
2060 #define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
|
|
|
2061 #define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
|
|
|
2062 #define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
|
|
|
2063 #define CAN_FS1R_FSC14 ((uint32_t)0x00004000) /*!<Filter Scale Configuration bit 14 */
|
|
|
2064 #define CAN_FS1R_FSC15 ((uint32_t)0x00008000) /*!<Filter Scale Configuration bit 15 */
|
|
|
2065 #define CAN_FS1R_FSC16 ((uint32_t)0x00010000) /*!<Filter Scale Configuration bit 16 */
|
|
|
2066 #define CAN_FS1R_FSC17 ((uint32_t)0x00020000) /*!<Filter Scale Configuration bit 17 */
|
|
|
2067 #define CAN_FS1R_FSC18 ((uint32_t)0x00040000) /*!<Filter Scale Configuration bit 18 */
|
|
|
2068 #define CAN_FS1R_FSC19 ((uint32_t)0x00080000) /*!<Filter Scale Configuration bit 19 */
|
|
|
2069 #define CAN_FS1R_FSC20 ((uint32_t)0x00100000) /*!<Filter Scale Configuration bit 20 */
|
|
|
2070 #define CAN_FS1R_FSC21 ((uint32_t)0x00200000) /*!<Filter Scale Configuration bit 21 */
|
|
|
2071 #define CAN_FS1R_FSC22 ((uint32_t)0x00400000) /*!<Filter Scale Configuration bit 22 */
|
|
|
2072 #define CAN_FS1R_FSC23 ((uint32_t)0x00800000) /*!<Filter Scale Configuration bit 23 */
|
|
|
2073 #define CAN_FS1R_FSC24 ((uint32_t)0x01000000) /*!<Filter Scale Configuration bit 24 */
|
|
|
2074 #define CAN_FS1R_FSC25 ((uint32_t)0x02000000) /*!<Filter Scale Configuration bit 25 */
|
|
|
2075 #define CAN_FS1R_FSC26 ((uint32_t)0x04000000) /*!<Filter Scale Configuration bit 26 */
|
|
|
2076 #define CAN_FS1R_FSC27 ((uint32_t)0x08000000) /*!<Filter Scale Configuration bit 27 */
|
|
|
2077
|
|
|
2078 /****************** Bit definition for CAN_FFA1R register *******************/
|
|
|
2079 #define CAN_FFA1R_FFA ((uint32_t)0x0FFFFFFF) /*!<Filter FIFO Assignment */
|
|
|
2080 #define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment bit 0 */
|
|
|
2081 #define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment bit 1 */
|
|
|
2082 #define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment bit 2 */
|
|
|
2083 #define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment bit 3 */
|
|
|
2084 #define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment bit 4 */
|
|
|
2085 #define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment bit 5 */
|
|
|
2086 #define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment bit 6 */
|
|
|
2087 #define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment bit 7 */
|
|
|
2088 #define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment bit 8 */
|
|
|
2089 #define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment bit 9 */
|
|
|
2090 #define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment bit 10 */
|
|
|
2091 #define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment bit 11 */
|
|
|
2092 #define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment bit 12 */
|
|
|
2093 #define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment bit 13 */
|
|
|
2094 #define CAN_FFA1R_FFA14 ((uint32_t)0x00004000) /*!<Filter FIFO Assignment bit 14 */
|
|
|
2095 #define CAN_FFA1R_FFA15 ((uint32_t)0x00008000) /*!<Filter FIFO Assignment bit 15 */
|
|
|
2096 #define CAN_FFA1R_FFA16 ((uint32_t)0x00010000) /*!<Filter FIFO Assignment bit 16 */
|
|
|
2097 #define CAN_FFA1R_FFA17 ((uint32_t)0x00020000) /*!<Filter FIFO Assignment bit 17 */
|
|
|
2098 #define CAN_FFA1R_FFA18 ((uint32_t)0x00040000) /*!<Filter FIFO Assignment bit 18 */
|
|
|
2099 #define CAN_FFA1R_FFA19 ((uint32_t)0x00080000) /*!<Filter FIFO Assignment bit 19 */
|
|
|
2100 #define CAN_FFA1R_FFA20 ((uint32_t)0x00100000) /*!<Filter FIFO Assignment bit 20 */
|
|
|
2101 #define CAN_FFA1R_FFA21 ((uint32_t)0x00200000) /*!<Filter FIFO Assignment bit 21 */
|
|
|
2102 #define CAN_FFA1R_FFA22 ((uint32_t)0x00400000) /*!<Filter FIFO Assignment bit 22 */
|
|
|
2103 #define CAN_FFA1R_FFA23 ((uint32_t)0x00800000) /*!<Filter FIFO Assignment bit 23 */
|
|
|
2104 #define CAN_FFA1R_FFA24 ((uint32_t)0x01000000) /*!<Filter FIFO Assignment bit 24 */
|
|
|
2105 #define CAN_FFA1R_FFA25 ((uint32_t)0x02000000) /*!<Filter FIFO Assignment bit 25 */
|
|
|
2106 #define CAN_FFA1R_FFA26 ((uint32_t)0x04000000) /*!<Filter FIFO Assignment bit 26 */
|
|
|
2107 #define CAN_FFA1R_FFA27 ((uint32_t)0x08000000) /*!<Filter FIFO Assignment bit 27 */
|
|
|
2108
|
|
|
2109 /******************* Bit definition for CAN_FA1R register *******************/
|
|
|
2110 #define CAN_FA1R_FACT ((uint32_t)0x0FFFFFFF) /*!<Filter Active */
|
|
|
2111 #define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter Active bit 0 */
|
|
|
2112 #define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter Active bit 1 */
|
|
|
2113 #define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter Active bit 2 */
|
|
|
2114 #define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter Active bit 3 */
|
|
|
2115 #define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter Active bit 4 */
|
|
|
2116 #define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter Active bit 5 */
|
|
|
2117 #define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter Active bit 6 */
|
|
|
2118 #define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter Active bit 7 */
|
|
|
2119 #define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter Active bit 8 */
|
|
|
2120 #define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter Active bit 9 */
|
|
|
2121 #define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter Active bit 10 */
|
|
|
2122 #define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter Active bit 11 */
|
|
|
2123 #define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter Active bit 12 */
|
|
|
2124 #define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter Active bit 13 */
|
|
|
2125 #define CAN_FA1R_FACT14 ((uint32_t)0x00004000) /*!<Filter Active bit 14 */
|
|
|
2126 #define CAN_FA1R_FACT15 ((uint32_t)0x00008000) /*!<Filter Active bit 15 */
|
|
|
2127 #define CAN_FA1R_FACT16 ((uint32_t)0x00010000) /*!<Filter Active bit 16 */
|
|
|
2128 #define CAN_FA1R_FACT17 ((uint32_t)0x00020000) /*!<Filter Active bit 17 */
|
|
|
2129 #define CAN_FA1R_FACT18 ((uint32_t)0x00040000) /*!<Filter Active bit 18 */
|
|
|
2130 #define CAN_FA1R_FACT19 ((uint32_t)0x00080000) /*!<Filter Active bit 19 */
|
|
|
2131 #define CAN_FA1R_FACT20 ((uint32_t)0x00100000) /*!<Filter Active bit 20 */
|
|
|
2132 #define CAN_FA1R_FACT21 ((uint32_t)0x00200000) /*!<Filter Active bit 21 */
|
|
|
2133 #define CAN_FA1R_FACT22 ((uint32_t)0x00400000) /*!<Filter Active bit 22 */
|
|
|
2134 #define CAN_FA1R_FACT23 ((uint32_t)0x00800000) /*!<Filter Active bit 23 */
|
|
|
2135 #define CAN_FA1R_FACT24 ((uint32_t)0x01000000) /*!<Filter Active bit 24 */
|
|
|
2136 #define CAN_FA1R_FACT25 ((uint32_t)0x02000000) /*!<Filter Active bit 25 */
|
|
|
2137 #define CAN_FA1R_FACT26 ((uint32_t)0x04000000) /*!<Filter Active bit 26 */
|
|
|
2138 #define CAN_FA1R_FACT27 ((uint32_t)0x08000000) /*!<Filter Active bit 27 */
|
|
|
2139
|
|
|
2140 /******************* Bit definition for CAN_F0R1 register *******************/
|
|
|
2141 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2142 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2143 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2144 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2145 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2146 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2147 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2148 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2149 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2150 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2151 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2152 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2153 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2154 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2155 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2156 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2157 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2158 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2159 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2160 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2161 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2162 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2163 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2164 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2165 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2166 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2167 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2168 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2169 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2170 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2171 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2172 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2173
|
|
|
2174 /******************* Bit definition for CAN_F1R1 register *******************/
|
|
|
2175 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2176 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2177 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2178 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2179 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2180 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2181 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2182 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2183 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2184 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2185 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2186 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2187 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2188 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2189 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2190 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2191 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2192 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2193 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2194 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2195 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2196 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2197 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2198 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2199 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2200 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2201 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2202 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2203 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2204 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2205 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2206 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2207
|
|
|
2208 /******************* Bit definition for CAN_F2R1 register *******************/
|
|
|
2209 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2210 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2211 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2212 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2213 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2214 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2215 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2216 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2217 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2218 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2219 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2220 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2221 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2222 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2223 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2224 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2225 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2226 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2227 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2228 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2229 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2230 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2231 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2232 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2233 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2234 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2235 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2236 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2237 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2238 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2239 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2240 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2241
|
|
|
2242 /******************* Bit definition for CAN_F3R1 register *******************/
|
|
|
2243 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2244 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2245 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2246 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2247 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2248 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2249 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2250 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2251 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2252 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2253 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2254 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2255 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2256 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2257 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2258 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2259 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2260 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2261 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2262 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2263 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2264 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2265 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2266 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2267 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2268 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2269 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2270 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2271 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2272 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2273 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2274 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2275
|
|
|
2276 /******************* Bit definition for CAN_F4R1 register *******************/
|
|
|
2277 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2278 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2279 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2280 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2281 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2282 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2283 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2284 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2285 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2286 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2287 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2288 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2289 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2290 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2291 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2292 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2293 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2294 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2295 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2296 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2297 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2298 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2299 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2300 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2301 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2302 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2303 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2304 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2305 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2306 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2307 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2308 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2309
|
|
|
2310 /******************* Bit definition for CAN_F5R1 register *******************/
|
|
|
2311 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2312 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2313 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2314 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2315 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2316 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2317 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2318 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2319 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2320 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2321 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2322 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2323 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2324 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2325 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2326 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2327 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2328 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2329 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2330 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2331 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2332 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2333 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2334 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2335 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2336 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2337 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2338 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2339 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2340 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2341 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2342 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2343
|
|
|
2344 /******************* Bit definition for CAN_F6R1 register *******************/
|
|
|
2345 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2346 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2347 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2348 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2349 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2350 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2351 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2352 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2353 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2354 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2355 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2356 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2357 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2358 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2359 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2360 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2361 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2362 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2363 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2364 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2365 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2366 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2367 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2368 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2369 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2370 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2371 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2372 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2373 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2374 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2375 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2376 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2377
|
|
|
2378 /******************* Bit definition for CAN_F7R1 register *******************/
|
|
|
2379 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2380 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2381 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2382 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2383 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2384 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2385 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2386 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2387 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2388 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2389 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2390 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2391 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2392 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2393 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2394 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2395 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2396 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2397 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2398 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2399 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2400 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2401 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2402 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2403 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2404 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2405 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2406 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2407 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2408 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2409 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2410 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2411
|
|
|
2412 /******************* Bit definition for CAN_F8R1 register *******************/
|
|
|
2413 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2414 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2415 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2416 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2417 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2418 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2419 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2420 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2421 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2422 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2423 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2424 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2425 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2426 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2427 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2428 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2429 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2430 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2431 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2432 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2433 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2434 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2435 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2436 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2437 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2438 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2439 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2440 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2441 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2442 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2443 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2444 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2445
|
|
|
2446 /******************* Bit definition for CAN_F9R1 register *******************/
|
|
|
2447 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2448 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2449 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2450 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2451 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2452 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2453 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2454 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2455 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2456 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2457 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2458 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2459 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2460 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2461 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2462 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2463 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2464 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2465 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2466 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2467 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2468 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2469 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2470 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2471 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2472 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2473 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2474 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2475 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2476 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2477 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2478 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2479
|
|
|
2480 /******************* Bit definition for CAN_F10R1 register ******************/
|
|
|
2481 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2482 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2483 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2484 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2485 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2486 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2487 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2488 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2489 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2490 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2491 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2492 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2493 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2494 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2495 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2496 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2497 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2498 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2499 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2500 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2501 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2502 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2503 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2504 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2505 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2506 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2507 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2508 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2509 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2510 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2511 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2512 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2513
|
|
|
2514 /******************* Bit definition for CAN_F11R1 register ******************/
|
|
|
2515 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2516 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2517 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2518 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2519 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2520 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2521 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2522 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2523 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2524 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2525 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2526 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2527 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2528 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2529 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2530 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2531 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2532 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2533 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2534 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2535 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2536 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2537 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2538 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2539 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2540 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2541 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2542 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2543 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2544 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2545 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2546 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2547
|
|
|
2548 /******************* Bit definition for CAN_F12R1 register ******************/
|
|
|
2549 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2550 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2551 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2552 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2553 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2554 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2555 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2556 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2557 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2558 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2559 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2560 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2561 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2562 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2563 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2564 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2565 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2566 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2567 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2568 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2569 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2570 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2571 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2572 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2573 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2574 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2575 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2576 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2577 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2578 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2579 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2580 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2581
|
|
|
2582 /******************* Bit definition for CAN_F13R1 register ******************/
|
|
|
2583 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2584 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2585 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2586 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2587 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2588 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2589 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2590 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2591 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2592 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2593 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2594 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2595 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2596 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2597 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2598 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2599 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2600 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2601 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2602 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2603 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2604 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2605 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2606 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2607 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2608 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2609 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2610 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2611 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2612 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2613 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2614 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2615
|
|
|
2616 /******************* Bit definition for CAN_F0R2 register *******************/
|
|
|
2617 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2618 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2619 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2620 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2621 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2622 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2623 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2624 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2625 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2626 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2627 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2628 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2629 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2630 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2631 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2632 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2633 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2634 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2635 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2636 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2637 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2638 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2639 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2640 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2641 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2642 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2643 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2644 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2645 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2646 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2647 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2648 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2649
|
|
|
2650 /******************* Bit definition for CAN_F1R2 register *******************/
|
|
|
2651 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2652 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2653 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2654 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2655 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2656 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2657 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2658 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2659 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2660 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2661 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2662 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2663 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2664 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2665 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2666 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2667 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2668 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2669 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2670 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2671 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2672 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2673 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2674 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2675 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2676 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2677 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2678 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2679 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2680 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2681 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2682 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2683
|
|
|
2684 /******************* Bit definition for CAN_F2R2 register *******************/
|
|
|
2685 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2686 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2687 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2688 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2689 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2690 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2691 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2692 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2693 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2694 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2695 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2696 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2697 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2698 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2699 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2700 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2701 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2702 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2703 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2704 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2705 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2706 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2707 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2708 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2709 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2710 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2711 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2712 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2713 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2714 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2715 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2716 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2717
|
|
|
2718 /******************* Bit definition for CAN_F3R2 register *******************/
|
|
|
2719 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2720 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2721 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2722 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2723 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2724 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2725 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2726 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2727 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2728 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2729 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2730 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2731 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2732 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2733 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2734 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2735 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2736 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2737 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2738 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2739 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2740 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2741 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2742 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2743 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2744 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2745 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2746 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2747 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2748 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2749 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2750 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2751
|
|
|
2752 /******************* Bit definition for CAN_F4R2 register *******************/
|
|
|
2753 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2754 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2755 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2756 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2757 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2758 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2759 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2760 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2761 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2762 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2763 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2764 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2765 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2766 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2767 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2768 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2769 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2770 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2771 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2772 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2773 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2774 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2775 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2776 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2777 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2778 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2779 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2780 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2781 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2782 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2783 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2784 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2785
|
|
|
2786 /******************* Bit definition for CAN_F5R2 register *******************/
|
|
|
2787 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2788 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2789 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2790 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2791 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2792 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2793 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2794 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2795 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2796 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2797 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2798 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2799 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2800 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2801 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2802 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2803 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2804 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2805 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2806 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2807 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2808 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2809 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2810 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2811 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2812 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2813 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2814 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2815 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2816 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2817 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2818 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2819
|
|
|
2820 /******************* Bit definition for CAN_F6R2 register *******************/
|
|
|
2821 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2822 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2823 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2824 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2825 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2826 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2827 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2828 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2829 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2830 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2831 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2832 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2833 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2834 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2835 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2836 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2837 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2838 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2839 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2840 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2841 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2842 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2843 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2844 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2845 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2846 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2847 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2848 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2849 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2850 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2851 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2852 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2853
|
|
|
2854 /******************* Bit definition for CAN_F7R2 register *******************/
|
|
|
2855 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2856 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2857 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2858 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2859 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2860 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2861 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2862 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2863 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2864 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2865 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2866 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2867 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2868 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2869 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2870 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2871 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2872 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2873 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2874 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2875 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2876 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2877 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2878 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2879 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2880 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2881 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2882 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2883 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2884 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2885 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2886 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2887
|
|
|
2888 /******************* Bit definition for CAN_F8R2 register *******************/
|
|
|
2889 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2890 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2891 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2892 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2893 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2894 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2895 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2896 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2897 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2898 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2899 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2900 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2901 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2902 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2903 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2904 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2905 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2906 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2907 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2908 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2909 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2910 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2911 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2912 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2913 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2914 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2915 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2916 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2917 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2918 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2919 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2920 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2921
|
|
|
2922 /******************* Bit definition for CAN_F9R2 register *******************/
|
|
|
2923 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2924 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2925 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2926 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2927 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2928 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2929 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2930 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2931 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2932 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2933 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2934 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2935 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2936 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2937 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2938 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2939 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2940 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2941 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2942 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2943 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2944 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2945 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2946 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2947 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2948 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2949 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2950 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2951 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2952 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2953 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2954 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2955
|
|
|
2956 /******************* Bit definition for CAN_F10R2 register ******************/
|
|
|
2957 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2958 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2959 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2960 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2961 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2962 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2963 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2964 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2965 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2966 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2967 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2968 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2969 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2970 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2971 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2972 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2973 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2974 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2975 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2976 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2977 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2978 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2979 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2980 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2981 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2982 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2983 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2984 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2985 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2986 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2987 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2988 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2989
|
|
|
2990 /******************* Bit definition for CAN_F11R2 register ******************/
|
|
|
2991 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2992 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2993 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2994 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2995 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2996 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2997 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2998 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2999 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
3000 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
3001 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
3002 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
3003 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
3004 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
3005 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
3006 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
3007 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
3008 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
3009 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
3010 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
3011 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
3012 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
3013 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
3014 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
3015 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
3016 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
3017 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
3018 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
3019 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
3020 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
3021 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
3022 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
3023
|
|
|
3024 /******************* Bit definition for CAN_F12R2 register ******************/
|
|
|
3025 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
3026 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
3027 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
3028 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
3029 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
3030 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
3031 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
3032 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
3033 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
3034 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
3035 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
3036 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
3037 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
3038 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
3039 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
3040 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
3041 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
3042 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
3043 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
3044 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
3045 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
3046 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
3047 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
3048 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
3049 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
3050 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
3051 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
3052 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
3053 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
3054 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
3055 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
3056 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
3057
|
|
|
3058 /******************* Bit definition for CAN_F13R2 register ******************/
|
|
|
3059 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
3060 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
3061 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
3062 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
3063 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
3064 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
3065 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
3066 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
3067 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
3068 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
3069 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
3070 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
3071 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
3072 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
3073 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
3074 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
3075 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
3076 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
3077 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
3078 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
3079 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
3080 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
3081 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
3082 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
3083 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
3084 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
3085 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
3086 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
3087 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
3088 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
3089 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
3090 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
3091
|
|
|
3092 /******************************************************************************/
|
|
|
3093 /* */
|
|
|
3094 /* CRC calculation unit */
|
|
|
3095 /* */
|
|
|
3096 /******************************************************************************/
|
|
|
3097 /******************* Bit definition for CRC_DR register *********************/
|
|
|
3098 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
|
|
|
3099
|
|
|
3100
|
|
|
3101 /******************* Bit definition for CRC_IDR register ********************/
|
|
|
3102 #define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
|
|
|
3103
|
|
|
3104
|
|
|
3105 /******************** Bit definition for CRC_CR register ********************/
|
|
|
3106 #define CRC_CR_RESET ((uint32_t)0x01) /*!< RESET bit */
|
|
|
3107
|
|
|
3108 /******************************************************************************/
|
|
|
3109 /* */
|
|
|
3110 /* Crypto Processor */
|
|
|
3111 /* */
|
|
|
3112 /******************************************************************************/
|
|
|
3113 /******************* Bits definition for CRYP_CR register ********************/
|
|
|
3114 #define CRYP_CR_ALGODIR ((uint32_t)0x00000004)
|
|
|
3115
|
|
|
3116 #define CRYP_CR_ALGOMODE ((uint32_t)0x00080038)
|
|
|
3117 #define CRYP_CR_ALGOMODE_0 ((uint32_t)0x00000008)
|
|
|
3118 #define CRYP_CR_ALGOMODE_1 ((uint32_t)0x00000010)
|
|
|
3119 #define CRYP_CR_ALGOMODE_2 ((uint32_t)0x00000020)
|
|
|
3120 #define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)
|
|
|
3121 #define CRYP_CR_ALGOMODE_TDES_CBC ((uint32_t)0x00000008)
|
|
|
3122 #define CRYP_CR_ALGOMODE_DES_ECB ((uint32_t)0x00000010)
|
|
|
3123 #define CRYP_CR_ALGOMODE_DES_CBC ((uint32_t)0x00000018)
|
|
|
3124 #define CRYP_CR_ALGOMODE_AES_ECB ((uint32_t)0x00000020)
|
|
|
3125 #define CRYP_CR_ALGOMODE_AES_CBC ((uint32_t)0x00000028)
|
|
|
3126 #define CRYP_CR_ALGOMODE_AES_CTR ((uint32_t)0x00000030)
|
|
|
3127 #define CRYP_CR_ALGOMODE_AES_KEY ((uint32_t)0x00000038)
|
|
|
3128
|
|
|
3129 #define CRYP_CR_DATATYPE ((uint32_t)0x000000C0)
|
|
|
3130 #define CRYP_CR_DATATYPE_0 ((uint32_t)0x00000040)
|
|
|
3131 #define CRYP_CR_DATATYPE_1 ((uint32_t)0x00000080)
|
|
|
3132 #define CRYP_CR_KEYSIZE ((uint32_t)0x00000300)
|
|
|
3133 #define CRYP_CR_KEYSIZE_0 ((uint32_t)0x00000100)
|
|
|
3134 #define CRYP_CR_KEYSIZE_1 ((uint32_t)0x00000200)
|
|
|
3135 #define CRYP_CR_FFLUSH ((uint32_t)0x00004000)
|
|
|
3136 #define CRYP_CR_CRYPEN ((uint32_t)0x00008000)
|
|
|
3137
|
|
|
3138 #define CRYP_CR_GCM_CCMPH ((uint32_t)0x00030000)
|
|
|
3139 #define CRYP_CR_GCM_CCMPH_0 ((uint32_t)0x00010000)
|
|
|
3140 #define CRYP_CR_GCM_CCMPH_1 ((uint32_t)0x00020000)
|
|
|
3141 #define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000)
|
|
|
3142
|
|
|
3143 /****************** Bits definition for CRYP_SR register *********************/
|
|
|
3144 #define CRYP_SR_IFEM ((uint32_t)0x00000001)
|
|
|
3145 #define CRYP_SR_IFNF ((uint32_t)0x00000002)
|
|
|
3146 #define CRYP_SR_OFNE ((uint32_t)0x00000004)
|
|
|
3147 #define CRYP_SR_OFFU ((uint32_t)0x00000008)
|
|
|
3148 #define CRYP_SR_BUSY ((uint32_t)0x00000010)
|
|
|
3149 /****************** Bits definition for CRYP_DMACR register ******************/
|
|
|
3150 #define CRYP_DMACR_DIEN ((uint32_t)0x00000001)
|
|
|
3151 #define CRYP_DMACR_DOEN ((uint32_t)0x00000002)
|
|
|
3152 /***************** Bits definition for CRYP_IMSCR register ******************/
|
|
|
3153 #define CRYP_IMSCR_INIM ((uint32_t)0x00000001)
|
|
|
3154 #define CRYP_IMSCR_OUTIM ((uint32_t)0x00000002)
|
|
|
3155 /****************** Bits definition for CRYP_RISR register *******************/
|
|
|
3156 #define CRYP_RISR_OUTRIS ((uint32_t)0x00000001)
|
|
|
3157 #define CRYP_RISR_INRIS ((uint32_t)0x00000002)
|
|
|
3158 /****************** Bits definition for CRYP_MISR register *******************/
|
|
|
3159 #define CRYP_MISR_INMIS ((uint32_t)0x00000001)
|
|
|
3160 #define CRYP_MISR_OUTMIS ((uint32_t)0x00000002)
|
|
|
3161
|
|
|
3162 /******************************************************************************/
|
|
|
3163 /* */
|
|
|
3164 /* Digital to Analog Converter */
|
|
|
3165 /* */
|
|
|
3166 /******************************************************************************/
|
|
|
3167 /******************** Bit definition for DAC_CR register ********************/
|
|
|
3168 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
|
|
|
3169 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
|
|
|
3170 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
|
|
|
3171
|
|
|
3172 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
|
|
|
3173 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
|
|
|
3174 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
|
|
|
3175 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
|
|
|
3176
|
|
|
3177 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
|
|
|
3178 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
|
|
|
3179 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
|
|
|
3180
|
|
|
3181 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
|
|
|
3182 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
|
|
3183 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
|
|
3184 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
|
|
3185 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
|
|
3186
|
|
|
3187 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
|
|
|
3188 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
|
|
|
3189 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
|
|
|
3190 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
|
|
|
3191
|
|
|
3192 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
|
|
|
3193 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
|
|
|
3194 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
|
|
|
3195 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
|
|
|
3196
|
|
|
3197 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
|
|
|
3198 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
|
|
|
3199 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
|
|
|
3200
|
|
|
3201 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
|
|
|
3202 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
3203 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
3204 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
3205 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
|
|
3206
|
|
|
3207 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
|
|
|
3208
|
|
|
3209 /***************** Bit definition for DAC_SWTRIGR register ******************/
|
|
|
3210 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x01) /*!<DAC channel1 software trigger */
|
|
|
3211 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x02) /*!<DAC channel2 software trigger */
|
|
|
3212
|
|
|
3213 /***************** Bit definition for DAC_DHR12R1 register ******************/
|
|
|
3214 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
|
|
|
3215
|
|
|
3216 /***************** Bit definition for DAC_DHR12L1 register ******************/
|
|
|
3217 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
|
|
|
3218
|
|
|
3219 /****************** Bit definition for DAC_DHR8R1 register ******************/
|
|
|
3220 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
|
|
|
3221
|
|
|
3222 /***************** Bit definition for DAC_DHR12R2 register ******************/
|
|
|
3223 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
|
|
|
3224
|
|
|
3225 /***************** Bit definition for DAC_DHR12L2 register ******************/
|
|
|
3226 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
|
|
|
3227
|
|
|
3228 /****************** Bit definition for DAC_DHR8R2 register ******************/
|
|
|
3229 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
|
|
|
3230
|
|
|
3231 /***************** Bit definition for DAC_DHR12RD register ******************/
|
|
|
3232 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
|
|
|
3233 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
|
|
|
3234
|
|
|
3235 /***************** Bit definition for DAC_DHR12LD register ******************/
|
|
|
3236 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
|
|
|
3237 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
|
|
|
3238
|
|
|
3239 /****************** Bit definition for DAC_DHR8RD register ******************/
|
|
|
3240 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
|
|
|
3241 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
|
|
|
3242
|
|
|
3243 /******************* Bit definition for DAC_DOR1 register *******************/
|
|
|
3244 #define DAC_DOR1_DACC1DOR ((uint32_t)0x0FFF) /*!<DAC channel1 data output */
|
|
|
3245
|
|
|
3246 /******************* Bit definition for DAC_DOR2 register *******************/
|
|
|
3247 #define DAC_DOR2_DACC2DOR ((uint32_t)0x0FFF) /*!<DAC channel2 data output */
|
|
|
3248
|
|
|
3249 /******************** Bit definition for DAC_SR register ********************/
|
|
|
3250 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
|
|
|
3251 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
|
|
|
3252
|
|
|
3253 /******************************************************************************/
|
|
|
3254 /* */
|
|
|
3255 /* Debug MCU */
|
|
|
3256 /* */
|
|
|
3257 /******************************************************************************/
|
|
|
3258
|
|
|
3259 /******************************************************************************/
|
|
|
3260 /* */
|
|
|
3261 /* DCMI */
|
|
|
3262 /* */
|
|
|
3263 /******************************************************************************/
|
|
|
3264 /******************** Bits definition for DCMI_CR register ******************/
|
|
|
3265 #define DCMI_CR_CAPTURE ((uint32_t)0x00000001)
|
|
|
3266 #define DCMI_CR_CM ((uint32_t)0x00000002)
|
|
|
3267 #define DCMI_CR_CROP ((uint32_t)0x00000004)
|
|
|
3268 #define DCMI_CR_JPEG ((uint32_t)0x00000008)
|
|
|
3269 #define DCMI_CR_ESS ((uint32_t)0x00000010)
|
|
|
3270 #define DCMI_CR_PCKPOL ((uint32_t)0x00000020)
|
|
|
3271 #define DCMI_CR_HSPOL ((uint32_t)0x00000040)
|
|
|
3272 #define DCMI_CR_VSPOL ((uint32_t)0x00000080)
|
|
|
3273 #define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)
|
|
|
3274 #define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)
|
|
|
3275 #define DCMI_CR_EDM_0 ((uint32_t)0x00000400)
|
|
|
3276 #define DCMI_CR_EDM_1 ((uint32_t)0x00000800)
|
|
|
3277 #define DCMI_CR_CRE ((uint32_t)0x00001000)
|
|
|
3278 #define DCMI_CR_ENABLE ((uint32_t)0x00004000)
|
|
|
3279
|
|
|
3280 /******************** Bits definition for DCMI_SR register ******************/
|
|
|
3281 #define DCMI_SR_HSYNC ((uint32_t)0x00000001)
|
|
|
3282 #define DCMI_SR_VSYNC ((uint32_t)0x00000002)
|
|
|
3283 #define DCMI_SR_FNE ((uint32_t)0x00000004)
|
|
|
3284
|
|
|
3285 /******************** Bits definition for DCMI_RISR register ****************/
|
|
|
3286 #define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)
|
|
|
3287 #define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)
|
|
|
3288 #define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)
|
|
|
3289 #define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)
|
|
|
3290 #define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)
|
|
|
3291
|
|
|
3292 /******************** Bits definition for DCMI_IER register *****************/
|
|
|
3293 #define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)
|
|
|
3294 #define DCMI_IER_OVF_IE ((uint32_t)0x00000002)
|
|
|
3295 #define DCMI_IER_ERR_IE ((uint32_t)0x00000004)
|
|
|
3296 #define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)
|
|
|
3297 #define DCMI_IER_LINE_IE ((uint32_t)0x00000010)
|
|
|
3298
|
|
|
3299 /******************** Bits definition for DCMI_MISR register ****************/
|
|
|
3300 #define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)
|
|
|
3301 #define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)
|
|
|
3302 #define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)
|
|
|
3303 #define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)
|
|
|
3304 #define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)
|
|
|
3305
|
|
|
3306 /******************** Bits definition for DCMI_ICR register *****************/
|
|
|
3307 #define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)
|
|
|
3308 #define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)
|
|
|
3309 #define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)
|
|
|
3310 #define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)
|
|
|
3311 #define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)
|
|
|
3312
|
|
|
3313 /******************************************************************************/
|
|
|
3314 /* */
|
|
|
3315 /* DMA Controller */
|
|
|
3316 /* */
|
|
|
3317 /******************************************************************************/
|
|
|
3318 /******************** Bits definition for DMA_SxCR register *****************/
|
|
|
3319 #define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
|
|
|
3320 #define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
|
|
|
3321 #define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
|
|
|
3322 #define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
|
|
|
3323 #define DMA_SxCR_MBURST ((uint32_t)0x01800000)
|
|
|
3324 #define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
|
|
|
3325 #define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
|
|
|
3326 #define DMA_SxCR_PBURST ((uint32_t)0x00600000)
|
|
|
3327 #define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
|
|
|
3328 #define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
|
|
|
3329 #define DMA_SxCR_ACK ((uint32_t)0x00100000)
|
|
|
3330 #define DMA_SxCR_CT ((uint32_t)0x00080000)
|
|
|
3331 #define DMA_SxCR_DBM ((uint32_t)0x00040000)
|
|
|
3332 #define DMA_SxCR_PL ((uint32_t)0x00030000)
|
|
|
3333 #define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
|
|
|
3334 #define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
|
|
|
3335 #define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
|
|
|
3336 #define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
|
|
|
3337 #define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
|
|
|
3338 #define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
|
|
|
3339 #define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
|
|
|
3340 #define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
|
|
|
3341 #define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
|
|
|
3342 #define DMA_SxCR_MINC ((uint32_t)0x00000400)
|
|
|
3343 #define DMA_SxCR_PINC ((uint32_t)0x00000200)
|
|
|
3344 #define DMA_SxCR_CIRC ((uint32_t)0x00000100)
|
|
|
3345 #define DMA_SxCR_DIR ((uint32_t)0x000000C0)
|
|
|
3346 #define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
|
|
|
3347 #define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
|
|
|
3348 #define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
|
|
|
3349 #define DMA_SxCR_TCIE ((uint32_t)0x00000010)
|
|
|
3350 #define DMA_SxCR_HTIE ((uint32_t)0x00000008)
|
|
|
3351 #define DMA_SxCR_TEIE ((uint32_t)0x00000004)
|
|
|
3352 #define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
|
|
|
3353 #define DMA_SxCR_EN ((uint32_t)0x00000001)
|
|
|
3354
|
|
|
3355 /******************** Bits definition for DMA_SxCNDTR register **************/
|
|
|
3356 #define DMA_SxNDT ((uint32_t)0x0000FFFF)
|
|
|
3357 #define DMA_SxNDT_0 ((uint32_t)0x00000001)
|
|
|
3358 #define DMA_SxNDT_1 ((uint32_t)0x00000002)
|
|
|
3359 #define DMA_SxNDT_2 ((uint32_t)0x00000004)
|
|
|
3360 #define DMA_SxNDT_3 ((uint32_t)0x00000008)
|
|
|
3361 #define DMA_SxNDT_4 ((uint32_t)0x00000010)
|
|
|
3362 #define DMA_SxNDT_5 ((uint32_t)0x00000020)
|
|
|
3363 #define DMA_SxNDT_6 ((uint32_t)0x00000040)
|
|
|
3364 #define DMA_SxNDT_7 ((uint32_t)0x00000080)
|
|
|
3365 #define DMA_SxNDT_8 ((uint32_t)0x00000100)
|
|
|
3366 #define DMA_SxNDT_9 ((uint32_t)0x00000200)
|
|
|
3367 #define DMA_SxNDT_10 ((uint32_t)0x00000400)
|
|
|
3368 #define DMA_SxNDT_11 ((uint32_t)0x00000800)
|
|
|
3369 #define DMA_SxNDT_12 ((uint32_t)0x00001000)
|
|
|
3370 #define DMA_SxNDT_13 ((uint32_t)0x00002000)
|
|
|
3371 #define DMA_SxNDT_14 ((uint32_t)0x00004000)
|
|
|
3372 #define DMA_SxNDT_15 ((uint32_t)0x00008000)
|
|
|
3373
|
|
|
3374 /******************** Bits definition for DMA_SxFCR register ****************/
|
|
|
3375 #define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
|
|
|
3376 #define DMA_SxFCR_FS ((uint32_t)0x00000038)
|
|
|
3377 #define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
|
|
|
3378 #define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
|
|
|
3379 #define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
|
|
|
3380 #define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
|
|
|
3381 #define DMA_SxFCR_FTH ((uint32_t)0x00000003)
|
|
|
3382 #define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
|
|
|
3383 #define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
|
|
|
3384
|
|
|
3385 /******************** Bits definition for DMA_LISR register *****************/
|
|
|
3386 #define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
|
|
|
3387 #define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
|
|
|
3388 #define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
|
|
|
3389 #define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
|
|
|
3390 #define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
|
|
|
3391 #define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
|
|
|
3392 #define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
|
|
|
3393 #define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
|
|
|
3394 #define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
|
|
|
3395 #define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
|
|
|
3396 #define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
|
|
|
3397 #define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
|
|
|
3398 #define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
|
|
|
3399 #define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
|
|
|
3400 #define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
|
|
|
3401 #define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
|
|
|
3402 #define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
|
|
|
3403 #define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
|
|
|
3404 #define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
|
|
|
3405 #define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
|
|
|
3406
|
|
|
3407 /******************** Bits definition for DMA_HISR register *****************/
|
|
|
3408 #define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
|
|
|
3409 #define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
|
|
|
3410 #define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
|
|
|
3411 #define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
|
|
|
3412 #define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
|
|
|
3413 #define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
|
|
|
3414 #define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
|
|
|
3415 #define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
|
|
|
3416 #define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
|
|
|
3417 #define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
|
|
|
3418 #define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
|
|
|
3419 #define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
|
|
|
3420 #define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
|
|
|
3421 #define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
|
|
|
3422 #define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
|
|
|
3423 #define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
|
|
|
3424 #define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
|
|
|
3425 #define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
|
|
|
3426 #define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
|
|
|
3427 #define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
|
|
|
3428
|
|
|
3429 /******************** Bits definition for DMA_LIFCR register ****************/
|
|
|
3430 #define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
|
|
|
3431 #define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
|
|
|
3432 #define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
|
|
|
3433 #define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
|
|
|
3434 #define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
|
|
|
3435 #define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
|
|
|
3436 #define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
|
|
|
3437 #define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
|
|
|
3438 #define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
|
|
|
3439 #define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
|
|
|
3440 #define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
|
|
|
3441 #define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
|
|
|
3442 #define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
|
|
|
3443 #define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
|
|
|
3444 #define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
|
|
|
3445 #define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
|
|
|
3446 #define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
|
|
|
3447 #define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
|
|
|
3448 #define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
|
|
|
3449 #define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
|
|
|
3450
|
|
|
3451 /******************** Bits definition for DMA_HIFCR register ****************/
|
|
|
3452 #define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
|
|
|
3453 #define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
|
|
|
3454 #define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
|
|
|
3455 #define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
|
|
|
3456 #define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
|
|
|
3457 #define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
|
|
|
3458 #define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
|
|
|
3459 #define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
|
|
|
3460 #define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
|
|
|
3461 #define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
|
|
|
3462 #define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
|
|
|
3463 #define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
|
|
|
3464 #define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
|
|
|
3465 #define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
|
|
|
3466 #define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
|
|
|
3467 #define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
|
|
|
3468 #define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
|
|
|
3469 #define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
|
|
|
3470 #define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
|
|
|
3471 #define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
|
|
|
3472
|
|
|
3473
|
|
|
3474 /******************************************************************************/
|
|
|
3475 /* */
|
|
|
3476 /* AHB Master DMA2D Controller (DMA2D) */
|
|
|
3477 /* */
|
|
|
3478 /******************************************************************************/
|
|
|
3479
|
|
|
3480 /******************** Bit definition for DMA2D_CR register ******************/
|
|
|
3481
|
|
|
3482 #define DMA2D_CR_START ((uint32_t)0x00000001) /*!< Start transfer */
|
|
|
3483 #define DMA2D_CR_SUSP ((uint32_t)0x00000002) /*!< Suspend transfer */
|
|
|
3484 #define DMA2D_CR_ABORT ((uint32_t)0x00000004) /*!< Abort transfer */
|
|
|
3485 #define DMA2D_CR_TEIE ((uint32_t)0x00000100) /*!< Transfer Error Interrupt Enable */
|
|
|
3486 #define DMA2D_CR_TCIE ((uint32_t)0x00000200) /*!< Transfer Complete Interrupt Enable */
|
|
|
3487 #define DMA2D_CR_TWIE ((uint32_t)0x00000400) /*!< Transfer Watermark Interrupt Enable */
|
|
|
3488 #define DMA2D_CR_CAEIE ((uint32_t)0x00000800) /*!< CLUT Access Error Interrupt Enable */
|
|
|
3489 #define DMA2D_CR_CTCIE ((uint32_t)0x00001000) /*!< CLUT Transfer Complete Interrupt Enable */
|
|
|
3490 #define DMA2D_CR_CEIE ((uint32_t)0x00002000) /*!< Configuration Error Interrupt Enable */
|
|
|
3491 #define DMA2D_CR_MODE ((uint32_t)0x00030000) /*!< DMA2D Mode */
|
|
|
3492
|
|
|
3493 /******************** Bit definition for DMA2D_ISR register *****************/
|
|
|
3494
|
|
|
3495 #define DMA2D_ISR_TEIF ((uint32_t)0x00000001) /*!< Transfer Error Interrupt Flag */
|
|
|
3496 #define DMA2D_ISR_TCIF ((uint32_t)0x00000002) /*!< Transfer Complete Interrupt Flag */
|
|
|
3497 #define DMA2D_ISR_TWIF ((uint32_t)0x00000004) /*!< Transfer Watermark Interrupt Flag */
|
|
|
3498 #define DMA2D_ISR_CAEIF ((uint32_t)0x00000008) /*!< CLUT Access Error Interrupt Flag */
|
|
|
3499 #define DMA2D_ISR_CTCIF ((uint32_t)0x00000010) /*!< CLUT Transfer Complete Interrupt Flag */
|
|
|
3500 #define DMA2D_ISR_CEIF ((uint32_t)0x00000020) /*!< Configuration Error Interrupt Flag */
|
|
|
3501
|
|
|
3502 /******************** Bit definition for DMA2D_IFSR register ****************/
|
|
|
3503
|
|
|
3504 #define DMA2D_IFSR_CTEIF ((uint32_t)0x00000001) /*!< Clears Transfer Error Interrupt Flag */
|
|
|
3505 #define DMA2D_IFSR_CTCIF ((uint32_t)0x00000002) /*!< Clears Transfer Complete Interrupt Flag */
|
|
|
3506 #define DMA2D_IFSR_CTWIF ((uint32_t)0x00000004) /*!< Clears Transfer Watermark Interrupt Flag */
|
|
|
3507 #define DMA2D_IFSR_CCAEIF ((uint32_t)0x00000008) /*!< Clears CLUT Access Error Interrupt Flag */
|
|
|
3508 #define DMA2D_IFSR_CCTCIF ((uint32_t)0x00000010) /*!< Clears CLUT Transfer Complete Interrupt Flag */
|
|
|
3509 #define DMA2D_IFSR_CCEIF ((uint32_t)0x00000020) /*!< Clears Configuration Error Interrupt Flag */
|
|
|
3510
|
|
|
3511 /******************** Bit definition for DMA2D_FGMAR register ***************/
|
|
|
3512
|
|
|
3513 #define DMA2D_FGMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
|
|
|
3514
|
|
|
3515 /******************** Bit definition for DMA2D_FGOR register ****************/
|
|
|
3516
|
|
|
3517 #define DMA2D_FGOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */
|
|
|
3518
|
|
|
3519 /******************** Bit definition for DMA2D_BGMAR register ***************/
|
|
|
3520
|
|
|
3521 #define DMA2D_BGMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
|
|
|
3522
|
|
|
3523 /******************** Bit definition for DMA2D_BGOR register ****************/
|
|
|
3524
|
|
|
3525 #define DMA2D_BGOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */
|
|
|
3526
|
|
|
3527 /******************** Bit definition for DMA2D_FGPFCCR register *************/
|
|
|
3528
|
|
|
3529 #define DMA2D_FGPFCCR_CM ((uint32_t)0x0000000F) /*!< Color mode */
|
|
|
3530 #define DMA2D_FGPFCCR_CCM ((uint32_t)0x00000010) /*!< CLUT Color mode */
|
|
|
3531 #define DMA2D_FGPFCCR_START ((uint32_t)0x00000020) /*!< Start */
|
|
|
3532 #define DMA2D_FGPFCCR_CS ((uint32_t)0x0000FF00) /*!< CLUT size */
|
|
|
3533 #define DMA2D_FGPFCCR_AM ((uint32_t)0x00030000) /*!< Alpha mode */
|
|
|
3534 #define DMA2D_FGPFCCR_ALPHA ((uint32_t)0xFF000000) /*!< Alpha value */
|
|
|
3535
|
|
|
3536 /******************** Bit definition for DMA2D_FGCOLR register **************/
|
|
|
3537
|
|
|
3538 #define DMA2D_FGCOLR_BLUE ((uint32_t)0x000000FF) /*!< Blue Value */
|
|
|
3539 #define DMA2D_FGCOLR_GREEN ((uint32_t)0x0000FF00) /*!< Green Value */
|
|
|
3540 #define DMA2D_FGCOLR_RED ((uint32_t)0x00FF0000) /*!< Red Value */
|
|
|
3541
|
|
|
3542 /******************** Bit definition for DMA2D_BGPFCCR register *************/
|
|
|
3543
|
|
|
3544 #define DMA2D_BGPFCCR_CM ((uint32_t)0x0000000F) /*!< Color mode */
|
|
|
3545 #define DMA2D_BGPFCCR_CCM ((uint32_t)0x00000010) /*!< CLUT Color mode */
|
|
|
3546 #define DMA2D_BGPFCCR_START ((uint32_t)0x00000020) /*!< Start */
|
|
|
3547 #define DMA2D_BGPFCCR_CS ((uint32_t)0x0000FF00) /*!< CLUT size */
|
|
|
3548 #define DMA2D_BGPFCCR_AM ((uint32_t)0x00030000) /*!< Alpha Mode */
|
|
|
3549 #define DMA2D_BGPFCCR_ALPHA ((uint32_t)0xFF000000) /*!< Alpha value */
|
|
|
3550
|
|
|
3551 /******************** Bit definition for DMA2D_BGCOLR register **************/
|
|
|
3552
|
|
|
3553 #define DMA2D_BGCOLR_BLUE ((uint32_t)0x000000FF) /*!< Blue Value */
|
|
|
3554 #define DMA2D_BGCOLR_GREEN ((uint32_t)0x0000FF00) /*!< Green Value */
|
|
|
3555 #define DMA2D_BGCOLR_RED ((uint32_t)0x00FF0000) /*!< Red Value */
|
|
|
3556
|
|
|
3557 /******************** Bit definition for DMA2D_FGCMAR register **************/
|
|
|
3558
|
|
|
3559 #define DMA2D_FGCMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
|
|
|
3560
|
|
|
3561 /******************** Bit definition for DMA2D_BGCMAR register **************/
|
|
|
3562
|
|
|
3563 #define DMA2D_BGCMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
|
|
|
3564
|
|
|
3565 /******************** Bit definition for DMA2D_OPFCCR register **************/
|
|
|
3566
|
|
|
3567 #define DMA2D_OPFCCR_CM ((uint32_t)0x00000007) /*!< Color mode */
|
|
|
3568
|
|
|
3569 /******************** Bit definition for DMA2D_OCOLR register ***************/
|
|
|
3570
|
|
|
3571 /*!<Mode_ARGB8888/RGB888 */
|
|
|
3572
|
|
|
3573 #define DMA2D_OCOLR_BLUE_1 ((uint32_t)0x000000FF) /*!< BLUE Value */
|
|
|
3574 #define DMA2D_OCOLR_GREEN_1 ((uint32_t)0x0000FF00) /*!< GREEN Value */
|
|
|
3575 #define DMA2D_OCOLR_RED_1 ((uint32_t)0x00FF0000) /*!< Red Value */
|
|
|
3576 #define DMA2D_OCOLR_ALPHA_1 ((uint32_t)0xFF000000) /*!< Alpha Channel Value */
|
|
|
3577
|
|
|
3578 /*!<Mode_RGB565 */
|
|
|
3579 #define DMA2D_OCOLR_BLUE_2 ((uint32_t)0x0000001F) /*!< BLUE Value */
|
|
|
3580 #define DMA2D_OCOLR_GREEN_2 ((uint32_t)0x000007E0) /*!< GREEN Value */
|
|
|
3581 #define DMA2D_OCOLR_RED_2 ((uint32_t)0x0000F800) /*!< Red Value */
|
|
|
3582
|
|
|
3583 /*!<Mode_ARGB1555 */
|
|
|
3584 #define DMA2D_OCOLR_BLUE_3 ((uint32_t)0x0000001F) /*!< BLUE Value */
|
|
|
3585 #define DMA2D_OCOLR_GREEN_3 ((uint32_t)0x000003E0) /*!< GREEN Value */
|
|
|
3586 #define DMA2D_OCOLR_RED_3 ((uint32_t)0x00007C00) /*!< Red Value */
|
|
|
3587 #define DMA2D_OCOLR_ALPHA_3 ((uint32_t)0x00008000) /*!< Alpha Channel Value */
|
|
|
3588
|
|
|
3589 /*!<Mode_ARGB4444 */
|
|
|
3590 #define DMA2D_OCOLR_BLUE_4 ((uint32_t)0x0000000F) /*!< BLUE Value */
|
|
|
3591 #define DMA2D_OCOLR_GREEN_4 ((uint32_t)0x000000F0) /*!< GREEN Value */
|
|
|
3592 #define DMA2D_OCOLR_RED_4 ((uint32_t)0x00000F00) /*!< Red Value */
|
|
|
3593 #define DMA2D_OCOLR_ALPHA_4 ((uint32_t)0x0000F000) /*!< Alpha Channel Value */
|
|
|
3594
|
|
|
3595 /******************** Bit definition for DMA2D_OMAR register ****************/
|
|
|
3596
|
|
|
3597 #define DMA2D_OMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
|
|
|
3598
|
|
|
3599 /******************** Bit definition for DMA2D_OOR register *****************/
|
|
|
3600
|
|
|
3601 #define DMA2D_OOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */
|
|
|
3602
|
|
|
3603 /******************** Bit definition for DMA2D_NLR register *****************/
|
|
|
3604
|
|
|
3605 #define DMA2D_NLR_NL ((uint32_t)0x0000FFFF) /*!< Number of Lines */
|
|
|
3606 #define DMA2D_NLR_PL ((uint32_t)0x3FFF0000) /*!< Pixel per Lines */
|
|
|
3607
|
|
|
3608 /******************** Bit definition for DMA2D_LWR register *****************/
|
|
|
3609
|
|
|
3610 #define DMA2D_LWR_LW ((uint32_t)0x0000FFFF) /*!< Line Watermark */
|
|
|
3611
|
|
|
3612 /******************** Bit definition for DMA2D_AMTCR register ***************/
|
|
|
3613
|
|
|
3614 #define DMA2D_AMTCR_EN ((uint32_t)0x00000001) /*!< Enable */
|
|
|
3615 #define DMA2D_AMTCR_DT ((uint32_t)0x0000FF00) /*!< Dead Time */
|
|
|
3616
|
|
|
3617
|
|
|
3618 /******************** Bit definition for DMA2D_FGCLUT register **************/
|
|
|
3619
|
|
|
3620 /******************** Bit definition for DMA2D_BGCLUT register **************/
|
|
|
3621
|
|
|
3622
|
|
|
3623
|
|
|
3624 /******************************************************************************/
|
|
|
3625 /* */
|
|
|
3626 /* External Interrupt/Event Controller */
|
|
|
3627 /* */
|
|
|
3628 /******************************************************************************/
|
|
|
3629 /******************* Bit definition for EXTI_IMR register *******************/
|
|
|
3630 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
|
|
|
3631 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
|
|
|
3632 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
|
|
|
3633 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
|
|
|
3634 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
|
|
|
3635 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
|
|
|
3636 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
|
|
|
3637 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
|
|
|
3638 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
|
|
|
3639 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
|
|
|
3640 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
|
|
|
3641 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
|
|
|
3642 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
|
|
|
3643 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
|
|
|
3644 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
|
|
|
3645 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
|
|
|
3646 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
|
|
|
3647 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
|
|
|
3648 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
|
|
|
3649 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
|
|
|
3650
|
|
|
3651 /******************* Bit definition for EXTI_EMR register *******************/
|
|
|
3652 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
|
|
|
3653 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
|
|
|
3654 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
|
|
|
3655 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
|
|
|
3656 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
|
|
|
3657 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
|
|
|
3658 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
|
|
|
3659 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
|
|
|
3660 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
|
|
|
3661 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
|
|
|
3662 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
|
|
|
3663 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
|
|
|
3664 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
|
|
|
3665 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
|
|
|
3666 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
|
|
|
3667 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
|
|
|
3668 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
|
|
|
3669 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
|
|
|
3670 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
|
|
|
3671 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
|
|
|
3672
|
|
|
3673 /****************** Bit definition for EXTI_RTSR register *******************/
|
|
|
3674 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
|
|
|
3675 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
|
|
|
3676 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
|
|
|
3677 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
|
|
|
3678 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
|
|
|
3679 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
|
|
|
3680 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
|
|
|
3681 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
|
|
|
3682 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
|
|
|
3683 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
|
|
|
3684 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
|
|
|
3685 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
|
|
|
3686 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
|
|
|
3687 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
|
|
|
3688 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
|
|
|
3689 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
|
|
|
3690 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
|
|
|
3691 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
|
|
|
3692 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
|
|
|
3693 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
|
|
|
3694
|
|
|
3695 /****************** Bit definition for EXTI_FTSR register *******************/
|
|
|
3696 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
|
|
|
3697 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
|
|
|
3698 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
|
|
|
3699 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
|
|
|
3700 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
|
|
|
3701 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
|
|
|
3702 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
|
|
|
3703 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
|
|
|
3704 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
|
|
|
3705 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
|
|
|
3706 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
|
|
|
3707 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
|
|
|
3708 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
|
|
|
3709 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
|
|
|
3710 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
|
|
|
3711 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
|
|
|
3712 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
|
|
|
3713 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
|
|
|
3714 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
|
|
|
3715 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
|
|
|
3716
|
|
|
3717 /****************** Bit definition for EXTI_SWIER register ******************/
|
|
|
3718 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
|
|
|
3719 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
|
|
|
3720 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
|
|
|
3721 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
|
|
|
3722 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
|
|
|
3723 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
|
|
|
3724 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
|
|
|
3725 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
|
|
|
3726 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
|
|
|
3727 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
|
|
|
3728 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
|
|
|
3729 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
|
|
|
3730 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
|
|
|
3731 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
|
|
|
3732 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
|
|
|
3733 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
|
|
|
3734 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
|
|
|
3735 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
|
|
|
3736 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
|
|
|
3737 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
|
|
|
3738
|
|
|
3739 /******************* Bit definition for EXTI_PR register ********************/
|
|
|
3740 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
|
|
|
3741 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
|
|
|
3742 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
|
|
|
3743 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
|
|
|
3744 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
|
|
|
3745 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
|
|
|
3746 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
|
|
|
3747 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
|
|
|
3748 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
|
|
|
3749 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
|
|
|
3750 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
|
|
|
3751 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
|
|
|
3752 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
|
|
|
3753 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
|
|
|
3754 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
|
|
|
3755 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
|
|
|
3756 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
|
|
|
3757 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
|
|
|
3758 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
|
|
|
3759 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
|
|
|
3760
|
|
|
3761 /******************************************************************************/
|
|
|
3762 /* */
|
|
|
3763 /* FLASH */
|
|
|
3764 /* */
|
|
|
3765 /******************************************************************************/
|
|
|
3766 /******************* Bits definition for FLASH_ACR register *****************/
|
|
|
3767 #define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
|
|
|
3768 #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
|
|
|
3769 #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
|
|
|
3770 #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
|
|
|
3771 #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
|
|
|
3772 #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
|
|
|
3773 #define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
|
|
|
3774 #define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
|
|
|
3775 #define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
|
|
|
3776 #define FLASH_ACR_LATENCY_8WS ((uint32_t)0x00000008)
|
|
|
3777 #define FLASH_ACR_LATENCY_9WS ((uint32_t)0x00000009)
|
|
|
3778 #define FLASH_ACR_LATENCY_10WS ((uint32_t)0x0000000A)
|
|
|
3779 #define FLASH_ACR_LATENCY_11WS ((uint32_t)0x0000000B)
|
|
|
3780 #define FLASH_ACR_LATENCY_12WS ((uint32_t)0x0000000C)
|
|
|
3781 #define FLASH_ACR_LATENCY_13WS ((uint32_t)0x0000000D)
|
|
|
3782 #define FLASH_ACR_LATENCY_14WS ((uint32_t)0x0000000E)
|
|
|
3783 #define FLASH_ACR_LATENCY_15WS ((uint32_t)0x0000000F)
|
|
|
3784 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
|
|
|
3785 #define FLASH_ACR_ICEN ((uint32_t)0x00000200)
|
|
|
3786 #define FLASH_ACR_DCEN ((uint32_t)0x00000400)
|
|
|
3787 #define FLASH_ACR_ICRST ((uint32_t)0x00000800)
|
|
|
3788 #define FLASH_ACR_DCRST ((uint32_t)0x00001000)
|
|
|
3789 #define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
|
|
|
3790 #define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
|
|
|
3791
|
|
|
3792 /******************* Bits definition for FLASH_SR register ******************/
|
|
|
3793 #define FLASH_SR_EOP ((uint32_t)0x00000001)
|
|
|
3794 #define FLASH_SR_SOP ((uint32_t)0x00000002)
|
|
|
3795 #define FLASH_SR_WRPERR ((uint32_t)0x00000010)
|
|
|
3796 #define FLASH_SR_PGAERR ((uint32_t)0x00000020)
|
|
|
3797 #define FLASH_SR_PGPERR ((uint32_t)0x00000040)
|
|
|
3798 #define FLASH_SR_PGSERR ((uint32_t)0x00000080)
|
|
|
3799 #define FLASH_SR_BSY ((uint32_t)0x00010000)
|
|
|
3800
|
|
|
3801 /******************* Bits definition for FLASH_CR register ******************/
|
|
|
3802 #define FLASH_CR_PG ((uint32_t)0x00000001)
|
|
|
3803 #define FLASH_CR_SER ((uint32_t)0x00000002)
|
|
|
3804 #define FLASH_CR_MER ((uint32_t)0x00000004)
|
|
|
3805 #define FLASH_CR_MER1 FLASH_CR_MER
|
|
|
3806 #define FLASH_CR_SNB ((uint32_t)0x000000F8)
|
|
|
3807 #define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
|
|
|
3808 #define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
|
|
|
3809 #define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
|
|
|
3810 #define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
|
|
|
3811 #define FLASH_CR_SNB_4 ((uint32_t)0x00000080)
|
|
|
3812 #define FLASH_CR_PSIZE ((uint32_t)0x00000300)
|
|
|
3813 #define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
|
|
|
3814 #define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
|
|
|
3815 #define FLASH_CR_MER2 ((uint32_t)0x00008000)
|
|
|
3816 #define FLASH_CR_STRT ((uint32_t)0x00010000)
|
|
|
3817 #define FLASH_CR_EOPIE ((uint32_t)0x01000000)
|
|
|
3818 #define FLASH_CR_LOCK ((uint32_t)0x80000000)
|
|
|
3819
|
|
|
3820 /******************* Bits definition for FLASH_OPTCR register ***************/
|
|
|
3821 #define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
|
|
|
3822 #define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
|
|
|
3823 #define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
|
|
|
3824 #define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
|
|
|
3825 #define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
|
|
|
3826 #define FLASH_OPTCR_BFB2 ((uint32_t)0x00000010)
|
|
|
3827 #define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
|
|
|
3828 #define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
|
|
|
3829 #define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
|
|
|
3830 #define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
|
|
|
3831 #define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
|
|
|
3832 #define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
|
|
|
3833 #define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
|
|
|
3834 #define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
|
|
|
3835 #define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
|
|
|
3836 #define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
|
|
|
3837 #define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
|
|
|
3838 #define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
|
|
|
3839 #define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)
|
|
|
3840 #define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
|
|
|
3841 #define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
|
|
|
3842 #define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
|
|
|
3843 #define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
|
|
|
3844 #define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
|
|
|
3845 #define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
|
|
|
3846 #define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
|
|
|
3847 #define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
|
|
|
3848 #define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
|
|
|
3849 #define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
|
|
|
3850 #define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
|
|
|
3851 #define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
|
|
|
3852 #define FLASH_OPTCR_DB1M ((uint32_t)0x40000000)
|
|
|
3853 #define FLASH_OPTCR_SPRMOD ((uint32_t)0x80000000)
|
|
|
3854
|
|
|
3855 /****************** Bits definition for FLASH_OPTCR1 register ***************/
|
|
|
3856 #define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)
|
|
|
3857 #define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)
|
|
|
3858 #define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)
|
|
|
3859 #define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)
|
|
|
3860 #define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)
|
|
|
3861 #define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)
|
|
|
3862 #define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)
|
|
|
3863 #define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)
|
|
|
3864 #define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)
|
|
|
3865 #define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)
|
|
|
3866 #define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)
|
|
|
3867 #define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)
|
|
|
3868 #define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)
|
|
|
3869
|
|
|
3870 /******************************************************************************/
|
|
|
3871 /* */
|
|
|
3872 /* Flexible Memory Controller */
|
|
|
3873 /* */
|
|
|
3874 /******************************************************************************/
|
|
|
3875 /****************** Bit definition for FMC_BCR1 register *******************/
|
|
|
3876 #define FMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
|
|
|
3877 #define FMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
|
|
|
3878
|
|
|
3879 #define FMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
|
|
|
3880 #define FMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
|
|
|
3881 #define FMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
|
|
|
3882
|
|
|
3883 #define FMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
|
|
|
3884 #define FMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
3885 #define FMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
3886
|
|
|
3887 #define FMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
|
|
|
3888 #define FMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
|
|
|
3889 #define FMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
|
|
|
3890 #define FMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
|
|
|
3891 #define FMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
|
|
|
3892 #define FMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
|
|
|
3893 #define FMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
|
|
|
3894 #define FMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
|
|
|
3895 #define FMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
|
|
|
3896 #define FMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
|
|
|
3897 #define FMC_BCR1_CCLKEN ((uint32_t)0x00100000) /*!<Continous clock enable */
|
|
|
3898
|
|
|
3899 /****************** Bit definition for FMC_BCR2 register *******************/
|
|
|
3900 #define FMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
|
|
|
3901 #define FMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
|
|
|
3902
|
|
|
3903 #define FMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
|
|
|
3904 #define FMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
|
|
|
3905 #define FMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
|
|
|
3906
|
|
|
3907 #define FMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
|
|
|
3908 #define FMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
3909 #define FMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
3910
|
|
|
3911 #define FMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
|
|
|
3912 #define FMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
|
|
|
3913 #define FMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
|
|
|
3914 #define FMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
|
|
|
3915 #define FMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
|
|
|
3916 #define FMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
|
|
|
3917 #define FMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
|
|
|
3918 #define FMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
|
|
|
3919 #define FMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
|
|
|
3920 #define FMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
|
|
|
3921
|
|
|
3922 /****************** Bit definition for FMC_BCR3 register *******************/
|
|
|
3923 #define FMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
|
|
|
3924 #define FMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
|
|
|
3925
|
|
|
3926 #define FMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
|
|
|
3927 #define FMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
|
|
|
3928 #define FMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
|
|
|
3929
|
|
|
3930 #define FMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
|
|
|
3931 #define FMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
3932 #define FMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
3933
|
|
|
3934 #define FMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
|
|
|
3935 #define FMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
|
|
|
3936 #define FMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
|
|
|
3937 #define FMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
|
|
|
3938 #define FMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
|
|
|
3939 #define FMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
|
|
|
3940 #define FMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
|
|
|
3941 #define FMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
|
|
|
3942 #define FMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
|
|
|
3943 #define FMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
|
|
|
3944
|
|
|
3945 /****************** Bit definition for FMC_BCR4 register *******************/
|
|
|
3946 #define FMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
|
|
|
3947 #define FMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
|
|
|
3948
|
|
|
3949 #define FMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
|
|
|
3950 #define FMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
|
|
|
3951 #define FMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
|
|
|
3952
|
|
|
3953 #define FMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
|
|
|
3954 #define FMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
3955 #define FMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
3956
|
|
|
3957 #define FMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
|
|
|
3958 #define FMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
|
|
|
3959 #define FMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
|
|
|
3960 #define FMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
|
|
|
3961 #define FMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
|
|
|
3962 #define FMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
|
|
|
3963 #define FMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
|
|
|
3964 #define FMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
|
|
|
3965 #define FMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
|
|
|
3966 #define FMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
|
|
|
3967
|
|
|
3968 /****************** Bit definition for FMC_BTR1 register ******************/
|
|
|
3969 #define FMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
|
|
|
3970 #define FMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
3971 #define FMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
3972 #define FMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
3973 #define FMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
3974
|
|
|
3975 #define FMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
|
|
|
3976 #define FMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
3977 #define FMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
3978 #define FMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
|
|
3979 #define FMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
|
|
|
3980
|
|
|
3981 #define FMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
|
|
|
3982 #define FMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
|
|
3983 #define FMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
|
|
3984 #define FMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
|
|
3985 #define FMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
|
|
3986 #define FMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
|
|
3987 #define FMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
|
|
3988 #define FMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
|
|
3989 #define FMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
|
|
3990
|
|
|
3991 #define FMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
|
|
|
3992 #define FMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
3993 #define FMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
3994 #define FMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
|
|
3995 #define FMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
|
|
3996
|
|
|
3997 #define FMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
|
|
|
3998 #define FMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
|
|
3999 #define FMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
|
|
4000 #define FMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
|
|
|
4001 #define FMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
|
|
|
4002
|
|
|
4003 #define FMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
|
|
|
4004 #define FMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
4005 #define FMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
4006 #define FMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
4007 #define FMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
|
|
4008
|
|
|
4009 #define FMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
|
|
|
4010 #define FMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
|
|
|
4011 #define FMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
|
|
|
4012
|
|
|
4013 /****************** Bit definition for FMC_BTR2 register *******************/
|
|
|
4014 #define FMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
|
|
|
4015 #define FMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
4016 #define FMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
4017 #define FMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
4018 #define FMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
4019
|
|
|
4020 #define FMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
|
|
|
4021 #define FMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
4022 #define FMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
4023 #define FMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
|
|
4024 #define FMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
|
|
|
4025
|
|
|
4026 #define FMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
|
|
|
4027 #define FMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
|
|
4028 #define FMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
|
|
4029 #define FMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
|
|
4030 #define FMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
|
|
4031 #define FMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
|
|
4032 #define FMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
|
|
4033 #define FMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
|
|
4034 #define FMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
|
|
4035
|
|
|
4036 #define FMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
|
|
|
4037 #define FMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
4038 #define FMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
4039 #define FMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
|
|
4040 #define FMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
|
|
4041
|
|
|
4042 #define FMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
|
|
|
4043 #define FMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
|
|
4044 #define FMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
|
|
4045 #define FMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
|
|
|
4046 #define FMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
|
|
|
4047
|
|
|
4048 #define FMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
|
|
|
4049 #define FMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
4050 #define FMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
4051 #define FMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
4052 #define FMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
|
|
4053
|
|
|
4054 #define FMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
|
|
|
4055 #define FMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
|
|
|
4056 #define FMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
|
|
|
4057
|
|
|
4058 /******************* Bit definition for FMC_BTR3 register *******************/
|
|
|
4059 #define FMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
|
|
|
4060 #define FMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
4061 #define FMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
4062 #define FMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
4063 #define FMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
4064
|
|
|
4065 #define FMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
|
|
|
4066 #define FMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
4067 #define FMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
4068 #define FMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
|
|
4069 #define FMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
|
|
|
4070
|
|
|
4071 #define FMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
|
|
|
4072 #define FMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
|
|
4073 #define FMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
|
|
4074 #define FMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
|
|
4075 #define FMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
|
|
4076 #define FMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
|
|
4077 #define FMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
|
|
4078 #define FMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
|
|
4079 #define FMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
|
|
4080
|
|
|
4081 #define FMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
|
|
|
4082 #define FMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
4083 #define FMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
4084 #define FMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
|
|
4085 #define FMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
|
|
4086
|
|
|
4087 #define FMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
|
|
|
4088 #define FMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
|
|
4089 #define FMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
|
|
4090 #define FMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
|
|
|
4091 #define FMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
|
|
|
4092
|
|
|
4093 #define FMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
|
|
|
4094 #define FMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
4095 #define FMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
4096 #define FMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
4097 #define FMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
|
|
4098
|
|
|
4099 #define FMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
|
|
|
4100 #define FMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
|
|
|
4101 #define FMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
|
|
|
4102
|
|
|
4103 /****************** Bit definition for FMC_BTR4 register *******************/
|
|
|
4104 #define FMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
|
|
|
4105 #define FMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
4106 #define FMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
4107 #define FMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
4108 #define FMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
4109
|
|
|
4110 #define FMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
|
|
|
4111 #define FMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
4112 #define FMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
4113 #define FMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
|
|
4114 #define FMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
|
|
|
4115
|
|
|
4116 #define FMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
|
|
|
4117 #define FMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
|
|
4118 #define FMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
|
|
4119 #define FMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
|
|
4120 #define FMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
|
|
4121 #define FMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
|
|
4122 #define FMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
|
|
4123 #define FMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
|
|
4124 #define FMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
|
|
4125
|
|
|
4126 #define FMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
|
|
|
4127 #define FMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
4128 #define FMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
4129 #define FMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
|
|
4130 #define FMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
|
|
4131
|
|
|
4132 #define FMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
|
|
|
4133 #define FMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
|
|
4134 #define FMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
|
|
4135 #define FMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
|
|
|
4136 #define FMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
|
|
|
4137
|
|
|
4138 #define FMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
|
|
|
4139 #define FMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
4140 #define FMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
4141 #define FMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
4142 #define FMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
|
|
4143
|
|
|
4144 #define FMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
|
|
|
4145 #define FMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
|
|
|
4146 #define FMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
|
|
|
4147
|
|
|
4148 /****************** Bit definition for FMC_BWTR1 register ******************/
|
|
|
4149 #define FMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
|
|
|
4150 #define FMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
4151 #define FMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
4152 #define FMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
4153 #define FMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
4154
|
|
|
4155 #define FMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
|
|
|
4156 #define FMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
4157 #define FMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
4158 #define FMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
|
|
4159 #define FMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
|
|
|
4160
|
|
|
4161 #define FMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
|
|
|
4162 #define FMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
|
|
4163 #define FMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
|
|
4164 #define FMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
|
|
4165 #define FMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
|
|
4166 #define FMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
|
|
4167 #define FMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
|
|
4168 #define FMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
|
|
4169 #define FMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
|
|
4170
|
|
|
4171 #define FMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
|
|
|
4172 #define FMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
4173 #define FMC_BWTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
4174 #define FMC_BWTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
|
|
4175 #define FMC_BWTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
|
|
4176
|
|
|
4177 #define FMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
|
|
|
4178 #define FMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
|
|
4179 #define FMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
|
|
4180 #define FMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
|
|
|
4181 #define FMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
|
|
|
4182
|
|
|
4183 #define FMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
|
|
|
4184 #define FMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
4185 #define FMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
4186 #define FMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
4187 #define FMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
|
|
4188
|
|
|
4189 #define FMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
|
|
|
4190 #define FMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
|
|
|
4191 #define FMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
|
|
|
4192
|
|
|
4193 /****************** Bit definition for FMC_BWTR2 register ******************/
|
|
|
4194 #define FMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
|
|
|
4195 #define FMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
4196 #define FMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
4197 #define FMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
4198 #define FMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
4199
|
|
|
4200 #define FMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
|
|
|
4201 #define FMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
4202 #define FMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
4203 #define FMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
|
|
4204 #define FMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
|
|
|
4205
|
|
|
4206 #define FMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
|
|
|
4207 #define FMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
|
|
4208 #define FMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
|
|
4209 #define FMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
|
|
4210 #define FMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
|
|
4211 #define FMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
|
|
4212 #define FMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
|
|
4213 #define FMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
|
|
4214 #define FMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
|
|
4215
|
|
|
4216 #define FMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
|
|
|
4217 #define FMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
4218 #define FMC_BWTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
4219 #define FMC_BWTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
|
|
4220 #define FMC_BWTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
|
|
4221
|
|
|
4222 #define FMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
|
|
|
4223 #define FMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
|
|
4224 #define FMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/
|
|
|
4225 #define FMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
|
|
|
4226 #define FMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
|
|
|
4227
|
|
|
4228 #define FMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
|
|
|
4229 #define FMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
4230 #define FMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
4231 #define FMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
4232 #define FMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
|
|
4233
|
|
|
4234 #define FMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
|
|
|
4235 #define FMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
|
|
|
4236 #define FMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
|
|
|
4237
|
|
|
4238 /****************** Bit definition for FMC_BWTR3 register ******************/
|
|
|
4239 #define FMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
|
|
|
4240 #define FMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
4241 #define FMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
4242 #define FMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
4243 #define FMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
4244
|
|
|
4245 #define FMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
|
|
|
4246 #define FMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
4247 #define FMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
4248 #define FMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
|
|
4249 #define FMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
|
|
|
4250
|
|
|
4251 #define FMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
|
|
|
4252 #define FMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
|
|
4253 #define FMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
|
|
4254 #define FMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
|
|
4255 #define FMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
|
|
4256 #define FMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
|
|
4257 #define FMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
|
|
4258 #define FMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
|
|
4259 #define FMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
|
|
4260
|
|
|
4261 #define FMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
|
|
|
4262 #define FMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
4263 #define FMC_BWTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
4264 #define FMC_BWTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
|
|
4265 #define FMC_BWTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
|
|
4266
|
|
|
4267 #define FMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
|
|
|
4268 #define FMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
|
|
4269 #define FMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
|
|
4270 #define FMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
|
|
|
4271 #define FMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
|
|
|
4272
|
|
|
4273 #define FMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
|
|
|
4274 #define FMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
4275 #define FMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
4276 #define FMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
4277 #define FMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
|
|
4278
|
|
|
4279 #define FMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
|
|
|
4280 #define FMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
|
|
|
4281 #define FMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
|
|
|
4282
|
|
|
4283 /****************** Bit definition for FMC_BWTR4 register ******************/
|
|
|
4284 #define FMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
|
|
|
4285 #define FMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
4286 #define FMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
4287 #define FMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
4288 #define FMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
4289
|
|
|
4290 #define FMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
|
|
|
4291 #define FMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
4292 #define FMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
4293 #define FMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
|
|
4294 #define FMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
|
|
|
4295
|
|
|
4296 #define FMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
|
|
|
4297 #define FMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
|
|
4298 #define FMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
|
|
4299 #define FMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
|
|
4300 #define FMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
|
|
4301 #define FMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
|
|
4302 #define FMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
|
|
4303 #define FMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
|
|
4304 #define FMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
|
|
4305
|
|
|
4306 #define FMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
|
|
|
4307 #define FMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
4308 #define FMC_BWTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
4309 #define FMC_BWTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
|
|
4310 #define FMC_BWTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
|
|
4311
|
|
|
4312 #define FMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
|
|
|
4313 #define FMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
|
|
4314 #define FMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
|
|
4315 #define FMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
|
|
|
4316 #define FMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
|
|
|
4317
|
|
|
4318 #define FMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
|
|
|
4319 #define FMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
4320 #define FMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
4321 #define FMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
4322 #define FMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
|
|
4323
|
|
|
4324 #define FMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
|
|
|
4325 #define FMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
|
|
|
4326 #define FMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
|
|
|
4327
|
|
|
4328 /****************** Bit definition for FMC_PCR2 register *******************/
|
|
|
4329 #define FMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
|
|
|
4330 #define FMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
|
|
|
4331 #define FMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */
|
|
|
4332
|
|
|
4333 #define FMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
|
|
|
4334 #define FMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
4335 #define FMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
4336
|
|
|
4337 #define FMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
|
|
|
4338
|
|
|
4339 #define FMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
|
|
|
4340 #define FMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
|
|
|
4341 #define FMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
|
|
|
4342 #define FMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
|
|
|
4343 #define FMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
|
|
|
4344
|
|
|
4345 #define FMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
|
|
|
4346 #define FMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
|
|
|
4347 #define FMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
|
|
|
4348 #define FMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
|
|
|
4349 #define FMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
|
|
|
4350
|
|
|
4351 #define FMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */
|
|
|
4352 #define FMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
|
|
|
4353 #define FMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
|
|
|
4354 #define FMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
|
|
|
4355
|
|
|
4356 /****************** Bit definition for FMC_PCR3 register *******************/
|
|
|
4357 #define FMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
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|
|
4358 #define FMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
|
|
|
4359 #define FMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */
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|
4360
|
|
|
4361 #define FMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
|
|
|
4362 #define FMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
4363 #define FMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
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|
|
4364
|
|
|
4365 #define FMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
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|
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4366
|
|
|
4367 #define FMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
|
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|
4368 #define FMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
|
|
|
4369 #define FMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
|
|
|
4370 #define FMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
|
|
|
4371 #define FMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
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|
|
4372
|
|
|
4373 #define FMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
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|
4374 #define FMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
|
|
|
4375 #define FMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
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|
|
4376 #define FMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
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|
|
4377 #define FMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
|
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|
4378
|
|
|
4379 #define FMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
|
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|
4380 #define FMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
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|
|
4381 #define FMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
|
|
|
4382 #define FMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
|
|
|
4383
|
|
|
4384 /****************** Bit definition for FMC_PCR4 register *******************/
|
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|
4385 #define FMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
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|
4386 #define FMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
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|
|
4387 #define FMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */
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|
4388
|
|
|
4389 #define FMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
|
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|
4390 #define FMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
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|
4391 #define FMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
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4392
|
|
|
4393 #define FMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
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4394
|
|
|
4395 #define FMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
|
|
|
4396 #define FMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
|
|
|
4397 #define FMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
|
|
|
4398 #define FMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
|
|
|
4399 #define FMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
|
|
|
4400
|
|
|
4401 #define FMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
|
|
|
4402 #define FMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
|
|
|
4403 #define FMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
|
|
|
4404 #define FMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
|
|
|
4405 #define FMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
|
|
|
4406
|
|
|
4407 #define FMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
|
|
|
4408 #define FMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
|
|
|
4409 #define FMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
|
|
|
4410 #define FMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
|
|
|
4411
|
|
|
4412 /******************* Bit definition for FMC_SR2 register *******************/
|
|
|
4413 #define FMC_SR2_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
|
|
|
4414 #define FMC_SR2_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
|
|
|
4415 #define FMC_SR2_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
|
|
|
4416 #define FMC_SR2_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
|
|
|
4417 #define FMC_SR2_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
|
|
|
4418 #define FMC_SR2_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
|
|
|
4419 #define FMC_SR2_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
|
|
|
4420
|
|
|
4421 /******************* Bit definition for FMC_SR3 register *******************/
|
|
|
4422 #define FMC_SR3_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
|
|
|
4423 #define FMC_SR3_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
|
|
|
4424 #define FMC_SR3_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
|
|
|
4425 #define FMC_SR3_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
|
|
|
4426 #define FMC_SR3_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
|
|
|
4427 #define FMC_SR3_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
|
|
|
4428 #define FMC_SR3_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
|
|
|
4429
|
|
|
4430 /******************* Bit definition for FMC_SR4 register *******************/
|
|
|
4431 #define FMC_SR4_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
|
|
|
4432 #define FMC_SR4_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
|
|
|
4433 #define FMC_SR4_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
|
|
|
4434 #define FMC_SR4_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
|
|
|
4435 #define FMC_SR4_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
|
|
|
4436 #define FMC_SR4_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
|
|
|
4437 #define FMC_SR4_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
|
|
|
4438
|
|
|
4439 /****************** Bit definition for FMC_PMEM2 register ******************/
|
|
|
4440 #define FMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
|
|
|
4441 #define FMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
4442 #define FMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
4443 #define FMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
4444 #define FMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
4445 #define FMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
|
|
4446 #define FMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
|
|
|
4447 #define FMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
|
|
|
4448 #define FMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
|
|
|
4449
|
|
|
4450 #define FMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
|
|
|
4451 #define FMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
|
|
4452 #define FMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
|
|
4453 #define FMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
|
|
4454 #define FMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
|
|
4455 #define FMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
|
|
4456 #define FMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
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|
|
4457 #define FMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
|
|
4458 #define FMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
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|
|
4459
|
|
|
4460 #define FMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
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|
|
4461 #define FMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
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|
|
4462 #define FMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
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|
|
4463 #define FMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
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|
4464 #define FMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
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|
4465 #define FMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
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|
4466 #define FMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
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|
4467 #define FMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
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|
4468 #define FMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
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|
4469
|
|
|
4470 #define FMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
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|
|
4471 #define FMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
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|
4472 #define FMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
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|
|
4473 #define FMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
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|
4474 #define FMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
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4475 #define FMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
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4476 #define FMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
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4477 #define FMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
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|
4478 #define FMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
|
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|
4479
|
|
|
4480 /****************** Bit definition for FMC_PMEM3 register ******************/
|
|
|
4481 #define FMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
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|
|
4482 #define FMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
4483 #define FMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
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|
4484 #define FMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
4485 #define FMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
4486 #define FMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
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|
4487 #define FMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
|
|
|
4488 #define FMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
|
|
|
4489 #define FMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
|
|
|
4490
|
|
|
4491 #define FMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
|
|
|
4492 #define FMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
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|
|
4493 #define FMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
|
|
4494 #define FMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
|
|
4495 #define FMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
|
|
4496 #define FMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
|
|
4497 #define FMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
|
|
4498 #define FMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
|
|
4499 #define FMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
|
|
4500
|
|
|
4501 #define FMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
|
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|
4502 #define FMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
4503 #define FMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
4504 #define FMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
|
|
4505 #define FMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
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|
4506 #define FMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
|
|
|
4507 #define FMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
|
|
|
4508 #define FMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
|
|
|
4509 #define FMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
|
|
|
4510
|
|
|
4511 #define FMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
|
|
|
4512 #define FMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
4513 #define FMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
4514 #define FMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
4515 #define FMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
|
|
4516 #define FMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
|
|
|
4517 #define FMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
|
|
|
4518 #define FMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
|
|
|
4519 #define FMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
|
|
|
4520
|
|
|
4521 /****************** Bit definition for FMC_PMEM4 register ******************/
|
|
|
4522 #define FMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
|
|
|
4523 #define FMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
4524 #define FMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
4525 #define FMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
4526 #define FMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
4527 #define FMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
|
|
4528 #define FMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
|
|
|
4529 #define FMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
|
|
|
4530 #define FMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
|
|
|
4531
|
|
|
4532 #define FMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
|
|
|
4533 #define FMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
|
|
4534 #define FMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
|
|
4535 #define FMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
|
|
4536 #define FMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
|
|
4537 #define FMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
|
|
4538 #define FMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
|
|
4539 #define FMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
|
|
4540 #define FMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
|
|
4541
|
|
|
4542 #define FMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
|
|
|
4543 #define FMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
4544 #define FMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
4545 #define FMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
|
|
4546 #define FMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
|
|
4547 #define FMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
|
|
|
4548 #define FMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
|
|
|
4549 #define FMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
|
|
|
4550 #define FMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
|
|
|
4551
|
|
|
4552 #define FMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
|
|
|
4553 #define FMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
4554 #define FMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
4555 #define FMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
4556 #define FMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
|
|
4557 #define FMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
|
|
|
4558 #define FMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
|
|
|
4559 #define FMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
|
|
|
4560 #define FMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
|
|
|
4561
|
|
|
4562 /****************** Bit definition for FMC_PATT2 register ******************/
|
|
|
4563 #define FMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
|
|
|
4564 #define FMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
4565 #define FMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
4566 #define FMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
4567 #define FMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
4568 #define FMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
|
|
4569 #define FMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
|
|
|
4570 #define FMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
|
|
|
4571 #define FMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
|
|
|
4572
|
|
|
4573 #define FMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
|
|
|
4574 #define FMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
|
|
4575 #define FMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
|
|
4576 #define FMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
|
|
4577 #define FMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
|
|
4578 #define FMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
|
|
4579 #define FMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
|
|
4580 #define FMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
|
|
4581 #define FMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
|
|
4582
|
|
|
4583 #define FMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
|
|
|
4584 #define FMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
4585 #define FMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
4586 #define FMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
|
|
4587 #define FMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
|
|
4588 #define FMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
|
|
|
4589 #define FMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
|
|
|
4590 #define FMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
|
|
|
4591 #define FMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
|
|
|
4592
|
|
|
4593 #define FMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
|
|
|
4594 #define FMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
4595 #define FMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
4596 #define FMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
4597 #define FMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
|
|
4598 #define FMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
|
|
|
4599 #define FMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
|
|
|
4600 #define FMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
|
|
|
4601 #define FMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
|
|
|
4602
|
|
|
4603 /****************** Bit definition for FMC_PATT3 register ******************/
|
|
|
4604 #define FMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
|
|
|
4605 #define FMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
4606 #define FMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
4607 #define FMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
4608 #define FMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
4609 #define FMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
|
|
4610 #define FMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
|
|
|
4611 #define FMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
|
|
|
4612 #define FMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
|
|
|
4613
|
|
|
4614 #define FMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
|
|
|
4615 #define FMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
|
|
4616 #define FMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
|
|
4617 #define FMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
|
|
4618 #define FMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
|
|
4619 #define FMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
|
|
4620 #define FMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
|
|
4621 #define FMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
|
|
4622 #define FMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
|
|
4623
|
|
|
4624 #define FMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
|
|
|
4625 #define FMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
4626 #define FMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
4627 #define FMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
|
|
4628 #define FMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
|
|
4629 #define FMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
|
|
|
4630 #define FMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
|
|
|
4631 #define FMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
|
|
|
4632 #define FMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
|
|
|
4633
|
|
|
4634 #define FMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
|
|
|
4635 #define FMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
4636 #define FMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
4637 #define FMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
4638 #define FMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
|
|
4639 #define FMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
|
|
|
4640 #define FMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
|
|
|
4641 #define FMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
|
|
|
4642 #define FMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
|
|
|
4643
|
|
|
4644 /****************** Bit definition for FMC_PATT4 register ******************/
|
|
|
4645 #define FMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
|
|
|
4646 #define FMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
4647 #define FMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
4648 #define FMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
4649 #define FMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
4650 #define FMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
|
|
4651 #define FMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
|
|
|
4652 #define FMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
|
|
|
4653 #define FMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
|
|
|
4654
|
|
|
4655 #define FMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
|
|
|
4656 #define FMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
|
|
4657 #define FMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
|
|
4658 #define FMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
|
|
4659 #define FMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
|
|
4660 #define FMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
|
|
4661 #define FMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
|
|
4662 #define FMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
|
|
4663 #define FMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
|
|
4664
|
|
|
4665 #define FMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
|
|
|
4666 #define FMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
4667 #define FMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
4668 #define FMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
|
|
4669 #define FMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
|
|
4670 #define FMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
|
|
|
4671 #define FMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
|
|
|
4672 #define FMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
|
|
|
4673 #define FMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
|
|
|
4674
|
|
|
4675 #define FMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
|
|
|
4676 #define FMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
4677 #define FMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
4678 #define FMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
4679 #define FMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
|
|
4680 #define FMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
|
|
|
4681 #define FMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
|
|
|
4682 #define FMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
|
|
|
4683 #define FMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
|
|
|
4684
|
|
|
4685 /****************** Bit definition for FMC_PIO4 register *******************/
|
|
|
4686 #define FMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */
|
|
|
4687 #define FMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
4688 #define FMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
4689 #define FMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
4690 #define FMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
4691 #define FMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
|
|
4692 #define FMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
|
|
|
4693 #define FMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
|
|
|
4694 #define FMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
|
|
|
4695
|
|
|
4696 #define FMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
|
|
|
4697 #define FMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
|
|
4698 #define FMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
|
|
4699 #define FMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
|
|
4700 #define FMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
|
|
4701 #define FMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
|
|
4702 #define FMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
|
|
4703 #define FMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
|
|
4704 #define FMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
|
|
4705
|
|
|
4706 #define FMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
|
|
|
4707 #define FMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
4708 #define FMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
4709 #define FMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
|
|
4710 #define FMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
|
|
4711 #define FMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
|
|
|
4712 #define FMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
|
|
|
4713 #define FMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
|
|
|
4714 #define FMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
|
|
|
4715
|
|
|
4716 #define FMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
|
|
|
4717 #define FMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
4718 #define FMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
4719 #define FMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
4720 #define FMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
|
|
4721 #define FMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
|
|
|
4722 #define FMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
|
|
|
4723 #define FMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
|
|
|
4724 #define FMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
|
|
|
4725
|
|
|
4726 /****************** Bit definition for FMC_ECCR2 register ******************/
|
|
|
4727 #define FMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
|
|
|
4728
|
|
|
4729 /****************** Bit definition for FMC_ECCR3 register ******************/
|
|
|
4730 #define FMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
|
|
|
4731
|
|
|
4732 /****************** Bit definition for FMC_SDCR1 register ******************/
|
|
|
4733 #define FMC_SDCR1_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */
|
|
|
4734 #define FMC_SDCR1_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
4735 #define FMC_SDCR1_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
4736
|
|
|
4737 #define FMC_SDCR1_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */
|
|
|
4738 #define FMC_SDCR1_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */
|
|
|
4739 #define FMC_SDCR1_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */
|
|
|
4740
|
|
|
4741 #define FMC_SDCR1_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */
|
|
|
4742 #define FMC_SDCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
4743 #define FMC_SDCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
4744
|
|
|
4745 #define FMC_SDCR1_NB ((uint32_t)0x00000040) /*!<Number of internal bank */
|
|
|
4746
|
|
|
4747 #define FMC_SDCR1_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */
|
|
|
4748 #define FMC_SDCR1_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */
|
|
|
4749 #define FMC_SDCR1_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */
|
|
|
4750
|
|
|
4751 #define FMC_SDCR1_WP ((uint32_t)0x00000200) /*!<Write protection */
|
|
|
4752
|
|
|
4753 #define FMC_SDCR1_SDCLK ((uint32_t)0x00000C00) /*!<SDRAM clock configuration */
|
|
|
4754 #define FMC_SDCR1_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */
|
|
|
4755 #define FMC_SDCR1_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */
|
|
|
4756
|
|
|
4757 #define FMC_SDCR1_RBURST ((uint32_t)0x00001000) /*!<Read burst */
|
|
|
4758
|
|
|
4759 #define FMC_SDCR1_RPIPE ((uint32_t)0x00006000) /*!<Write protection */
|
|
|
4760 #define FMC_SDCR1_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */
|
|
|
4761 #define FMC_SDCR1_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */
|
|
|
4762
|
|
|
4763 /****************** Bit definition for FMC_SDCR2 register ******************/
|
|
|
4764 #define FMC_SDCR2_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */
|
|
|
4765 #define FMC_SDCR2_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
4766 #define FMC_SDCR2_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
4767
|
|
|
4768 #define FMC_SDCR2_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */
|
|
|
4769 #define FMC_SDCR2_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */
|
|
|
4770 #define FMC_SDCR2_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */
|
|
|
4771
|
|
|
4772 #define FMC_SDCR2_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */
|
|
|
4773 #define FMC_SDCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
4774 #define FMC_SDCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
4775
|
|
|
4776 #define FMC_SDCR2_NB ((uint32_t)0x00000040) /*!<Number of internal bank */
|
|
|
4777
|
|
|
4778 #define FMC_SDCR2_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */
|
|
|
4779 #define FMC_SDCR2_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */
|
|
|
4780 #define FMC_SDCR2_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */
|
|
|
4781
|
|
|
4782 #define FMC_SDCR2_WP ((uint32_t)0x00000200) /*!<Write protection */
|
|
|
4783
|
|
|
4784 #define FMC_SDCR2_SDCLK ((uint32_t)0x00000C00) /*!<SDCLK[1:0] (SDRAM clock configuration) */
|
|
|
4785 #define FMC_SDCR2_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */
|
|
|
4786 #define FMC_SDCR2_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */
|
|
|
4787
|
|
|
4788 #define FMC_SDCR2_RBURST ((uint32_t)0x00001000) /*!<Read burst */
|
|
|
4789
|
|
|
4790 #define FMC_SDCR2_RPIPE ((uint32_t)0x00006000) /*!<RPIPE[1:0](Read pipe) */
|
|
|
4791 #define FMC_SDCR2_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */
|
|
|
4792 #define FMC_SDCR2_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */
|
|
|
4793
|
|
|
4794 /****************** Bit definition for FMC_SDTR1 register ******************/
|
|
|
4795 #define FMC_SDTR1_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */
|
|
|
4796 #define FMC_SDTR1_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
4797 #define FMC_SDTR1_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
4798 #define FMC_SDTR1_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
4799 #define FMC_SDTR1_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
4800
|
|
|
4801 #define FMC_SDTR1_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */
|
|
|
4802 #define FMC_SDTR1_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
4803 #define FMC_SDTR1_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
4804 #define FMC_SDTR1_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
|
|
4805 #define FMC_SDTR1_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */
|
|
|
4806
|
|
|
4807 #define FMC_SDTR1_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */
|
|
|
4808 #define FMC_SDTR1_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
|
|
4809 #define FMC_SDTR1_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
|
|
4810 #define FMC_SDTR1_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
|
|
4811 #define FMC_SDTR1_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
|
|
4812
|
|
|
4813 #define FMC_SDTR1_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */
|
|
|
4814 #define FMC_SDTR1_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
|
|
|
4815 #define FMC_SDTR1_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
|
|
|
4816 #define FMC_SDTR1_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
|
|
|
4817
|
|
|
4818 #define FMC_SDTR1_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */
|
|
|
4819 #define FMC_SDTR1_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
4820 #define FMC_SDTR1_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
4821 #define FMC_SDTR1_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
|
|
4822
|
|
|
4823 #define FMC_SDTR1_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */
|
|
|
4824 #define FMC_SDTR1_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
|
|
4825 #define FMC_SDTR1_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
|
|
4826 #define FMC_SDTR1_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */
|
|
|
4827
|
|
|
4828 #define FMC_SDTR1_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */
|
|
|
4829 #define FMC_SDTR1_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
4830 #define FMC_SDTR1_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
4831 #define FMC_SDTR1_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
4832
|
|
|
4833 /****************** Bit definition for FMC_SDTR2 register ******************/
|
|
|
4834 #define FMC_SDTR2_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */
|
|
|
4835 #define FMC_SDTR2_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
4836 #define FMC_SDTR2_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
4837 #define FMC_SDTR2_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
4838 #define FMC_SDTR2_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
4839
|
|
|
4840 #define FMC_SDTR2_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */
|
|
|
4841 #define FMC_SDTR2_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
4842 #define FMC_SDTR2_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
4843 #define FMC_SDTR2_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
|
|
4844 #define FMC_SDTR2_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */
|
|
|
4845
|
|
|
4846 #define FMC_SDTR2_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */
|
|
|
4847 #define FMC_SDTR2_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
|
|
4848 #define FMC_SDTR2_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
|
|
4849 #define FMC_SDTR2_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
|
|
4850 #define FMC_SDTR2_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
|
|
4851
|
|
|
4852 #define FMC_SDTR2_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */
|
|
|
4853 #define FMC_SDTR2_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
|
|
|
4854 #define FMC_SDTR2_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
|
|
|
4855 #define FMC_SDTR2_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
|
|
|
4856
|
|
|
4857 #define FMC_SDTR2_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */
|
|
|
4858 #define FMC_SDTR2_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
4859 #define FMC_SDTR2_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
4860 #define FMC_SDTR2_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
|
|
4861
|
|
|
4862 #define FMC_SDTR2_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */
|
|
|
4863 #define FMC_SDTR2_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
|
|
4864 #define FMC_SDTR2_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
|
|
4865 #define FMC_SDTR2_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */
|
|
|
4866
|
|
|
4867 #define FMC_SDTR2_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */
|
|
|
4868 #define FMC_SDTR2_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
4869 #define FMC_SDTR2_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
4870 #define FMC_SDTR2_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
4871
|
|
|
4872 /****************** Bit definition for FMC_SDCMR register ******************/
|
|
|
4873 #define FMC_SDCMR_MODE ((uint32_t)0x00000007) /*!<MODE[2:0] bits (Command mode) */
|
|
|
4874 #define FMC_SDCMR_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
4875 #define FMC_SDCMR_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
4876 #define FMC_SDCMR_MODE_2 ((uint32_t)0x00000003) /*!<Bit 2 */
|
|
|
4877
|
|
|
4878 #define FMC_SDCMR_CTB2 ((uint32_t)0x00000008) /*!<Command target 2 */
|
|
|
4879
|
|
|
4880 #define FMC_SDCMR_CTB1 ((uint32_t)0x00000010) /*!<Command target 1 */
|
|
|
4881
|
|
|
4882 #define FMC_SDCMR_NRFS ((uint32_t)0x000001E0) /*!<NRFS[3:0] bits (Number of auto-refresh) */
|
|
|
4883 #define FMC_SDCMR_NRFS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
|
|
|
4884 #define FMC_SDCMR_NRFS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
|
|
|
4885 #define FMC_SDCMR_NRFS_2 ((uint32_t)0x00000080) /*!<Bit 2 */
|
|
|
4886 #define FMC_SDCMR_NRFS_3 ((uint32_t)0x00000100) /*!<Bit 3 */
|
|
|
4887
|
|
|
4888 #define FMC_SDCMR_MRD ((uint32_t)0x003FFE00) /*!<MRD[12:0] bits (Mode register definition) */
|
|
|
4889
|
|
|
4890 /****************** Bit definition for FMC_SDRTR register ******************/
|
|
|
4891 #define FMC_SDRTR_CRE ((uint32_t)0x00000001) /*!<Clear refresh error flag */
|
|
|
4892
|
|
|
4893 #define FMC_SDRTR_COUNT ((uint32_t)0x00003FFE) /*!<COUNT[12:0] bits (Refresh timer count) */
|
|
|
4894
|
|
|
4895 #define FMC_SDRTR_REIE ((uint32_t)0x00004000) /*!<RES interupt enable */
|
|
|
4896
|
|
|
4897 /****************** Bit definition for FMC_SDSR register ******************/
|
|
|
4898 #define FMC_SDSR_RE ((uint32_t)0x00000001) /*!<Refresh error flag */
|
|
|
4899
|
|
|
4900 #define FMC_SDSR_MODES1 ((uint32_t)0x00000006) /*!<MODES1[1:0]bits (Status mode for bank 1) */
|
|
|
4901 #define FMC_SDSR_MODES1_0 ((uint32_t)0x00000002) /*!<Bit 0 */
|
|
|
4902 #define FMC_SDSR_MODES1_1 ((uint32_t)0x00000004) /*!<Bit 1 */
|
|
|
4903
|
|
|
4904 #define FMC_SDSR_MODES2 ((uint32_t)0x00000018) /*!<MODES2[1:0]bits (Status mode for bank 2) */
|
|
|
4905 #define FMC_SDSR_MODES2_0 ((uint32_t)0x00000008) /*!<Bit 0 */
|
|
|
4906 #define FMC_SDSR_MODES2_1 ((uint32_t)0x00000010) /*!<Bit 1 */
|
|
|
4907 #define FMC_SDSR_BUSY ((uint32_t)0x00000020) /*!<Busy status */
|
|
|
4908
|
|
|
4909
|
|
|
4910
|
|
|
4911 /******************************************************************************/
|
|
|
4912 /* */
|
|
|
4913 /* General Purpose I/O */
|
|
|
4914 /* */
|
|
|
4915 /******************************************************************************/
|
|
|
4916 /****************** Bits definition for GPIO_MODER register *****************/
|
|
|
4917 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
|
|
|
4918 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
|
|
|
4919 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
|
|
|
4920
|
|
|
4921 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
|
|
|
4922 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
|
|
|
4923 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
|
|
|
4924
|
|
|
4925 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
|
|
|
4926 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
|
|
|
4927 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
|
|
|
4928
|
|
|
4929 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
|
|
|
4930 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
|
|
|
4931 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
|
|
|
4932
|
|
|
4933 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
|
|
|
4934 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
|
|
|
4935 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
|
|
|
4936
|
|
|
4937 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
|
|
|
4938 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
|
|
|
4939 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
|
|
|
4940
|
|
|
4941 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
|
|
|
4942 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
|
|
|
4943 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
|
|
|
4944
|
|
|
4945 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
|
|
|
4946 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
|
|
|
4947 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
|
|
|
4948
|
|
|
4949 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
|
|
|
4950 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
|
|
|
4951 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
|
|
|
4952
|
|
|
4953 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
|
|
|
4954 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
|
|
|
4955 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
|
|
|
4956
|
|
|
4957 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
|
|
|
4958 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
|
|
|
4959 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
|
|
|
4960
|
|
|
4961 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
|
|
|
4962 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
|
|
|
4963 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
|
|
|
4964
|
|
|
4965 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
|
|
|
4966 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
|
|
|
4967 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
|
|
|
4968
|
|
|
4969 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
|
|
|
4970 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
|
|
|
4971 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
|
|
|
4972
|
|
|
4973 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
|
|
|
4974 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
|
|
|
4975 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
|
|
|
4976
|
|
|
4977 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
|
|
|
4978 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
|
|
|
4979 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
|
|
|
4980
|
|
|
4981 /****************** Bits definition for GPIO_OTYPER register ****************/
|
|
|
4982 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
|
|
|
4983 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
|
|
|
4984 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
|
|
|
4985 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
|
|
|
4986 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
|
|
|
4987 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
|
|
|
4988 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
|
|
|
4989 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
|
|
|
4990 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
|
|
|
4991 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
|
|
|
4992 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
|
|
|
4993 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
|
|
|
4994 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
|
|
|
4995 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
|
|
|
4996 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
|
|
|
4997 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
|
|
|
4998
|
|
|
4999 /****************** Bits definition for GPIO_OSPEEDR register ***************/
|
|
|
5000 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
|
|
|
5001 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
|
|
|
5002 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
|
|
|
5003
|
|
|
5004 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
|
|
|
5005 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
|
|
|
5006 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
|
|
|
5007
|
|
|
5008 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
|
|
|
5009 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
|
|
|
5010 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
|
|
|
5011
|
|
|
5012 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
|
|
|
5013 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
|
|
|
5014 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
|
|
|
5015
|
|
|
5016 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
|
|
|
5017 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
|
|
|
5018 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
|
|
|
5019
|
|
|
5020 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
|
|
|
5021 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
|
|
|
5022 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
|
|
|
5023
|
|
|
5024 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
|
|
|
5025 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
|
|
|
5026 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
|
|
|
5027
|
|
|
5028 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
|
|
|
5029 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
|
|
|
5030 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
|
|
|
5031
|
|
|
5032 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
|
|
|
5033 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
|
|
|
5034 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
|
|
|
5035
|
|
|
5036 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
|
|
|
5037 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
|
|
|
5038 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
|
|
|
5039
|
|
|
5040 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
|
|
|
5041 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
|
|
|
5042 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
|
|
|
5043
|
|
|
5044 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
|
|
|
5045 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
|
|
|
5046 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
|
|
|
5047
|
|
|
5048 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
|
|
|
5049 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
|
|
|
5050 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
|
|
|
5051
|
|
|
5052 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
|
|
|
5053 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
|
|
|
5054 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
|
|
|
5055
|
|
|
5056 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
|
|
|
5057 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
|
|
|
5058 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
|
|
|
5059
|
|
|
5060 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
|
|
|
5061 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
|
|
|
5062 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
|
|
|
5063
|
|
|
5064 /****************** Bits definition for GPIO_PUPDR register *****************/
|
|
|
5065 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
|
|
|
5066 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
|
|
|
5067 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
|
|
|
5068
|
|
|
5069 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
|
|
|
5070 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
|
|
|
5071 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
|
|
|
5072
|
|
|
5073 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
|
|
|
5074 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
|
|
|
5075 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
|
|
|
5076
|
|
|
5077 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
|
|
|
5078 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
|
|
|
5079 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
|
|
|
5080
|
|
|
5081 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
|
|
|
5082 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
|
|
|
5083 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
|
|
|
5084
|
|
|
5085 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
|
|
|
5086 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
|
|
|
5087 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
|
|
|
5088
|
|
|
5089 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
|
|
|
5090 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
|
|
|
5091 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
|
|
|
5092
|
|
|
5093 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
|
|
|
5094 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
|
|
|
5095 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
|
|
|
5096
|
|
|
5097 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
|
|
|
5098 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
|
|
|
5099 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
|
|
|
5100
|
|
|
5101 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
|
|
|
5102 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
|
|
|
5103 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
|
|
|
5104
|
|
|
5105 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
|
|
|
5106 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
|
|
|
5107 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
|
|
|
5108
|
|
|
5109 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
|
|
|
5110 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
|
|
|
5111 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
|
|
|
5112
|
|
|
5113 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
|
|
|
5114 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
|
|
|
5115 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
|
|
|
5116
|
|
|
5117 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
|
|
|
5118 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
|
|
|
5119 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
|
|
|
5120
|
|
|
5121 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
|
|
|
5122 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
|
|
|
5123 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
|
|
|
5124
|
|
|
5125 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
|
|
|
5126 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
|
|
|
5127 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
|
|
|
5128
|
|
|
5129 /****************** Bits definition for GPIO_IDR register *******************/
|
|
|
5130 #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
|
|
|
5131 #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
|
|
|
5132 #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
|
|
|
5133 #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
|
|
|
5134 #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
|
|
|
5135 #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
|
|
|
5136 #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
|
|
|
5137 #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
|
|
|
5138 #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
|
|
|
5139 #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
|
|
|
5140 #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
|
|
|
5141 #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
|
|
|
5142 #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
|
|
|
5143 #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
|
|
|
5144 #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
|
|
|
5145 #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
|
|
|
5146 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
|
|
|
5147 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
|
|
|
5148 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
|
|
|
5149 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
|
|
|
5150 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
|
|
|
5151 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
|
|
|
5152 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
|
|
|
5153 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
|
|
|
5154 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
|
|
|
5155 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
|
|
|
5156 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
|
|
|
5157 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
|
|
|
5158 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
|
|
|
5159 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
|
|
|
5160 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
|
|
|
5161 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
|
|
|
5162 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
|
|
|
5163
|
|
|
5164 /****************** Bits definition for GPIO_ODR register *******************/
|
|
|
5165 #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
|
|
|
5166 #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
|
|
|
5167 #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
|
|
|
5168 #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
|
|
|
5169 #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
|
|
|
5170 #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
|
|
|
5171 #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
|
|
|
5172 #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
|
|
|
5173 #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
|
|
|
5174 #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
|
|
|
5175 #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
|
|
|
5176 #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
|
|
|
5177 #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
|
|
|
5178 #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
|
|
|
5179 #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
|
|
|
5180 #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
|
|
|
5181 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
|
|
|
5182 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
|
|
|
5183 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
|
|
|
5184 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
|
|
|
5185 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
|
|
|
5186 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
|
|
|
5187 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
|
|
|
5188 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
|
|
|
5189 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
|
|
|
5190 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
|
|
|
5191 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
|
|
|
5192 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
|
|
|
5193 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
|
|
|
5194 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
|
|
|
5195 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
|
|
|
5196 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
|
|
|
5197 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
|
|
|
5198
|
|
|
5199 /****************** Bits definition for GPIO_BSRR register ******************/
|
|
|
5200 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
|
|
|
5201 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
|
|
|
5202 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
|
|
|
5203 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
|
|
|
5204 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
|
|
|
5205 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
|
|
|
5206 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
|
|
|
5207 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
|
|
|
5208 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
|
|
|
5209 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
|
|
|
5210 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
|
|
|
5211 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
|
|
|
5212 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
|
|
|
5213 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
|
|
|
5214 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
|
|
|
5215 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
|
|
|
5216 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
|
|
|
5217 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
|
|
|
5218 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
|
|
|
5219 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
|
|
|
5220 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
|
|
|
5221 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
|
|
|
5222 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
|
|
|
5223 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
|
|
|
5224 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
|
|
|
5225 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
|
|
|
5226 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
|
|
|
5227 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
|
|
|
5228 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
|
|
|
5229 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
|
|
|
5230 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
|
|
|
5231 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
|
|
|
5232
|
|
|
5233 /****************** Bit definition for GPIO_LCKR register *********************/
|
|
|
5234 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
|
|
|
5235 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
|
|
|
5236 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
|
|
|
5237 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
|
|
|
5238 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
|
|
|
5239 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
|
|
|
5240 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
|
|
|
5241 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
|
|
|
5242 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
|
|
|
5243 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
|
|
|
5244 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
|
|
|
5245 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
|
|
|
5246 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
|
|
|
5247 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
|
|
|
5248 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
|
|
|
5249 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
|
|
|
5250 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
|
|
|
5251
|
|
|
5252 /******************************************************************************/
|
|
|
5253 /* */
|
|
|
5254 /* HASH */
|
|
|
5255 /* */
|
|
|
5256 /******************************************************************************/
|
|
|
5257 /****************** Bits definition for HASH_CR register ********************/
|
|
|
5258 #define HASH_CR_INIT ((uint32_t)0x00000004)
|
|
|
5259 #define HASH_CR_DMAE ((uint32_t)0x00000008)
|
|
|
5260 #define HASH_CR_DATATYPE ((uint32_t)0x00000030)
|
|
|
5261 #define HASH_CR_DATATYPE_0 ((uint32_t)0x00000010)
|
|
|
5262 #define HASH_CR_DATATYPE_1 ((uint32_t)0x00000020)
|
|
|
5263 #define HASH_CR_MODE ((uint32_t)0x00000040)
|
|
|
5264 #define HASH_CR_ALGO ((uint32_t)0x00040080)
|
|
|
5265 #define HASH_CR_ALGO_0 ((uint32_t)0x00000080)
|
|
|
5266 #define HASH_CR_ALGO_1 ((uint32_t)0x00040000)
|
|
|
5267 #define HASH_CR_NBW ((uint32_t)0x00000F00)
|
|
|
5268 #define HASH_CR_NBW_0 ((uint32_t)0x00000100)
|
|
|
5269 #define HASH_CR_NBW_1 ((uint32_t)0x00000200)
|
|
|
5270 #define HASH_CR_NBW_2 ((uint32_t)0x00000400)
|
|
|
5271 #define HASH_CR_NBW_3 ((uint32_t)0x00000800)
|
|
|
5272 #define HASH_CR_DINNE ((uint32_t)0x00001000)
|
|
|
5273 #define HASH_CR_MDMAT ((uint32_t)0x00002000)
|
|
|
5274 #define HASH_CR_LKEY ((uint32_t)0x00010000)
|
|
|
5275
|
|
|
5276 /****************** Bits definition for HASH_STR register *******************/
|
|
|
5277 #define HASH_STR_NBW ((uint32_t)0x0000001F)
|
|
|
5278 #define HASH_STR_NBW_0 ((uint32_t)0x00000001)
|
|
|
5279 #define HASH_STR_NBW_1 ((uint32_t)0x00000002)
|
|
|
5280 #define HASH_STR_NBW_2 ((uint32_t)0x00000004)
|
|
|
5281 #define HASH_STR_NBW_3 ((uint32_t)0x00000008)
|
|
|
5282 #define HASH_STR_NBW_4 ((uint32_t)0x00000010)
|
|
|
5283 #define HASH_STR_DCAL ((uint32_t)0x00000100)
|
|
|
5284
|
|
|
5285 /****************** Bits definition for HASH_IMR register *******************/
|
|
|
5286 #define HASH_IMR_DINIM ((uint32_t)0x00000001)
|
|
|
5287 #define HASH_IMR_DCIM ((uint32_t)0x00000002)
|
|
|
5288
|
|
|
5289 /****************** Bits definition for HASH_SR register ********************/
|
|
|
5290 #define HASH_SR_DINIS ((uint32_t)0x00000001)
|
|
|
5291 #define HASH_SR_DCIS ((uint32_t)0x00000002)
|
|
|
5292 #define HASH_SR_DMAS ((uint32_t)0x00000004)
|
|
|
5293 #define HASH_SR_BUSY ((uint32_t)0x00000008)
|
|
|
5294
|
|
|
5295 /******************************************************************************/
|
|
|
5296 /* */
|
|
|
5297 /* Inter-integrated Circuit Interface */
|
|
|
5298 /* */
|
|
|
5299 /******************************************************************************/
|
|
|
5300 /******************* Bit definition for I2C_CR1 register ********************/
|
|
|
5301 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!<Peripheral Enable */
|
|
|
5302 #define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!<SMBus Mode */
|
|
|
5303 #define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!<SMBus Type */
|
|
|
5304 #define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!<ARP Enable */
|
|
|
5305 #define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!<PEC Enable */
|
|
|
5306 #define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!<General Call Enable */
|
|
|
5307 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!<Clock Stretching Disable (Slave mode) */
|
|
|
5308 #define I2C_CR1_START ((uint32_t)0x00000100) /*!<Start Generation */
|
|
|
5309 #define I2C_CR1_STOP ((uint32_t)0x00000200) /*!<Stop Generation */
|
|
|
5310 #define I2C_CR1_ACK ((uint32_t)0x00000400) /*!<Acknowledge Enable */
|
|
|
5311 #define I2C_CR1_POS ((uint32_t)0x00000800) /*!<Acknowledge/PEC Position (for data reception) */
|
|
|
5312 #define I2C_CR1_PEC ((uint32_t)0x00001000) /*!<Packet Error Checking */
|
|
|
5313 #define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!<SMBus Alert */
|
|
|
5314 #define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!<Software Reset */
|
|
|
5315
|
|
|
5316 /******************* Bit definition for I2C_CR2 register ********************/
|
|
|
5317 #define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
|
|
|
5318 #define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
5319 #define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
5320 #define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
5321 #define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
5322 #define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
|
|
5323 #define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!<Bit 5 */
|
|
|
5324
|
|
|
5325 #define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!<Error Interrupt Enable */
|
|
|
5326 #define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!<Event Interrupt Enable */
|
|
|
5327 #define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!<Buffer Interrupt Enable */
|
|
|
5328 #define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!<DMA Requests Enable */
|
|
|
5329 #define I2C_CR2_LAST ((uint32_t)0x00001000) /*!<DMA Last Transfer */
|
|
|
5330
|
|
|
5331 /******************* Bit definition for I2C_OAR1 register *******************/
|
|
|
5332 #define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!<Interface Address */
|
|
|
5333 #define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!<Interface Address */
|
|
|
5334
|
|
|
5335 #define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
5336 #define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
5337 #define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
5338 #define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
5339 #define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
|
|
5340 #define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!<Bit 5 */
|
|
|
5341 #define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!<Bit 6 */
|
|
|
5342 #define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!<Bit 7 */
|
|
|
5343 #define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!<Bit 8 */
|
|
|
5344 #define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!<Bit 9 */
|
|
|
5345
|
|
|
5346 #define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!<Addressing Mode (Slave mode) */
|
|
|
5347
|
|
|
5348 /******************* Bit definition for I2C_OAR2 register *******************/
|
|
|
5349 #define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!<Dual addressing mode enable */
|
|
|
5350 #define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!<Interface address */
|
|
|
5351
|
|
|
5352 /******************** Bit definition for I2C_DR register ********************/
|
|
|
5353 #define I2C_DR_DR ((uint32_t)0x000000FF) /*!<8-bit Data Register */
|
|
|
5354
|
|
|
5355 /******************* Bit definition for I2C_SR1 register ********************/
|
|
|
5356 #define I2C_SR1_SB ((uint32_t)0x00000001) /*!<Start Bit (Master mode) */
|
|
|
5357 #define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!<Address sent (master mode)/matched (slave mode) */
|
|
|
5358 #define I2C_SR1_BTF ((uint32_t)0x00000004) /*!<Byte Transfer Finished */
|
|
|
5359 #define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!<10-bit header sent (Master mode) */
|
|
|
5360 #define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!<Stop detection (Slave mode) */
|
|
|
5361 #define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!<Data Register not Empty (receivers) */
|
|
|
5362 #define I2C_SR1_TXE ((uint32_t)0x00000080) /*!<Data Register Empty (transmitters) */
|
|
|
5363 #define I2C_SR1_BERR ((uint32_t)0x00000100) /*!<Bus Error */
|
|
|
5364 #define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!<Arbitration Lost (master mode) */
|
|
|
5365 #define I2C_SR1_AF ((uint32_t)0x00000400) /*!<Acknowledge Failure */
|
|
|
5366 #define I2C_SR1_OVR ((uint32_t)0x00000800) /*!<Overrun/Underrun */
|
|
|
5367 #define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!<PEC Error in reception */
|
|
|
5368 #define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!<Timeout or Tlow Error */
|
|
|
5369 #define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!<SMBus Alert */
|
|
|
5370
|
|
|
5371 /******************* Bit definition for I2C_SR2 register ********************/
|
|
|
5372 #define I2C_SR2_MSL ((uint32_t)0x00000001) /*!<Master/Slave */
|
|
|
5373 #define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!<Bus Busy */
|
|
|
5374 #define I2C_SR2_TRA ((uint32_t)0x00000004) /*!<Transmitter/Receiver */
|
|
|
5375 #define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!<General Call Address (Slave mode) */
|
|
|
5376 #define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!<SMBus Device Default Address (Slave mode) */
|
|
|
5377 #define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!<SMBus Host Header (Slave mode) */
|
|
|
5378 #define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!<Dual Flag (Slave mode) */
|
|
|
5379 #define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!<Packet Error Checking Register */
|
|
|
5380
|
|
|
5381 /******************* Bit definition for I2C_CCR register ********************/
|
|
|
5382 #define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
|
|
|
5383 #define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!<Fast Mode Duty Cycle */
|
|
|
5384 #define I2C_CCR_FS ((uint32_t)0x00008000) /*!<I2C Master Mode Selection */
|
|
|
5385
|
|
|
5386 /****************** Bit definition for I2C_TRISE register *******************/
|
|
|
5387 #define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
|
|
|
5388
|
|
|
5389 /****************** Bit definition for I2C_FLTR register *******************/
|
|
|
5390 #define I2C_FLTR_DNF ((uint32_t)0x0000000F) /*!<Digital Noise Filter */
|
|
|
5391 #define I2C_FLTR_ANOFF ((uint32_t)0x00000010) /*!<Analog Noise Filter OFF */
|
|
|
5392
|
|
|
5393 /******************************************************************************/
|
|
|
5394 /* */
|
|
|
5395 /* Independent WATCHDOG */
|
|
|
5396 /* */
|
|
|
5397 /******************************************************************************/
|
|
|
5398 /******************* Bit definition for IWDG_KR register ********************/
|
|
|
5399 #define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */
|
|
|
5400
|
|
|
5401 /******************* Bit definition for IWDG_PR register ********************/
|
|
|
5402 #define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */
|
|
|
5403 #define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */
|
|
|
5404 #define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */
|
|
|
5405 #define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */
|
|
|
5406
|
|
|
5407 /******************* Bit definition for IWDG_RLR register *******************/
|
|
|
5408 #define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */
|
|
|
5409
|
|
|
5410 /******************* Bit definition for IWDG_SR register ********************/
|
|
|
5411 #define IWDG_SR_PVU ((uint32_t)0x01) /*!<Watchdog prescaler value update */
|
|
|
5412 #define IWDG_SR_RVU ((uint32_t)0x02) /*!<Watchdog counter reload value update */
|
|
|
5413
|
|
|
5414
|
|
|
5415 /******************************************************************************/
|
|
|
5416 /* */
|
|
|
5417 /* LCD-TFT Display Controller (LTDC) */
|
|
|
5418 /* */
|
|
|
5419 /******************************************************************************/
|
|
|
5420
|
|
|
5421 /******************** Bit definition for LTDC_SSCR register *****************/
|
|
|
5422
|
|
|
5423 #define LTDC_SSCR_VSH ((uint32_t)0x000007FF) /*!< Vertical Synchronization Height */
|
|
|
5424 #define LTDC_SSCR_HSW ((uint32_t)0x0FFF0000) /*!< Horizontal Synchronization Width */
|
|
|
5425
|
|
|
5426 /******************** Bit definition for LTDC_BPCR register *****************/
|
|
|
5427
|
|
|
5428 #define LTDC_BPCR_AVBP ((uint32_t)0x000007FF) /*!< Accumulated Vertical Back Porch */
|
|
|
5429 #define LTDC_BPCR_AHBP ((uint32_t)0x0FFF0000) /*!< Accumulated Horizontal Back Porch */
|
|
|
5430
|
|
|
5431 /******************** Bit definition for LTDC_AWCR register *****************/
|
|
|
5432
|
|
|
5433 #define LTDC_AWCR_AAH ((uint32_t)0x000007FF) /*!< Accumulated Active heigh */
|
|
|
5434 #define LTDC_AWCR_AAW ((uint32_t)0x0FFF0000) /*!< Accumulated Active Width */
|
|
|
5435
|
|
|
5436 /******************** Bit definition for LTDC_TWCR register *****************/
|
|
|
5437
|
|
|
5438 #define LTDC_TWCR_TOTALH ((uint32_t)0x000007FF) /*!< Total Heigh */
|
|
|
5439 #define LTDC_TWCR_TOTALW ((uint32_t)0x0FFF0000) /*!< Total Width */
|
|
|
5440
|
|
|
5441 /******************** Bit definition for LTDC_GCR register ******************/
|
|
|
5442
|
|
|
5443 #define LTDC_GCR_LTDCEN ((uint32_t)0x00000001) /*!< LCD-TFT controller enable bit */
|
|
|
5444 #define LTDC_GCR_DBW ((uint32_t)0x00000070) /*!< Dither Blue Width */
|
|
|
5445 #define LTDC_GCR_DGW ((uint32_t)0x00000700) /*!< Dither Green Width */
|
|
|
5446 #define LTDC_GCR_DRW ((uint32_t)0x00007000) /*!< Dither Red Width */
|
|
|
5447 #define LTDC_GCR_DTEN ((uint32_t)0x00010000) /*!< Dither Enable */
|
|
|
5448 #define LTDC_GCR_PCPOL ((uint32_t)0x10000000) /*!< Pixel Clock Polarity */
|
|
|
5449 #define LTDC_GCR_DEPOL ((uint32_t)0x20000000) /*!< Data Enable Polarity */
|
|
|
5450 #define LTDC_GCR_VSPOL ((uint32_t)0x40000000) /*!< Vertical Synchronization Polarity */
|
|
|
5451 #define LTDC_GCR_HSPOL ((uint32_t)0x80000000) /*!< Horizontal Synchronization Polarity */
|
|
|
5452
|
|
|
5453 /******************** Bit definition for LTDC_SRCR register *****************/
|
|
|
5454
|
|
|
5455 #define LTDC_SRCR_IMR ((uint32_t)0x00000001) /*!< Immediate Reload */
|
|
|
5456 #define LTDC_SRCR_VBR ((uint32_t)0x00000002) /*!< Vertical Blanking Reload */
|
|
|
5457
|
|
|
5458 /******************** Bit definition for LTDC_BCCR register *****************/
|
|
|
5459
|
|
|
5460 #define LTDC_BCCR_BCBLUE ((uint32_t)0x000000FF) /*!< Background Blue value */
|
|
|
5461 #define LTDC_BCCR_BCGREEN ((uint32_t)0x0000FF00) /*!< Background Green value */
|
|
|
5462 #define LTDC_BCCR_BCRED ((uint32_t)0x00FF0000) /*!< Background Red value */
|
|
|
5463
|
|
|
5464 /******************** Bit definition for LTDC_IER register ******************/
|
|
|
5465
|
|
|
5466 #define LTDC_IER_LIE ((uint32_t)0x00000001) /*!< Line Interrupt Enable */
|
|
|
5467 #define LTDC_IER_FUIE ((uint32_t)0x00000002) /*!< FIFO Underrun Interrupt Enable */
|
|
|
5468 #define LTDC_IER_TERRIE ((uint32_t)0x00000004) /*!< Transfer Error Interrupt Enable */
|
|
|
5469 #define LTDC_IER_RRIE ((uint32_t)0x00000008) /*!< Register Reload interrupt enable */
|
|
|
5470
|
|
|
5471 /******************** Bit definition for LTDC_ISR register ******************/
|
|
|
5472
|
|
|
5473 #define LTDC_ISR_LIF ((uint32_t)0x00000001) /*!< Line Interrupt Flag */
|
|
|
5474 #define LTDC_ISR_FUIF ((uint32_t)0x00000002) /*!< FIFO Underrun Interrupt Flag */
|
|
|
5475 #define LTDC_ISR_TERRIF ((uint32_t)0x00000004) /*!< Transfer Error Interrupt Flag */
|
|
|
5476 #define LTDC_ISR_RRIF ((uint32_t)0x00000008) /*!< Register Reload interrupt Flag */
|
|
|
5477
|
|
|
5478 /******************** Bit definition for LTDC_ICR register ******************/
|
|
|
5479
|
|
|
5480 #define LTDC_ICR_CLIF ((uint32_t)0x00000001) /*!< Clears the Line Interrupt Flag */
|
|
|
5481 #define LTDC_ICR_CFUIF ((uint32_t)0x00000002) /*!< Clears the FIFO Underrun Interrupt Flag */
|
|
|
5482 #define LTDC_ICR_CTERRIF ((uint32_t)0x00000004) /*!< Clears the Transfer Error Interrupt Flag */
|
|
|
5483 #define LTDC_ICR_CRRIF ((uint32_t)0x00000008) /*!< Clears Register Reload interrupt Flag */
|
|
|
5484
|
|
|
5485 /******************** Bit definition for LTDC_LIPCR register ****************/
|
|
|
5486
|
|
|
5487 #define LTDC_LIPCR_LIPOS ((uint32_t)0x000007FF) /*!< Line Interrupt Position */
|
|
|
5488
|
|
|
5489 /******************** Bit definition for LTDC_CPSR register *****************/
|
|
|
5490
|
|
|
5491 #define LTDC_CPSR_CYPOS ((uint32_t)0x0000FFFF) /*!< Current Y Position */
|
|
|
5492 #define LTDC_CPSR_CXPOS ((uint32_t)0xFFFF0000) /*!< Current X Position */
|
|
|
5493
|
|
|
5494 /******************** Bit definition for LTDC_CDSR register *****************/
|
|
|
5495
|
|
|
5496 #define LTDC_CDSR_VDES ((uint32_t)0x00000001) /*!< Vertical Data Enable Status */
|
|
|
5497 #define LTDC_CDSR_HDES ((uint32_t)0x00000002) /*!< Horizontal Data Enable Status */
|
|
|
5498 #define LTDC_CDSR_VSYNCS ((uint32_t)0x00000004) /*!< Vertical Synchronization Status */
|
|
|
5499 #define LTDC_CDSR_HSYNCS ((uint32_t)0x00000008) /*!< Horizontal Synchronization Status */
|
|
|
5500
|
|
|
5501 /******************** Bit definition for LTDC_LxCR register *****************/
|
|
|
5502
|
|
|
5503 #define LTDC_LxCR_LEN ((uint32_t)0x00000001) /*!< Layer Enable */
|
|
|
5504 #define LTDC_LxCR_COLKEN ((uint32_t)0x00000002) /*!< Color Keying Enable */
|
|
|
5505 #define LTDC_LxCR_CLUTEN ((uint32_t)0x00000010) /*!< Color Lockup Table Enable */
|
|
|
5506
|
|
|
5507 /******************** Bit definition for LTDC_LxWHPCR register **************/
|
|
|
5508
|
|
|
5509 #define LTDC_LxWHPCR_WHSTPOS ((uint32_t)0x00000FFF) /*!< Window Horizontal Start Position */
|
|
|
5510 #define LTDC_LxWHPCR_WHSPPOS ((uint32_t)0xFFFF0000) /*!< Window Horizontal Stop Position */
|
|
|
5511
|
|
|
5512 /******************** Bit definition for LTDC_LxWVPCR register **************/
|
|
|
5513
|
|
|
5514 #define LTDC_LxWVPCR_WVSTPOS ((uint32_t)0x00000FFF) /*!< Window Vertical Start Position */
|
|
|
5515 #define LTDC_LxWVPCR_WVSPPOS ((uint32_t)0xFFFF0000) /*!< Window Vertical Stop Position */
|
|
|
5516
|
|
|
5517 /******************** Bit definition for LTDC_LxCKCR register ***************/
|
|
|
5518
|
|
|
5519 #define LTDC_LxCKCR_CKBLUE ((uint32_t)0x000000FF) /*!< Color Key Blue value */
|
|
|
5520 #define LTDC_LxCKCR_CKGREEN ((uint32_t)0x0000FF00) /*!< Color Key Green value */
|
|
|
5521 #define LTDC_LxCKCR_CKRED ((uint32_t)0x00FF0000) /*!< Color Key Red value */
|
|
|
5522
|
|
|
5523 /******************** Bit definition for LTDC_LxPFCR register ***************/
|
|
|
5524
|
|
|
5525 #define LTDC_LxPFCR_PF ((uint32_t)0x00000007) /*!< Pixel Format */
|
|
|
5526
|
|
|
5527 /******************** Bit definition for LTDC_LxCACR register ***************/
|
|
|
5528
|
|
|
5529 #define LTDC_LxCACR_CONSTA ((uint32_t)0x000000FF) /*!< Constant Alpha */
|
|
|
5530
|
|
|
5531 /******************** Bit definition for LTDC_LxDCCR register ***************/
|
|
|
5532
|
|
|
5533 #define LTDC_LxDCCR_DCBLUE ((uint32_t)0x000000FF) /*!< Default Color Blue */
|
|
|
5534 #define LTDC_LxDCCR_DCGREEN ((uint32_t)0x0000FF00) /*!< Default Color Green */
|
|
|
5535 #define LTDC_LxDCCR_DCRED ((uint32_t)0x00FF0000) /*!< Default Color Red */
|
|
|
5536 #define LTDC_LxDCCR_DCALPHA ((uint32_t)0xFF000000) /*!< Default Color Alpha */
|
|
|
5537
|
|
|
5538 /******************** Bit definition for LTDC_LxBFCR register ***************/
|
|
|
5539
|
|
|
5540 #define LTDC_LxBFCR_BF2 ((uint32_t)0x00000007) /*!< Blending Factor 2 */
|
|
|
5541 #define LTDC_LxBFCR_BF1 ((uint32_t)0x00000700) /*!< Blending Factor 1 */
|
|
|
5542
|
|
|
5543 /******************** Bit definition for LTDC_LxCFBAR register **************/
|
|
|
5544
|
|
|
5545 #define LTDC_LxCFBAR_CFBADD ((uint32_t)0xFFFFFFFF) /*!< Color Frame Buffer Start Address */
|
|
|
5546
|
|
|
5547 /******************** Bit definition for LTDC_LxCFBLR register **************/
|
|
|
5548
|
|
|
5549 #define LTDC_LxCFBLR_CFBLL ((uint32_t)0x00001FFF) /*!< Color Frame Buffer Line Length */
|
|
|
5550 #define LTDC_LxCFBLR_CFBP ((uint32_t)0x1FFF0000) /*!< Color Frame Buffer Pitch in bytes */
|
|
|
5551
|
|
|
5552 /******************** Bit definition for LTDC_LxCFBLNR register *************/
|
|
|
5553
|
|
|
5554 #define LTDC_LxCFBLNR_CFBLNBR ((uint32_t)0x000007FF) /*!< Frame Buffer Line Number */
|
|
|
5555
|
|
|
5556 /******************** Bit definition for LTDC_LxCLUTWR register *************/
|
|
|
5557
|
|
|
5558 #define LTDC_LxCLUTWR_BLUE ((uint32_t)0x000000FF) /*!< Blue value */
|
|
|
5559 #define LTDC_LxCLUTWR_GREEN ((uint32_t)0x0000FF00) /*!< Green value */
|
|
|
5560 #define LTDC_LxCLUTWR_RED ((uint32_t)0x00FF0000) /*!< Red value */
|
|
|
5561 #define LTDC_LxCLUTWR_CLUTADD ((uint32_t)0xFF000000) /*!< CLUT address */
|
|
|
5562
|
|
|
5563
|
|
|
5564 /******************************************************************************/
|
|
|
5565 /* */
|
|
|
5566 /* Power Control */
|
|
|
5567 /* */
|
|
|
5568 /******************************************************************************/
|
|
|
5569 /******************** Bit definition for PWR_CR register ********************/
|
|
|
5570 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
|
|
|
5571 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
|
|
|
5572 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
|
|
|
5573 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
|
|
|
5574 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
|
|
|
5575
|
|
|
5576 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
|
|
|
5577 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
|
|
|
5578 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
|
|
|
5579 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
|
|
|
5580
|
|
|
5581 /*!< PVD level configuration */
|
|
|
5582 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
|
|
|
5583 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
|
|
|
5584 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
|
|
|
5585 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
|
|
|
5586 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
|
|
|
5587 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
|
|
|
5588 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
|
|
|
5589 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
|
|
|
5590 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
|
|
|
5591 #define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
|
|
|
5592 #define PWR_CR_LPLVDS ((uint32_t)0x00000400) /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */
|
|
|
5593 #define PWR_CR_MRLVDS ((uint32_t)0x00000800) /*!< Main regulator Low Voltage Scaling in Stop mode */
|
|
|
5594 #define PWR_CR_ADCDC1 ((uint32_t)0x00002000) /*!< Refer to AN4073 on how to use this bit */
|
|
|
5595 #define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
|
|
|
5596 #define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
|
|
|
5597 #define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
|
|
|
5598 #define PWR_CR_ODEN ((uint32_t)0x00010000) /*!< Over Drive enable */
|
|
|
5599 #define PWR_CR_ODSWEN ((uint32_t)0x00020000) /*!< Over Drive switch enabled */
|
|
|
5600 #define PWR_CR_UDEN ((uint32_t)0x000C0000) /*!< Under Drive enable in stop mode */
|
|
|
5601 #define PWR_CR_UDEN_0 ((uint32_t)0x00040000) /*!< Bit 0 */
|
|
|
5602 #define PWR_CR_UDEN_1 ((uint32_t)0x00080000) /*!< Bit 1 */
|
|
|
5603
|
|
|
5604 /* Legacy define */
|
|
|
5605 #define PWR_CR_PMODE PWR_CR_VOS
|
|
|
5606 #define PWR_CR_LPUDS PWR_CR_LPLVDS /*!< Low-Power Regulator in deepsleep under-drive mode */
|
|
|
5607 #define PWR_CR_MRUDS PWR_CR_MRLVDS /*!< Main regulator in deepsleep under-drive mode */
|
|
|
5608
|
|
|
5609 /******************* Bit definition for PWR_CSR register ********************/
|
|
|
5610 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
|
|
|
5611 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
|
|
|
5612 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
|
|
|
5613 #define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
|
|
|
5614 #define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */
|
|
|
5615 #define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
|
|
|
5616 #define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
|
|
|
5617 #define PWR_CSR_ODRDY ((uint32_t)0x00010000) /*!< Over Drive generator ready */
|
|
|
5618 #define PWR_CSR_ODSWRDY ((uint32_t)0x00020000) /*!< Over Drive Switch ready */
|
|
|
5619 #define PWR_CSR_UDSWRDY ((uint32_t)0x000C0000) /*!< Under Drive ready */
|
|
|
5620
|
|
|
5621 /* Legacy define */
|
|
|
5622 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
|
|
|
5623
|
|
|
5624 /******************************************************************************/
|
|
|
5625 /* */
|
|
|
5626 /* Reset and Clock Control */
|
|
|
5627 /* */
|
|
|
5628 /******************************************************************************/
|
|
|
5629 /******************** Bit definition for RCC_CR register ********************/
|
|
|
5630 #define RCC_CR_HSION ((uint32_t)0x00000001)
|
|
|
5631 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
|
|
|
5632
|
|
|
5633 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
|
|
|
5634 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
|
|
|
5635 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
|
|
|
5636 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
|
|
|
5637 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
|
|
|
5638 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
|
|
|
5639
|
|
|
5640 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
|
|
|
5641 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
|
|
|
5642 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
|
|
|
5643 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
|
|
|
5644 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
|
|
|
5645 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
|
|
|
5646 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
|
|
|
5647 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
|
|
|
5648 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
|
|
|
5649
|
|
|
5650 #define RCC_CR_HSEON ((uint32_t)0x00010000)
|
|
|
5651 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
|
|
|
5652 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
|
|
|
5653 #define RCC_CR_CSSON ((uint32_t)0x00080000)
|
|
|
5654 #define RCC_CR_PLLON ((uint32_t)0x01000000)
|
|
|
5655 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
|
|
|
5656 #define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
|
|
|
5657 #define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
|
|
|
5658 #define RCC_CR_PLLSAION ((uint32_t)0x10000000)
|
|
|
5659 #define RCC_CR_PLLSAIRDY ((uint32_t)0x20000000)
|
|
|
5660
|
|
|
5661 /******************** Bit definition for RCC_PLLCFGR register ***************/
|
|
|
5662 #define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
|
|
|
5663 #define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
|
|
|
5664 #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
|
|
|
5665 #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
|
|
|
5666 #define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
|
|
|
5667 #define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
|
|
|
5668 #define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
|
|
|
5669
|
|
|
5670 #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
|
|
|
5671 #define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
|
|
|
5672 #define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
|
|
|
5673 #define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
|
|
|
5674 #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
|
|
|
5675 #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
|
|
|
5676 #define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
|
|
|
5677 #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
|
|
|
5678 #define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
|
|
|
5679 #define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
|
|
|
5680
|
|
|
5681 #define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
|
|
|
5682 #define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
|
|
|
5683 #define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
|
|
|
5684
|
|
|
5685 #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
|
|
|
5686 #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
|
|
|
5687 #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
|
|
|
5688
|
|
|
5689 #define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
|
|
|
5690 #define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
|
|
|
5691 #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
|
|
|
5692 #define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
|
|
|
5693 #define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
|
|
|
5694
|
|
|
5695 /******************** Bit definition for RCC_CFGR register ******************/
|
|
|
5696 /*!< SW configuration */
|
|
|
5697 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
|
|
|
5698 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
|
|
5699 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
|
|
5700
|
|
|
5701 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
|
|
|
5702 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
|
|
|
5703 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
|
|
|
5704
|
|
|
5705 /*!< SWS configuration */
|
|
|
5706 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
|
|
|
5707 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
|
|
|
5708 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
|
|
|
5709
|
|
|
5710 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
|
|
|
5711 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
|
|
|
5712 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
|
|
|
5713
|
|
|
5714 /*!< HPRE configuration */
|
|
|
5715 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
|
|
|
5716 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
|
|
|
5717 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
|
|
|
5718 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
|
|
|
5719 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
|
|
|
5720
|
|
|
5721 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
|
|
|
5722 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
|
|
|
5723 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
|
|
|
5724 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
|
|
|
5725 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
|
|
|
5726 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
|
|
|
5727 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
|
|
|
5728 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
|
|
|
5729 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
|
|
|
5730
|
|
|
5731 /*!< PPRE1 configuration */
|
|
|
5732 #define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
|
|
|
5733 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
|
|
|
5734 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
|
|
|
5735 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
|
|
|
5736
|
|
|
5737 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
|
|
|
5738 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
|
|
|
5739 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
|
|
|
5740 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
|
|
|
5741 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
|
|
|
5742
|
|
|
5743 /*!< PPRE2 configuration */
|
|
|
5744 #define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
|
|
|
5745 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
|
|
|
5746 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
|
|
|
5747 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
|
|
|
5748
|
|
|
5749 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
|
|
|
5750 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
|
|
|
5751 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
|
|
|
5752 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
|
|
|
5753 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
|
|
|
5754
|
|
|
5755 /*!< RTCPRE configuration */
|
|
|
5756 #define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
|
|
|
5757 #define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
|
|
|
5758 #define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
|
|
|
5759 #define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
|
|
|
5760 #define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
|
|
|
5761 #define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
|
|
|
5762
|
|
|
5763 /*!< MCO1 configuration */
|
|
|
5764 #define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
|
|
|
5765 #define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
|
|
|
5766 #define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
|
|
|
5767
|
|
|
5768 #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
|
|
|
5769
|
|
|
5770 #define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
|
|
|
5771 #define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
|
|
|
5772 #define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
|
|
|
5773 #define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
|
|
|
5774
|
|
|
5775 #define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
|
|
|
5776 #define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
|
|
|
5777 #define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
|
|
|
5778 #define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
|
|
|
5779
|
|
|
5780 #define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
|
|
|
5781 #define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
|
|
|
5782 #define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
|
|
|
5783
|
|
|
5784 /******************** Bit definition for RCC_CIR register *******************/
|
|
|
5785 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
|
|
|
5786 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
|
|
|
5787 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
|
|
|
5788 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
|
|
|
5789 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
|
|
|
5790 #define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
|
|
|
5791 #define RCC_CIR_PLLSAIRDYF ((uint32_t)0x00000040)
|
|
|
5792 #define RCC_CIR_CSSF ((uint32_t)0x00000080)
|
|
|
5793 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
|
|
|
5794 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
|
|
|
5795 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
|
|
|
5796 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
|
|
|
5797 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
|
|
|
5798 #define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
|
|
|
5799 #define RCC_CIR_PLLSAIRDYIE ((uint32_t)0x00004000)
|
|
|
5800 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
|
|
|
5801 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
|
|
|
5802 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
|
|
|
5803 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
|
|
|
5804 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
|
|
|
5805 #define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
|
|
|
5806 #define RCC_CIR_PLLSAIRDYC ((uint32_t)0x00400000)
|
|
|
5807 #define RCC_CIR_CSSC ((uint32_t)0x00800000)
|
|
|
5808
|
|
|
5809 /******************** Bit definition for RCC_AHB1RSTR register **************/
|
|
|
5810 #define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
|
|
|
5811 #define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
|
|
|
5812 #define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
|
|
|
5813 #define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
|
|
|
5814 #define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
|
|
|
5815 #define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
|
|
|
5816 #define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)
|
|
|
5817 #define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
|
|
|
5818 #define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)
|
|
|
5819 #define RCC_AHB1RSTR_GPIOJRST ((uint32_t)0x00000200)
|
|
|
5820 #define RCC_AHB1RSTR_GPIOKRST ((uint32_t)0x00000400)
|
|
|
5821 #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
|
|
|
5822 #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
|
|
|
5823 #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
|
|
|
5824 #define RCC_AHB1RSTR_DMA2DRST ((uint32_t)0x00800000)
|
|
|
5825 #define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
|
|
|
5826 #define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)
|
|
|
5827
|
|
|
5828 /******************** Bit definition for RCC_AHB2RSTR register **************/
|
|
|
5829 #define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
|
|
|
5830 #define RCC_AHB2RSTR_CRYPRST ((uint32_t)0x00000010)
|
|
|
5831 #define RCC_AHB2RSTR_HASHRST ((uint32_t)0x00000020)
|
|
|
5832 /* maintained for legacy purpose */
|
|
|
5833 #define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST
|
|
|
5834 #define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
|
|
|
5835 #define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
|
|
|
5836
|
|
|
5837 /******************** Bit definition for RCC_AHB3RSTR register **************/
|
|
|
5838 #define RCC_AHB3RSTR_FMCRST ((uint32_t)0x00000001)
|
|
|
5839
|
|
|
5840 /******************** Bit definition for RCC_APB1RSTR register **************/
|
|
|
5841 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
|
|
|
5842 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
|
|
|
5843 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
|
|
|
5844 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
|
|
|
5845 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
|
|
|
5846 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
|
|
|
5847 #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
|
|
|
5848 #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
|
|
|
5849 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
|
|
|
5850 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
|
|
|
5851 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
|
|
|
5852 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
|
|
|
5853 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
|
|
|
5854 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
|
|
|
5855 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
|
|
|
5856 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
|
|
|
5857 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
|
|
|
5858 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
|
|
|
5859 #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
|
|
|
5860 #define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
|
|
|
5861 #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
|
|
|
5862 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
|
|
|
5863 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
|
|
|
5864 #define RCC_APB1RSTR_UART7RST ((uint32_t)0x40000000)
|
|
|
5865 #define RCC_APB1RSTR_UART8RST ((uint32_t)0x80000000)
|
|
|
5866
|
|
|
5867 /******************** Bit definition for RCC_APB2RSTR register **************/
|
|
|
5868 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
|
|
|
5869 #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)
|
|
|
5870 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
|
|
|
5871 #define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
|
|
|
5872 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
|
|
|
5873 #define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
|
|
|
5874 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
|
|
|
5875 #define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)
|
|
|
5876 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
|
|
|
5877 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
|
|
|
5878 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
|
|
|
5879 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
|
|
|
5880 #define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000)
|
|
|
5881 #define RCC_APB2RSTR_SPI6RST ((uint32_t)0x00200000)
|
|
|
5882 #define RCC_APB2RSTR_SAI1RST ((uint32_t)0x00400000)
|
|
|
5883 #define RCC_APB2RSTR_LTDCRST ((uint32_t)0x04000000)
|
|
|
5884
|
|
|
5885 /* Old SPI1RST bit definition, maintained for legacy purpose */
|
|
|
5886 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
|
|
|
5887
|
|
|
5888 /******************** Bit definition for RCC_AHB1ENR register ***************/
|
|
|
5889 #define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
|
|
|
5890 #define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
|
|
|
5891 #define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
|
|
|
5892 #define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
|
|
|
5893 #define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
|
|
|
5894 #define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)
|
|
|
5895 #define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)
|
|
|
5896 #define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
|
|
|
5897 #define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)
|
|
|
5898 #define RCC_AHB1ENR_GPIOJEN ((uint32_t)0x00000200)
|
|
|
5899 #define RCC_AHB1ENR_GPIOKEN ((uint32_t)0x00000400)
|
|
|
5900
|
|
|
5901 #define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
|
|
|
5902 #define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
|
|
|
5903 #define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
|
|
|
5904 #define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
|
|
|
5905 #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
|
|
|
5906 #define RCC_AHB1ENR_DMA2DEN ((uint32_t)0x00800000)
|
|
|
5907
|
|
|
5908 #define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)
|
|
|
5909 #define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)
|
|
|
5910 #define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)
|
|
|
5911 #define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)
|
|
|
5912 #define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)
|
|
|
5913 #define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)
|
|
|
5914
|
|
|
5915 /******************** Bit definition for RCC_AHB2ENR register ***************/
|
|
|
5916 #define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)
|
|
|
5917 #define RCC_AHB2ENR_CRYPEN ((uint32_t)0x00000010)
|
|
|
5918 #define RCC_AHB2ENR_HASHEN ((uint32_t)0x00000020)
|
|
|
5919 #define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
|
|
|
5920 #define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
|
|
|
5921
|
|
|
5922 /******************** Bit definition for RCC_AHB3ENR register ***************/
|
|
|
5923 #define RCC_AHB3ENR_FMCEN ((uint32_t)0x00000001)
|
|
|
5924
|
|
|
5925 /******************** Bit definition for RCC_APB1ENR register ***************/
|
|
|
5926 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
|
|
|
5927 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
|
|
|
5928 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
|
|
|
5929 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
|
|
|
5930 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
|
|
|
5931 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
|
|
|
5932 #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
|
|
|
5933 #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
|
|
|
5934 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
|
|
|
5935 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
|
|
|
5936 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
|
|
|
5937 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
|
|
|
5938 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
|
|
|
5939 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
|
|
|
5940 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
|
|
|
5941 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
|
|
|
5942 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
|
|
|
5943 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
|
|
|
5944 #define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
|
|
|
5945 #define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
|
|
|
5946 #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
|
|
|
5947 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
|
|
|
5948 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
|
|
|
5949 #define RCC_APB1ENR_UART7EN ((uint32_t)0x40000000)
|
|
|
5950 #define RCC_APB1ENR_UART8EN ((uint32_t)0x80000000)
|
|
|
5951
|
|
|
5952 /******************** Bit definition for RCC_APB2ENR register ***************/
|
|
|
5953 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
|
|
|
5954 #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
|
|
|
5955 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
|
|
|
5956 #define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
|
|
|
5957 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
|
|
|
5958 #define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)
|
|
|
5959 #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
|
|
|
5960 #define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
|
|
|
5961 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
|
|
|
5962 #define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)
|
|
|
5963 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
|
|
|
5964 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
|
|
|
5965 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
|
|
|
5966 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
|
|
|
5967 #define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)
|
|
|
5968 #define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000)
|
|
|
5969 #define RCC_APB2ENR_SAI1EN ((uint32_t)0x00400000)
|
|
|
5970 #define RCC_APB2ENR_LTDCEN ((uint32_t)0x04000000)
|
|
|
5971
|
|
|
5972 /******************** Bit definition for RCC_AHB1LPENR register *************/
|
|
|
5973 #define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
|
|
|
5974 #define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
|
|
|
5975 #define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
|
|
|
5976 #define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
|
|
|
5977 #define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
|
|
|
5978 #define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)
|
|
|
5979 #define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)
|
|
|
5980 #define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
|
|
|
5981 #define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)
|
|
|
5982 #define RCC_AHB1LPENR_GPIOJLPEN ((uint32_t)0x00000200)
|
|
|
5983 #define RCC_AHB1LPENR_GPIOKLPEN ((uint32_t)0x00000400)
|
|
|
5984
|
|
|
5985 #define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
|
|
|
5986 #define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
|
|
|
5987 #define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
|
|
|
5988 #define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
|
|
|
5989 #define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
|
|
|
5990 #define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
|
|
|
5991 #define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
|
|
|
5992 #define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
|
|
|
5993 #define RCC_AHB1LPENR_DMA2DLPEN ((uint32_t)0x00800000)
|
|
|
5994
|
|
|
5995 #define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)
|
|
|
5996 #define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)
|
|
|
5997 #define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)
|
|
|
5998 #define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)
|
|
|
5999 #define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
|
|
|
6000 #define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)
|
|
|
6001
|
|
|
6002 /******************** Bit definition for RCC_AHB2LPENR register *************/
|
|
|
6003 #define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)
|
|
|
6004 #define RCC_AHB2LPENR_CRYPLPEN ((uint32_t)0x00000010)
|
|
|
6005 #define RCC_AHB2LPENR_HASHLPEN ((uint32_t)0x00000020)
|
|
|
6006 #define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
|
|
|
6007 #define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
|
|
|
6008
|
|
|
6009 /******************** Bit definition for RCC_AHB3LPENR register *************/
|
|
|
6010 #define RCC_AHB3LPENR_FMCLPEN ((uint32_t)0x00000001)
|
|
|
6011
|
|
|
6012 /******************** Bit definition for RCC_APB1LPENR register *************/
|
|
|
6013 #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
|
|
|
6014 #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
|
|
|
6015 #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
|
|
|
6016 #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
|
|
|
6017 #define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
|
|
|
6018 #define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
|
|
|
6019 #define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)
|
|
|
6020 #define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
|
|
|
6021 #define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)
|
|
|
6022 #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
|
|
|
6023 #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
|
|
|
6024 #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
|
|
|
6025 #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
|
|
|
6026 #define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
|
|
|
6027 #define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)
|
|
|
6028 #define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)
|
|
|
6029 #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
|
|
|
6030 #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
|
|
|
6031 #define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
|
|
|
6032 #define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)
|
|
|
6033 #define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)
|
|
|
6034 #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
|
|
|
6035 #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
|
|
|
6036 #define RCC_APB1LPENR_UART7LPEN ((uint32_t)0x40000000)
|
|
|
6037 #define RCC_APB1LPENR_UART8LPEN ((uint32_t)0x80000000)
|
|
|
6038
|
|
|
6039 /******************** Bit definition for RCC_APB2LPENR register *************/
|
|
|
6040 #define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
|
|
|
6041 #define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
|
|
|
6042 #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
|
|
|
6043 #define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
|
|
|
6044 #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
|
|
|
6045 #define RCC_APB2LPENR_ADC2LPEN ((uint32_t)0x00000200)
|
|
|
6046 #define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
|
|
|
6047 #define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
|
|
|
6048 #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
|
|
|
6049 #define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)
|
|
|
6050 #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
|
|
|
6051 #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
|
|
|
6052 #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
|
|
|
6053 #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
|
|
|
6054 #define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000)
|
|
|
6055 #define RCC_APB2LPENR_SPI6LPEN ((uint32_t)0x00200000)
|
|
|
6056 #define RCC_APB2LPENR_SAI1LPEN ((uint32_t)0x00400000)
|
|
|
6057 #define RCC_APB2LPENR_LTDCLPEN ((uint32_t)0x04000000)
|
|
|
6058
|
|
|
6059 /******************** Bit definition for RCC_BDCR register ******************/
|
|
|
6060 #define RCC_BDCR_LSEON ((uint32_t)0x00000001)
|
|
|
6061 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
|
|
|
6062 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
|
|
|
6063
|
|
|
6064 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
|
|
|
6065 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
|
|
|
6066 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
|
|
|
6067
|
|
|
6068 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
|
|
|
6069 #define RCC_BDCR_BDRST ((uint32_t)0x00010000)
|
|
|
6070
|
|
|
6071 /******************** Bit definition for RCC_CSR register *******************/
|
|
|
6072 #define RCC_CSR_LSION ((uint32_t)0x00000001)
|
|
|
6073 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
|
|
|
6074 #define RCC_CSR_RMVF ((uint32_t)0x01000000)
|
|
|
6075 #define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
|
|
|
6076 #define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
|
|
|
6077 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
|
|
|
6078 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
|
|
|
6079 #define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
|
|
|
6080 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
|
|
|
6081 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
|
|
|
6082
|
|
|
6083 /******************** Bit definition for RCC_SSCGR register *****************/
|
|
|
6084 #define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
|
|
|
6085 #define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
|
|
|
6086 #define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
|
|
|
6087 #define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
|
|
|
6088
|
|
|
6089 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
|
|
|
6090 #define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
|
|
|
6091 #define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040)
|
|
|
6092 #define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080)
|
|
|
6093 #define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)
|
|
|
6094 #define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)
|
|
|
6095 #define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)
|
|
|
6096 #define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)
|
|
|
6097 #define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)
|
|
|
6098 #define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)
|
|
|
6099 #define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)
|
|
|
6100
|
|
|
6101 #define RCC_PLLI2SCFGR_PLLI2SQ ((uint32_t)0x0F000000)
|
|
|
6102 #define RCC_PLLI2SCFGR_PLLI2SQ_0 ((uint32_t)0x01000000)
|
|
|
6103 #define RCC_PLLI2SCFGR_PLLI2SQ_1 ((uint32_t)0x02000000)
|
|
|
6104 #define RCC_PLLI2SCFGR_PLLI2SQ_2 ((uint32_t)0x04000000)
|
|
|
6105 #define RCC_PLLI2SCFGR_PLLI2SQ_3 ((uint32_t)0x08000000)
|
|
|
6106
|
|
|
6107 #define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
|
|
|
6108 #define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)
|
|
|
6109 #define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)
|
|
|
6110 #define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)
|
|
|
6111
|
|
|
6112
|
|
|
6113 /******************** Bit definition for RCC_PLLSAICFGR register ************/
|
|
|
6114 #define RCC_PLLSAICFGR_PLLSAIN ((uint32_t)0x00007FC0)
|
|
|
6115 #define RCC_PLLSAICFGR_PLLSAIN_0 ((uint32_t)0x00000040)
|
|
|
6116 #define RCC_PLLSAICFGR_PLLSAIN_1 ((uint32_t)0x00000080)
|
|
|
6117 #define RCC_PLLSAICFGR_PLLSAIN_2 ((uint32_t)0x00000100)
|
|
|
6118 #define RCC_PLLSAICFGR_PLLSAIN_3 ((uint32_t)0x00000200)
|
|
|
6119 #define RCC_PLLSAICFGR_PLLSAIN_4 ((uint32_t)0x00000400)
|
|
|
6120 #define RCC_PLLSAICFGR_PLLSAIN_5 ((uint32_t)0x00000800)
|
|
|
6121 #define RCC_PLLSAICFGR_PLLSAIN_6 ((uint32_t)0x00001000)
|
|
|
6122 #define RCC_PLLSAICFGR_PLLSAIN_7 ((uint32_t)0x00002000)
|
|
|
6123 #define RCC_PLLSAICFGR_PLLSAIN_8 ((uint32_t)0x00004000)
|
|
|
6124
|
|
|
6125 #define RCC_PLLSAICFGR_PLLSAIQ ((uint32_t)0x0F000000)
|
|
|
6126 #define RCC_PLLSAICFGR_PLLSAIQ_0 ((uint32_t)0x01000000)
|
|
|
6127 #define RCC_PLLSAICFGR_PLLSAIQ_1 ((uint32_t)0x02000000)
|
|
|
6128 #define RCC_PLLSAICFGR_PLLSAIQ_2 ((uint32_t)0x04000000)
|
|
|
6129 #define RCC_PLLSAICFGR_PLLSAIQ_3 ((uint32_t)0x08000000)
|
|
|
6130
|
|
|
6131 #define RCC_PLLSAICFGR_PLLSAIR ((uint32_t)0x70000000)
|
|
|
6132 #define RCC_PLLSAICFGR_PLLSAIR_0 ((uint32_t)0x10000000)
|
|
|
6133 #define RCC_PLLSAICFGR_PLLSAIR_1 ((uint32_t)0x20000000)
|
|
|
6134 #define RCC_PLLSAICFGR_PLLSAIR_2 ((uint32_t)0x40000000)
|
|
|
6135
|
|
|
6136 /******************** Bit definition for RCC_DCKCFGR register ***************/
|
|
|
6137 #define RCC_DCKCFGR_PLLI2SDIVQ ((uint32_t)0x0000001F)
|
|
|
6138 #define RCC_DCKCFGR_PLLSAIDIVQ ((uint32_t)0x00001F00)
|
|
|
6139 #define RCC_DCKCFGR_PLLSAIDIVR ((uint32_t)0x00030000)
|
|
|
6140 #define RCC_DCKCFGR_SAI1ASRC ((uint32_t)0x00300000)
|
|
|
6141 #define RCC_DCKCFGR_SAI1BSRC ((uint32_t)0x00C00000)
|
|
|
6142 #define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000)
|
|
|
6143
|
|
|
6144
|
|
|
6145 /******************************************************************************/
|
|
|
6146 /* */
|
|
|
6147 /* RNG */
|
|
|
6148 /* */
|
|
|
6149 /******************************************************************************/
|
|
|
6150 /******************** Bits definition for RNG_CR register *******************/
|
|
|
6151 #define RNG_CR_RNGEN ((uint32_t)0x00000004)
|
|
|
6152 #define RNG_CR_IE ((uint32_t)0x00000008)
|
|
|
6153
|
|
|
6154 /******************** Bits definition for RNG_SR register *******************/
|
|
|
6155 #define RNG_SR_DRDY ((uint32_t)0x00000001)
|
|
|
6156 #define RNG_SR_CECS ((uint32_t)0x00000002)
|
|
|
6157 #define RNG_SR_SECS ((uint32_t)0x00000004)
|
|
|
6158 #define RNG_SR_CEIS ((uint32_t)0x00000020)
|
|
|
6159 #define RNG_SR_SEIS ((uint32_t)0x00000040)
|
|
|
6160
|
|
|
6161 /******************************************************************************/
|
|
|
6162 /* */
|
|
|
6163 /* Real-Time Clock (RTC) */
|
|
|
6164 /* */
|
|
|
6165 /******************************************************************************/
|
|
|
6166 /******************** Bits definition for RTC_TR register *******************/
|
|
|
6167 #define RTC_TR_PM ((uint32_t)0x00400000)
|
|
|
6168 #define RTC_TR_HT ((uint32_t)0x00300000)
|
|
|
6169 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
|
|
|
6170 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
|
|
|
6171 #define RTC_TR_HU ((uint32_t)0x000F0000)
|
|
|
6172 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
|
|
|
6173 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
|
|
|
6174 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
|
|
|
6175 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
|
|
|
6176 #define RTC_TR_MNT ((uint32_t)0x00007000)
|
|
|
6177 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
|
|
|
6178 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
|
|
|
6179 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
|
|
|
6180 #define RTC_TR_MNU ((uint32_t)0x00000F00)
|
|
|
6181 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
|
|
|
6182 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
|
|
|
6183 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
|
|
|
6184 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
|
|
|
6185 #define RTC_TR_ST ((uint32_t)0x00000070)
|
|
|
6186 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
|
|
|
6187 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
|
|
|
6188 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
|
|
|
6189 #define RTC_TR_SU ((uint32_t)0x0000000F)
|
|
|
6190 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
|
|
|
6191 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
|
|
|
6192 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
|
|
|
6193 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
|
|
|
6194
|
|
|
6195 /******************** Bits definition for RTC_DR register *******************/
|
|
|
6196 #define RTC_DR_YT ((uint32_t)0x00F00000)
|
|
|
6197 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
|
|
|
6198 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
|
|
|
6199 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
|
|
|
6200 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
|
|
|
6201 #define RTC_DR_YU ((uint32_t)0x000F0000)
|
|
|
6202 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
|
|
|
6203 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
|
|
|
6204 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
|
|
|
6205 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
|
|
|
6206 #define RTC_DR_WDU ((uint32_t)0x0000E000)
|
|
|
6207 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
|
|
|
6208 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
|
|
|
6209 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
|
|
|
6210 #define RTC_DR_MT ((uint32_t)0x00001000)
|
|
|
6211 #define RTC_DR_MU ((uint32_t)0x00000F00)
|
|
|
6212 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
|
|
|
6213 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
|
|
|
6214 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
|
|
|
6215 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
|
|
|
6216 #define RTC_DR_DT ((uint32_t)0x00000030)
|
|
|
6217 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
|
|
|
6218 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
|
|
|
6219 #define RTC_DR_DU ((uint32_t)0x0000000F)
|
|
|
6220 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
|
|
|
6221 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
|
|
|
6222 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
|
|
|
6223 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
|
|
|
6224
|
|
|
6225 /******************** Bits definition for RTC_CR register *******************/
|
|
|
6226 #define RTC_CR_COE ((uint32_t)0x00800000)
|
|
|
6227 #define RTC_CR_OSEL ((uint32_t)0x00600000)
|
|
|
6228 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
|
|
|
6229 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
|
|
|
6230 #define RTC_CR_POL ((uint32_t)0x00100000)
|
|
|
6231 #define RTC_CR_COSEL ((uint32_t)0x00080000)
|
|
|
6232 #define RTC_CR_BCK ((uint32_t)0x00040000)
|
|
|
6233 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
|
|
|
6234 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
|
|
|
6235 #define RTC_CR_TSIE ((uint32_t)0x00008000)
|
|
|
6236 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
|
|
|
6237 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
|
|
|
6238 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
|
|
|
6239 #define RTC_CR_TSE ((uint32_t)0x00000800)
|
|
|
6240 #define RTC_CR_WUTE ((uint32_t)0x00000400)
|
|
|
6241 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
|
|
|
6242 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
|
|
|
6243 #define RTC_CR_DCE ((uint32_t)0x00000080)
|
|
|
6244 #define RTC_CR_FMT ((uint32_t)0x00000040)
|
|
|
6245 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
|
|
|
6246 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
|
|
|
6247 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
|
|
|
6248 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
|
|
|
6249 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
|
|
|
6250 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
|
|
|
6251 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
|
|
|
6252
|
|
|
6253 /******************** Bits definition for RTC_ISR register ******************/
|
|
|
6254 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
|
|
|
6255 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
|
|
|
6256 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
|
|
|
6257 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
|
|
|
6258 #define RTC_ISR_TSF ((uint32_t)0x00000800)
|
|
|
6259 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
|
|
|
6260 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
|
|
|
6261 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
|
|
|
6262 #define RTC_ISR_INIT ((uint32_t)0x00000080)
|
|
|
6263 #define RTC_ISR_INITF ((uint32_t)0x00000040)
|
|
|
6264 #define RTC_ISR_RSF ((uint32_t)0x00000020)
|
|
|
6265 #define RTC_ISR_INITS ((uint32_t)0x00000010)
|
|
|
6266 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
|
|
|
6267 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
|
|
|
6268 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
|
|
|
6269 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
|
|
|
6270
|
|
|
6271 /******************** Bits definition for RTC_PRER register *****************/
|
|
|
6272 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
|
|
|
6273 #define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
|
|
|
6274
|
|
|
6275 /******************** Bits definition for RTC_WUTR register *****************/
|
|
|
6276 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
|
|
|
6277
|
|
|
6278 /******************** Bits definition for RTC_CALIBR register ***************/
|
|
|
6279 #define RTC_CALIBR_DCS ((uint32_t)0x00000080)
|
|
|
6280 #define RTC_CALIBR_DC ((uint32_t)0x0000001F)
|
|
|
6281
|
|
|
6282 /******************** Bits definition for RTC_ALRMAR register ***************/
|
|
|
6283 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
|
|
|
6284 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
|
|
|
6285 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
|
|
|
6286 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
|
|
|
6287 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
|
|
|
6288 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
|
|
|
6289 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
|
|
|
6290 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
|
|
|
6291 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
|
|
|
6292 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
|
|
|
6293 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
|
|
|
6294 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
|
|
|
6295 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
|
|
|
6296 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
|
|
|
6297 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
|
|
|
6298 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
|
|
|
6299 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
|
|
|
6300 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
|
|
|
6301 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
|
|
|
6302 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
|
|
|
6303 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
|
|
|
6304 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
|
|
|
6305 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
|
|
|
6306 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
|
|
|
6307 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
|
|
|
6308 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
|
|
|
6309 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
|
|
|
6310 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
|
|
|
6311 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
|
|
|
6312 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
|
|
|
6313 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
|
|
|
6314 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
|
|
|
6315 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
|
|
|
6316 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
|
|
|
6317 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
|
|
|
6318 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
|
|
|
6319 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
|
|
|
6320 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
|
|
|
6321 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
|
|
|
6322 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
|
|
|
6323
|
|
|
6324 /******************** Bits definition for RTC_ALRMBR register ***************/
|
|
|
6325 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
|
|
|
6326 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
|
|
|
6327 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
|
|
|
6328 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
|
|
|
6329 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
|
|
|
6330 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
|
|
|
6331 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
|
|
|
6332 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
|
|
|
6333 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
|
|
|
6334 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
|
|
|
6335 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
|
|
|
6336 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
|
|
|
6337 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
|
|
|
6338 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
|
|
|
6339 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
|
|
|
6340 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
|
|
|
6341 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
|
|
|
6342 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
|
|
|
6343 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
|
|
|
6344 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
|
|
|
6345 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
|
|
|
6346 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
|
|
|
6347 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
|
|
|
6348 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
|
|
|
6349 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
|
|
|
6350 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
|
|
|
6351 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
|
|
|
6352 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
|
|
|
6353 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
|
|
|
6354 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
|
|
|
6355 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
|
|
|
6356 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
|
|
|
6357 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
|
|
|
6358 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
|
|
|
6359 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
|
|
|
6360 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
|
|
|
6361 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
|
|
|
6362 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
|
|
|
6363 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
|
|
|
6364 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
|
|
|
6365
|
|
|
6366 /******************** Bits definition for RTC_WPR register ******************/
|
|
|
6367 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
|
|
|
6368
|
|
|
6369 /******************** Bits definition for RTC_SSR register ******************/
|
|
|
6370 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
|
|
|
6371
|
|
|
6372 /******************** Bits definition for RTC_SHIFTR register ***************/
|
|
|
6373 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
|
|
|
6374 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
|
|
|
6375
|
|
|
6376 /******************** Bits definition for RTC_TSTR register *****************/
|
|
|
6377 #define RTC_TSTR_PM ((uint32_t)0x00400000)
|
|
|
6378 #define RTC_TSTR_HT ((uint32_t)0x00300000)
|
|
|
6379 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
|
|
|
6380 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
|
|
|
6381 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
|
|
|
6382 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
|
|
|
6383 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
|
|
|
6384 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
|
|
|
6385 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
|
|
|
6386 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
|
|
|
6387 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
|
|
|
6388 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
|
|
|
6389 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
|
|
|
6390 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
|
|
|
6391 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
|
|
|
6392 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
|
|
|
6393 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
|
|
|
6394 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
|
|
|
6395 #define RTC_TSTR_ST ((uint32_t)0x00000070)
|
|
|
6396 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
|
|
|
6397 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
|
|
|
6398 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
|
|
|
6399 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
|
|
|
6400 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
|
|
|
6401 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
|
|
|
6402 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
|
|
|
6403 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
|
|
|
6404
|
|
|
6405 /******************** Bits definition for RTC_TSDR register *****************/
|
|
|
6406 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
|
|
|
6407 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
|
|
|
6408 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
|
|
|
6409 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
|
|
|
6410 #define RTC_TSDR_MT ((uint32_t)0x00001000)
|
|
|
6411 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
|
|
|
6412 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
|
|
|
6413 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
|
|
|
6414 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
|
|
|
6415 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
|
|
|
6416 #define RTC_TSDR_DT ((uint32_t)0x00000030)
|
|
|
6417 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
|
|
|
6418 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
|
|
|
6419 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
|
|
|
6420 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
|
|
|
6421 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
|
|
|
6422 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
|
|
|
6423 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
|
|
|
6424
|
|
|
6425 /******************** Bits definition for RTC_TSSSR register ****************/
|
|
|
6426 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
|
|
|
6427
|
|
|
6428 /******************** Bits definition for RTC_CAL register *****************/
|
|
|
6429 #define RTC_CALR_CALP ((uint32_t)0x00008000)
|
|
|
6430 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
|
|
|
6431 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
|
|
|
6432 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
|
|
|
6433 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
|
|
|
6434 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
|
|
|
6435 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
|
|
|
6436 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
|
|
|
6437 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
|
|
|
6438 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
|
|
|
6439 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
|
|
|
6440 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
|
|
|
6441 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
|
|
|
6442
|
|
|
6443 /******************** Bits definition for RTC_TAFCR register ****************/
|
|
|
6444 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
|
|
|
6445 #define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
|
|
|
6446 #define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
|
|
|
6447 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
|
|
|
6448 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
|
|
|
6449 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
|
|
|
6450 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
|
|
|
6451 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
|
|
|
6452 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
|
|
|
6453 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
|
|
|
6454 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
|
|
|
6455 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
|
|
|
6456 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
|
|
|
6457 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
|
|
|
6458 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
|
|
|
6459 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
|
|
|
6460 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
|
|
|
6461 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
|
|
|
6462 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
|
|
|
6463 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
|
|
|
6464
|
|
|
6465 /******************** Bits definition for RTC_ALRMASSR register *************/
|
|
|
6466 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
|
|
|
6467 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
|
|
|
6468 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
|
|
|
6469 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
|
|
|
6470 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
|
|
|
6471 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
|
|
|
6472
|
|
|
6473 /******************** Bits definition for RTC_ALRMBSSR register *************/
|
|
|
6474 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
|
|
|
6475 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
|
|
|
6476 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
|
|
|
6477 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
|
|
|
6478 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
|
|
|
6479 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
|
|
|
6480
|
|
|
6481 /******************** Bits definition for RTC_BKP0R register ****************/
|
|
|
6482 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
|
|
|
6483
|
|
|
6484 /******************** Bits definition for RTC_BKP1R register ****************/
|
|
|
6485 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
|
|
|
6486
|
|
|
6487 /******************** Bits definition for RTC_BKP2R register ****************/
|
|
|
6488 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
|
|
|
6489
|
|
|
6490 /******************** Bits definition for RTC_BKP3R register ****************/
|
|
|
6491 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
|
|
|
6492
|
|
|
6493 /******************** Bits definition for RTC_BKP4R register ****************/
|
|
|
6494 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
|
|
|
6495
|
|
|
6496 /******************** Bits definition for RTC_BKP5R register ****************/
|
|
|
6497 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
|
|
|
6498
|
|
|
6499 /******************** Bits definition for RTC_BKP6R register ****************/
|
|
|
6500 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
|
|
|
6501
|
|
|
6502 /******************** Bits definition for RTC_BKP7R register ****************/
|
|
|
6503 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
|
|
|
6504
|
|
|
6505 /******************** Bits definition for RTC_BKP8R register ****************/
|
|
|
6506 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
|
|
|
6507
|
|
|
6508 /******************** Bits definition for RTC_BKP9R register ****************/
|
|
|
6509 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
|
|
|
6510
|
|
|
6511 /******************** Bits definition for RTC_BKP10R register ***************/
|
|
|
6512 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
|
|
|
6513
|
|
|
6514 /******************** Bits definition for RTC_BKP11R register ***************/
|
|
|
6515 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
|
|
|
6516
|
|
|
6517 /******************** Bits definition for RTC_BKP12R register ***************/
|
|
|
6518 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
|
|
|
6519
|
|
|
6520 /******************** Bits definition for RTC_BKP13R register ***************/
|
|
|
6521 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
|
|
|
6522
|
|
|
6523 /******************** Bits definition for RTC_BKP14R register ***************/
|
|
|
6524 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
|
|
|
6525
|
|
|
6526 /******************** Bits definition for RTC_BKP15R register ***************/
|
|
|
6527 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
|
|
|
6528
|
|
|
6529 /******************** Bits definition for RTC_BKP16R register ***************/
|
|
|
6530 #define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
|
|
|
6531
|
|
|
6532 /******************** Bits definition for RTC_BKP17R register ***************/
|
|
|
6533 #define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
|
|
|
6534
|
|
|
6535 /******************** Bits definition for RTC_BKP18R register ***************/
|
|
|
6536 #define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
|
|
|
6537
|
|
|
6538 /******************** Bits definition for RTC_BKP19R register ***************/
|
|
|
6539 #define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
|
|
|
6540
|
|
|
6541 /******************************************************************************/
|
|
|
6542 /* */
|
|
|
6543 /* Serial Audio Interface */
|
|
|
6544 /* */
|
|
|
6545 /******************************************************************************/
|
|
|
6546 /******************** Bit definition for SAI_GCR register *******************/
|
|
|
6547 #define SAI_GCR_SYNCIN ((uint32_t)0x00000003) /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
|
|
|
6548 #define SAI_GCR_SYNCIN_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
6549 #define SAI_GCR_SYNCIN_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
6550
|
|
|
6551 #define SAI_GCR_SYNCOUT ((uint32_t)0x00000030) /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
|
|
|
6552 #define SAI_GCR_SYNCOUT_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
6553 #define SAI_GCR_SYNCOUT_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
6554
|
|
|
6555 /******************* Bit definition for SAI_xCR1 register *******************/
|
|
|
6556 #define SAI_xCR1_MODE ((uint32_t)0x00000003) /*!<MODE[1:0] bits (Audio Block Mode) */
|
|
|
6557 #define SAI_xCR1_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
6558 #define SAI_xCR1_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
6559
|
|
|
6560 #define SAI_xCR1_PRTCFG ((uint32_t)0x0000000C) /*!<PRTCFG[1:0] bits (Protocol Configuration) */
|
|
|
6561 #define SAI_xCR1_PRTCFG_0 ((uint32_t)0x00000004) /*!<Bit 0 */
|
|
|
6562 #define SAI_xCR1_PRTCFG_1 ((uint32_t)0x00000008) /*!<Bit 1 */
|
|
|
6563
|
|
|
6564 #define SAI_xCR1_DS ((uint32_t)0x000000E0) /*!<DS[1:0] bits (Data Size) */
|
|
|
6565 #define SAI_xCR1_DS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
|
|
|
6566 #define SAI_xCR1_DS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
|
|
|
6567 #define SAI_xCR1_DS_2 ((uint32_t)0x00000080) /*!<Bit 2 */
|
|
|
6568
|
|
|
6569 #define SAI_xCR1_LSBFIRST ((uint32_t)0x00000100) /*!<LSB First Configuration */
|
|
|
6570 #define SAI_xCR1_CKSTR ((uint32_t)0x00000200) /*!<ClocK STRobing edge */
|
|
|
6571
|
|
|
6572 #define SAI_xCR1_SYNCEN ((uint32_t)0x00000C00) /*!<SYNCEN[1:0](SYNChronization ENable) */
|
|
|
6573 #define SAI_xCR1_SYNCEN_0 ((uint32_t)0x00000400) /*!<Bit 0 */
|
|
|
6574 #define SAI_xCR1_SYNCEN_1 ((uint32_t)0x00000800) /*!<Bit 1 */
|
|
|
6575
|
|
|
6576 #define SAI_xCR1_MONO ((uint32_t)0x00001000) /*!<Mono mode */
|
|
|
6577 #define SAI_xCR1_OUTDRIV ((uint32_t)0x00002000) /*!<Output Drive */
|
|
|
6578 #define SAI_xCR1_SAIEN ((uint32_t)0x00010000) /*!<Audio Block enable */
|
|
|
6579 #define SAI_xCR1_DMAEN ((uint32_t)0x00020000) /*!<DMA enable */
|
|
|
6580 #define SAI_xCR1_NODIV ((uint32_t)0x00080000) /*!<No Divider Configuration */
|
|
|
6581
|
|
|
6582 #define SAI_xCR1_MCKDIV ((uint32_t)0x00780000) /*!<MCKDIV[3:0] (Master ClocK Divider) */
|
|
|
6583 #define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00080000) /*!<Bit 0 */
|
|
|
6584 #define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00100000) /*!<Bit 1 */
|
|
|
6585 #define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00200000) /*!<Bit 2 */
|
|
|
6586 #define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00400000) /*!<Bit 3 */
|
|
|
6587
|
|
|
6588 /******************* Bit definition for SAI_xCR2 register *******************/
|
|
|
6589 #define SAI_xCR2_FTH ((uint32_t)0x00000003) /*!<FTH[1:0](Fifo THreshold) */
|
|
|
6590 #define SAI_xCR2_FTH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
6591 #define SAI_xCR2_FTH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
6592
|
|
|
6593 #define SAI_xCR2_FFLUSH ((uint32_t)0x00000008) /*!<Fifo FLUSH */
|
|
|
6594 #define SAI_xCR2_TRIS ((uint32_t)0x00000010) /*!<TRIState Management on data line */
|
|
|
6595 #define SAI_xCR2_MUTE ((uint32_t)0x00000020) /*!<Mute mode */
|
|
|
6596 #define SAI_xCR2_MUTEVAL ((uint32_t)0x00000040) /*!<Muate value */
|
|
|
6597
|
|
|
6598 #define SAI_xCR2_MUTECNT ((uint32_t)0x00001F80) /*!<MUTECNT[5:0] (MUTE counter) */
|
|
|
6599 #define SAI_xCR2_MUTECNT_0 ((uint32_t)0x00000080) /*!<Bit 0 */
|
|
|
6600 #define SAI_xCR2_MUTECNT_1 ((uint32_t)0x00000100) /*!<Bit 1 */
|
|
|
6601 #define SAI_xCR2_MUTECNT_2 ((uint32_t)0x00000200) /*!<Bit 2 */
|
|
|
6602 #define SAI_xCR2_MUTECNT_3 ((uint32_t)0x00000400) /*!<Bit 3 */
|
|
|
6603 #define SAI_xCR2_MUTECNT_4 ((uint32_t)0x00000800) /*!<Bit 4 */
|
|
|
6604 #define SAI_xCR2_MUTECNT_5 ((uint32_t)0x00001000) /*!<Bit 5 */
|
|
|
6605
|
|
|
6606 #define SAI_xCR2_CPL ((uint32_t)0x00080000) /*!< Complement Bit */
|
|
|
6607
|
|
|
6608 #define SAI_xCR2_COMP ((uint32_t)0x0000C000) /*!<COMP[1:0] (Companding mode) */
|
|
|
6609 #define SAI_xCR2_COMP_0 ((uint32_t)0x00004000) /*!<Bit 0 */
|
|
|
6610 #define SAI_xCR2_COMP_1 ((uint32_t)0x00008000) /*!<Bit 1 */
|
|
|
6611
|
|
|
6612 /****************** Bit definition for SAI_xFRCR register *******************/
|
|
|
6613 #define SAI_xFRCR_FRL ((uint32_t)0x000000FF) /*!<FRL[1:0](Frame length) */
|
|
|
6614 #define SAI_xFRCR_FRL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
6615 #define SAI_xFRCR_FRL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
6616 #define SAI_xFRCR_FRL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
6617 #define SAI_xFRCR_FRL_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
6618 #define SAI_xFRCR_FRL_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
|
|
6619 #define SAI_xFRCR_FRL_5 ((uint32_t)0x00000020) /*!<Bit 5 */
|
|
|
6620 #define SAI_xFRCR_FRL_6 ((uint32_t)0x00000040) /*!<Bit 6 */
|
|
|
6621 #define SAI_xFRCR_FRL_7 ((uint32_t)0x00000080) /*!<Bit 7 */
|
|
|
6622
|
|
|
6623 #define SAI_xFRCR_FSALL ((uint32_t)0x00007F00) /*!<FRL[1:0] (Frame synchronization active level length) */
|
|
|
6624 #define SAI_xFRCR_FSALL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
|
|
6625 #define SAI_xFRCR_FSALL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
|
|
6626 #define SAI_xFRCR_FSALL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
|
|
6627 #define SAI_xFRCR_FSALL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
|
|
6628 #define SAI_xFRCR_FSALL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
|
|
6629 #define SAI_xFRCR_FSALL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
|
|
6630 #define SAI_xFRCR_FSALL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
|
|
6631
|
|
|
6632 #define SAI_xFRCR_FSDEF ((uint32_t)0x00010000) /*!< Frame Synchronization Definition */
|
|
|
6633 #define SAI_xFRCR_FSPO ((uint32_t)0x00020000) /*!<Frame Synchronization POLarity */
|
|
|
6634 #define SAI_xFRCR_FSOFF ((uint32_t)0x00040000) /*!<Frame Synchronization OFFset */
|
|
|
6635
|
|
|
6636 /****************** Bit definition for SAI_xSLOTR register *******************/
|
|
|
6637 #define SAI_xSLOTR_FBOFF ((uint32_t)0x0000001F) /*!<FRL[4:0](First Bit Offset) */
|
|
|
6638 #define SAI_xSLOTR_FBOFF_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
6639 #define SAI_xSLOTR_FBOFF_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
6640 #define SAI_xSLOTR_FBOFF_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
6641 #define SAI_xSLOTR_FBOFF_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
6642 #define SAI_xSLOTR_FBOFF_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
|
|
6643
|
|
|
6644 #define SAI_xSLOTR_SLOTSZ ((uint32_t)0x000000C0) /*!<SLOTSZ[1:0] (Slot size) */
|
|
|
6645 #define SAI_xSLOTR_SLOTSZ_0 ((uint32_t)0x00000040) /*!<Bit 0 */
|
|
|
6646 #define SAI_xSLOTR_SLOTSZ_1 ((uint32_t)0x00000080) /*!<Bit 1 */
|
|
|
6647
|
|
|
6648 #define SAI_xSLOTR_NBSLOT ((uint32_t)0x00000F00) /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
|
|
|
6649 #define SAI_xSLOTR_NBSLOT_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
|
|
6650 #define SAI_xSLOTR_NBSLOT_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
|
|
6651 #define SAI_xSLOTR_NBSLOT_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
|
|
6652 #define SAI_xSLOTR_NBSLOT_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
|
|
6653
|
|
|
6654 #define SAI_xSLOTR_SLOTEN ((uint32_t)0xFFFF0000) /*!<SLOTEN[15:0] (Slot Enable) */
|
|
|
6655
|
|
|
6656 /******************* Bit definition for SAI_xIMR register *******************/
|
|
|
6657 #define SAI_xIMR_OVRUDRIE ((uint32_t)0x00000001) /*!<Overrun underrun interrupt enable */
|
|
|
6658 #define SAI_xIMR_MUTEDETIE ((uint32_t)0x00000002) /*!<Mute detection interrupt enable */
|
|
|
6659 #define SAI_xIMR_WCKCFGIE ((uint32_t)0x00000004) /*!<Wrong Clock Configuration interrupt enable */
|
|
|
6660 #define SAI_xIMR_FREQIE ((uint32_t)0x00000008) /*!<FIFO request interrupt enable */
|
|
|
6661 #define SAI_xIMR_CNRDYIE ((uint32_t)0x00000010) /*!<Codec not ready interrupt enable */
|
|
|
6662 #define SAI_xIMR_AFSDETIE ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection interrupt enable */
|
|
|
6663 #define SAI_xIMR_LFSDETIE ((uint32_t)0x00000040) /*!<Late frame synchronization detection interrupt enable */
|
|
|
6664
|
|
|
6665 /******************** Bit definition for SAI_xSR register *******************/
|
|
|
6666 #define SAI_xSR_OVRUDR ((uint32_t)0x00000001) /*!<Overrun underrun */
|
|
|
6667 #define SAI_xSR_MUTEDET ((uint32_t)0x00000002) /*!<Mute detection */
|
|
|
6668 #define SAI_xSR_WCKCFG ((uint32_t)0x00000004) /*!<Wrong Clock Configuration */
|
|
|
6669 #define SAI_xSR_FREQ ((uint32_t)0x00000008) /*!<FIFO request */
|
|
|
6670 #define SAI_xSR_CNRDY ((uint32_t)0x00000010) /*!<Codec not ready */
|
|
|
6671 #define SAI_xSR_AFSDET ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection */
|
|
|
6672 #define SAI_xSR_LFSDET ((uint32_t)0x00000040) /*!<Late frame synchronization detection */
|
|
|
6673
|
|
|
6674 #define SAI_xSR_FLVL ((uint32_t)0x00070000) /*!<FLVL[2:0] (FIFO Level Threshold) */
|
|
|
6675 #define SAI_xSR_FLVL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
6676 #define SAI_xSR_FLVL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
6677 #define SAI_xSR_FLVL_2 ((uint32_t)0x00030000) /*!<Bit 2 */
|
|
|
6678
|
|
|
6679 /****************** Bit definition for SAI_xCLRFR register ******************/
|
|
|
6680 #define SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001) /*!<Clear Overrun underrun */
|
|
|
6681 #define SAI_xCLRFR_CMUTEDET ((uint32_t)0x00000002) /*!<Clear Mute detection */
|
|
|
6682 #define SAI_xCLRFR_CWCKCFG ((uint32_t)0x00000004) /*!<Clear Wrong Clock Configuration */
|
|
|
6683 #define SAI_xCLRFR_CFREQ ((uint32_t)0x00000008) /*!<Clear FIFO request */
|
|
|
6684 #define SAI_xCLRFR_CCNRDY ((uint32_t)0x00000010) /*!<Clear Codec not ready */
|
|
|
6685 #define SAI_xCLRFR_CAFSDET ((uint32_t)0x00000020) /*!<Clear Anticipated frame synchronization detection */
|
|
|
6686 #define SAI_xCLRFR_CLFSDET ((uint32_t)0x00000040) /*!<Clear Late frame synchronization detection */
|
|
|
6687
|
|
|
6688 /****************** Bit definition for SAI_xDR register ******************/
|
|
|
6689 #define SAI_xDR_DATA ((uint32_t)0xFFFFFFFF)
|
|
|
6690
|
|
|
6691
|
|
|
6692 /******************************************************************************/
|
|
|
6693 /* */
|
|
|
6694 /* SD host Interface */
|
|
|
6695 /* */
|
|
|
6696 /******************************************************************************/
|
|
|
6697 /****************** Bit definition for SDIO_POWER register ******************/
|
|
|
6698 #define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
|
|
|
6699 #define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!<Bit 0 */
|
|
|
6700 #define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!<Bit 1 */
|
|
|
6701
|
|
|
6702 /****************** Bit definition for SDIO_CLKCR register ******************/
|
|
|
6703 #define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!<Clock divide factor */
|
|
|
6704 #define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /*!<Clock enable bit */
|
|
|
6705 #define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /*!<Power saving configuration bit */
|
|
|
6706 #define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /*!<Clock divider bypass enable bit */
|
|
|
6707
|
|
|
6708 #define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
|
|
|
6709 #define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!<Bit 0 */
|
|
|
6710 #define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!<Bit 1 */
|
|
|
6711
|
|
|
6712 #define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!<SDIO_CK dephasing selection bit */
|
|
|
6713 #define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!<HW Flow Control enable */
|
|
|
6714
|
|
|
6715 /******************* Bit definition for SDIO_ARG register *******************/
|
|
|
6716 #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
|
|
|
6717
|
|
|
6718 /******************* Bit definition for SDIO_CMD register *******************/
|
|
|
6719 #define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /*!<Command Index */
|
|
|
6720
|
|
|
6721 #define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
|
|
|
6722 #define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */
|
|
|
6723 #define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */
|
|
|
6724
|
|
|
6725 #define SDIO_CMD_WAITINT ((uint32_t)0x0100) /*!<CPSM Waits for Interrupt Request */
|
|
|
6726 #define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
|
|
|
6727 #define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
|
|
|
6728 #define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!<SD I/O suspend command */
|
|
|
6729 #define SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) /*!<Enable CMD completion */
|
|
|
6730 #define SDIO_CMD_NIEN ((uint32_t)0x2000) /*!<Not Interrupt Enable */
|
|
|
6731 #define SDIO_CMD_CEATACMD ((uint32_t)0x4000) /*!<CE-ATA command */
|
|
|
6732
|
|
|
6733 /***************** Bit definition for SDIO_RESPCMD register *****************/
|
|
|
6734 #define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!<Response command index */
|
|
|
6735
|
|
|
6736 /****************** Bit definition for SDIO_RESP0 register ******************/
|
|
|
6737 #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
|
|
|
6738
|
|
|
6739 /****************** Bit definition for SDIO_RESP1 register ******************/
|
|
|
6740 #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
|
|
|
6741
|
|
|
6742 /****************** Bit definition for SDIO_RESP2 register ******************/
|
|
|
6743 #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
|
|
|
6744
|
|
|
6745 /****************** Bit definition for SDIO_RESP3 register ******************/
|
|
|
6746 #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
|
|
|
6747
|
|
|
6748 /****************** Bit definition for SDIO_RESP4 register ******************/
|
|
|
6749 #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
|
|
|
6750
|
|
|
6751 /****************** Bit definition for SDIO_DTIMER register *****************/
|
|
|
6752 #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
|
|
|
6753
|
|
|
6754 /****************** Bit definition for SDIO_DLEN register *******************/
|
|
|
6755 #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
|
|
|
6756
|
|
|
6757 /****************** Bit definition for SDIO_DCTRL register ******************/
|
|
|
6758 #define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /*!<Data transfer enabled bit */
|
|
|
6759 #define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /*!<Data transfer direction selection */
|
|
|
6760 #define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /*!<Data transfer mode selection */
|
|
|
6761 #define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /*!<DMA enabled bit */
|
|
|
6762
|
|
|
6763 #define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
|
|
|
6764 #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!<Bit 0 */
|
|
|
6765 #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!<Bit 1 */
|
|
|
6766 #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!<Bit 2 */
|
|
|
6767 #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!<Bit 3 */
|
|
|
6768
|
|
|
6769 #define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /*!<Read wait start */
|
|
|
6770 #define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /*!<Read wait stop */
|
|
|
6771 #define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /*!<Read wait mode */
|
|
|
6772 #define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /*!<SD I/O enable functions */
|
|
|
6773
|
|
|
6774 /****************** Bit definition for SDIO_DCOUNT register *****************/
|
|
|
6775 #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
|
|
|
6776
|
|
|
6777 /****************** Bit definition for SDIO_STA register ********************/
|
|
|
6778 #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
|
|
|
6779 #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
|
|
|
6780 #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
|
|
|
6781 #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
|
|
|
6782 #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
|
|
|
6783 #define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
|
|
|
6784 #define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
|
|
|
6785 #define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
|
|
|
6786 #define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
|
|
|
6787 #define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */
|
|
|
6788 #define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
|
|
|
6789 #define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
|
|
|
6790 #define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
|
|
|
6791 #define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
|
|
|
6792 #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
|
|
|
6793 #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
|
|
|
6794 #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
|
|
|
6795 #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
|
|
|
6796 #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
|
|
|
6797 #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
|
|
|
6798 #define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
|
|
|
6799 #define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
|
|
|
6800 #define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
|
|
|
6801 #define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */
|
|
|
6802
|
|
|
6803 /******************* Bit definition for SDIO_ICR register *******************/
|
|
|
6804 #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
|
|
|
6805 #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
|
|
|
6806 #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
|
|
|
6807 #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
|
|
|
6808 #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
|
|
|
6809 #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
|
|
|
6810 #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
|
|
|
6811 #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
|
|
|
6812 #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
|
|
|
6813 #define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */
|
|
|
6814 #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
|
|
|
6815 #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
|
|
|
6816 #define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */
|
|
|
6817
|
|
|
6818 /****************** Bit definition for SDIO_MASK register *******************/
|
|
|
6819 #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
|
|
|
6820 #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
|
|
|
6821 #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
|
|
|
6822 #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
|
|
|
6823 #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
|
|
|
6824 #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
|
|
|
6825 #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
|
|
|
6826 #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
|
|
|
6827 #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
|
|
|
6828 #define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */
|
|
|
6829 #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
|
|
|
6830 #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
|
|
|
6831 #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
|
|
|
6832 #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
|
|
|
6833 #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
|
|
|
6834 #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
|
|
|
6835 #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
|
|
|
6836 #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
|
|
|
6837 #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
|
|
|
6838 #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
|
|
|
6839 #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
|
|
|
6840 #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
|
|
|
6841 #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
|
|
|
6842 #define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */
|
|
|
6843
|
|
|
6844 /***************** Bit definition for SDIO_FIFOCNT register *****************/
|
|
|
6845 #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
|
|
|
6846
|
|
|
6847 /****************** Bit definition for SDIO_FIFO register *******************/
|
|
|
6848 #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
|
|
|
6849
|
|
|
6850 /******************************************************************************/
|
|
|
6851 /* */
|
|
|
6852 /* Serial Peripheral Interface */
|
|
|
6853 /* */
|
|
|
6854 /******************************************************************************/
|
|
|
6855 /******************* Bit definition for SPI_CR1 register ********************/
|
|
|
6856 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!<Clock Phase */
|
|
|
6857 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!<Clock Polarity */
|
|
|
6858 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!<Master Selection */
|
|
|
6859
|
|
|
6860 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!<BR[2:0] bits (Baud Rate Control) */
|
|
|
6861 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!<Bit 0 */
|
|
|
6862 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!<Bit 1 */
|
|
|
6863 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!<Bit 2 */
|
|
|
6864
|
|
|
6865 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!<SPI Enable */
|
|
|
6866 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!<Frame Format */
|
|
|
6867 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!<Internal slave select */
|
|
|
6868 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!<Software slave management */
|
|
|
6869 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!<Receive only */
|
|
|
6870 #define SPI_CR1_DFF ((uint32_t)0x00000800) /*!<Data Frame Format */
|
|
|
6871 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!<Transmit CRC next */
|
|
|
6872 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!<Hardware CRC calculation enable */
|
|
|
6873 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!<Output enable in bidirectional mode */
|
|
|
6874 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!<Bidirectional data mode enable */
|
|
|
6875
|
|
|
6876 /******************* Bit definition for SPI_CR2 register ********************/
|
|
|
6877 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!<Rx Buffer DMA Enable */
|
|
|
6878 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!<Tx Buffer DMA Enable */
|
|
|
6879 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!<SS Output Enable */
|
|
|
6880 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!<Frame Format */
|
|
|
6881 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!<Error Interrupt Enable */
|
|
|
6882 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!<RX buffer Not Empty Interrupt Enable */
|
|
|
6883 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!<Tx buffer Empty Interrupt Enable */
|
|
|
6884
|
|
|
6885 /******************** Bit definition for SPI_SR register ********************/
|
|
|
6886 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!<Receive buffer Not Empty */
|
|
|
6887 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!<Transmit buffer Empty */
|
|
|
6888 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!<Channel side */
|
|
|
6889 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!<Underrun flag */
|
|
|
6890 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!<CRC Error flag */
|
|
|
6891 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!<Mode fault */
|
|
|
6892 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!<Overrun flag */
|
|
|
6893 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!<Busy flag */
|
|
|
6894 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!<Frame format error flag */
|
|
|
6895
|
|
|
6896 /******************** Bit definition for SPI_DR register ********************/
|
|
|
6897 #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!<Data Register */
|
|
|
6898
|
|
|
6899 /******************* Bit definition for SPI_CRCPR register ******************/
|
|
|
6900 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!<CRC polynomial register */
|
|
|
6901
|
|
|
6902 /****************** Bit definition for SPI_RXCRCR register ******************/
|
|
|
6903 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!<Rx CRC Register */
|
|
|
6904
|
|
|
6905 /****************** Bit definition for SPI_TXCRCR register ******************/
|
|
|
6906 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!<Tx CRC Register */
|
|
|
6907
|
|
|
6908 /****************** Bit definition for SPI_I2SCFGR register *****************/
|
|
|
6909 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
|
|
|
6910
|
|
|
6911 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
|
|
|
6912 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
|
|
|
6913 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
|
|
|
6914
|
|
|
6915 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
|
|
|
6916
|
|
|
6917 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
|
|
|
6918 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
6919 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
6920
|
|
|
6921 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
|
|
|
6922
|
|
|
6923 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
|
|
|
6924 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
|
|
6925 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
|
|
6926
|
|
|
6927 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
|
|
|
6928 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
|
|
|
6929
|
|
|
6930 /****************** Bit definition for SPI_I2SPR register *******************/
|
|
|
6931 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
|
|
|
6932 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
|
|
|
6933 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
|
|
|
6934
|
|
|
6935 /******************************************************************************/
|
|
|
6936 /* */
|
|
|
6937 /* SYSCFG */
|
|
|
6938 /* */
|
|
|
6939 /******************************************************************************/
|
|
|
6940 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
|
|
|
6941 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
|
|
|
6942 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
|
|
|
6943 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
|
|
|
6944 #define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
|
|
|
6945
|
|
|
6946 #define SYSCFG_MEMRMP_UFB_MODE ((uint32_t)0x00000100) /*!< User Flash Bank mode */
|
|
|
6947 #define SYSCFG_SWP_FMC ((uint32_t)0x00000C00) /*!< FMC memory mapping swap */
|
|
|
6948
|
|
|
6949 /****************** Bit definition for SYSCFG_PMC register ******************/
|
|
|
6950 #define SYSCFG_PMC_ADCxDC2 ((uint32_t)0x00070000) /*!< Refer to AN4073 on how to use this bit */
|
|
|
6951 #define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit */
|
|
|
6952 #define SYSCFG_PMC_ADC2DC2 ((uint32_t)0x00020000) /*!< Refer to AN4073 on how to use this bit */
|
|
|
6953 #define SYSCFG_PMC_ADC3DC2 ((uint32_t)0x00040000) /*!< Refer to AN4073 on how to use this bit */
|
|
|
6954
|
|
|
6955 #define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */
|
|
|
6956 /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
|
|
|
6957 #define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
|
|
|
6958
|
|
|
6959 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
|
|
|
6960 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */
|
|
|
6961 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
|
|
|
6962 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
|
|
|
6963 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */
|
|
|
6964 /**
|
|
|
6965 * @brief EXTI0 configuration
|
|
|
6966 */
|
|
|
6967 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */
|
|
|
6968 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */
|
|
|
6969 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */
|
|
|
6970 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x0003) /*!<PD[0] pin */
|
|
|
6971 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x0004) /*!<PE[0] pin */
|
|
|
6972 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x0005) /*!<PF[0] pin */
|
|
|
6973 #define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x0006) /*!<PG[0] pin */
|
|
|
6974 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */
|
|
|
6975 #define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x0008) /*!<PI[0] pin */
|
|
|
6976 #define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x0009) /*!<PJ[0] pin */
|
|
|
6977 #define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x000A) /*!<PK[0] pin */
|
|
|
6978
|
|
|
6979 /**
|
|
|
6980 * @brief EXTI1 configuration
|
|
|
6981 */
|
|
|
6982 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */
|
|
|
6983 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */
|
|
|
6984 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */
|
|
|
6985 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x0030) /*!<PD[1] pin */
|
|
|
6986 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x0040) /*!<PE[1] pin */
|
|
|
6987 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x0050) /*!<PF[1] pin */
|
|
|
6988 #define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x0060) /*!<PG[1] pin */
|
|
|
6989 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */
|
|
|
6990 #define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x0080) /*!<PI[1] pin */
|
|
|
6991 #define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x0090) /*!<PJ[1] pin */
|
|
|
6992 #define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x00A0) /*!<PK[1] pin */
|
|
|
6993
|
|
|
6994
|
|
|
6995 /**
|
|
|
6996 * @brief EXTI2 configuration
|
|
|
6997 */
|
|
|
6998 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */
|
|
|
6999 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */
|
|
|
7000 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */
|
|
|
7001 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x0300) /*!<PD[2] pin */
|
|
|
7002 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x0400) /*!<PE[2] pin */
|
|
|
7003 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x0500) /*!<PF[2] pin */
|
|
|
7004 #define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x0600) /*!<PG[2] pin */
|
|
|
7005 #define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */
|
|
|
7006 #define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x0800) /*!<PI[2] pin */
|
|
|
7007 #define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x0900) /*!<PJ[2] pin */
|
|
|
7008 #define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x0A00) /*!<PK[2] pin */
|
|
|
7009
|
|
|
7010
|
|
|
7011 /**
|
|
|
7012 * @brief EXTI3 configuration
|
|
|
7013 */
|
|
|
7014 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */
|
|
|
7015 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */
|
|
|
7016 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */
|
|
|
7017 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x3000) /*!<PD[3] pin */
|
|
|
7018 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x4000) /*!<PE[3] pin */
|
|
|
7019 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x5000) /*!<PF[3] pin */
|
|
|
7020 #define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x6000) /*!<PG[3] pin */
|
|
|
7021 #define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */
|
|
|
7022 #define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x8000) /*!<PI[3] pin */
|
|
|
7023 #define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x9000) /*!<PJ[3] pin */
|
|
|
7024 #define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0xA000) /*!<PK[3] pin */
|
|
|
7025
|
|
|
7026
|
|
|
7027 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
|
|
|
7028 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */
|
|
|
7029 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
|
|
|
7030 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
|
|
|
7031 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */
|
|
|
7032 /**
|
|
|
7033 * @brief EXTI4 configuration
|
|
|
7034 */
|
|
|
7035 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */
|
|
|
7036 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */
|
|
|
7037 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */
|
|
|
7038 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x0003) /*!<PD[4] pin */
|
|
|
7039 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x0004) /*!<PE[4] pin */
|
|
|
7040 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x0005) /*!<PF[4] pin */
|
|
|
7041 #define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x0006) /*!<PG[4] pin */
|
|
|
7042 #define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */
|
|
|
7043 #define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x0008) /*!<PI[4] pin */
|
|
|
7044 #define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x0009) /*!<PJ[4] pin */
|
|
|
7045 #define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x000A) /*!<PK[4] pin */
|
|
|
7046
|
|
|
7047 /**
|
|
|
7048 * @brief EXTI5 configuration
|
|
|
7049 */
|
|
|
7050 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */
|
|
|
7051 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */
|
|
|
7052 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */
|
|
|
7053 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x0030) /*!<PD[5] pin */
|
|
|
7054 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x0040) /*!<PE[5] pin */
|
|
|
7055 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x0050) /*!<PF[5] pin */
|
|
|
7056 #define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x0060) /*!<PG[5] pin */
|
|
|
7057 #define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */
|
|
|
7058 #define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x0080) /*!<PI[5] pin */
|
|
|
7059 #define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x0090) /*!<PJ[5] pin */
|
|
|
7060 #define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x00A0) /*!<PK[5] pin */
|
|
|
7061
|
|
|
7062 /**
|
|
|
7063 * @brief EXTI6 configuration
|
|
|
7064 */
|
|
|
7065 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */
|
|
|
7066 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */
|
|
|
7067 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */
|
|
|
7068 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x0300) /*!<PD[6] pin */
|
|
|
7069 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x0400) /*!<PE[6] pin */
|
|
|
7070 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x0500) /*!<PF[6] pin */
|
|
|
7071 #define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x0600) /*!<PG[6] pin */
|
|
|
7072 #define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */
|
|
|
7073 #define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x0800) /*!<PI[6] pin */
|
|
|
7074 #define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x0900) /*!<PJ[6] pin */
|
|
|
7075 #define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x0A00) /*!<PK[6] pin */
|
|
|
7076
|
|
|
7077
|
|
|
7078 /**
|
|
|
7079 * @brief EXTI7 configuration
|
|
|
7080 */
|
|
|
7081 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */
|
|
|
7082 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */
|
|
|
7083 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */
|
|
|
7084 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x3000) /*!<PD[7] pin */
|
|
|
7085 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x4000) /*!<PE[7] pin */
|
|
|
7086 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x5000) /*!<PF[7] pin */
|
|
|
7087 #define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x6000) /*!<PG[7] pin */
|
|
|
7088 #define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */
|
|
|
7089 #define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x8000) /*!<PI[7] pin */
|
|
|
7090 #define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x9000) /*!<PJ[7] pin */
|
|
|
7091 #define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0xA000) /*!<PK[7] pin */
|
|
|
7092
|
|
|
7093 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
|
|
|
7094 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */
|
|
|
7095 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
|
|
|
7096 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
|
|
|
7097 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */
|
|
|
7098
|
|
|
7099 /**
|
|
|
7100 * @brief EXTI8 configuration
|
|
|
7101 */
|
|
|
7102 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */
|
|
|
7103 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */
|
|
|
7104 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */
|
|
|
7105 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x0003) /*!<PD[8] pin */
|
|
|
7106 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x0004) /*!<PE[8] pin */
|
|
|
7107 #define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x0005) /*!<PF[8] pin */
|
|
|
7108 #define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x0006) /*!<PG[8] pin */
|
|
|
7109 #define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */
|
|
|
7110 #define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x0008) /*!<PI[8] pin */
|
|
|
7111 #define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x0009) /*!<PJ[8] pin */
|
|
|
7112
|
|
|
7113 /**
|
|
|
7114 * @brief EXTI9 configuration
|
|
|
7115 */
|
|
|
7116 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */
|
|
|
7117 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */
|
|
|
7118 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */
|
|
|
7119 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x0030) /*!<PD[9] pin */
|
|
|
7120 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x0040) /*!<PE[9] pin */
|
|
|
7121 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x0050) /*!<PF[9] pin */
|
|
|
7122 #define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x0060) /*!<PG[9] pin */
|
|
|
7123 #define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */
|
|
|
7124 #define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x0080) /*!<PI[9] pin */
|
|
|
7125 #define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x0090) /*!<PJ[9] pin */
|
|
|
7126
|
|
|
7127
|
|
|
7128 /**
|
|
|
7129 * @brief EXTI10 configuration
|
|
|
7130 */
|
|
|
7131 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */
|
|
|
7132 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */
|
|
|
7133 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */
|
|
|
7134 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x0300) /*!<PD[10] pin */
|
|
|
7135 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x0400) /*!<PE[10] pin */
|
|
|
7136 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x0500) /*!<PF[10] pin */
|
|
|
7137 #define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x0600) /*!<PG[10] pin */
|
|
|
7138 #define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */
|
|
|
7139 #define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x0800) /*!<PI[10] pin */
|
|
|
7140 #define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x0900) /*!<PJ[10] pin */
|
|
|
7141
|
|
|
7142
|
|
|
7143 /**
|
|
|
7144 * @brief EXTI11 configuration
|
|
|
7145 */
|
|
|
7146 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */
|
|
|
7147 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */
|
|
|
7148 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */
|
|
|
7149 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x3000) /*!<PD[11] pin */
|
|
|
7150 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x4000) /*!<PE[11] pin */
|
|
|
7151 #define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x5000) /*!<PF[11] pin */
|
|
|
7152 #define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x6000) /*!<PG[11] pin */
|
|
|
7153 #define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */
|
|
|
7154 #define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x8000) /*!<PI[11] pin */
|
|
|
7155 #define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x9000) /*!<PJ[11] pin */
|
|
|
7156
|
|
|
7157
|
|
|
7158 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
|
|
|
7159 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */
|
|
|
7160 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
|
|
|
7161 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
|
|
|
7162 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */
|
|
|
7163 /**
|
|
|
7164 * @brief EXTI12 configuration
|
|
|
7165 */
|
|
|
7166 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */
|
|
|
7167 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */
|
|
|
7168 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */
|
|
|
7169 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x0003) /*!<PD[12] pin */
|
|
|
7170 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x0004) /*!<PE[12] pin */
|
|
|
7171 #define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x0005) /*!<PF[12] pin */
|
|
|
7172 #define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x0006) /*!<PG[12] pin */
|
|
|
7173 #define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */
|
|
|
7174 #define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x0008) /*!<PI[12] pin */
|
|
|
7175 #define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x0009) /*!<PJ[12] pin */
|
|
|
7176
|
|
|
7177
|
|
|
7178 /**
|
|
|
7179 * @brief EXTI13 configuration
|
|
|
7180 */
|
|
|
7181 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */
|
|
|
7182 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */
|
|
|
7183 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */
|
|
|
7184 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x0030) /*!<PD[13] pin */
|
|
|
7185 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x0040) /*!<PE[13] pin */
|
|
|
7186 #define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x0050) /*!<PF[13] pin */
|
|
|
7187 #define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x0060) /*!<PG[13] pin */
|
|
|
7188 #define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */
|
|
|
7189 #define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x0008) /*!<PI[13] pin */
|
|
|
7190 #define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x0009) /*!<PJ[13] pin */
|
|
|
7191
|
|
|
7192
|
|
|
7193 /**
|
|
|
7194 * @brief EXTI14 configuration
|
|
|
7195 */
|
|
|
7196 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */
|
|
|
7197 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */
|
|
|
7198 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */
|
|
|
7199 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x0300) /*!<PD[14] pin */
|
|
|
7200 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x0400) /*!<PE[14] pin */
|
|
|
7201 #define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x0500) /*!<PF[14] pin */
|
|
|
7202 #define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x0600) /*!<PG[14] pin */
|
|
|
7203 #define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */
|
|
|
7204 #define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x0800) /*!<PI[14] pin */
|
|
|
7205 #define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x0900) /*!<PJ[14] pin */
|
|
|
7206
|
|
|
7207
|
|
|
7208 /**
|
|
|
7209 * @brief EXTI15 configuration
|
|
|
7210 */
|
|
|
7211 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */
|
|
|
7212 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */
|
|
|
7213 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */
|
|
|
7214 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x3000) /*!<PD[15] pin */
|
|
|
7215 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x4000) /*!<PE[15] pin */
|
|
|
7216 #define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x5000) /*!<PF[15] pin */
|
|
|
7217 #define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x6000) /*!<PG[15] pin */
|
|
|
7218 #define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */
|
|
|
7219 #define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x8000) /*!<PI[15] pin */
|
|
|
7220 #define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x9000) /*!<PJ[15] pin */
|
|
|
7221
|
|
|
7222 /****************** Bit definition for SYSCFG_CMPCR register ****************/
|
|
|
7223 #define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
|
|
|
7224 #define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */
|
|
|
7225
|
|
|
7226 /******************************************************************************/
|
|
|
7227 /* */
|
|
|
7228 /* TIM */
|
|
|
7229 /* */
|
|
|
7230 /******************************************************************************/
|
|
|
7231 /******************* Bit definition for TIM_CR1 register ********************/
|
|
|
7232 #define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */
|
|
|
7233 #define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */
|
|
|
7234 #define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */
|
|
|
7235 #define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */
|
|
|
7236 #define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */
|
|
|
7237
|
|
|
7238 #define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
|
|
|
7239 #define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */
|
|
|
7240 #define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */
|
|
|
7241
|
|
|
7242 #define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */
|
|
|
7243
|
|
|
7244 #define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */
|
|
|
7245 #define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */
|
|
|
7246 #define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */
|
|
|
7247
|
|
|
7248 /******************* Bit definition for TIM_CR2 register ********************/
|
|
|
7249 #define TIM_CR2_CCPC ((uint32_t)0x0001) /*!<Capture/Compare Preloaded Control */
|
|
|
7250 #define TIM_CR2_CCUS ((uint32_t)0x0004) /*!<Capture/Compare Control Update Selection */
|
|
|
7251 #define TIM_CR2_CCDS ((uint32_t)0x0008) /*!<Capture/Compare DMA Selection */
|
|
|
7252
|
|
|
7253 #define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
|
|
|
7254 #define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */
|
|
|
7255 #define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */
|
|
|
7256 #define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */
|
|
|
7257
|
|
|
7258 #define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */
|
|
|
7259 #define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
|
|
|
7260 #define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
|
|
|
7261 #define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
|
|
|
7262 #define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
|
|
|
7263 #define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
|
|
|
7264 #define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
|
|
|
7265 #define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
|
|
|
7266
|
|
|
7267 /******************* Bit definition for TIM_SMCR register *******************/
|
|
|
7268 #define TIM_SMCR_SMS ((uint32_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
|
|
|
7269 #define TIM_SMCR_SMS_0 ((uint32_t)0x0001) /*!<Bit 0 */
|
|
|
7270 #define TIM_SMCR_SMS_1 ((uint32_t)0x0002) /*!<Bit 1 */
|
|
|
7271 #define TIM_SMCR_SMS_2 ((uint32_t)0x0004) /*!<Bit 2 */
|
|
|
7272
|
|
|
7273 #define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
|
|
|
7274 #define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */
|
|
|
7275 #define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */
|
|
|
7276 #define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */
|
|
|
7277
|
|
|
7278 #define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */
|
|
|
7279
|
|
|
7280 #define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
|
|
|
7281 #define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */
|
|
|
7282 #define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */
|
|
|
7283 #define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */
|
|
|
7284 #define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */
|
|
|
7285
|
|
|
7286 #define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
|
|
|
7287 #define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */
|
|
|
7288 #define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */
|
|
|
7289
|
|
|
7290 #define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */
|
|
|
7291 #define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */
|
|
|
7292
|
|
|
7293 /******************* Bit definition for TIM_DIER register *******************/
|
|
|
7294 #define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */
|
|
|
7295 #define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
|
|
|
7296 #define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
|
|
|
7297 #define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
|
|
|
7298 #define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
|
|
|
7299 #define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */
|
|
|
7300 #define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */
|
|
|
7301 #define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */
|
|
|
7302 #define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */
|
|
|
7303 #define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
|
|
|
7304 #define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
|
|
|
7305 #define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
|
|
|
7306 #define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
|
|
|
7307 #define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */
|
|
|
7308 #define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */
|
|
|
7309
|
|
|
7310 /******************** Bit definition for TIM_SR register ********************/
|
|
|
7311 #define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */
|
|
|
7312 #define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
|
|
|
7313 #define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
|
|
|
7314 #define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
|
|
|
7315 #define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
|
|
|
7316 #define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */
|
|
|
7317 #define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */
|
|
|
7318 #define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */
|
|
|
7319 #define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
|
|
|
7320 #define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
|
|
|
7321 #define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
|
|
|
7322 #define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
|
|
|
7323
|
|
|
7324 /******************* Bit definition for TIM_EGR register ********************/
|
|
|
7325 #define TIM_EGR_UG ((uint32_t)0x01) /*!<Update Generation */
|
|
|
7326 #define TIM_EGR_CC1G ((uint32_t)0x02) /*!<Capture/Compare 1 Generation */
|
|
|
7327 #define TIM_EGR_CC2G ((uint32_t)0x04) /*!<Capture/Compare 2 Generation */
|
|
|
7328 #define TIM_EGR_CC3G ((uint32_t)0x08) /*!<Capture/Compare 3 Generation */
|
|
|
7329 #define TIM_EGR_CC4G ((uint32_t)0x10) /*!<Capture/Compare 4 Generation */
|
|
|
7330 #define TIM_EGR_COMG ((uint32_t)0x20) /*!<Capture/Compare Control Update Generation */
|
|
|
7331 #define TIM_EGR_TG ((uint32_t)0x40) /*!<Trigger Generation */
|
|
|
7332 #define TIM_EGR_BG ((uint32_t)0x80) /*!<Break Generation */
|
|
|
7333
|
|
|
7334 /****************** Bit definition for TIM_CCMR1 register *******************/
|
|
|
7335 #define TIM_CCMR1_CC1S ((uint32_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
|
|
|
7336 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x0001) /*!<Bit 0 */
|
|
|
7337 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x0002) /*!<Bit 1 */
|
|
|
7338
|
|
|
7339 #define TIM_CCMR1_OC1FE ((uint32_t)0x0004) /*!<Output Compare 1 Fast enable */
|
|
|
7340 #define TIM_CCMR1_OC1PE ((uint32_t)0x0008) /*!<Output Compare 1 Preload enable */
|
|
|
7341
|
|
|
7342 #define TIM_CCMR1_OC1M ((uint32_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
|
|
|
7343 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x0010) /*!<Bit 0 */
|
|
|
7344 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x0020) /*!<Bit 1 */
|
|
|
7345 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x0040) /*!<Bit 2 */
|
|
|
7346
|
|
|
7347 #define TIM_CCMR1_OC1CE ((uint32_t)0x0080) /*!<Output Compare 1Clear Enable */
|
|
|
7348
|
|
|
7349 #define TIM_CCMR1_CC2S ((uint32_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
|
|
|
7350 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x0100) /*!<Bit 0 */
|
|
|
7351 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x0200) /*!<Bit 1 */
|
|
|
7352
|
|
|
7353 #define TIM_CCMR1_OC2FE ((uint32_t)0x0400) /*!<Output Compare 2 Fast enable */
|
|
|
7354 #define TIM_CCMR1_OC2PE ((uint32_t)0x0800) /*!<Output Compare 2 Preload enable */
|
|
|
7355
|
|
|
7356 #define TIM_CCMR1_OC2M ((uint32_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
|
|
|
7357 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x1000) /*!<Bit 0 */
|
|
|
7358 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x2000) /*!<Bit 1 */
|
|
|
7359 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x4000) /*!<Bit 2 */
|
|
|
7360
|
|
|
7361 #define TIM_CCMR1_OC2CE ((uint32_t)0x8000) /*!<Output Compare 2 Clear Enable */
|
|
|
7362
|
|
|
7363 /*----------------------------------------------------------------------------*/
|
|
|
7364
|
|
|
7365 #define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
|
|
|
7366 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
|
|
|
7367 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
|
|
|
7368
|
|
|
7369 #define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
|
|
|
7370 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */
|
|
|
7371 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */
|
|
|
7372 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */
|
|
|
7373 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */
|
|
|
7374
|
|
|
7375 #define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
|
|
|
7376 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
|
|
|
7377 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
|
|
|
7378
|
|
|
7379 #define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
|
|
|
7380 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */
|
|
|
7381 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */
|
|
|
7382 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */
|
|
|
7383 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */
|
|
|
7384
|
|
|
7385 /****************** Bit definition for TIM_CCMR2 register *******************/
|
|
|
7386 #define TIM_CCMR2_CC3S ((uint32_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
|
|
|
7387 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x0001) /*!<Bit 0 */
|
|
|
7388 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x0002) /*!<Bit 1 */
|
|
|
7389
|
|
|
7390 #define TIM_CCMR2_OC3FE ((uint32_t)0x0004) /*!<Output Compare 3 Fast enable */
|
|
|
7391 #define TIM_CCMR2_OC3PE ((uint32_t)0x0008) /*!<Output Compare 3 Preload enable */
|
|
|
7392
|
|
|
7393 #define TIM_CCMR2_OC3M ((uint32_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
|
|
|
7394 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x0010) /*!<Bit 0 */
|
|
|
7395 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x0020) /*!<Bit 1 */
|
|
|
7396 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x0040) /*!<Bit 2 */
|
|
|
7397
|
|
|
7398 #define TIM_CCMR2_OC3CE ((uint32_t)0x0080) /*!<Output Compare 3 Clear Enable */
|
|
|
7399
|
|
|
7400 #define TIM_CCMR2_CC4S ((uint32_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
|
|
|
7401 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x0100) /*!<Bit 0 */
|
|
|
7402 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x0200) /*!<Bit 1 */
|
|
|
7403
|
|
|
7404 #define TIM_CCMR2_OC4FE ((uint32_t)0x0400) /*!<Output Compare 4 Fast enable */
|
|
|
7405 #define TIM_CCMR2_OC4PE ((uint32_t)0x0800) /*!<Output Compare 4 Preload enable */
|
|
|
7406
|
|
|
7407 #define TIM_CCMR2_OC4M ((uint32_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
|
|
7408 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x1000) /*!<Bit 0 */
|
|
|
7409 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x2000) /*!<Bit 1 */
|
|
|
7410 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x4000) /*!<Bit 2 */
|
|
|
7411
|
|
|
7412 #define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */
|
|
|
7413
|
|
|
7414 /*----------------------------------------------------------------------------*/
|
|
|
7415
|
|
|
7416 #define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
|
|
|
7417 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
|
|
|
7418 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
|
|
|
7419
|
|
|
7420 #define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
|
|
|
7421 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */
|
|
|
7422 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */
|
|
|
7423 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */
|
|
|
7424 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */
|
|
|
7425
|
|
|
7426 #define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
|
|
|
7427 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
|
|
|
7428 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
|
|
|
7429
|
|
|
7430 #define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
|
|
|
7431 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */
|
|
|
7432 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */
|
|
|
7433 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */
|
|
|
7434 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */
|
|
|
7435
|
|
|
7436 /******************* Bit definition for TIM_CCER register *******************/
|
|
|
7437 #define TIM_CCER_CC1E ((uint32_t)0x0001) /*!<Capture/Compare 1 output enable */
|
|
|
7438 #define TIM_CCER_CC1P ((uint32_t)0x0002) /*!<Capture/Compare 1 output Polarity */
|
|
|
7439 #define TIM_CCER_CC1NE ((uint32_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
|
|
|
7440 #define TIM_CCER_CC1NP ((uint32_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
|
|
|
7441 #define TIM_CCER_CC2E ((uint32_t)0x0010) /*!<Capture/Compare 2 output enable */
|
|
|
7442 #define TIM_CCER_CC2P ((uint32_t)0x0020) /*!<Capture/Compare 2 output Polarity */
|
|
|
7443 #define TIM_CCER_CC2NE ((uint32_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
|
|
|
7444 #define TIM_CCER_CC2NP ((uint32_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
|
|
|
7445 #define TIM_CCER_CC3E ((uint32_t)0x0100) /*!<Capture/Compare 3 output enable */
|
|
|
7446 #define TIM_CCER_CC3P ((uint32_t)0x0200) /*!<Capture/Compare 3 output Polarity */
|
|
|
7447 #define TIM_CCER_CC3NE ((uint32_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
|
|
|
7448 #define TIM_CCER_CC3NP ((uint32_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
|
|
|
7449 #define TIM_CCER_CC4E ((uint32_t)0x1000) /*!<Capture/Compare 4 output enable */
|
|
|
7450 #define TIM_CCER_CC4P ((uint32_t)0x2000) /*!<Capture/Compare 4 output Polarity */
|
|
|
7451 #define TIM_CCER_CC4NP ((uint32_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
|
|
|
7452
|
|
|
7453 /******************* Bit definition for TIM_CNT register ********************/
|
|
|
7454 #define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */
|
|
|
7455
|
|
|
7456 /******************* Bit definition for TIM_PSC register ********************/
|
|
|
7457 #define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */
|
|
|
7458
|
|
|
7459 /******************* Bit definition for TIM_ARR register ********************/
|
|
|
7460 #define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */
|
|
|
7461
|
|
|
7462 /******************* Bit definition for TIM_RCR register ********************/
|
|
|
7463 #define TIM_RCR_REP ((uint32_t)0xFF) /*!<Repetition Counter Value */
|
|
|
7464
|
|
|
7465 /******************* Bit definition for TIM_CCR1 register *******************/
|
|
|
7466 #define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */
|
|
|
7467
|
|
|
7468 /******************* Bit definition for TIM_CCR2 register *******************/
|
|
|
7469 #define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */
|
|
|
7470
|
|
|
7471 /******************* Bit definition for TIM_CCR3 register *******************/
|
|
|
7472 #define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */
|
|
|
7473
|
|
|
7474 /******************* Bit definition for TIM_CCR4 register *******************/
|
|
|
7475 #define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */
|
|
|
7476
|
|
|
7477 /******************* Bit definition for TIM_BDTR register *******************/
|
|
|
7478 #define TIM_BDTR_DTG ((uint32_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
|
|
|
7479 #define TIM_BDTR_DTG_0 ((uint32_t)0x0001) /*!<Bit 0 */
|
|
|
7480 #define TIM_BDTR_DTG_1 ((uint32_t)0x0002) /*!<Bit 1 */
|
|
|
7481 #define TIM_BDTR_DTG_2 ((uint32_t)0x0004) /*!<Bit 2 */
|
|
|
7482 #define TIM_BDTR_DTG_3 ((uint32_t)0x0008) /*!<Bit 3 */
|
|
|
7483 #define TIM_BDTR_DTG_4 ((uint32_t)0x0010) /*!<Bit 4 */
|
|
|
7484 #define TIM_BDTR_DTG_5 ((uint32_t)0x0020) /*!<Bit 5 */
|
|
|
7485 #define TIM_BDTR_DTG_6 ((uint32_t)0x0040) /*!<Bit 6 */
|
|
|
7486 #define TIM_BDTR_DTG_7 ((uint32_t)0x0080) /*!<Bit 7 */
|
|
|
7487
|
|
|
7488 #define TIM_BDTR_LOCK ((uint32_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
|
|
|
7489 #define TIM_BDTR_LOCK_0 ((uint32_t)0x0100) /*!<Bit 0 */
|
|
|
7490 #define TIM_BDTR_LOCK_1 ((uint32_t)0x0200) /*!<Bit 1 */
|
|
|
7491
|
|
|
7492 #define TIM_BDTR_OSSI ((uint32_t)0x0400) /*!<Off-State Selection for Idle mode */
|
|
|
7493 #define TIM_BDTR_OSSR ((uint32_t)0x0800) /*!<Off-State Selection for Run mode */
|
|
|
7494 #define TIM_BDTR_BKE ((uint32_t)0x1000) /*!<Break enable */
|
|
|
7495 #define TIM_BDTR_BKP ((uint32_t)0x2000) /*!<Break Polarity */
|
|
|
7496 #define TIM_BDTR_AOE ((uint32_t)0x4000) /*!<Automatic Output enable */
|
|
|
7497 #define TIM_BDTR_MOE ((uint32_t)0x8000) /*!<Main Output enable */
|
|
|
7498
|
|
|
7499 /******************* Bit definition for TIM_DCR register ********************/
|
|
|
7500 #define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
|
|
|
7501 #define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */
|
|
|
7502 #define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */
|
|
|
7503 #define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */
|
|
|
7504 #define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */
|
|
|
7505 #define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */
|
|
|
7506
|
|
|
7507 #define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
|
|
|
7508 #define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */
|
|
|
7509 #define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */
|
|
|
7510 #define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */
|
|
|
7511 #define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */
|
|
|
7512 #define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */
|
|
|
7513
|
|
|
7514 /******************* Bit definition for TIM_DMAR register *******************/
|
|
|
7515 #define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */
|
|
|
7516
|
|
|
7517 /******************* Bit definition for TIM_OR register *********************/
|
|
|
7518 #define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
|
|
|
7519 #define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */
|
|
|
7520 #define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */
|
|
|
7521 #define TIM_OR_ITR1_RMP ((uint32_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
|
|
|
7522 #define TIM_OR_ITR1_RMP_0 ((uint32_t)0x0400) /*!<Bit 0 */
|
|
|
7523 #define TIM_OR_ITR1_RMP_1 ((uint32_t)0x0800) /*!<Bit 1 */
|
|
|
7524
|
|
|
7525
|
|
|
7526 /******************************************************************************/
|
|
|
7527 /* */
|
|
|
7528 /* Universal Synchronous Asynchronous Receiver Transmitter */
|
|
|
7529 /* */
|
|
|
7530 /******************************************************************************/
|
|
|
7531 /******************* Bit definition for USART_SR register *******************/
|
|
|
7532 #define USART_SR_PE ((uint32_t)0x0001) /*!<Parity Error */
|
|
|
7533 #define USART_SR_FE ((uint32_t)0x0002) /*!<Framing Error */
|
|
|
7534 #define USART_SR_NE ((uint32_t)0x0004) /*!<Noise Error Flag */
|
|
|
7535 #define USART_SR_ORE ((uint32_t)0x0008) /*!<OverRun Error */
|
|
|
7536 #define USART_SR_IDLE ((uint32_t)0x0010) /*!<IDLE line detected */
|
|
|
7537 #define USART_SR_RXNE ((uint32_t)0x0020) /*!<Read Data Register Not Empty */
|
|
|
7538 #define USART_SR_TC ((uint32_t)0x0040) /*!<Transmission Complete */
|
|
|
7539 #define USART_SR_TXE ((uint32_t)0x0080) /*!<Transmit Data Register Empty */
|
|
|
7540 #define USART_SR_LBD ((uint32_t)0x0100) /*!<LIN Break Detection Flag */
|
|
|
7541 #define USART_SR_CTS ((uint32_t)0x0200) /*!<CTS Flag */
|
|
|
7542
|
|
|
7543 /******************* Bit definition for USART_DR register *******************/
|
|
|
7544 #define USART_DR_DR ((uint32_t)0x01FF) /*!<Data value */
|
|
|
7545
|
|
|
7546 /****************** Bit definition for USART_BRR register *******************/
|
|
|
7547 #define USART_BRR_DIV_Fraction ((uint32_t)0x000F) /*!<Fraction of USARTDIV */
|
|
|
7548 #define USART_BRR_DIV_Mantissa ((uint32_t)0xFFF0) /*!<Mantissa of USARTDIV */
|
|
|
7549
|
|
|
7550 /****************** Bit definition for USART_CR1 register *******************/
|
|
|
7551 #define USART_CR1_SBK ((uint32_t)0x0001) /*!<Send Break */
|
|
|
7552 #define USART_CR1_RWU ((uint32_t)0x0002) /*!<Receiver wakeup */
|
|
|
7553 #define USART_CR1_RE ((uint32_t)0x0004) /*!<Receiver Enable */
|
|
|
7554 #define USART_CR1_TE ((uint32_t)0x0008) /*!<Transmitter Enable */
|
|
|
7555 #define USART_CR1_IDLEIE ((uint32_t)0x0010) /*!<IDLE Interrupt Enable */
|
|
|
7556 #define USART_CR1_RXNEIE ((uint32_t)0x0020) /*!<RXNE Interrupt Enable */
|
|
|
7557 #define USART_CR1_TCIE ((uint32_t)0x0040) /*!<Transmission Complete Interrupt Enable */
|
|
|
7558 #define USART_CR1_TXEIE ((uint32_t)0x0080) /*!<PE Interrupt Enable */
|
|
|
7559 #define USART_CR1_PEIE ((uint32_t)0x0100) /*!<PE Interrupt Enable */
|
|
|
7560 #define USART_CR1_PS ((uint32_t)0x0200) /*!<Parity Selection */
|
|
|
7561 #define USART_CR1_PCE ((uint32_t)0x0400) /*!<Parity Control Enable */
|
|
|
7562 #define USART_CR1_WAKE ((uint32_t)0x0800) /*!<Wakeup method */
|
|
|
7563 #define USART_CR1_M ((uint32_t)0x1000) /*!<Word length */
|
|
|
7564 #define USART_CR1_UE ((uint32_t)0x2000) /*!<USART Enable */
|
|
|
7565 #define USART_CR1_OVER8 ((uint32_t)0x8000) /*!<USART Oversampling by 8 enable */
|
|
|
7566
|
|
|
7567 /****************** Bit definition for USART_CR2 register *******************/
|
|
|
7568 #define USART_CR2_ADD ((uint32_t)0x000F) /*!<Address of the USART node */
|
|
|
7569 #define USART_CR2_LBDL ((uint32_t)0x0020) /*!<LIN Break Detection Length */
|
|
|
7570 #define USART_CR2_LBDIE ((uint32_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
|
|
|
7571 #define USART_CR2_LBCL ((uint32_t)0x0100) /*!<Last Bit Clock pulse */
|
|
|
7572 #define USART_CR2_CPHA ((uint32_t)0x0200) /*!<Clock Phase */
|
|
|
7573 #define USART_CR2_CPOL ((uint32_t)0x0400) /*!<Clock Polarity */
|
|
|
7574 #define USART_CR2_CLKEN ((uint32_t)0x0800) /*!<Clock Enable */
|
|
|
7575
|
|
|
7576 #define USART_CR2_STOP ((uint32_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
|
|
|
7577 #define USART_CR2_STOP_0 ((uint32_t)0x1000) /*!<Bit 0 */
|
|
|
7578 #define USART_CR2_STOP_1 ((uint32_t)0x2000) /*!<Bit 1 */
|
|
|
7579
|
|
|
7580 #define USART_CR2_LINEN ((uint32_t)0x4000) /*!<LIN mode enable */
|
|
|
7581
|
|
|
7582 /****************** Bit definition for USART_CR3 register *******************/
|
|
|
7583 #define USART_CR3_EIE ((uint32_t)0x0001) /*!<Error Interrupt Enable */
|
|
|
7584 #define USART_CR3_IREN ((uint32_t)0x0002) /*!<IrDA mode Enable */
|
|
|
7585 #define USART_CR3_IRLP ((uint32_t)0x0004) /*!<IrDA Low-Power */
|
|
|
7586 #define USART_CR3_HDSEL ((uint32_t)0x0008) /*!<Half-Duplex Selection */
|
|
|
7587 #define USART_CR3_NACK ((uint32_t)0x0010) /*!<Smartcard NACK enable */
|
|
|
7588 #define USART_CR3_SCEN ((uint32_t)0x0020) /*!<Smartcard mode enable */
|
|
|
7589 #define USART_CR3_DMAR ((uint32_t)0x0040) /*!<DMA Enable Receiver */
|
|
|
7590 #define USART_CR3_DMAT ((uint32_t)0x0080) /*!<DMA Enable Transmitter */
|
|
|
7591 #define USART_CR3_RTSE ((uint32_t)0x0100) /*!<RTS Enable */
|
|
|
7592 #define USART_CR3_CTSE ((uint32_t)0x0200) /*!<CTS Enable */
|
|
|
7593 #define USART_CR3_CTSIE ((uint32_t)0x0400) /*!<CTS Interrupt Enable */
|
|
|
7594 #define USART_CR3_ONEBIT ((uint32_t)0x0800) /*!<USART One bit method enable */
|
|
|
7595
|
|
|
7596 /****************** Bit definition for USART_GTPR register ******************/
|
|
|
7597 #define USART_GTPR_PSC ((uint32_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
|
|
|
7598 #define USART_GTPR_PSC_0 ((uint32_t)0x0001) /*!<Bit 0 */
|
|
|
7599 #define USART_GTPR_PSC_1 ((uint32_t)0x0002) /*!<Bit 1 */
|
|
|
7600 #define USART_GTPR_PSC_2 ((uint32_t)0x0004) /*!<Bit 2 */
|
|
|
7601 #define USART_GTPR_PSC_3 ((uint32_t)0x0008) /*!<Bit 3 */
|
|
|
7602 #define USART_GTPR_PSC_4 ((uint32_t)0x0010) /*!<Bit 4 */
|
|
|
7603 #define USART_GTPR_PSC_5 ((uint32_t)0x0020) /*!<Bit 5 */
|
|
|
7604 #define USART_GTPR_PSC_6 ((uint32_t)0x0040) /*!<Bit 6 */
|
|
|
7605 #define USART_GTPR_PSC_7 ((uint32_t)0x0080) /*!<Bit 7 */
|
|
|
7606
|
|
|
7607 #define USART_GTPR_GT ((uint32_t)0xFF00) /*!<Guard time value */
|
|
|
7608
|
|
|
7609 /******************************************************************************/
|
|
|
7610 /* */
|
|
|
7611 /* Window WATCHDOG */
|
|
|
7612 /* */
|
|
|
7613 /******************************************************************************/
|
|
|
7614 /******************* Bit definition for WWDG_CR register ********************/
|
|
|
7615 #define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
|
|
|
7616 #define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
|
|
|
7617 #define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
|
|
|
7618 #define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
|
|
|
7619 #define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
|
|
|
7620 #define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
|
|
|
7621 #define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
|
|
|
7622 #define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
|
|
|
7623
|
|
|
7624 #define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
|
|
|
7625
|
|
|
7626 /******************* Bit definition for WWDG_CFR register *******************/
|
|
|
7627 #define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
|
|
|
7628 #define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
|
|
|
7629 #define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
|
|
|
7630 #define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
|
|
|
7631 #define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
|
|
|
7632 #define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
|
|
|
7633 #define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
|
|
|
7634 #define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
|
|
|
7635
|
|
|
7636 #define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
|
|
|
7637 #define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
|
|
|
7638 #define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
|
|
|
7639
|
|
|
7640 #define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
|
|
|
7641
|
|
|
7642 /******************* Bit definition for WWDG_SR register ********************/
|
|
|
7643 #define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
|
|
|
7644
|
|
|
7645
|
|
|
7646 /******************************************************************************/
|
|
|
7647 /* */
|
|
|
7648 /* DBG */
|
|
|
7649 /* */
|
|
|
7650 /******************************************************************************/
|
|
|
7651 /******************** Bit definition for DBGMCU_IDCODE register *************/
|
|
|
7652 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
|
|
|
7653 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
|
|
|
7654
|
|
|
7655 /******************** Bit definition for DBGMCU_CR register *****************/
|
|
|
7656 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
|
|
|
7657 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
|
|
|
7658 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
|
|
|
7659 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
|
|
|
7660
|
|
|
7661 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
|
|
|
7662 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
|
|
|
7663 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
|
|
|
7664
|
|
|
7665 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
|
|
|
7666 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
|
|
|
7667 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
|
|
|
7668 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
|
|
|
7669 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
|
|
|
7670 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
|
|
|
7671 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
|
|
|
7672 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
|
|
|
7673 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
|
|
|
7674 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
|
|
|
7675 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
|
|
|
7676 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
|
|
|
7677 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
|
|
|
7678 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
|
|
|
7679 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
|
|
|
7680 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
|
|
|
7681 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
|
|
|
7682 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
|
|
|
7683 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
|
|
|
7684 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
|
|
|
7685
|
|
|
7686 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
|
|
|
7687 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
|
|
|
7688 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
|
|
|
7689 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
|
|
|
7690 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
|
|
|
7691 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
|
|
|
7692
|
|
|
7693 /******************************************************************************/
|
|
|
7694 /* */
|
|
|
7695 /* Ethernet MAC Registers bits definitions */
|
|
|
7696 /* */
|
|
|
7697 /******************************************************************************/
|
|
|
7698 /* Bit definition for Ethernet MAC Control Register register */
|
|
|
7699 #define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
|
|
|
7700 #define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
|
|
|
7701 #define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
|
|
|
7702 #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
|
|
|
7703 #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
|
|
|
7704 #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
|
|
|
7705 #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
|
|
|
7706 #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
|
|
|
7707 #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
|
|
|
7708 #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
|
|
|
7709 #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
|
|
|
7710 #define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
|
|
|
7711 #define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
|
|
|
7712 #define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
|
|
|
7713 #define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
|
|
|
7714 #define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
|
|
|
7715 #define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
|
|
|
7716 #define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
|
|
|
7717 #define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
|
|
|
7718 #define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
|
|
|
7719 a transmission attempt during retries after a collision: 0 =< r <2^k */
|
|
|
7720 #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
|
|
|
7721 #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
|
|
|
7722 #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
|
|
|
7723 #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
|
|
|
7724 #define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
|
|
|
7725 #define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
|
|
|
7726 #define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
|
|
|
7727
|
|
|
7728 /* Bit definition for Ethernet MAC Frame Filter Register */
|
|
|
7729 #define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
|
|
|
7730 #define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
|
|
|
7731 #define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
|
|
|
7732 #define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
|
|
|
7733 #define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
|
|
|
7734 #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
|
|
|
7735 #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
|
|
|
7736 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
|
|
|
7737 #define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
|
|
|
7738 #define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
|
|
|
7739 #define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
|
|
|
7740 #define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
|
|
|
7741 #define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
|
|
|
7742 #define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
|
|
|
7743
|
|
|
7744 /* Bit definition for Ethernet MAC Hash Table High Register */
|
|
|
7745 #define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
|
|
|
7746
|
|
|
7747 /* Bit definition for Ethernet MAC Hash Table Low Register */
|
|
|
7748 #define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
|
|
|
7749
|
|
|
7750 /* Bit definition for Ethernet MAC MII Address Register */
|
|
|
7751 #define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
|
|
|
7752 #define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
|
|
|
7753 #define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
|
|
|
7754 #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
|
|
|
7755 #define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
|
|
|
7756 #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
|
|
|
7757 #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
|
|
|
7758 #define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
|
|
|
7759 #define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
|
|
|
7760 #define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
|
|
|
7761
|
|
|
7762 /* Bit definition for Ethernet MAC MII Data Register */
|
|
|
7763 #define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
|
|
|
7764
|
|
|
7765 /* Bit definition for Ethernet MAC Flow Control Register */
|
|
|
7766 #define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
|
|
|
7767 #define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
|
|
|
7768 #define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
|
|
|
7769 #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
|
|
|
7770 #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
|
|
|
7771 #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
|
|
|
7772 #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
|
|
|
7773 #define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
|
|
|
7774 #define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
|
|
|
7775 #define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
|
|
|
7776 #define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
|
|
|
7777
|
|
|
7778 /* Bit definition for Ethernet MAC VLAN Tag Register */
|
|
|
7779 #define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
|
|
|
7780 #define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
|
|
|
7781
|
|
|
7782 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
|
|
|
7783 #define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
|
|
|
7784 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
|
|
|
7785 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
|
|
|
7786 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
|
|
|
7787 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
|
|
|
7788 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
|
|
|
7789 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
|
|
|
7790 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
|
|
|
7791 RSVD - Filter1 Command - RSVD - Filter0 Command
|
|
|
7792 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
|
|
|
7793 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
|
|
|
7794 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
|
|
|
7795
|
|
|
7796 /* Bit definition for Ethernet MAC PMT Control and Status Register */
|
|
|
7797 #define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
|
|
|
7798 #define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
|
|
|
7799 #define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
|
|
|
7800 #define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
|
|
|
7801 #define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
|
|
|
7802 #define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
|
|
|
7803 #define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
|
|
|
7804
|
|
|
7805 /* Bit definition for Ethernet MAC Status Register */
|
|
|
7806 #define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
|
|
|
7807 #define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
|
|
|
7808 #define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
|
|
|
7809 #define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
|
|
|
7810 #define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
|
|
|
7811
|
|
|
7812 /* Bit definition for Ethernet MAC Interrupt Mask Register */
|
|
|
7813 #define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
|
|
|
7814 #define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
|
|
|
7815
|
|
|
7816 /* Bit definition for Ethernet MAC Address0 High Register */
|
|
|
7817 #define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
|
|
|
7818
|
|
|
7819 /* Bit definition for Ethernet MAC Address0 Low Register */
|
|
|
7820 #define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
|
|
|
7821
|
|
|
7822 /* Bit definition for Ethernet MAC Address1 High Register */
|
|
|
7823 #define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
|
|
|
7824 #define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
|
|
|
7825 #define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
|
|
|
7826 #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
|
|
|
7827 #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
|
|
|
7828 #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
|
|
|
7829 #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
|
|
|
7830 #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
|
|
|
7831 #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
|
|
|
7832 #define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
|
|
|
7833
|
|
|
7834 /* Bit definition for Ethernet MAC Address1 Low Register */
|
|
|
7835 #define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
|
|
|
7836
|
|
|
7837 /* Bit definition for Ethernet MAC Address2 High Register */
|
|
|
7838 #define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
|
|
|
7839 #define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
|
|
|
7840 #define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
|
|
|
7841 #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
|
|
|
7842 #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
|
|
|
7843 #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
|
|
|
7844 #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
|
|
|
7845 #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
|
|
|
7846 #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
|
|
|
7847 #define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
|
|
|
7848
|
|
|
7849 /* Bit definition for Ethernet MAC Address2 Low Register */
|
|
|
7850 #define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
|
|
|
7851
|
|
|
7852 /* Bit definition for Ethernet MAC Address3 High Register */
|
|
|
7853 #define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
|
|
|
7854 #define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
|
|
|
7855 #define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
|
|
|
7856 #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
|
|
|
7857 #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
|
|
|
7858 #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
|
|
|
7859 #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
|
|
|
7860 #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
|
|
|
7861 #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
|
|
|
7862 #define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
|
|
|
7863
|
|
|
7864 /* Bit definition for Ethernet MAC Address3 Low Register */
|
|
|
7865 #define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
|
|
|
7866
|
|
|
7867 /******************************************************************************/
|
|
|
7868 /* Ethernet MMC Registers bits definition */
|
|
|
7869 /******************************************************************************/
|
|
|
7870
|
|
|
7871 /* Bit definition for Ethernet MMC Contol Register */
|
|
|
7872 #define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */
|
|
|
7873 #define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */
|
|
|
7874 #define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
|
|
|
7875 #define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
|
|
|
7876 #define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
|
|
|
7877 #define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
|
|
|
7878
|
|
|
7879 /* Bit definition for Ethernet MMC Receive Interrupt Register */
|
|
|
7880 #define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
|
|
|
7881 #define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
|
|
|
7882 #define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
|
|
|
7883
|
|
|
7884 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
|
|
|
7885 #define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
|
|
|
7886 #define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
|
|
|
7887 #define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
|
|
|
7888
|
|
|
7889 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
|
|
|
7890 #define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
|
|
|
7891 #define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
|
|
|
7892 #define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
|
|
|
7893
|
|
|
7894 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
|
|
|
7895 #define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
|
|
|
7896 #define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
|
|
|
7897 #define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
|
|
|
7898
|
|
|
7899 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
|
|
|
7900 #define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
|
|
|
7901
|
|
|
7902 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
|
|
|
7903 #define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
|
|
|
7904
|
|
|
7905 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
|
|
|
7906 #define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
|
|
|
7907
|
|
|
7908 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
|
|
|
7909 #define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
|
|
|
7910
|
|
|
7911 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
|
|
|
7912 #define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
|
|
|
7913
|
|
|
7914 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
|
|
|
7915 #define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
|
|
|
7916
|
|
|
7917 /******************************************************************************/
|
|
|
7918 /* Ethernet PTP Registers bits definition */
|
|
|
7919 /******************************************************************************/
|
|
|
7920
|
|
|
7921 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
|
|
|
7922 #define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */
|
|
|
7923 #define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */
|
|
|
7924 #define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */
|
|
|
7925 #define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */
|
|
|
7926 #define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */
|
|
|
7927 #define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */
|
|
|
7928 #define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */
|
|
|
7929 #define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */
|
|
|
7930 #define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */
|
|
|
7931
|
|
|
7932 #define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
|
|
|
7933 #define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
|
|
|
7934 #define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
|
|
|
7935 #define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
|
|
|
7936 #define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
|
|
|
7937 #define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
|
|
|
7938
|
|
|
7939 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
|
|
|
7940 #define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
|
|
|
7941
|
|
|
7942 /* Bit definition for Ethernet PTP Time Stamp High Register */
|
|
|
7943 #define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
|
|
|
7944
|
|
|
7945 /* Bit definition for Ethernet PTP Time Stamp Low Register */
|
|
|
7946 #define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
|
|
|
7947 #define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
|
|
|
7948
|
|
|
7949 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
|
|
|
7950 #define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
|
|
|
7951
|
|
|
7952 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
|
|
|
7953 #define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
|
|
|
7954 #define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
|
|
|
7955
|
|
|
7956 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
|
|
|
7957 #define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
|
|
|
7958
|
|
|
7959 /* Bit definition for Ethernet PTP Target Time High Register */
|
|
|
7960 #define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
|
|
|
7961
|
|
|
7962 /* Bit definition for Ethernet PTP Target Time Low Register */
|
|
|
7963 #define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
|
|
|
7964
|
|
|
7965 /* Bit definition for Ethernet PTP Time Stamp Status Register */
|
|
|
7966 #define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */
|
|
|
7967 #define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */
|
|
|
7968
|
|
|
7969 /******************************************************************************/
|
|
|
7970 /* Ethernet DMA Registers bits definition */
|
|
|
7971 /******************************************************************************/
|
|
|
7972
|
|
|
7973 /* Bit definition for Ethernet DMA Bus Mode Register */
|
|
|
7974 #define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
|
|
|
7975 #define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
|
|
|
7976 #define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
|
|
|
7977 #define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
|
|
|
7978 #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
|
|
|
7979 #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
|
|
|
7980 #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
|
|
|
7981 #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
|
|
|
7982 #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
|
|
|
7983 #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
|
|
|
7984 #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
|
|
|
7985 #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
|
|
|
7986 #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
|
|
|
7987 #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
|
|
|
7988 #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
|
|
|
7989 #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
|
|
|
7990 #define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
|
|
|
7991 #define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
|
|
|
7992 #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
|
|
|
7993 #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
|
|
|
7994 #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
|
|
|
7995 #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
|
|
|
7996 #define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
|
|
|
7997 #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
|
|
|
7998 #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
|
|
|
7999 #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
|
|
|
8000 #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
|
|
|
8001 #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
|
|
|
8002 #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
|
|
|
8003 #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
|
|
|
8004 #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
|
|
|
8005 #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
|
|
|
8006 #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
|
|
|
8007 #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
|
|
|
8008 #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
|
|
|
8009 #define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */
|
|
|
8010 #define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
|
|
|
8011 #define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
|
|
|
8012 #define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
|
|
|
8013
|
|
|
8014 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
|
|
|
8015 #define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
|
|
|
8016
|
|
|
8017 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
|
|
|
8018 #define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
|
|
|
8019
|
|
|
8020 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
|
|
|
8021 #define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
|
|
|
8022
|
|
|
8023 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
|
|
|
8024 #define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
|
|
|
8025
|
|
|
8026 /* Bit definition for Ethernet DMA Status Register */
|
|
|
8027 #define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
|
|
|
8028 #define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
|
|
|
8029 #define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
|
|
|
8030 #define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
|
|
|
8031 /* combination with EBS[2:0] for GetFlagStatus function */
|
|
|
8032 #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
|
|
|
8033 #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
|
|
|
8034 #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
|
|
|
8035 #define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
|
|
|
8036 #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
|
|
|
8037 #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
|
|
|
8038 #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
|
|
|
8039 #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
|
|
|
8040 #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
|
|
|
8041 #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
|
|
|
8042 #define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
|
|
|
8043 #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
|
|
|
8044 #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
|
|
|
8045 #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
|
|
|
8046 #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
|
|
|
8047 #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
|
|
|
8048 #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
|
|
|
8049 #define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
|
|
|
8050 #define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
|
|
|
8051 #define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
|
|
|
8052 #define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
|
|
|
8053 #define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
|
|
|
8054 #define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
|
|
|
8055 #define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
|
|
|
8056 #define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
|
|
|
8057 #define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
|
|
|
8058 #define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
|
|
|
8059 #define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
|
|
|
8060 #define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
|
|
|
8061 #define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
|
|
|
8062 #define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
|
|
|
8063 #define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
|
|
|
8064
|
|
|
8065 /* Bit definition for Ethernet DMA Operation Mode Register */
|
|
|
8066 #define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
|
|
|
8067 #define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
|
|
|
8068 #define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
|
|
|
8069 #define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
|
|
|
8070 #define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
|
|
|
8071 #define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
|
|
|
8072 #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
|
|
|
8073 #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
|
|
|
8074 #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
|
|
|
8075 #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
|
|
|
8076 #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
|
|
|
8077 #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
|
|
|
8078 #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
|
|
|
8079 #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
|
|
|
8080 #define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
|
|
|
8081 #define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
|
|
|
8082 #define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
|
|
|
8083 #define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
|
|
|
8084 #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
|
|
|
8085 #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
|
|
|
8086 #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
|
|
|
8087 #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
|
|
|
8088 #define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
|
|
|
8089 #define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
|
|
|
8090
|
|
|
8091 /* Bit definition for Ethernet DMA Interrupt Enable Register */
|
|
|
8092 #define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
|
|
|
8093 #define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
|
|
|
8094 #define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
|
|
|
8095 #define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
|
|
|
8096 #define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
|
|
|
8097 #define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
|
|
|
8098 #define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
|
|
|
8099 #define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
|
|
|
8100 #define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
|
|
|
8101 #define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
|
|
|
8102 #define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
|
|
|
8103 #define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
|
|
|
8104 #define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
|
|
|
8105 #define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
|
|
|
8106 #define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
|
|
|
8107
|
|
|
8108 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
|
|
|
8109 #define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
|
|
|
8110 #define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
|
|
|
8111 #define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
|
|
|
8112 #define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
|
|
|
8113
|
|
|
8114 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
|
|
|
8115 #define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
|
|
|
8116
|
|
|
8117 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
|
|
|
8118 #define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
|
|
|
8119
|
|
|
8120 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
|
|
|
8121 #define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
|
|
|
8122
|
|
|
8123 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
|
|
|
8124 #define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
|
|
|
8125
|
|
|
8126 /******************************************************************************/
|
|
|
8127 /* */
|
|
|
8128 /* USB_OTG */
|
|
|
8129 /* */
|
|
|
8130 /******************************************************************************/
|
|
|
8131 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
|
|
|
8132 #define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */
|
|
|
8133 #define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */
|
|
|
8134 #define USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) /*!< Host negotiation success */
|
|
|
8135 #define USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) /*!< HNP request */
|
|
|
8136 #define USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) /*!< Host set HNP enable */
|
|
|
8137 #define USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) /*!< Device HNP enabled */
|
|
|
8138 #define USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) /*!< Connector ID status */
|
|
|
8139 #define USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) /*!< Long/short debounce time */
|
|
|
8140 #define USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) /*!< A-session valid */
|
|
|
8141 #define USB_OTG_GOTGCTL_BSVLD ((uint32_t)0x00080000) /*!< B-session valid */
|
|
|
8142
|
|
|
8143 /******************** Bit definition forUSB_OTG_HCFG register ********************/
|
|
|
8144
|
|
|
8145 #define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */
|
|
|
8146 #define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
8147 #define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
8148 #define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /*!< FS- and LS-only support */
|
|
|
8149
|
|
|
8150 /******************** Bit definition forUSB_OTG_DCFG register ********************/
|
|
|
8151
|
|
|
8152 #define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /*!< Device speed */
|
|
|
8153 #define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
8154 #define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
8155 #define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /*!< Nonzero-length status OUT handshake */
|
|
|
8156
|
|
|
8157 #define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /*!< Device address */
|
|
|
8158 #define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
8159 #define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
8160 #define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
|
|
8161 #define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
|
|
|
8162 #define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /*!<Bit 4 */
|
|
|
8163 #define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /*!<Bit 5 */
|
|
|
8164 #define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /*!<Bit 6 */
|
|
|
8165
|
|
|
8166 #define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /*!< Periodic (micro)frame interval */
|
|
|
8167 #define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /*!<Bit 0 */
|
|
|
8168 #define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /*!<Bit 1 */
|
|
|
8169
|
|
|
8170 #define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /*!< Periodic scheduling interval */
|
|
|
8171 #define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
8172 #define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
8173
|
|
|
8174 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
|
|
|
8175 #define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /*!< Stop PHY clock */
|
|
|
8176 #define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /*!< Gate HCLK */
|
|
|
8177 #define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /*!< PHY suspended */
|
|
|
8178
|
|
|
8179 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
|
|
|
8180 #define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /*!< Session end detected */
|
|
|
8181 #define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /*!< Session request success status change */
|
|
|
8182 #define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /*!< Host negotiation success status change */
|
|
|
8183 #define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /*!< Host negotiation detected */
|
|
|
8184 #define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /*!< A-device timeout change */
|
|
|
8185 #define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /*!< Debounce done */
|
|
|
8186
|
|
|
8187 /******************** Bit definition forUSB_OTG_DCTL register ********************/
|
|
|
8188 #define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /*!< Remote wakeup signaling */
|
|
|
8189 #define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /*!< Soft disconnect */
|
|
|
8190 #define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /*!< Global IN NAK status */
|
|
|
8191 #define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /*!< Global OUT NAK status */
|
|
|
8192
|
|
|
8193 #define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /*!< Test control */
|
|
|
8194 #define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
8195 #define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
8196 #define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
|
|
8197 #define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /*!< Set global IN NAK */
|
|
|
8198 #define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /*!< Clear global IN NAK */
|
|
|
8199 #define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /*!< Set global OUT NAK */
|
|
|
8200 #define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /*!< Clear global OUT NAK */
|
|
|
8201 #define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /*!< Power-on programming done */
|
|
|
8202
|
|
|
8203 /******************** Bit definition forUSB_OTG_HFIR register ********************/
|
|
|
8204 #define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /*!< Frame interval */
|
|
|
8205
|
|
|
8206 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
|
|
|
8207 #define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /*!< Frame number */
|
|
|
8208 #define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /*!< Frame time remaining */
|
|
|
8209
|
|
|
8210 /******************** Bit definition forUSB_OTG_DSTS register ********************/
|
|
|
8211 #define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /*!< Suspend status */
|
|
|
8212
|
|
|
8213 #define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /*!< Enumerated speed */
|
|
|
8214 #define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /*!<Bit 0 */
|
|
|
8215 #define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /*!<Bit 1 */
|
|
|
8216 #define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /*!< Erratic error */
|
|
|
8217 #define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /*!< Frame number of the received SOF */
|
|
|
8218
|
|
|
8219 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
|
|
|
8220 #define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /*!< Global interrupt mask */
|
|
|
8221
|
|
|
8222 #define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /*!< Burst length/type */
|
|
|
8223 #define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
|
|
|
8224 #define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
|
|
|
8225 #define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /*!<Bit 2 */
|
|
|
8226 #define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /*!<Bit 3 */
|
|
|
8227 #define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /*!< DMA enable */
|
|
|
8228 #define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /*!< TxFIFO empty level */
|
|
|
8229 #define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /*!< Periodic TxFIFO empty level */
|
|
|
8230
|
|
|
8231 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
|
|
|
8232
|
|
|
8233 #define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /*!< FS timeout calibration */
|
|
|
8234 #define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
8235 #define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
8236 #define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
8237 #define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
|
|
|
8238 #define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /*!< SRP-capable */
|
|
|
8239 #define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /*!< HNP-capable */
|
|
|
8240
|
|
|
8241 #define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /*!< USB turnaround time */
|
|
|
8242 #define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /*!<Bit 0 */
|
|
|
8243 #define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /*!<Bit 1 */
|
|
|
8244 #define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /*!<Bit 2 */
|
|
|
8245 #define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /*!<Bit 3 */
|
|
|
8246 #define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /*!< PHY Low-power clock select */
|
|
|
8247 #define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /*!< ULPI FS/LS select */
|
|
|
8248 #define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /*!< ULPI Auto-resume */
|
|
|
8249 #define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /*!< ULPI Clock SuspendM */
|
|
|
8250 #define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /*!< ULPI External VBUS Drive */
|
|
|
8251 #define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /*!< ULPI external VBUS indicator */
|
|
|
8252 #define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /*!< TermSel DLine pulsing selection */
|
|
|
8253 #define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /*!< Indicator complement */
|
|
|
8254 #define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /*!< Indicator pass through */
|
|
|
8255 #define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /*!< ULPI interface protect disable */
|
|
|
8256 #define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /*!< Forced host mode */
|
|
|
8257 #define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /*!< Forced peripheral mode */
|
|
|
8258 #define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /*!< Corrupt Tx packet */
|
|
|
8259
|
|
|
8260 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
|
|
|
8261 #define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /*!< Core soft reset */
|
|
|
8262 #define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /*!< HCLK soft reset */
|
|
|
8263 #define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /*!< Host frame counter reset */
|
|
|
8264 #define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /*!< RxFIFO flush */
|
|
|
8265 #define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /*!< TxFIFO flush */
|
|
|
8266
|
|
|
8267 #define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /*!< TxFIFO number */
|
|
|
8268 #define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /*!<Bit 0 */
|
|
|
8269 #define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /*!<Bit 1 */
|
|
|
8270 #define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /*!<Bit 2 */
|
|
|
8271 #define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /*!<Bit 3 */
|
|
|
8272 #define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /*!<Bit 4 */
|
|
|
8273 #define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /*!< DMA request signal */
|
|
|
8274 #define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /*!< AHB master idle */
|
|
|
8275
|
|
|
8276 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
|
|
|
8277 #define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
|
|
|
8278 #define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
|
|
|
8279 #define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
|
|
|
8280 #define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
|
|
|
8281 #define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
|
|
|
8282 #define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
|
|
|
8283 #define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
|
|
|
8284 #define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
|
|
|
8285
|
|
|
8286 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
|
|
|
8287 #define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /*!< Periodic transmit data FIFO space available */
|
|
|
8288
|
|
|
8289 #define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /*!< Periodic transmit request queue space available */
|
|
|
8290 #define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
8291 #define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
8292 #define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
|
|
8293 #define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
|
|
8294 #define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
|
|
|
8295 #define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
|
|
|
8296 #define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
|
|
|
8297 #define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
|
|
|
8298
|
|
|
8299 #define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /*!< Top of the periodic transmit request queue */
|
|
|
8300 #define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
8301 #define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
8302 #define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
8303 #define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
|
|
8304 #define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
|
|
|
8305 #define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
|
|
|
8306 #define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
|
|
|
8307 #define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /*!<Bit 7 */
|
|
|
8308
|
|
|
8309 /******************** Bit definition forUSB_OTG_HAINT register ********************/
|
|
|
8310 #define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /*!< Channel interrupts */
|
|
|
8311
|
|
|
8312 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
|
|
|
8313 #define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
|
|
|
8314 #define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
|
|
|
8315 #define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */
|
|
|
8316 #define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled mask */
|
|
|
8317 #define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received mask */
|
|
|
8318 #define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */
|
|
|
8319 #define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
|
|
|
8320
|
|
|
8321 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
|
|
|
8322 #define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /*!< Current mode of operation */
|
|
|
8323 #define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /*!< Mode mismatch interrupt */
|
|
|
8324 #define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt */
|
|
|
8325 #define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /*!< Start of frame */
|
|
|
8326 #define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /*!< RxFIFO nonempty */
|
|
|
8327 #define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty */
|
|
|
8328 #define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /*!< Global IN nonperiodic NAK effective */
|
|
|
8329 #define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /*!< Global OUT NAK effective */
|
|
|
8330 #define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /*!< Early suspend */
|
|
|
8331 #define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /*!< USB suspend */
|
|
|
8332 #define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /*!< USB reset */
|
|
|
8333 #define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /*!< Enumeration done */
|
|
|
8334 #define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt */
|
|
|
8335 #define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /*!< End of periodic frame interrupt */
|
|
|
8336 #define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /*!< IN endpoint interrupt */
|
|
|
8337 #define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoint interrupt */
|
|
|
8338 #define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer */
|
|
|
8339 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /*!< Incomplete periodic transfer */
|
|
|
8340 #define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /*!< Data fetch suspended */
|
|
|
8341 #define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /*!< Host port interrupt */
|
|
|
8342 #define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /*!< Host channels interrupt */
|
|
|
8343 #define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty */
|
|
|
8344 #define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /*!< Connector ID status change */
|
|
|
8345 #define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt */
|
|
|
8346 #define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt */
|
|
|
8347 #define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt */
|
|
|
8348
|
|
|
8349 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
|
|
|
8350 #define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /*!< Mode mismatch interrupt mask */
|
|
|
8351 #define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt mask */
|
|
|
8352 #define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /*!< Start of frame mask */
|
|
|
8353 #define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /*!< Receive FIFO nonempty mask */
|
|
|
8354 #define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty mask */
|
|
|
8355 #define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /*!< Global nonperiodic IN NAK effective mask */
|
|
|
8356 #define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /*!< Global OUT NAK effective mask */
|
|
|
8357 #define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /*!< Early suspend mask */
|
|
|
8358 #define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /*!< USB suspend mask */
|
|
|
8359 #define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /*!< USB reset mask */
|
|
|
8360 #define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /*!< Enumeration done mask */
|
|
|
8361 #define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt mask */
|
|
|
8362 #define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /*!< End of periodic frame interrupt mask */
|
|
|
8363 #define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /*!< Endpoint mismatch interrupt mask */
|
|
|
8364 #define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /*!< IN endpoints interrupt mask */
|
|
|
8365 #define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoints interrupt mask */
|
|
|
8366 #define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer mask */
|
|
|
8367 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /*!< Incomplete periodic transfer mask */
|
|
|
8368 #define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /*!< Data fetch suspended mask */
|
|
|
8369 #define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /*!< Host port interrupt mask */
|
|
|
8370 #define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /*!< Host channels interrupt mask */
|
|
|
8371 #define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty mask */
|
|
|
8372 #define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /*!< Connector ID status change mask */
|
|
|
8373 #define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt mask */
|
|
|
8374 #define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt mask */
|
|
|
8375 #define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt mask */
|
|
|
8376
|
|
|
8377 /******************** Bit definition forUSB_OTG_DAINT register ********************/
|
|
|
8378 #define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /*!< IN endpoint interrupt bits */
|
|
|
8379 #define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /*!< OUT endpoint interrupt bits */
|
|
|
8380
|
|
|
8381 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
|
|
|
8382 #define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /*!< Channel interrupt mask */
|
|
|
8383
|
|
|
8384 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
|
|
|
8385 #define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /*!< IN EP interrupt mask bits */
|
|
|
8386 #define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< OUT EP interrupt mask bits */
|
|
|
8387 #define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< OUT EP interrupt mask bits */
|
|
|
8388 #define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< OUT EP interrupt mask bits */
|
|
|
8389
|
|
|
8390 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
|
|
|
8391 #define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /*!< IN EP interrupt mask bits */
|
|
|
8392 #define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /*!< OUT EP interrupt mask bits */
|
|
|
8393
|
|
|
8394 /******************** Bit definition for OTG register ********************/
|
|
|
8395
|
|
|
8396 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
|
|
|
8397 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
8398 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
8399 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
8400 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
8401 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
|
|
|
8402
|
|
|
8403 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
|
|
|
8404 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
|
|
|
8405 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
|
|
|
8406
|
|
|
8407 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
|
|
|
8408 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
|
|
|
8409 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
|
|
|
8410 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
|
|
|
8411 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
|
|
|
8412
|
|
|
8413 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
|
|
|
8414 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
8415 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
8416 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
8417 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
8418
|
|
|
8419 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
|
|
|
8420 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
|
|
|
8421 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
|
|
|
8422 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
|
|
|
8423 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
|
|
|
8424
|
|
|
8425 /******************** Bit definition for OTG register ********************/
|
|
|
8426
|
|
|
8427 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
|
|
|
8428 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
8429 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
8430 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
8431 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
8432 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
|
|
|
8433
|
|
|
8434 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
|
|
|
8435 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
|
|
|
8436 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
|
|
|
8437
|
|
|
8438 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
|
|
|
8439 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
|
|
|
8440 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
|
|
|
8441 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
|
|
|
8442 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
|
|
|
8443
|
|
|
8444 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
|
|
|
8445 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
8446 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
8447 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
8448 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
8449
|
|
|
8450 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
|
|
|
8451 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
|
|
|
8452 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
|
|
|
8453 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
|
|
|
8454 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
|
|
|
8455
|
|
|
8456 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
|
|
|
8457 #define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /*!< RxFIFO depth */
|
|
|
8458
|
|
|
8459 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
|
|
|
8460 #define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /*!< Device VBUS discharge time */
|
|
|
8461
|
|
|
8462 /******************** Bit definition for OTG register ********************/
|
|
|
8463 #define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /*!< Nonperiodic transmit RAM start address */
|
|
|
8464 #define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /*!< Nonperiodic TxFIFO depth */
|
|
|
8465 #define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /*!< Endpoint 0 transmit RAM start address */
|
|
|
8466 #define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /*!< Endpoint 0 TxFIFO depth */
|
|
|
8467
|
|
|
8468 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
|
|
|
8469 #define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /*!< Device VBUS pulsing time */
|
|
|
8470
|
|
|
8471 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
|
|
|
8472 #define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /*!< Nonperiodic TxFIFO space available */
|
|
|
8473
|
|
|
8474 #define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /*!< Nonperiodic transmit request queue space available */
|
|
|
8475 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
8476 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
8477 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
|
|
8478 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
|
|
8479 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
|
|
|
8480 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
|
|
|
8481 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
|
|
|
8482 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
|
|
|
8483
|
|
|
8484 #define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /*!< Top of the nonperiodic transmit request queue */
|
|
|
8485 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
8486 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
8487 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
8488 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
|
|
8489 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
|
|
|
8490 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
|
|
|
8491 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
|
|
|
8492
|
|
|
8493 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
|
|
|
8494 #define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /*!< Nonisochronous IN endpoints threshold enable */
|
|
|
8495 #define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /*!< ISO IN endpoint threshold enable */
|
|
|
8496
|
|
|
8497 #define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /*!< Transmit threshold length */
|
|
|
8498 #define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /*!<Bit 0 */
|
|
|
8499 #define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /*!<Bit 1 */
|
|
|
8500 #define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /*!<Bit 2 */
|
|
|
8501 #define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /*!<Bit 3 */
|
|
|
8502 #define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /*!<Bit 4 */
|
|
|
8503 #define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /*!<Bit 5 */
|
|
|
8504 #define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /*!<Bit 6 */
|
|
|
8505 #define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /*!<Bit 7 */
|
|
|
8506 #define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /*!<Bit 8 */
|
|
|
8507 #define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /*!< Receive threshold enable */
|
|
|
8508
|
|
|
8509 #define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /*!< Receive threshold length */
|
|
|
8510 #define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /*!<Bit 0 */
|
|
|
8511 #define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /*!<Bit 1 */
|
|
|
8512 #define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /*!<Bit 2 */
|
|
|
8513 #define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /*!<Bit 3 */
|
|
|
8514 #define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /*!<Bit 4 */
|
|
|
8515 #define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /*!<Bit 5 */
|
|
|
8516 #define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /*!<Bit 6 */
|
|
|
8517 #define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /*!<Bit 7 */
|
|
|
8518 #define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /*!<Bit 8 */
|
|
|
8519 #define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /*!< Arbiter parking enable */
|
|
|
8520
|
|
|
8521 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
|
|
|
8522 #define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /*!< IN EP Tx FIFO empty interrupt mask bits */
|
|
|
8523
|
|
|
8524 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
|
|
|
8525 #define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /*!< IN endpoint 1interrupt bit */
|
|
|
8526 #define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /*!< OUT endpoint 1 interrupt bit */
|
|
|
8527
|
|
|
8528 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
|
|
|
8529 #define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /*!< Power down */
|
|
|
8530 #define USB_OTG_GCCFG_I2CPADEN ((uint32_t)0x00020000) /*!< Enable I2C bus connection for the external I2C PHY interface */
|
|
|
8531 #define USB_OTG_GCCFG_VBUSASEN ((uint32_t)0x00040000) /*!< Enable the VBUS sensing device */
|
|
|
8532 #define USB_OTG_GCCFG_VBUSBSEN ((uint32_t)0x00080000) /*!< Enable the VBUS sensing device */
|
|
|
8533 #define USB_OTG_GCCFG_SOFOUTEN ((uint32_t)0x00100000) /*!< SOF output enable */
|
|
|
8534 #define USB_OTG_GCCFG_NOVBUSSENS ((uint32_t)0x00200000) /*!< VBUS sensing disable option */
|
|
|
8535
|
|
|
8536 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
|
|
|
8537 #define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /*!< IN Endpoint 1 interrupt mask bit */
|
|
|
8538 #define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /*!< OUT Endpoint 1 interrupt mask bit */
|
|
|
8539
|
|
|
8540 /******************** Bit definition forUSB_OTG_CID register ********************/
|
|
|
8541 #define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /*!< Product ID field */
|
|
|
8542
|
|
|
8543 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
|
|
|
8544 #define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
|
|
|
8545 #define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
|
|
|
8546 #define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
|
|
|
8547 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
|
|
|
8548 #define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
|
|
|
8549 #define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
|
|
|
8550 #define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
|
|
|
8551 #define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
|
|
|
8552 #define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
|
|
|
8553
|
|
|
8554 /******************** Bit definition forUSB_OTG_HPRT register ********************/
|
|
|
8555 #define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /*!< Port connect status */
|
|
|
8556 #define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /*!< Port connect detected */
|
|
|
8557 #define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /*!< Port enable */
|
|
|
8558 #define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /*!< Port enable/disable change */
|
|
|
8559 #define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /*!< Port overcurrent active */
|
|
|
8560 #define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /*!< Port overcurrent change */
|
|
|
8561 #define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /*!< Port resume */
|
|
|
8562 #define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /*!< Port suspend */
|
|
|
8563 #define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /*!< Port reset */
|
|
|
8564
|
|
|
8565 #define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /*!< Port line status */
|
|
|
8566 #define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /*!<Bit 0 */
|
|
|
8567 #define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /*!<Bit 1 */
|
|
|
8568 #define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /*!< Port power */
|
|
|
8569
|
|
|
8570 #define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /*!< Port test control */
|
|
|
8571 #define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /*!<Bit 0 */
|
|
|
8572 #define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /*!<Bit 1 */
|
|
|
8573 #define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /*!<Bit 2 */
|
|
|
8574 #define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /*!<Bit 3 */
|
|
|
8575
|
|
|
8576 #define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /*!< Port speed */
|
|
|
8577 #define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
|
|
|
8578 #define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
|
|
|
8579
|
|
|
8580 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
|
|
|
8581 #define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
|
|
|
8582 #define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
|
|
|
8583 #define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask */
|
|
|
8584 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
|
|
|
8585 #define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
|
|
|
8586 #define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
|
|
|
8587 #define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< OUT packet error mask */
|
|
|
8588 #define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
|
|
|
8589 #define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /*!< Bubble error interrupt mask */
|
|
|
8590 #define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
|
|
|
8591 #define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /*!< NYET interrupt mask */
|
|
|
8592
|
|
|
8593 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
|
|
|
8594 #define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /*!< Host periodic TxFIFO start address */
|
|
|
8595 #define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /*!< Host periodic TxFIFO depth */
|
|
|
8596
|
|
|
8597 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
|
|
|
8598 #define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
|
|
|
8599 #define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
|
|
|
8600 #define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /*!< Even/odd frame */
|
|
|
8601 #define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
|
|
|
8602
|
|
|
8603 #define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
|
|
|
8604 #define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
|
|
|
8605 #define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
|
|
|
8606 #define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
|
|
|
8607
|
|
|
8608 #define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /*!< TxFIFO number */
|
|
|
8609 #define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /*!<Bit 0 */
|
|
|
8610 #define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /*!<Bit 1 */
|
|
|
8611 #define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /*!<Bit 2 */
|
|
|
8612 #define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /*!<Bit 3 */
|
|
|
8613 #define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
|
|
|
8614 #define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
|
|
|
8615 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
|
|
|
8616 #define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
|
|
|
8617 #define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
|
|
|
8618 #define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
|
|
|
8619
|
|
|
8620 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
|
|
|
8621 #define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
|
|
|
8622
|
|
|
8623 #define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /*!< Endpoint number */
|
|
|
8624 #define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /*!<Bit 0 */
|
|
|
8625 #define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /*!<Bit 1 */
|
|
|
8626 #define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /*!<Bit 2 */
|
|
|
8627 #define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /*!<Bit 3 */
|
|
|
8628 #define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /*!< Endpoint direction */
|
|
|
8629 #define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /*!< Low-speed device */
|
|
|
8630
|
|
|
8631 #define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
|
|
|
8632 #define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
|
|
|
8633 #define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
|
|
|
8634
|
|
|
8635 #define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< Multi Count (MC) / Error Count (EC) */
|
|
|
8636 #define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
|
|
8637 #define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
|
|
8638
|
|
|
8639 #define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /*!< Device address */
|
|
|
8640 #define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /*!<Bit 0 */
|
|
|
8641 #define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /*!<Bit 1 */
|
|
|
8642 #define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /*!<Bit 2 */
|
|
|
8643 #define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /*!<Bit 3 */
|
|
|
8644 #define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /*!<Bit 4 */
|
|
|
8645 #define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /*!<Bit 5 */
|
|
|
8646 #define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /*!<Bit 6 */
|
|
|
8647 #define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< Odd frame */
|
|
|
8648 #define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< Channel disable */
|
|
|
8649 #define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< Channel enable */
|
|
|
8650
|
|
|
8651 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
|
|
|
8652
|
|
|
8653 #define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /*!< Port address */
|
|
|
8654 #define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
8655 #define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
8656 #define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
8657 #define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
8658 #define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
|
|
8659 #define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /*!<Bit 5 */
|
|
|
8660 #define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /*!<Bit 6 */
|
|
|
8661
|
|
|
8662 #define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /*!< Hub address */
|
|
|
8663 #define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /*!<Bit 0 */
|
|
|
8664 #define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /*!<Bit 1 */
|
|
|
8665 #define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /*!<Bit 2 */
|
|
|
8666 #define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /*!<Bit 3 */
|
|
|
8667 #define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /*!<Bit 4 */
|
|
|
8668 #define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /*!<Bit 5 */
|
|
|
8669 #define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /*!<Bit 6 */
|
|
|
8670
|
|
|
8671 #define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /*!< XACTPOS */
|
|
|
8672 #define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /*!<Bit 0 */
|
|
|
8673 #define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /*!<Bit 1 */
|
|
|
8674 #define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /*!< Do complete split */
|
|
|
8675 #define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /*!< Split enable */
|
|
|
8676
|
|
|
8677 /******************** Bit definition forUSB_OTG_HCINT register ********************/
|
|
|
8678 #define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed */
|
|
|
8679 #define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /*!< Channel halted */
|
|
|
8680 #define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
|
|
|
8681 #define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /*!< STALL response received interrupt */
|
|
|
8682 #define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /*!< NAK response received interrupt */
|
|
|
8683 #define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt */
|
|
|
8684 #define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /*!< Response received interrupt */
|
|
|
8685 #define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /*!< Transaction error */
|
|
|
8686 #define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /*!< Babble error */
|
|
|
8687 #define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /*!< Frame overrun */
|
|
|
8688 #define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /*!< Data toggle error */
|
|
|
8689
|
|
|
8690 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
|
|
|
8691 #define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
|
|
|
8692 #define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
|
|
|
8693 #define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /*!< Timeout condition */
|
|
|
8694 #define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /*!< IN token received when TxFIFO is empty */
|
|
|
8695 #define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /*!< IN endpoint NAK effective */
|
|
|
8696 #define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /*!< Transmit FIFO empty */
|
|
|
8697 #define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /*!< Transmit Fifo Underrun */
|
|
|
8698 #define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /*!< Buffer not available interrupt */
|
|
|
8699 #define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /*!< Packet dropped status */
|
|
|
8700 #define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /*!< Babble error interrupt */
|
|
|
8701 #define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /*!< NAK interrupt */
|
|
|
8702
|
|
|
8703 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
|
|
|
8704 #define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed mask */
|
|
|
8705 #define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /*!< Channel halted mask */
|
|
|
8706 #define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
|
|
|
8707 #define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /*!< STALL response received interrupt mask */
|
|
|
8708 #define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /*!< NAK response received interrupt mask */
|
|
|
8709 #define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt mask */
|
|
|
8710 #define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /*!< response received interrupt mask */
|
|
|
8711 #define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /*!< Transaction error mask */
|
|
|
8712 #define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /*!< Babble error mask */
|
|
|
8713 #define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /*!< Frame overrun mask */
|
|
|
8714 #define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /*!< Data toggle error mask */
|
|
|
8715
|
|
|
8716 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
|
|
|
8717
|
|
|
8718 #define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
|
|
|
8719 #define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
|
|
|
8720 #define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /*!< Packet count */
|
|
|
8721 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
|
|
|
8722 #define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
|
|
|
8723 #define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
|
|
|
8724 #define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /*!< Do PING */
|
|
|
8725 #define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /*!< Data PID */
|
|
|
8726 #define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /*!<Bit 0 */
|
|
|
8727 #define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /*!<Bit 1 */
|
|
|
8728
|
|
|
8729 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
|
|
|
8730 #define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
|
|
|
8731
|
|
|
8732 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
|
|
|
8733 #define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
|
|
|
8734
|
|
|
8735 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
|
|
|
8736 #define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< IN endpoint TxFIFO space available */
|
|
|
8737
|
|
|
8738 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
|
|
|
8739 #define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /*!< IN endpoint FIFOx transmit RAM start address */
|
|
|
8740 #define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /*!< IN endpoint TxFIFO depth */
|
|
|
8741
|
|
|
8742 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
|
|
|
8743
|
|
|
8744 #define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ /*!<Bit 1 */
|
|
|
8745 #define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
|
|
|
8746 #define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
|
|
|
8747 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
|
|
|
8748 #define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
|
|
|
8749 #define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
|
|
|
8750 #define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
|
|
|
8751 #define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
|
|
|
8752 #define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /*!< Snoop mode */
|
|
|
8753 #define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
|
|
|
8754 #define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
|
|
|
8755 #define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
|
|
|
8756 #define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
|
|
|
8757 #define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
|
|
|
8758
|
|
|
8759 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
|
|
|
8760 #define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
|
|
|
8761 #define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
|
|
|
8762 #define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */
|
|
|
8763 #define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled */
|
|
|
8764 #define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */
|
|
|
8765 #define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */
|
|
|
8766
|
|
|
8767 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
|
|
|
8768
|
|
|
8769 #define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
|
|
|
8770 #define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
|
|
|
8771
|
|
|
8772 #define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /*!< SETUP packet count */
|
|
|
8773 #define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /*!<Bit 0 */
|
|
|
8774 #define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /*!<Bit 1 */
|
|
|
8775
|
|
|
8776 /******************** Bit definition for PCGCCTL register ********************/
|
|
|
8777 #define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /*!< SETUP packet count */
|
|
|
8778 #define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /*!<Bit 0 */
|
|
|
8779 #define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /*!<Bit 1 */
|
|
|
8780
|
|
|
8781
|
|
|
8782 /**
|
|
|
8783 * @}
|
|
|
8784 */
|
|
|
8785
|
|
|
8786 /**
|
|
|
8787 * @}
|
|
|
8788 */
|
|
|
8789
|
|
|
8790 /** @addtogroup Exported_macros
|
|
|
8791 * @{
|
|
|
8792 */
|
|
|
8793
|
|
|
8794 /******************************* ADC Instances ********************************/
|
|
|
8795 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
|
|
|
8796 ((INSTANCE) == ADC2) || \
|
|
|
8797 ((INSTANCE) == ADC3))
|
|
|
8798
|
|
|
8799 /******************************* CAN Instances ********************************/
|
|
|
8800 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
|
|
|
8801 ((INSTANCE) == CAN2))
|
|
|
8802
|
|
|
8803 /******************************* CRC Instances ********************************/
|
|
|
8804 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
|
|
|
8805
|
|
|
8806 /******************************* DAC Instances ********************************/
|
|
|
8807 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
|
|
|
8808
|
|
|
8809 /******************************* DCMI Instances *******************************/
|
|
|
8810 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
|
|
|
8811
|
|
|
8812 /******************************* DMA2D Instances *******************************/
|
|
|
8813 #define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
|
|
|
8814
|
|
|
8815 /******************************** DMA Instances *******************************/
|
|
|
8816 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
|
|
|
8817 ((INSTANCE) == DMA1_Stream1) || \
|
|
|
8818 ((INSTANCE) == DMA1_Stream2) || \
|
|
|
8819 ((INSTANCE) == DMA1_Stream3) || \
|
|
|
8820 ((INSTANCE) == DMA1_Stream4) || \
|
|
|
8821 ((INSTANCE) == DMA1_Stream5) || \
|
|
|
8822 ((INSTANCE) == DMA1_Stream6) || \
|
|
|
8823 ((INSTANCE) == DMA1_Stream7) || \
|
|
|
8824 ((INSTANCE) == DMA2_Stream0) || \
|
|
|
8825 ((INSTANCE) == DMA2_Stream1) || \
|
|
|
8826 ((INSTANCE) == DMA2_Stream2) || \
|
|
|
8827 ((INSTANCE) == DMA2_Stream3) || \
|
|
|
8828 ((INSTANCE) == DMA2_Stream4) || \
|
|
|
8829 ((INSTANCE) == DMA2_Stream5) || \
|
|
|
8830 ((INSTANCE) == DMA2_Stream6) || \
|
|
|
8831 ((INSTANCE) == DMA2_Stream7))
|
|
|
8832
|
|
|
8833 /******************************* GPIO Instances *******************************/
|
|
|
8834 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
|
|
8835 ((INSTANCE) == GPIOB) || \
|
|
|
8836 ((INSTANCE) == GPIOC) || \
|
|
|
8837 ((INSTANCE) == GPIOD) || \
|
|
|
8838 ((INSTANCE) == GPIOE) || \
|
|
|
8839 ((INSTANCE) == GPIOF) || \
|
|
|
8840 ((INSTANCE) == GPIOG) || \
|
|
|
8841 ((INSTANCE) == GPIOH) || \
|
|
|
8842 ((INSTANCE) == GPIOI) || \
|
|
|
8843 ((INSTANCE) == GPIOJ) || \
|
|
|
8844 ((INSTANCE) == GPIOK))
|
|
|
8845
|
|
|
8846 /******************************** I2C Instances *******************************/
|
|
|
8847 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
|
|
|
8848 ((INSTANCE) == I2C2) || \
|
|
|
8849 ((INSTANCE) == I2C3))
|
|
|
8850
|
|
|
8851 /******************************** I2S Instances *******************************/
|
|
|
8852 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
|
|
|
8853 ((INSTANCE) == SPI3))
|
|
|
8854
|
|
|
8855 /*************************** I2S Extended Instances ***************************/
|
|
|
8856 #define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
|
|
|
8857 ((INSTANCE) == SPI3) || \
|
|
|
8858 ((INSTANCE) == I2S2ext) || \
|
|
|
8859 ((INSTANCE) == I2S3ext))
|
|
|
8860
|
|
|
8861 /****************************** LTDC Instances ********************************/
|
|
|
8862 #define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
|
|
|
8863
|
|
|
8864 /******************************* RNG Instances ********************************/
|
|
|
8865 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
|
|
|
8866
|
|
|
8867 /****************************** RTC Instances *********************************/
|
|
|
8868 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
|
|
|
8869
|
|
|
8870 /******************************* SAI Instances ********************************/
|
|
|
8871 #define IS_SAI_BLOCK_PERIPH(PERIPH) (((PERIPH) == SAI1_Block_A) || \
|
|
|
8872 ((PERIPH) == SAI1_Block_B))
|
|
|
8873
|
|
|
8874 /******************************** SPI Instances *******************************/
|
|
|
8875 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
|
|
|
8876 ((INSTANCE) == SPI2) || \
|
|
|
8877 ((INSTANCE) == SPI3) || \
|
|
|
8878 ((INSTANCE) == SPI4) || \
|
|
|
8879 ((INSTANCE) == SPI5) || \
|
|
|
8880 ((INSTANCE) == SPI6))
|
|
|
8881
|
|
|
8882 /*************************** SPI Extended Instances ***************************/
|
|
|
8883 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
|
|
|
8884 ((INSTANCE) == SPI2) || \
|
|
|
8885 ((INSTANCE) == SPI3) || \
|
|
|
8886 ((INSTANCE) == SPI4) || \
|
|
|
8887 ((INSTANCE) == SPI5) || \
|
|
|
8888 ((INSTANCE) == SPI6) || \
|
|
|
8889 ((INSTANCE) == I2S2ext) || \
|
|
|
8890 ((INSTANCE) == I2S3ext))
|
|
|
8891
|
|
|
8892 /****************** TIM Instances : All supported instances *******************/
|
|
|
8893 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
8894 ((INSTANCE) == TIM2) || \
|
|
|
8895 ((INSTANCE) == TIM3) || \
|
|
|
8896 ((INSTANCE) == TIM4) || \
|
|
|
8897 ((INSTANCE) == TIM5) || \
|
|
|
8898 ((INSTANCE) == TIM6) || \
|
|
|
8899 ((INSTANCE) == TIM7) || \
|
|
|
8900 ((INSTANCE) == TIM8) || \
|
|
|
8901 ((INSTANCE) == TIM9) || \
|
|
|
8902 ((INSTANCE) == TIM10) || \
|
|
|
8903 ((INSTANCE) == TIM11) || \
|
|
|
8904 ((INSTANCE) == TIM12) || \
|
|
|
8905 ((INSTANCE) == TIM13) || \
|
|
|
8906 ((INSTANCE) == TIM14))
|
|
|
8907
|
|
|
8908 /************* TIM Instances : at least 1 capture/compare channel *************/
|
|
|
8909 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
8910 ((INSTANCE) == TIM2) || \
|
|
|
8911 ((INSTANCE) == TIM3) || \
|
|
|
8912 ((INSTANCE) == TIM4) || \
|
|
|
8913 ((INSTANCE) == TIM5) || \
|
|
|
8914 ((INSTANCE) == TIM8) || \
|
|
|
8915 ((INSTANCE) == TIM9) || \
|
|
|
8916 ((INSTANCE) == TIM10) || \
|
|
|
8917 ((INSTANCE) == TIM11) || \
|
|
|
8918 ((INSTANCE) == TIM12) || \
|
|
|
8919 ((INSTANCE) == TIM13) || \
|
|
|
8920 ((INSTANCE) == TIM14))
|
|
|
8921
|
|
|
8922 /************ TIM Instances : at least 2 capture/compare channels *************/
|
|
|
8923 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
8924 ((INSTANCE) == TIM2) || \
|
|
|
8925 ((INSTANCE) == TIM3) || \
|
|
|
8926 ((INSTANCE) == TIM4) || \
|
|
|
8927 ((INSTANCE) == TIM5) || \
|
|
|
8928 ((INSTANCE) == TIM8) || \
|
|
|
8929 ((INSTANCE) == TIM9) || \
|
|
|
8930 ((INSTANCE) == TIM12))
|
|
|
8931
|
|
|
8932 /************ TIM Instances : at least 3 capture/compare channels *************/
|
|
|
8933 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
8934 ((INSTANCE) == TIM2) || \
|
|
|
8935 ((INSTANCE) == TIM3) || \
|
|
|
8936 ((INSTANCE) == TIM4) || \
|
|
|
8937 ((INSTANCE) == TIM5) || \
|
|
|
8938 ((INSTANCE) == TIM8))
|
|
|
8939
|
|
|
8940 /************ TIM Instances : at least 4 capture/compare channels *************/
|
|
|
8941 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
8942 ((INSTANCE) == TIM2) || \
|
|
|
8943 ((INSTANCE) == TIM3) || \
|
|
|
8944 ((INSTANCE) == TIM4) || \
|
|
|
8945 ((INSTANCE) == TIM5) || \
|
|
|
8946 ((INSTANCE) == TIM8))
|
|
|
8947
|
|
|
8948 /******************** TIM Instances : Advanced-control timers *****************/
|
|
|
8949 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
8950 ((INSTANCE) == TIM8))
|
|
|
8951
|
|
|
8952 /******************* TIM Instances : Timer input XOR function *****************/
|
|
|
8953 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
8954 ((INSTANCE) == TIM2) || \
|
|
|
8955 ((INSTANCE) == TIM3) || \
|
|
|
8956 ((INSTANCE) == TIM4) || \
|
|
|
8957 ((INSTANCE) == TIM5) || \
|
|
|
8958 ((INSTANCE) == TIM8))
|
|
|
8959
|
|
|
8960 /****************** TIM Instances : DMA requests generation (UDE) *************/
|
|
|
8961 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
8962 ((INSTANCE) == TIM2) || \
|
|
|
8963 ((INSTANCE) == TIM3) || \
|
|
|
8964 ((INSTANCE) == TIM4) || \
|
|
|
8965 ((INSTANCE) == TIM5) || \
|
|
|
8966 ((INSTANCE) == TIM6) || \
|
|
|
8967 ((INSTANCE) == TIM7) || \
|
|
|
8968 ((INSTANCE) == TIM8))
|
|
|
8969
|
|
|
8970 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
|
|
|
8971 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
8972 ((INSTANCE) == TIM2) || \
|
|
|
8973 ((INSTANCE) == TIM3) || \
|
|
|
8974 ((INSTANCE) == TIM4) || \
|
|
|
8975 ((INSTANCE) == TIM5) || \
|
|
|
8976 ((INSTANCE) == TIM8))
|
|
|
8977
|
|
|
8978 /************ TIM Instances : DMA requests generation (COMDE) *****************/
|
|
|
8979 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
8980 ((INSTANCE) == TIM2) || \
|
|
|
8981 ((INSTANCE) == TIM3) || \
|
|
|
8982 ((INSTANCE) == TIM4) || \
|
|
|
8983 ((INSTANCE) == TIM5) || \
|
|
|
8984 ((INSTANCE) == TIM8))
|
|
|
8985
|
|
|
8986 /******************** TIM Instances : DMA burst feature ***********************/
|
|
|
8987 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
8988 ((INSTANCE) == TIM2) || \
|
|
|
8989 ((INSTANCE) == TIM3) || \
|
|
|
8990 ((INSTANCE) == TIM4) || \
|
|
|
8991 ((INSTANCE) == TIM5) || \
|
|
|
8992 ((INSTANCE) == TIM8))
|
|
|
8993
|
|
|
8994 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
|
|
|
8995 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
8996 ((INSTANCE) == TIM2) || \
|
|
|
8997 ((INSTANCE) == TIM3) || \
|
|
|
8998 ((INSTANCE) == TIM4) || \
|
|
|
8999 ((INSTANCE) == TIM5) || \
|
|
|
9000 ((INSTANCE) == TIM6) || \
|
|
|
9001 ((INSTANCE) == TIM7) || \
|
|
|
9002 ((INSTANCE) == TIM8) || \
|
|
|
9003 ((INSTANCE) == TIM9) || \
|
|
|
9004 ((INSTANCE) == TIM12))
|
|
|
9005
|
|
|
9006 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
|
|
|
9007 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
9008 ((INSTANCE) == TIM2) || \
|
|
|
9009 ((INSTANCE) == TIM3) || \
|
|
|
9010 ((INSTANCE) == TIM4) || \
|
|
|
9011 ((INSTANCE) == TIM5) || \
|
|
|
9012 ((INSTANCE) == TIM8) || \
|
|
|
9013 ((INSTANCE) == TIM9) || \
|
|
|
9014 ((INSTANCE) == TIM12))
|
|
|
9015
|
|
|
9016 /********************** TIM Instances : 32 bit Counter ************************/
|
|
|
9017 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
|
|
|
9018 ((INSTANCE) == TIM5))
|
|
|
9019
|
|
|
9020 /***************** TIM Instances : external trigger input availabe ************/
|
|
|
9021 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
9022 ((INSTANCE) == TIM2) || \
|
|
|
9023 ((INSTANCE) == TIM3) || \
|
|
|
9024 ((INSTANCE) == TIM4) || \
|
|
|
9025 ((INSTANCE) == TIM5) || \
|
|
|
9026 ((INSTANCE) == TIM8))
|
|
|
9027
|
|
|
9028 /****************** TIM Instances : remapping capability **********************/
|
|
|
9029 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
|
|
|
9030 ((INSTANCE) == TIM5) || \
|
|
|
9031 ((INSTANCE) == TIM11))
|
|
|
9032
|
|
|
9033 /******************* TIM Instances : output(s) available **********************/
|
|
|
9034 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
|
|
|
9035 ((((INSTANCE) == TIM1) && \
|
|
|
9036 (((CHANNEL) == TIM_CHANNEL_1) || \
|
|
|
9037 ((CHANNEL) == TIM_CHANNEL_2) || \
|
|
|
9038 ((CHANNEL) == TIM_CHANNEL_3) || \
|
|
|
9039 ((CHANNEL) == TIM_CHANNEL_4))) \
|
|
|
9040 || \
|
|
|
9041 (((INSTANCE) == TIM2) && \
|
|
|
9042 (((CHANNEL) == TIM_CHANNEL_1) || \
|
|
|
9043 ((CHANNEL) == TIM_CHANNEL_2) || \
|
|
|
9044 ((CHANNEL) == TIM_CHANNEL_3) || \
|
|
|
9045 ((CHANNEL) == TIM_CHANNEL_4))) \
|
|
|
9046 || \
|
|
|
9047 (((INSTANCE) == TIM3) && \
|
|
|
9048 (((CHANNEL) == TIM_CHANNEL_1) || \
|
|
|
9049 ((CHANNEL) == TIM_CHANNEL_2) || \
|
|
|
9050 ((CHANNEL) == TIM_CHANNEL_3) || \
|
|
|
9051 ((CHANNEL) == TIM_CHANNEL_4))) \
|
|
|
9052 || \
|
|
|
9053 (((INSTANCE) == TIM4) && \
|
|
|
9054 (((CHANNEL) == TIM_CHANNEL_1) || \
|
|
|
9055 ((CHANNEL) == TIM_CHANNEL_2) || \
|
|
|
9056 ((CHANNEL) == TIM_CHANNEL_3) || \
|
|
|
9057 ((CHANNEL) == TIM_CHANNEL_4))) \
|
|
|
9058 || \
|
|
|
9059 (((INSTANCE) == TIM5) && \
|
|
|
9060 (((CHANNEL) == TIM_CHANNEL_1) || \
|
|
|
9061 ((CHANNEL) == TIM_CHANNEL_2) || \
|
|
|
9062 ((CHANNEL) == TIM_CHANNEL_3) || \
|
|
|
9063 ((CHANNEL) == TIM_CHANNEL_4))) \
|
|
|
9064 || \
|
|
|
9065 (((INSTANCE) == TIM8) && \
|
|
|
9066 (((CHANNEL) == TIM_CHANNEL_1) || \
|
|
|
9067 ((CHANNEL) == TIM_CHANNEL_2) || \
|
|
|
9068 ((CHANNEL) == TIM_CHANNEL_3) || \
|
|
|
9069 ((CHANNEL) == TIM_CHANNEL_4))) \
|
|
|
9070 || \
|
|
|
9071 (((INSTANCE) == TIM9) && \
|
|
|
9072 (((CHANNEL) == TIM_CHANNEL_1) || \
|
|
|
9073 ((CHANNEL) == TIM_CHANNEL_2))) \
|
|
|
9074 || \
|
|
|
9075 (((INSTANCE) == TIM10) && \
|
|
|
9076 (((CHANNEL) == TIM_CHANNEL_1))) \
|
|
|
9077 || \
|
|
|
9078 (((INSTANCE) == TIM11) && \
|
|
|
9079 (((CHANNEL) == TIM_CHANNEL_1))) \
|
|
|
9080 || \
|
|
|
9081 (((INSTANCE) == TIM12) && \
|
|
|
9082 (((CHANNEL) == TIM_CHANNEL_1) || \
|
|
|
9083 ((CHANNEL) == TIM_CHANNEL_2))) \
|
|
|
9084 || \
|
|
|
9085 (((INSTANCE) == TIM13) && \
|
|
|
9086 (((CHANNEL) == TIM_CHANNEL_1))) \
|
|
|
9087 || \
|
|
|
9088 (((INSTANCE) == TIM14) && \
|
|
|
9089 (((CHANNEL) == TIM_CHANNEL_1))))
|
|
|
9090
|
|
|
9091 /************ TIM Instances : complementary output(s) available ***************/
|
|
|
9092 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
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|
9093 ((((INSTANCE) == TIM1) && \
|
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|
9094 (((CHANNEL) == TIM_CHANNEL_1) || \
|
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9095 ((CHANNEL) == TIM_CHANNEL_2) || \
|
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9096 ((CHANNEL) == TIM_CHANNEL_3))) \
|
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|
9097 || \
|
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|
9098 (((INSTANCE) == TIM8) && \
|
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|
9099 (((CHANNEL) == TIM_CHANNEL_1) || \
|
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|
9100 ((CHANNEL) == TIM_CHANNEL_2) || \
|
|
|
9101 ((CHANNEL) == TIM_CHANNEL_3))))
|
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9102
|
|
|
9103 /******************** USART Instances : Synchronous mode **********************/
|
|
|
9104 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
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|
9105 ((INSTANCE) == USART2) || \
|
|
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9106 ((INSTANCE) == USART3) || \
|
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|
9107 ((INSTANCE) == USART6))
|
|
|
9108
|
|
|
9109 /******************** UART Instances : Asynchronous mode **********************/
|
|
|
9110 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
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|
9111 ((INSTANCE) == USART2) || \
|
|
|
9112 ((INSTANCE) == USART3) || \
|
|
|
9113 ((INSTANCE) == UART4) || \
|
|
|
9114 ((INSTANCE) == UART5) || \
|
|
|
9115 ((INSTANCE) == USART6) || \
|
|
|
9116 ((INSTANCE) == UART7) || \
|
|
|
9117 ((INSTANCE) == UART8))
|
|
|
9118
|
|
|
9119 /****************** UART Instances : Hardware Flow control ********************/
|
|
|
9120 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
|
|
9121 ((INSTANCE) == USART2) || \
|
|
|
9122 ((INSTANCE) == USART3) || \
|
|
|
9123 ((INSTANCE) == USART6))
|
|
|
9124
|
|
|
9125 /********************* UART Instances : Smard card mode ***********************/
|
|
|
9126 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
|
|
9127 ((INSTANCE) == USART2) || \
|
|
|
9128 ((INSTANCE) == USART3) || \
|
|
|
9129 ((INSTANCE) == USART6))
|
|
|
9130
|
|
|
9131 /*********************** UART Instances : IRDA mode ***************************/
|
|
|
9132 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
|
|
9133 ((INSTANCE) == USART2) || \
|
|
|
9134 ((INSTANCE) == USART3) || \
|
|
|
9135 ((INSTANCE) == UART4) || \
|
|
|
9136 ((INSTANCE) == UART5) || \
|
|
|
9137 ((INSTANCE) == USART6) || \
|
|
|
9138 ((INSTANCE) == UART7) || \
|
|
|
9139 ((INSTANCE) == UART8))
|
|
|
9140
|
|
|
9141 /****************************** IWDG Instances ********************************/
|
|
|
9142 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
|
|
|
9143
|
|
|
9144 /****************************** WWDG Instances ********************************/
|
|
|
9145 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
|
|
|
9146
|
|
|
9147 /****************************** SDIO Instances ********************************/
|
|
|
9148 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
|
|
|
9149
|
|
|
9150 /****************************** USB Exported Constants ************************/
|
|
|
9151 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8
|
|
|
9152 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4 /* Including EP0 */
|
|
|
9153 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4 /* Including EP0 */
|
|
|
9154 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */
|
|
|
9155
|
|
|
9156 #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12
|
|
|
9157 #define USB_OTG_HS_MAX_IN_ENDPOINTS 6 /* Including EP0 */
|
|
|
9158 #define USB_OTG_HS_MAX_IN_ENDPOINTS 6 /* Including EP0 */
|
|
|
9159 #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096 /* in Bytes */
|
|
|
9160
|
|
|
9161 /******************************************************************************/
|
|
|
9162 /* For a painless codes migration between the STM32F4xx device product */
|
|
|
9163 /* lines, the aliases defined below are put in place to overcome the */
|
|
|
9164 /* differences in the interrupt handlers and IRQn definitions. */
|
|
|
9165 /* No need to update developed interrupt code when moving across */
|
|
|
9166 /* product lines within the same STM32F4 Family */
|
|
|
9167 /******************************************************************************/
|
|
|
9168
|
|
|
9169 /* Aliases for __IRQn */
|
|
|
9170 #define FSMC_IRQn FMC_IRQn
|
|
|
9171
|
|
|
9172 /* Aliases for __IRQHandler */
|
|
|
9173 #define FSMC_IRQHandler FMC_IRQHandler
|
|
|
9174
|
|
|
9175 /**
|
|
|
9176 * @}
|
|
|
9177 */
|
|
|
9178
|
|
|
9179 /**
|
|
|
9180 * @}
|
|
|
9181 */
|
|
|
9182
|
|
|
9183 /**
|
|
|
9184 * @}
|
|
|
9185 */
|
|
|
9186
|
|
|
9187 #ifdef __cplusplus
|
|
|
9188 }
|
|
|
9189 #endif /* __cplusplus */
|
|
|
9190
|
|
|
9191 #endif /* __STM32F439xx_H */
|
|
|
9192
|
|
|
9193
|
|
|
9194
|
|
|
9195 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
