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38
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1 /**
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2 ******************************************************************************
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3 * @file stm32f4xx_hal_sram.c
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4 * @author MCD Application Team
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5 * @version V1.2.0
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6 * @date 26-December-2014
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7 * @brief SRAM HAL module driver.
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8 * This file provides a generic firmware to drive SRAM memories
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9 * mounted as external device.
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10 *
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11 @verbatim
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12 ==============================================================================
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13 ##### How to use this driver #####
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14 ==============================================================================
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15 [..]
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16 This driver is a generic layered driver which contains a set of APIs used to
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17 control SRAM memories. It uses the FMC layer functions to interface
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18 with SRAM devices.
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19 The following sequence should be followed to configure the FMC/FSMC to interface
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20 with SRAM/PSRAM memories:
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21
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22 (#) Declare a SRAM_HandleTypeDef handle structure, for example:
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23 SRAM_HandleTypeDef hsram; and:
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24
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25 (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
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26 values of the structure member.
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27
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28 (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
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29 base register instance for NOR or SRAM device
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30
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31 (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
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32 base register instance for NOR or SRAM extended mode
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33
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34 (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
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35 mode timings; for example:
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36 FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming;
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37 and fill its fields with the allowed values of the structure member.
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38
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39 (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
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40 performs the following sequence:
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41
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42 (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
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43 (##) Control register configuration using the FMC NORSRAM interface function
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44 FMC_NORSRAM_Init()
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45 (##) Timing register configuration using the FMC NORSRAM interface function
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46 FMC_NORSRAM_Timing_Init()
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47 (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
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48 FMC_NORSRAM_Extended_Timing_Init()
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49 (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
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50
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51 (#) At this stage you can perform read/write accesses from/to the memory connected
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52 to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
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53 following APIs:
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54 (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
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55 (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
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56
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57 (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
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58 HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
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59
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60 (#) You can continuously monitor the SRAM device HAL state by calling the function
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61 HAL_SRAM_GetState()
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62
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63 @endverbatim
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64 ******************************************************************************
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65 * @attention
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66 *
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67 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
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68 *
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69 * Redistribution and use in source and binary forms, with or without modification,
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70 * are permitted provided that the following conditions are met:
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71 * 1. Redistributions of source code must retain the above copyright notice,
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72 * this list of conditions and the following disclaimer.
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73 * 2. Redistributions in binary form must reproduce the above copyright notice,
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74 * this list of conditions and the following disclaimer in the documentation
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75 * and/or other materials provided with the distribution.
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76 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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77 * may be used to endorse or promote products derived from this software
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78 * without specific prior written permission.
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79 *
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80 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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81 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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82 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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83 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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84 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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85 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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86 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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87 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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88 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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89 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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90 *
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91 ******************************************************************************
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92 */
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93
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94 /* Includes ------------------------------------------------------------------*/
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95 #include "stm32f4xx_hal.h"
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96
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97 /** @addtogroup STM32F4xx_HAL_Driver
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98 * @{
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99 */
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100
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101 /** @defgroup SRAM SRAM
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102 * @brief SRAM driver modules
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103 * @{
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104 */
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105 #ifdef HAL_SRAM_MODULE_ENABLED
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106
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107 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
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108
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109 /* Private typedef -----------------------------------------------------------*/
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110 /* Private define ------------------------------------------------------------*/
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111 /* Private macro -------------------------------------------------------------*/
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112 /* Private variables ---------------------------------------------------------*/
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113 /* Private functions ---------------------------------------------------------*/
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114
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115 /* Exported functions --------------------------------------------------------*/
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116 /** @defgroup SRAM_Exported_Functions SRAM Exported Functions
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117 * @{
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118 */
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119 /** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
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120 * @brief Initialization and Configuration functions
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121 *
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122 @verbatim
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123 ==============================================================================
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124 ##### SRAM Initialization and de_initialization functions #####
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125 ==============================================================================
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126 [..] This section provides functions allowing to initialize/de-initialize
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127 the SRAM memory
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128
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129 @endverbatim
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130 * @{
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131 */
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132
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133 /**
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134 * @brief Performs the SRAM device initialization sequence
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135 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
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136 * the configuration information for SRAM module.
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137 * @param Timing: Pointer to SRAM control timing structure
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138 * @param ExtTiming: Pointer to SRAM extended mode timing structure
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139 * @retval HAL status
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140 */
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141 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
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142 {
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143 /* Check the SRAM handle parameter */
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144 if(hsram == NULL)
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145 {
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146 return HAL_ERROR;
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147 }
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148
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149 if(hsram->State == HAL_SRAM_STATE_RESET)
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150 {
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151 /* Initialize the low level hardware (MSP) */
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152 HAL_SRAM_MspInit(hsram);
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153 }
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154
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155 /* Initialize SRAM control Interface */
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156 FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
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157
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158 /* Initialize SRAM timing Interface */
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159 FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
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160
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161 /* Initialize SRAM extended mode timing Interface */
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162 FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
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163
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164 /* Enable the NORSRAM device */
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165 __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
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166
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167 return HAL_OK;
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168 }
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169
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170 /**
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171 * @brief Performs the SRAM device De-initialization sequence.
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172 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
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173 * the configuration information for SRAM module.
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174 * @retval HAL status
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175 */
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176 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
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177 {
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178 /* De-Initialize the low level hardware (MSP) */
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179 HAL_SRAM_MspDeInit(hsram);
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180
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181 /* Configure the SRAM registers with their reset values */
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182 FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
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183
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184 hsram->State = HAL_SRAM_STATE_RESET;
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185
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186 /* Release Lock */
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187 __HAL_UNLOCK(hsram);
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188
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189 return HAL_OK;
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190 }
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191
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192 /**
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193 * @brief SRAM MSP Init.
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194 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
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195 * the configuration information for SRAM module.
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196 * @retval None
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197 */
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198 __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
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199 {
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200 /* NOTE : This function Should not be modified, when the callback is needed,
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201 the HAL_SRAM_MspInit could be implemented in the user file
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202 */
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203 }
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204
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205 /**
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206 * @brief SRAM MSP DeInit.
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207 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
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208 * the configuration information for SRAM module.
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209 * @retval None
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210 */
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211 __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
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212 {
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213 /* NOTE : This function Should not be modified, when the callback is needed,
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214 the HAL_SRAM_MspDeInit could be implemented in the user file
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215 */
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216 }
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217
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218 /**
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219 * @brief DMA transfer complete callback.
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220 * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
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221 * the configuration information for SRAM module.
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222 * @retval None
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223 */
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224 __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
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225 {
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226 /* NOTE : This function Should not be modified, when the callback is needed,
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227 the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
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228 */
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229 }
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230
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231 /**
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232 * @brief DMA transfer complete error callback.
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233 * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
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234 * the configuration information for SRAM module.
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235 * @retval None
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236 */
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237 __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
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238 {
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239 /* NOTE : This function Should not be modified, when the callback is needed,
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240 the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
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241 */
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242 }
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243
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244 /**
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245 * @}
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246 */
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247
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248 /** @defgroup SRAM_Exported_Functions_Group2 Input and Output functions
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249 * @brief Input Output and memory control functions
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250 *
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251 @verbatim
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252 ==============================================================================
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253 ##### SRAM Input and Output functions #####
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254 ==============================================================================
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255 [..]
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256 This section provides functions allowing to use and control the SRAM memory
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257
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258 @endverbatim
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259 * @{
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260 */
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261
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262 /**
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263 * @brief Reads 8-bit buffer from SRAM memory.
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264 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
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265 * the configuration information for SRAM module.
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266 * @param pAddress: Pointer to read start address
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267 * @param pDstBuffer: Pointer to destination buffer
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268 * @param BufferSize: Size of the buffer to read from memory
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269 * @retval HAL status
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270 */
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271 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
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272 {
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273 __IO uint8_t * pSramAddress = (uint8_t *)pAddress;
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274
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275 /* Process Locked */
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276 __HAL_LOCK(hsram);
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277
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278 /* Update the SRAM controller state */
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279 hsram->State = HAL_SRAM_STATE_BUSY;
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280
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281 /* Read data from memory */
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282 for(; BufferSize != 0; BufferSize--)
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283 {
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284 *pDstBuffer = *(__IO uint8_t *)pSramAddress;
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285 pDstBuffer++;
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286 pSramAddress++;
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287 }
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288
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289 /* Update the SRAM controller state */
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290 hsram->State = HAL_SRAM_STATE_READY;
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291
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292 /* Process unlocked */
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293 __HAL_UNLOCK(hsram);
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294
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295 return HAL_OK;
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296 }
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297
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298 /**
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299 * @brief Writes 8-bit buffer to SRAM memory.
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300 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
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301 * the configuration information for SRAM module.
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302 * @param pAddress: Pointer to write start address
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303 * @param pSrcBuffer: Pointer to source buffer to write
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304 * @param BufferSize: Size of the buffer to write to memory
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305 * @retval HAL status
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306 */
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307 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
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308 {
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309 __IO uint8_t * pSramAddress = (uint8_t *)pAddress;
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310
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311 /* Check the SRAM controller state */
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312 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
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313 {
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314 return HAL_ERROR;
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315 }
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316
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317 /* Process Locked */
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318 __HAL_LOCK(hsram);
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319
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320 /* Update the SRAM controller state */
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321 hsram->State = HAL_SRAM_STATE_BUSY;
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322
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323 /* Write data to memory */
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324 for(; BufferSize != 0; BufferSize--)
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325 {
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326 *(__IO uint8_t *)pSramAddress = *pSrcBuffer;
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327 pSrcBuffer++;
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328 pSramAddress++;
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329 }
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330
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331 /* Update the SRAM controller state */
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332 hsram->State = HAL_SRAM_STATE_READY;
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333
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334 /* Process unlocked */
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335 __HAL_UNLOCK(hsram);
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336
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337 return HAL_OK;
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338 }
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339
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340 /**
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341 * @brief Reads 16-bit buffer from SRAM memory.
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342 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
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343 * the configuration information for SRAM module.
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344 * @param pAddress: Pointer to read start address
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345 * @param pDstBuffer: Pointer to destination buffer
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346 * @param BufferSize: Size of the buffer to read from memory
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347 * @retval HAL status
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348 */
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349 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
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350 {
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351 __IO uint16_t * pSramAddress = (uint16_t *)pAddress;
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352
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353 /* Process Locked */
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354 __HAL_LOCK(hsram);
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355
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356 /* Update the SRAM controller state */
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357 hsram->State = HAL_SRAM_STATE_BUSY;
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358
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359 /* Read data from memory */
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360 for(; BufferSize != 0; BufferSize--)
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361 {
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362 *pDstBuffer = *(__IO uint16_t *)pSramAddress;
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363 pDstBuffer++;
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364 pSramAddress++;
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365 }
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366
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367 /* Update the SRAM controller state */
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368 hsram->State = HAL_SRAM_STATE_READY;
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369
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370 /* Process unlocked */
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371 __HAL_UNLOCK(hsram);
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372
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373 return HAL_OK;
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374 }
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375
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376 /**
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377 * @brief Writes 16-bit buffer to SRAM memory.
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378 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
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379 * the configuration information for SRAM module.
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380 * @param pAddress: Pointer to write start address
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381 * @param pSrcBuffer: Pointer to source buffer to write
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382 * @param BufferSize: Size of the buffer to write to memory
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383 * @retval HAL status
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384 */
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385 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
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386 {
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387 __IO uint16_t * pSramAddress = (uint16_t *)pAddress;
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388
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389 /* Check the SRAM controller state */
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390 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
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391 {
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392 return HAL_ERROR;
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393 }
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394
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395 /* Process Locked */
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396 __HAL_LOCK(hsram);
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397
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398 /* Update the SRAM controller state */
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399 hsram->State = HAL_SRAM_STATE_BUSY;
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400
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401 /* Write data to memory */
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402 for(; BufferSize != 0; BufferSize--)
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403 {
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404 *(__IO uint16_t *)pSramAddress = *pSrcBuffer;
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405 pSrcBuffer++;
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406 pSramAddress++;
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407 }
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408
|
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409 /* Update the SRAM controller state */
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410 hsram->State = HAL_SRAM_STATE_READY;
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411
|
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412 /* Process unlocked */
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413 __HAL_UNLOCK(hsram);
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414
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415 return HAL_OK;
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416 }
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417
|
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418 /**
|
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419 * @brief Reads 32-bit buffer from SRAM memory.
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420 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
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421 * the configuration information for SRAM module.
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422 * @param pAddress: Pointer to read start address
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423 * @param pDstBuffer: Pointer to destination buffer
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424 * @param BufferSize: Size of the buffer to read from memory
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425 * @retval HAL status
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|
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426 */
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427 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
|
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428 {
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429 /* Process Locked */
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430 __HAL_LOCK(hsram);
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431
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432 /* Update the SRAM controller state */
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433 hsram->State = HAL_SRAM_STATE_BUSY;
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434
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435 /* Read data from memory */
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436 for(; BufferSize != 0; BufferSize--)
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437 {
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438 *pDstBuffer = *(__IO uint32_t *)pAddress;
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439 pDstBuffer++;
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440 pAddress++;
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441 }
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442
|
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443 /* Update the SRAM controller state */
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444 hsram->State = HAL_SRAM_STATE_READY;
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445
|
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446 /* Process unlocked */
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447 __HAL_UNLOCK(hsram);
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448
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449 return HAL_OK;
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|
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450 }
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451
|
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|
452 /**
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453 * @brief Writes 32-bit buffer to SRAM memory.
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454 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
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455 * the configuration information for SRAM module.
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456 * @param pAddress: Pointer to write start address
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457 * @param pSrcBuffer: Pointer to source buffer to write
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|
458 * @param BufferSize: Size of the buffer to write to memory
|
|
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459 * @retval HAL status
|
|
|
460 */
|
|
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461 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
|
|
|
462 {
|
|
|
463 /* Check the SRAM controller state */
|
|
|
464 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
|
|
|
465 {
|
|
|
466 return HAL_ERROR;
|
|
|
467 }
|
|
|
468
|
|
|
469 /* Process Locked */
|
|
|
470 __HAL_LOCK(hsram);
|
|
|
471
|
|
|
472 /* Update the SRAM controller state */
|
|
|
473 hsram->State = HAL_SRAM_STATE_BUSY;
|
|
|
474
|
|
|
475 /* Write data to memory */
|
|
|
476 for(; BufferSize != 0; BufferSize--)
|
|
|
477 {
|
|
|
478 *(__IO uint32_t *)pAddress = *pSrcBuffer;
|
|
|
479 pSrcBuffer++;
|
|
|
480 pAddress++;
|
|
|
481 }
|
|
|
482
|
|
|
483 /* Update the SRAM controller state */
|
|
|
484 hsram->State = HAL_SRAM_STATE_READY;
|
|
|
485
|
|
|
486 /* Process unlocked */
|
|
|
487 __HAL_UNLOCK(hsram);
|
|
|
488
|
|
|
489 return HAL_OK;
|
|
|
490 }
|
|
|
491
|
|
|
492 /**
|
|
|
493 * @brief Reads a Words data from the SRAM memory using DMA transfer.
|
|
|
494 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
|
|
495 * the configuration information for SRAM module.
|
|
|
496 * @param pAddress: Pointer to read start address
|
|
|
497 * @param pDstBuffer: Pointer to destination buffer
|
|
|
498 * @param BufferSize: Size of the buffer to read from memory
|
|
|
499 * @retval HAL status
|
|
|
500 */
|
|
|
501 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
|
|
|
502 {
|
|
|
503 /* Process Locked */
|
|
|
504 __HAL_LOCK(hsram);
|
|
|
505
|
|
|
506 /* Update the SRAM controller state */
|
|
|
507 hsram->State = HAL_SRAM_STATE_BUSY;
|
|
|
508
|
|
|
509 /* Configure DMA user callbacks */
|
|
|
510 hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
|
|
|
511 hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
|
|
|
512
|
|
|
513 /* Enable the DMA Stream */
|
|
|
514 HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
|
|
|
515
|
|
|
516 /* Update the SRAM controller state */
|
|
|
517 hsram->State = HAL_SRAM_STATE_READY;
|
|
|
518
|
|
|
519 /* Process unlocked */
|
|
|
520 __HAL_UNLOCK(hsram);
|
|
|
521
|
|
|
522 return HAL_OK;
|
|
|
523 }
|
|
|
524
|
|
|
525 /**
|
|
|
526 * @brief Writes a Words data buffer to SRAM memory using DMA transfer.
|
|
|
527 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
|
|
528 * the configuration information for SRAM module.
|
|
|
529 * @param pAddress: Pointer to write start address
|
|
|
530 * @param pSrcBuffer: Pointer to source buffer to write
|
|
|
531 * @param BufferSize: Size of the buffer to write to memory
|
|
|
532 * @retval HAL status
|
|
|
533 */
|
|
|
534 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
|
|
|
535 {
|
|
|
536 /* Check the SRAM controller state */
|
|
|
537 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
|
|
|
538 {
|
|
|
539 return HAL_ERROR;
|
|
|
540 }
|
|
|
541
|
|
|
542 /* Process Locked */
|
|
|
543 __HAL_LOCK(hsram);
|
|
|
544
|
|
|
545 /* Update the SRAM controller state */
|
|
|
546 hsram->State = HAL_SRAM_STATE_BUSY;
|
|
|
547
|
|
|
548 /* Configure DMA user callbacks */
|
|
|
549 hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
|
|
|
550 hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
|
|
|
551
|
|
|
552 /* Enable the DMA Stream */
|
|
|
553 HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
|
|
|
554
|
|
|
555 /* Update the SRAM controller state */
|
|
|
556 hsram->State = HAL_SRAM_STATE_READY;
|
|
|
557
|
|
|
558 /* Process unlocked */
|
|
|
559 __HAL_UNLOCK(hsram);
|
|
|
560
|
|
|
561 return HAL_OK;
|
|
|
562 }
|
|
|
563
|
|
|
564 /**
|
|
|
565 * @}
|
|
|
566 */
|
|
|
567
|
|
|
568 /** @defgroup SRAM_Exported_Functions_Group3 Control functions
|
|
|
569 * @brief management functions
|
|
|
570 *
|
|
|
571 @verbatim
|
|
|
572 ==============================================================================
|
|
|
573 ##### SRAM Control functions #####
|
|
|
574 ==============================================================================
|
|
|
575 [..]
|
|
|
576 This subsection provides a set of functions allowing to control dynamically
|
|
|
577 the SRAM interface.
|
|
|
578
|
|
|
579 @endverbatim
|
|
|
580 * @{
|
|
|
581 */
|
|
|
582
|
|
|
583 /**
|
|
|
584 * @brief Enables dynamically SRAM write operation.
|
|
|
585 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
|
|
586 * the configuration information for SRAM module.
|
|
|
587 * @retval HAL status
|
|
|
588 */
|
|
|
589 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
|
|
|
590 {
|
|
|
591 /* Process Locked */
|
|
|
592 __HAL_LOCK(hsram);
|
|
|
593
|
|
|
594 /* Enable write operation */
|
|
|
595 FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
|
|
|
596
|
|
|
597 /* Update the SRAM controller state */
|
|
|
598 hsram->State = HAL_SRAM_STATE_READY;
|
|
|
599
|
|
|
600 /* Process unlocked */
|
|
|
601 __HAL_UNLOCK(hsram);
|
|
|
602
|
|
|
603 return HAL_OK;
|
|
|
604 }
|
|
|
605
|
|
|
606 /**
|
|
|
607 * @brief Disables dynamically SRAM write operation.
|
|
|
608 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
|
|
609 * the configuration information for SRAM module.
|
|
|
610 * @retval HAL status
|
|
|
611 */
|
|
|
612 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
|
|
|
613 {
|
|
|
614 /* Process Locked */
|
|
|
615 __HAL_LOCK(hsram);
|
|
|
616
|
|
|
617 /* Update the SRAM controller state */
|
|
|
618 hsram->State = HAL_SRAM_STATE_BUSY;
|
|
|
619
|
|
|
620 /* Disable write operation */
|
|
|
621 FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
|
|
|
622
|
|
|
623 /* Update the SRAM controller state */
|
|
|
624 hsram->State = HAL_SRAM_STATE_PROTECTED;
|
|
|
625
|
|
|
626 /* Process unlocked */
|
|
|
627 __HAL_UNLOCK(hsram);
|
|
|
628
|
|
|
629 return HAL_OK;
|
|
|
630 }
|
|
|
631
|
|
|
632 /**
|
|
|
633 * @}
|
|
|
634 */
|
|
|
635
|
|
|
636 /** @defgroup SRAM_Exported_Functions_Group4 State functions
|
|
|
637 * @brief Peripheral State functions
|
|
|
638 *
|
|
|
639 @verbatim
|
|
|
640 ==============================================================================
|
|
|
641 ##### SRAM State functions #####
|
|
|
642 ==============================================================================
|
|
|
643 [..]
|
|
|
644 This subsection permits to get in run-time the status of the SRAM controller
|
|
|
645 and the data flow.
|
|
|
646
|
|
|
647 @endverbatim
|
|
|
648 * @{
|
|
|
649 */
|
|
|
650
|
|
|
651 /**
|
|
|
652 * @brief Returns the SRAM controller state
|
|
|
653 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
|
|
654 * the configuration information for SRAM module.
|
|
|
655 * @retval HAL state
|
|
|
656 */
|
|
|
657 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
|
|
|
658 {
|
|
|
659 return hsram->State;
|
|
|
660 }
|
|
|
661 /**
|
|
|
662 * @}
|
|
|
663 */
|
|
|
664
|
|
|
665 /**
|
|
|
666 * @}
|
|
|
667 */
|
|
|
668 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
|
|
669 #endif /* HAL_SRAM_MODULE_ENABLED */
|
|
|
670 /**
|
|
|
671 * @}
|
|
|
672 */
|
|
|
673
|
|
|
674 /**
|
|
|
675 * @}
|
|
|
676 */
|
|
|
677
|
|
|
678 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
