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1 /**
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2 ******************************************************************************
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3 * @file system_stm32f4xx.c
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4 * @author MCD Application Team
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5 * @version V1.1.0
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6 * @date 17-February-2017
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7 * @brief - CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
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8 * - This file is dedicated only for STM32F29 NUCLEO 144 boards.
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9 *
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10 * This file provides two functions and one global variable to be called from
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11 * user application:
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12 * - SystemInit(): This function is called at startup just after reset and
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13 * before branch to main program. This call is made inside
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14 * the "startup_stm32f4xx.s" file.
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15 *
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16 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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17 * by the user application to setup the SysTick
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18 * timer or configure other parameters.
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19 *
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20 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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21 * be called whenever the core clock is changed
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22 * during program execution.
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23 *
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24 *
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25 ******************************************************************************
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26 * @attention
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27 *
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28 * <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2>
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29 *
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30 * Redistribution and use in source and binary forms, with or without modification,
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31 * are permitted provided that the following conditions are met:
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32 * 1. Redistributions of source code must retain the above copyright notice,
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33 * this list of conditions and the following disclaimer.
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34 * 2. Redistributions in binary form must reproduce the above copyright notice,
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35 * this list of conditions and the following disclaimer in the documentation
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36 * and/or other materials provided with the distribution.
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37 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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38 * may be used to endorse or promote products derived from this software
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39 * without specific prior written permission.
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40 *
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41 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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42 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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44 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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47 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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48 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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49 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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50 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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51 *
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52 ******************************************************************************
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53 */
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54
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55 /** @addtogroup CMSIS
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56 * @{
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57 */
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58
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59 /** @addtogroup stm32f4xx_system
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60 * @{
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61 */
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62
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63 /** @addtogroup STM32F4xx_System_Private_Includes
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64 * @{
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65 */
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66
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67
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68 #include "stm32f4xx.h"
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69
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70 #if !defined (HSE_VALUE)
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71 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
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72 #endif /* HSE_VALUE */
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73
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74 #if !defined (HSI_VALUE)
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75 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
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76 #endif /* HSI_VALUE */
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77
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78 /**
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79 * @}
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80 */
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81
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82 /** @addtogroup STM32F4xx_System_Private_TypesDefinitions
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83 * @{
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84 */
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85
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86 /**
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87 * @}
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88 */
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89
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90 /** @addtogroup STM32F4xx_System_Private_Defines
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91 * @{
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92 */
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93
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94 /************************* Miscellaneous Configuration ************************/
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95 /*!< Uncomment the following line if you need to relocate your vector Table in
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96 Internal SRAM. */
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97 /* #define VECT_TAB_SRAM */
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98 #define VECT_TAB_OFFSET 0x40000 /*!< Vector Table base offset field.
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99 This value must be a multiple of 0x200. */
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100 /******************************************************************************/
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101
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102 /**
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103 * @}
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104 */
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105
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106 /** @addtogroup STM32F4xx_System_Private_Macros
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107 * @{
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108 */
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109
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110 /**
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111 * @}
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112 */
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113
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114 /** @addtogroup STM32F4xx_System_Private_Variables
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115 * @{
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116 */
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117 /* This variable is updated in three ways:
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118 1) by calling CMSIS function SystemCoreClockUpdate()
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119 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
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120 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
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121 Note: If you use this function to configure the system clock; then there
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122 is no need to call the 2 first functions listed above, since SystemCoreClock
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123 variable is updated automatically.
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124 */
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125 uint32_t SystemCoreClock = 16000000;
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126 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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127 const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
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128 /**
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129 * @}
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130 */
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131
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132
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133 /** @addtogroup STM32F4xx_System_Private_Functions
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134 * @{
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135 */
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136
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137 /**
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138 * @brief Setup the microcontroller system
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139 * Initialize the FPU setting, vector table location and External memory
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140 * configuration.
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141 * @param None
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142 * @retval None
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143 */
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144 void SystemInit(void)
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145 {
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146 /* FPU settings ------------------------------------------------------------*/
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147 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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148 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
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149 #endif
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150 /* Reset the RCC clock configuration to the default reset state ------------*/
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151 /* Set HSION bit */
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152 RCC->CR |= (uint32_t)0x00000001;
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153
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154 /* Reset CFGR register */
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155 RCC->CFGR = 0x00000000;
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156
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157 /* Reset HSEON, CSSON and PLLON bits */
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158 RCC->CR &= (uint32_t)0xFEF6FFFF;
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159
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160 /* Reset PLLCFGR register */
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161 RCC->PLLCFGR = 0x24003010;
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162
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163 /* Reset HSEBYP bit */
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164 RCC->CR &= (uint32_t)0xFFFBFFFF;
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165
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166 /* Disable all interrupts */
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167 RCC->CIR = 0x00000000;
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168
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169
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170 /* Configure the Vector Table location add offset address ------------------*/
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171 #ifdef VECT_TAB_SRAM
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172 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
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173 #else
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174 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
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175 #endif
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176 }
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177
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178 /**
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179 * @brief Update SystemCoreClock variable according to Clock Register Values.
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180 * The SystemCoreClock variable contains the core clock (HCLK), it can
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181 * be used by the user application to setup the SysTick timer or configure
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182 * other parameters.
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183 *
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184 * @note Each time the core clock (HCLK) changes, this function must be called
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185 * to update SystemCoreClock variable value. Otherwise, any configuration
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186 * based on this variable will be incorrect.
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187 *
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188 * @note - The system frequency computed by this function is not the real
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189 * frequency in the chip. It is calculated based on the predefined
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190 * constant and the selected clock source:
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191 *
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192 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
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193 *
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194 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
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195 *
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196 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
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197 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
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198 *
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199 * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
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200 * 16 MHz) but the real value may vary depending on the variations
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201 * in voltage and temperature.
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202 *
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203 * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
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204 * depends on the application requirements), user has to ensure that HSE_VALUE
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205 * is same as the real frequency of the crystal used. Otherwise, this function
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206 * may have wrong result.
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207 *
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208 * - The result of this function could be not correct when using fractional
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209 * value for HSE crystal.
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210 *
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211 * @param None
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212 * @retval None
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213 */
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214 void SystemCoreClockUpdate(void)
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215 {
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216 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
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217
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218 /* Get SYSCLK source -------------------------------------------------------*/
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219 tmp = RCC->CFGR & RCC_CFGR_SWS;
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220
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221 switch (tmp)
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222 {
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223 case 0x00: /* HSI used as system clock source */
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224 SystemCoreClock = HSI_VALUE;
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225 break;
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226 case 0x04: /* HSE used as system clock source */
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227 SystemCoreClock = HSE_VALUE;
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228 break;
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229 case 0x08: /* PLL used as system clock source */
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230
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231 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
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232 SYSCLK = PLL_VCO / PLL_P
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233 */
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234 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
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235 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
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236
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237 if (pllsource != 0)
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238 {
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239 /* HSE used as PLL clock source */
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240 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
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241 }
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242 else
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243 {
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244 /* HSI used as PLL clock source */
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245 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
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246 }
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247
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248 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
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249 SystemCoreClock = pllvco/pllp;
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250 break;
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251 default:
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252 SystemCoreClock = HSI_VALUE;
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253 break;
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254 }
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255 /* Compute HCLK frequency --------------------------------------------------*/
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256 /* Get HCLK prescaler */
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257 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
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258 /* HCLK frequency */
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259 SystemCoreClock >>= tmp;
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260 }
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261
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262 /**
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263 * @}
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264 */
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265
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266 /**
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267 * @}
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268 */
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269
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270 /**
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271 * @}
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272 */
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273 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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