annotate Small_CPU/Src/uart.c @ 686:b1e24513b83e Betatest

Bugfix Battery charge complete event: In previous version it could happen that the battery charge state was set to 100% even the battery was not completly charged. Rootcause was that the external charger IC signals sometimes completion because e.g. the connection between charger unit and OSTC is disconnected within a short time slot. This may happen while the user is trying to get the OSTC in a good charging position. To avoid this the state machine now checks the voltage everytime for valid charging complete range before a charging complete is signaled.
author Ideenmodellierer
date Fri, 05 Aug 2022 14:56:17 +0200
parents 1b995079c045
children fca2bd25e6e2
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
38
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1 /**
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2 ******************************************************************************
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3 * @file uart.c
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4 * @author heinrichs weikamp gmbh
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5 * @version V0.0.1
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6 * @date 27-March-2014
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7 * @brief button control
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8 *
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
9 @verbatim
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
10 ==============================================================================
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
11 ##### How to use #####
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
12 ==============================================================================
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
13 @endverbatim
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
14 ******************************************************************************
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
15 * @attention
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
16 *
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
17 * <h2><center>&copy; COPYRIGHT(c) 2015 heinrichs weikamp</center></h2>
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
18 *
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
19 ******************************************************************************
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
20 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
21 /* Includes ------------------------------------------------------------------*/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
22 #include "uart.h"
662
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
23 #include "externalInterface.h"
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
24 #include "data_exchange.h"
38
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
25
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
26 /* Private variables ---------------------------------------------------------*/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
27
662
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
28 #define CHUNK_SIZE (20u) /* the DMA will handle chunk size transfers */
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
29 #define CHUNKS_PER_BUFFER (3u)
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
30 UART_HandleTypeDef huart1;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
31
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
32 DMA_HandleTypeDef hdma_usart1_rx;
38
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
33
662
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
34 uint8_t rxBuffer[CHUNK_SIZE * CHUNKS_PER_BUFFER]; /* The complete buffer has a X * chunk size to allow fariations in buffer read time */
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
35 static uint8_t rxWriteIndex; /* Index of the data item which is analysed */
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
36 static uint8_t rxReadIndex; /* Index at which new data is stared */
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
37 static uint8_t lastCmdIndex; /* Index of last command which has not been completly received */
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
38 static uint8_t dmaActive; /* Indicator if DMA receiption needs to be started */
38
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
39
662
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
40 float LED_Level = 0.0; /* Normalized LED value which may be used as indication for the health status of the sensor */
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
41 float LED_ZeroOffset = 0.0;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
42 float pCO2 = 0.0;
38
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
43 /* Exported functions --------------------------------------------------------*/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
44
662
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
45 void MX_USART1_UART_Init(void)
38
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
46 {
662
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
47 /* regular init */
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
48
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
49 huart1.Instance = USART1;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
50 huart1.Init.BaudRate = 9600;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
51 huart1.Init.WordLength = UART_WORDLENGTH_8B;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
52 huart1.Init.StopBits = UART_STOPBITS_1;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
53 huart1.Init.Parity = UART_PARITY_NONE;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
54 huart1.Init.Mode = UART_MODE_TX_RX;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
55 huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
56 huart1.Init.OverSampling = UART_OVERSAMPLING_16;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
57
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
58 HAL_UART_Init(&huart1);
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
59
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
60 rxReadIndex = 0;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
61 lastCmdIndex = 0;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
62 rxWriteIndex = 0;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
63 dmaActive = 0;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
64 }
38
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
65
662
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
66 void MX_USART1_UART_DeInit(void)
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
67 {
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
68 HAL_DMA_DeInit(&hdma_usart1_rx);
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
69 HAL_UART_DeInit(&huart1);
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
70 }
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
71
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
72 void MX_USART1_DMA_Init()
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
73 {
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
74 /* DMA controller clock enable */
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
75 __DMA2_CLK_ENABLE();
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
76
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
77 /* Peripheral DMA init*/
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
78 hdma_usart1_rx.Instance = DMA2_Stream5;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
79 hdma_usart1_rx.Init.Channel = DMA_CHANNEL_4;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
80 hdma_usart1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; //DMA_MEMORY_TO_PERIPH;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
81 hdma_usart1_rx.Init.PeriphInc = DMA_PINC_DISABLE;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
82 hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
83 hdma_usart1_rx.Init.PeriphDataAlignment = DMA_MDATAALIGN_BYTE;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
84 hdma_usart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
85 hdma_usart1_rx.Init.Mode = DMA_NORMAL;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
86 hdma_usart1_rx.Init.Priority = DMA_PRIORITY_LOW;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
87 hdma_usart1_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
88 HAL_DMA_Init(&hdma_usart1_rx);
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
89
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
90 __HAL_LINKDMA(&huart1,hdmarx,hdma_usart1_rx);
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
91
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
92 /* DMA interrupt init */
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
93 HAL_NVIC_SetPriority(DMA2_Stream5_IRQn, 0, 0);
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
94 HAL_NVIC_EnableIRQ(DMA2_Stream5_IRQn);
38
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
95 }
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
96
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
97
662
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
98 uint32_t dataValue = 0;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
99
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
100 void HandleUARTData(void)
38
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
101 {
662
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
102 uint8_t localRX = rxReadIndex;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
103 uint8_t dataType = 0;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
104 static receiveState_t rxState = RX_Ready;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
105 static uint32_t lastReceiveTick = 0;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
106
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
107 while(localRX != rxWriteIndex)
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
108 {
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
109 lastReceiveTick = HAL_GetTick();
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
110 if(rxState == RX_Ready) /* identify data content */
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
111 {
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
112 switch(rxBuffer[localRX])
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
113 {
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
114 case 'l':
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
115 case 'D':
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
116 case 'Z':
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
117 dataType = rxBuffer[localRX];
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
118 rxState = RX_Data0;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
119 dataValue = 0;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
120 break;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
121
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
122 default: /* unknown or corrupted => ignore */
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
123 break;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
124 }
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
125 }
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
126 else if((rxState >= RX_Data0) && (rxState <= RX_Data4))
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
127 {
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
128 if((rxBuffer[localRX] >= '0') && (rxBuffer[localRX] <= '9'))
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
129 {
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
130 dataValue = dataValue * 10 + (rxBuffer[localRX] - '0');
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
131 rxState++;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
132 }
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
133 }
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
134 if((rxBuffer[localRX] == ' ') || (rxBuffer[localRX] == '\n')) /* Abort data detection */
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
135 {
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
136 if(rxState == RX_DataComplete)
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
137 {
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
138 if(externalInterface_GetCO2State() == 0)
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
139 {
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
140 externalInterface_SetCO2State(EXT_INTERFACE_33V_ON);
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
141 }
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
142 switch(dataType)
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
143 {
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
144 case 'D': externalInterface_SetCO2SignalStrength(dataValue);
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
145 break;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
146 case 'l': LED_ZeroOffset = dataValue;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
147 break;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
148 case 'Z': externalInterface_SetCO2Value(dataValue);
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
149 break;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
150 default: break;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
151 }
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
152 }
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
153 if(rxState != RX_Data0) /* reset state machine because message in wrong format */
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
154 {
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
155 rxState = RX_Ready;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
156 }
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
157 }
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
158
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
159 localRX++;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
160 rxReadIndex++;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
161 if(rxReadIndex >= CHUNK_SIZE * CHUNKS_PER_BUFFER)
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
162 {
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
163 localRX = 0;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
164 rxReadIndex = 0;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
165 }
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
166 }
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
167
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
168 if(time_elapsed_ms(lastReceiveTick,HAL_GetTick()) > 2000) /* check for communication timeout */
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
169 {
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
170 externalInterface_SetCO2State(0);
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
171 }
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
172
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
173 if((dmaActive == 0) && (externalInterface_isEnabledPower33())) /* Should never happen in normal operation => restart in case of communication error */
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
174 {
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
175 if(HAL_OK == HAL_UART_Receive_DMA (&huart1, &rxBuffer[rxWriteIndex], CHUNK_SIZE))
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
176 {
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
177 dmaActive = 1;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
178 }
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
179 }
38
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
180 }
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
181
662
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
182 void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
38
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
183 {
662
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
184 if(huart == &huart1)
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
185 {
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
186 dmaActive = 0;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
187 rxWriteIndex+=CHUNK_SIZE;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
188 if(rxWriteIndex >= CHUNK_SIZE * CHUNKS_PER_BUFFER)
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
189 {
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
190 rxWriteIndex = 0;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
191 }
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
192 if((rxWriteIndex / CHUNK_SIZE) != (rxReadIndex / CHUNK_SIZE)) /* start next transfer if we did not catch up with read index */
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
193 {
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
194 if(externalInterface_isEnabledPower33())
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
195 {
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
196 if(HAL_OK == HAL_UART_Receive_DMA (&huart1, &rxBuffer[rxWriteIndex], CHUNK_SIZE))
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
197 {
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
198 dmaActive = 1;
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
199 }
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
200 }
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
201 }
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
202 }
38
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
203 }
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
204
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
205
662
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
206
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
207
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
208
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
209
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
210
1b995079c045 PSCR Mode
heinrichs weikamp
parents: 38
diff changeset
211
38
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
212 /************************ (C) COPYRIGHT heinrichs weikamp *****END OF FILE****/