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annotate Common/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dfsdm.h @ 248:ac2b06b5d09f bm-1
Fix stupid commit error
Forgot to add one file, so add this to make things compile.
Signed-off-by: Jan Mulder <jlmulder@xs4all.nl>
author | Jan Mulder <jlmulder@xs4all.nl> |
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date | Wed, 10 Apr 2019 17:55:46 +0200 |
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1 /** |
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2 ****************************************************************************** |
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3 * @file stm32f4xx_hal_dfsdm.h |
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4 * @author MCD Application Team |
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5 * @brief Header file of DFSDM HAL module. |
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6 ****************************************************************************** |
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7 * @attention |
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8 * |
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9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
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10 * |
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11 * Redistribution and use in source and binary forms, with or without modification, |
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12 * are permitted provided that the following conditions are met: |
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13 * 1. Redistributions of source code must retain the above copyright notice, |
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14 * this list of conditions and the following disclaimer. |
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15 * 2. Redistributions in binary form must reproduce the above copyright notice, |
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16 * this list of conditions and the following disclaimer in the documentation |
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17 * and/or other materials provided with the distribution. |
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18 * 3. Neither the name of STMicroelectronics nor the names of its contributors |
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19 * may be used to endorse or promote products derived from this software |
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20 * without specific prior written permission. |
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21 * |
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22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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32 * |
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33 ****************************************************************************** |
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34 */ |
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35 |
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36 /* Define to prevent recursive inclusion -------------------------------------*/ |
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37 #ifndef __STM32F4xx_HAL_DFSDM_H |
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38 #define __STM32F4xx_HAL_DFSDM_H |
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39 |
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40 #ifdef __cplusplus |
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41 extern "C" { |
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42 #endif |
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43 |
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44 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) |
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45 /* Includes ------------------------------------------------------------------*/ |
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46 #include "stm32f4xx_hal_def.h" |
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47 |
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48 /** @addtogroup STM32F4xx_HAL_Driver |
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49 * @{ |
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50 */ |
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51 |
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52 /** @addtogroup DFSDM |
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53 * @{ |
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54 */ |
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55 |
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56 /* Exported types ------------------------------------------------------------*/ |
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57 /** @defgroup DFSDM_Exported_Types DFSDM Exported Types |
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58 * @{ |
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59 */ |
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60 |
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61 /** |
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62 * @brief HAL DFSDM Channel states definition |
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63 */ |
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64 typedef enum |
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65 { |
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66 HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */ |
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67 HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, /*!< DFSDM channel initialized and ready for use */ |
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68 HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU /*!< DFSDM channel state error */ |
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69 }HAL_DFSDM_Channel_StateTypeDef; |
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70 |
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71 /** |
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72 * @brief DFSDM channel output clock structure definition |
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73 */ |
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74 typedef struct |
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75 { |
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76 FunctionalState Activation; /*!< Output clock enable/disable */ |
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77 uint32_t Selection; /*!< Output clock is system clock or audio clock. |
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78 This parameter can be a value of @ref DFSDM_Channel_OuputClock */ |
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79 uint32_t Divider; /*!< Output clock divider. |
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80 This parameter must be a number between Min_Data = 2 and Max_Data = 256 */ |
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81 }DFSDM_Channel_OutputClockTypeDef; |
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82 |
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83 /** |
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84 * @brief DFSDM channel input structure definition |
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85 */ |
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86 typedef struct |
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87 { |
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88 uint32_t Multiplexer; /*!< Input is external serial inputs or internal register. |
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89 This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */ |
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90 uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register. |
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91 This parameter can be a value of @ref DFSDM_Channel_DataPacking */ |
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92 uint32_t Pins; /*!< Input pins are taken from same or following channel. |
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93 This parameter can be a value of @ref DFSDM_Channel_InputPins */ |
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94 }DFSDM_Channel_InputTypeDef; |
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95 |
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96 /** |
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97 * @brief DFSDM channel serial interface structure definition |
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98 */ |
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99 typedef struct |
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100 { |
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101 uint32_t Type; /*!< SPI or Manchester modes. |
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102 This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */ |
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103 uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point). |
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104 This parameter can be a value of @ref DFSDM_Channel_SpiClock */ |
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105 }DFSDM_Channel_SerialInterfaceTypeDef; |
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106 |
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107 /** |
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108 * @brief DFSDM channel analog watchdog structure definition |
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109 */ |
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110 typedef struct |
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111 { |
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112 uint32_t FilterOrder; /*!< Analog watchdog Sinc filter order. |
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113 This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */ |
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114 uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio. |
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115 This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ |
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116 }DFSDM_Channel_AwdTypeDef; |
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117 |
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118 /** |
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119 * @brief DFSDM channel init structure definition |
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120 */ |
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121 typedef struct |
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122 { |
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123 DFSDM_Channel_OutputClockTypeDef OutputClock; /*!< DFSDM channel output clock parameters */ |
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124 DFSDM_Channel_InputTypeDef Input; /*!< DFSDM channel input parameters */ |
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125 DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /*!< DFSDM channel serial interface parameters */ |
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126 DFSDM_Channel_AwdTypeDef Awd; /*!< DFSDM channel analog watchdog parameters */ |
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127 int32_t Offset; /*!< DFSDM channel offset. |
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128 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ |
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129 uint32_t RightBitShift; /*!< DFSDM channel right bit shift. |
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130 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ |
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131 }DFSDM_Channel_InitTypeDef; |
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132 |
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133 /** |
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134 * @brief DFSDM channel handle structure definition |
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135 */ |
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136 typedef struct |
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137 { |
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138 DFSDM_Channel_TypeDef *Instance; /*!< DFSDM channel instance */ |
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139 DFSDM_Channel_InitTypeDef Init; /*!< DFSDM channel init parameters */ |
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140 HAL_DFSDM_Channel_StateTypeDef State; /*!< DFSDM channel state */ |
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141 }DFSDM_Channel_HandleTypeDef; |
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142 |
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143 /** |
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144 * @brief HAL DFSDM Filter states definition |
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145 */ |
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146 typedef enum |
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147 { |
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148 HAL_DFSDM_FILTER_STATE_RESET = 0x00U, /*!< DFSDM filter not initialized */ |
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149 HAL_DFSDM_FILTER_STATE_READY = 0x01U, /*!< DFSDM filter initialized and ready for use */ |
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150 HAL_DFSDM_FILTER_STATE_REG = 0x02U, /*!< DFSDM filter regular conversion in progress */ |
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151 HAL_DFSDM_FILTER_STATE_INJ = 0x03U, /*!< DFSDM filter injected conversion in progress */ |
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152 HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, /*!< DFSDM filter regular and injected conversions in progress */ |
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153 HAL_DFSDM_FILTER_STATE_ERROR = 0xFFU /*!< DFSDM filter state error */ |
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154 }HAL_DFSDM_Filter_StateTypeDef; |
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155 |
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156 /** |
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157 * @brief DFSDM filter regular conversion parameters structure definition |
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158 */ |
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159 typedef struct |
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160 { |
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161 uint32_t Trigger; /*!< Trigger used to start regular conversion: software or synchronous. |
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162 This parameter can be a value of @ref DFSDM_Filter_Trigger */ |
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163 FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */ |
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164 FunctionalState DmaMode; /*!< Enable/disable DMA for regular conversion */ |
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165 }DFSDM_Filter_RegularParamTypeDef; |
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166 |
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167 /** |
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168 * @brief DFSDM filter injected conversion parameters structure definition |
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169 */ |
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170 typedef struct |
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171 { |
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172 uint32_t Trigger; /*!< Trigger used to start injected conversion: software, external or synchronous. |
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173 This parameter can be a value of @ref DFSDM_Filter_Trigger */ |
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174 FunctionalState ScanMode; /*!< Enable/disable scanning mode for injected conversion */ |
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175 FunctionalState DmaMode; /*!< Enable/disable DMA for injected conversion */ |
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176 uint32_t ExtTrigger; /*!< External trigger. |
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177 This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */ |
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178 uint32_t ExtTriggerEdge; /*!< External trigger edge: rising, falling or both. |
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179 This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */ |
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180 }DFSDM_Filter_InjectedParamTypeDef; |
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181 |
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182 /** |
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183 * @brief DFSDM filter parameters structure definition |
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184 */ |
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185 typedef struct |
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186 { |
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187 uint32_t SincOrder; /*!< Sinc filter order. |
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188 This parameter can be a value of @ref DFSDM_Filter_SincOrder */ |
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189 uint32_t Oversampling; /*!< Filter oversampling ratio. |
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190 This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */ |
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191 uint32_t IntOversampling; /*!< Integrator oversampling ratio. |
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192 This parameter must be a number between Min_Data = 1 and Max_Data = 256 */ |
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193 }DFSDM_Filter_FilterParamTypeDef; |
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194 |
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195 /** |
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196 * @brief DFSDM filter init structure definition |
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197 */ |
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198 typedef struct |
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199 { |
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200 DFSDM_Filter_RegularParamTypeDef RegularParam; /*!< DFSDM regular conversion parameters */ |
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201 DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */ |
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202 DFSDM_Filter_FilterParamTypeDef FilterParam; /*!< DFSDM filter parameters */ |
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203 }DFSDM_Filter_InitTypeDef; |
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204 |
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205 /** |
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206 * @brief DFSDM filter handle structure definition |
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207 */ |
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208 typedef struct |
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209 { |
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210 DFSDM_Filter_TypeDef *Instance; /*!< DFSDM filter instance */ |
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211 DFSDM_Filter_InitTypeDef Init; /*!< DFSDM filter init parameters */ |
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212 DMA_HandleTypeDef *hdmaReg; /*!< Pointer on DMA handler for regular conversions */ |
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213 DMA_HandleTypeDef *hdmaInj; /*!< Pointer on DMA handler for injected conversions */ |
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214 uint32_t RegularContMode; /*!< Regular conversion continuous mode */ |
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215 uint32_t RegularTrigger; /*!< Trigger used for regular conversion */ |
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216 uint32_t InjectedTrigger; /*!< Trigger used for injected conversion */ |
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217 uint32_t ExtTriggerEdge; /*!< Rising, falling or both edges selected */ |
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218 FunctionalState InjectedScanMode; /*!< Injected scanning mode */ |
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219 uint32_t InjectedChannelsNbr; /*!< Number of channels in injected sequence */ |
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220 uint32_t InjConvRemaining; /*!< Injected conversions remaining */ |
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221 HAL_DFSDM_Filter_StateTypeDef State; /*!< DFSDM filter state */ |
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222 uint32_t ErrorCode; /*!< DFSDM filter error code */ |
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223 }DFSDM_Filter_HandleTypeDef; |
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224 |
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225 /** |
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226 * @brief DFSDM filter analog watchdog parameters structure definition |
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227 */ |
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228 typedef struct |
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229 { |
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230 uint32_t DataSource; /*!< Values from digital filter or from channel watchdog filter. |
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231 This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */ |
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232 uint32_t Channel; /*!< Analog watchdog channel selection. |
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233 This parameter can be a values combination of @ref DFSDM_Channel_Selection */ |
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234 int32_t HighThreshold; /*!< High threshold for the analog watchdog. |
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235 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ |
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236 int32_t LowThreshold; /*!< Low threshold for the analog watchdog. |
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237 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ |
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238 uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event. |
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239 This parameter can be a values combination of @ref DFSDM_BreakSignals */ |
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240 uint32_t LowBreakSignal; /*!< Break signal assigned to analog watchdog low threshold event. |
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241 This parameter can be a values combination of @ref DFSDM_BreakSignals */ |
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242 }DFSDM_Filter_AwdParamTypeDef; |
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243 |
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244 /** |
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245 * @} |
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246 */ |
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247 #if defined(SYSCFG_MCHDLYCR_BSCKSEL) |
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248 /** |
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249 * @brief Synchronization parameters structure definition for STM32F413xx/STM32F423xx devices |
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250 */ |
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251 typedef struct |
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252 { |
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253 uint32_t DFSDM1ClockIn; /*!< Source selection for DFSDM1_Ckin. |
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254 This parameter can be a value of @ref DFSDM_1_CLOCKIN_SELECTION*/ |
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255 uint32_t DFSDM2ClockIn; /*!< Source selection for DFSDM2_Ckin. |
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256 This parameter can be a value of @ref DFSDM_2_CLOCKIN_SELECTION*/ |
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257 uint32_t DFSDM1ClockOut; /*!< Source selection for DFSDM1_Ckout. |
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258 This parameter can be a value of @ref DFSDM_1_CLOCKOUT_SELECTION*/ |
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259 uint32_t DFSDM2ClockOut; /*!< Source selection for DFSDM2_Ckout. |
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260 This parameter can be a value of @ref DFSDM_2_CLOCKOUT_SELECTION*/ |
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261 uint32_t DFSDM1BitClkDistribution; /*!< Distribution of the DFSDM1 bitstream clock gated by TIM4 OC1 or TIM4 OC2. |
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262 This parameter can be a value of @ref DFSDM_1_BIT_STREAM_DISTRIBUTION |
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263 @note The DFSDM2 audio gated by TIM4 OC2 can be injected on CKIN0 or CKIN2 |
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264 @note The DFSDM2 audio gated by TIM4 OC1 can be injected on CKIN1 or CKIN3 */ |
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265 uint32_t DFSDM2BitClkDistribution; /*!< Distribution of the DFSDM2 bitstream clock gated by TIM3 OC1 or TIM3 OC2 or TIM3 OC3 or TIM3 OC4. |
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266 This parameter can be a value of @ref DFSDM_2_BIT_STREAM_DISTRIBUTION |
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267 @note The DFSDM2 audio gated by TIM3 OC4 can be injected on CKIN0 or CKIN4 |
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268 @note The DFSDM2 audio gated by TIM3 OC3 can be injected on CKIN1 or CKIN5 |
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269 @note The DFSDM2 audio gated by TIM3 OC2 can be injected on CKIN2 or CKIN6 |
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270 @note The DFSDM2 audio gated by TIM3 OC1 can be injected on CKIN3 or CKIN7 */ |
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271 uint32_t DFSDM1DataDistribution; /*!< Source selection for DatIn0 and DatIn2 of DFSDM1. |
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272 This parameter can be a value of @ref DFSDM_1_DATA_DISTRIBUTION */ |
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273 uint32_t DFSDM2DataDistribution; /*!< Source selection for DatIn0, DatIn2, DatIn4 and DatIn6 of DFSDM2. |
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274 This parameter can be a value of @ref DFSDM_2_DATA_DISTRIBUTION */ |
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275 }DFSDM_MultiChannelConfigTypeDef; |
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276 #endif /* SYSCFG_MCHDLYCR_BSCKSEL */ |
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277 /** |
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278 * @} |
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279 */ |
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280 |
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281 /* End of exported types -----------------------------------------------------*/ |
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282 |
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283 /* Exported constants --------------------------------------------------------*/ |
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284 /** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants |
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285 * @{ |
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286 */ |
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287 |
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288 /** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection |
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289 * @{ |
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290 */ |
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291 #define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM 0x00000000U /*!< Source for ouput clock is system clock */ |
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292 #define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */ |
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293 /** |
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294 * @} |
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295 */ |
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296 |
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297 /** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer |
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298 * @{ |
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299 */ |
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300 #define DFSDM_CHANNEL_EXTERNAL_INPUTS 0x00000000U /*!< Data are taken from external inputs */ |
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301 #define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1 /*!< Data are taken from internal register */ |
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302 /** |
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303 * @} |
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304 */ |
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305 |
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306 /** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing |
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307 * @{ |
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308 */ |
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309 #define DFSDM_CHANNEL_STANDARD_MODE 0x00000000U /*!< Standard data packing mode */ |
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310 #define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */ |
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311 #define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */ |
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312 /** |
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313 * @} |
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314 */ |
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315 |
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316 /** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins |
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317 * @{ |
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318 */ |
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319 #define DFSDM_CHANNEL_SAME_CHANNEL_PINS 0x00000000U /*!< Input from pins on same channel */ |
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320 #define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL /*!< Input from pins on following channel */ |
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321 /** |
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322 * @} |
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323 */ |
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324 |
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325 /** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type |
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326 * @{ |
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327 */ |
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328 #define DFSDM_CHANNEL_SPI_RISING 0x00000000U /*!< SPI with rising edge */ |
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329 #define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0 /*!< SPI with falling edge */ |
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330 #define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1 /*!< Manchester with rising edge */ |
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331 #define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP /*!< Manchester with falling edge */ |
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332 /** |
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333 * @} |
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334 */ |
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335 |
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336 /** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection |
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337 * @{ |
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338 */ |
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339 #define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL 0x00000000U /*!< External SPI clock */ |
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340 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */ |
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341 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */ |
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342 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL /*!< Internal SPI clock divided by 2, rising edge */ |
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343 /** |
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344 * @} |
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345 */ |
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346 |
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347 /** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order |
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348 * @{ |
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349 */ |
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350 #define DFSDM_CHANNEL_FASTSINC_ORDER 0x00000000U /*!< FastSinc filter type */ |
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351 #define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */ |
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352 #define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */ |
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353 #define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD /*!< Sinc 3 filter type */ |
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354 /** |
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355 * @} |
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356 */ |
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357 |
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358 /** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger |
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359 * @{ |
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360 */ |
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361 #define DFSDM_FILTER_SW_TRIGGER 0x00000000U /*!< Software trigger */ |
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362 #define DFSDM_FILTER_SYNC_TRIGGER 0x00000001U /*!< Synchronous with DFSDM_FLT0 */ |
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363 #define DFSDM_FILTER_EXT_TRIGGER 0x00000002U /*!< External trigger (only for injected conversion) */ |
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364 /** |
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365 * @} |
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366 */ |
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367 |
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368 /** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger |
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369 * @{ |
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370 */ |
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371 #if defined(STM32F413xx) || defined(STM32F423xx) |
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372 /* Trigger for stm32f413xx and STM32f423xx devices */ |
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373 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For All DFSDM1/2 filters */ |
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374 #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_0 /*!< For All DFSDM1/2 filters */ |
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375 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For All DFSDM1/2 filters */ |
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376 #define DFSDM_FILTER_EXT_TRIG_TIM10_OC1 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM1 filter 0 and 1 and DFSDM2 filter 0, 1 and 2 */ |
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377 #define DFSDM_FILTER_EXT_TRIG_TIM2_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM2 filter 3 */ |
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378 #define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM1 filter 0 and 1 and DFSDM2 filter 0, 1 and 2 */ |
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379 #define DFSDM_FILTER_EXT_TRIG_TIM11_OC1 DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM2 filter 3 */ |
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380 #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM1 filter 0 and 1 and DFSDM2 filter 0 and 1 */ |
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381 #define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM2 filter 2 and 3*/ |
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382 #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For All DFSDM1/2 filters */ |
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383 #define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL /*!< For All DFSDM1/2 filters */ |
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384 #else |
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385 /* Trigger for stm32f412xx devices */ |
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386 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For DFSDM1 filter 0 and 1*/ |
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387 #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM1 filter 0 and 1*/ |
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388 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM1 filter 0 and 1*/ |
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389 #define DFSDM_FILTER_EXT_TRIG_TIM10_OC1 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM1 filter 0 and 1*/ |
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390 #define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM1 filter 0 and 1*/ |
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391 #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM1 filter 0 and 1*/ |
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392 #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM1 filter 0 and 1*/ |
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393 #define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL /*!< For DFSDM1 filter 0 and 1*/ |
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394 #endif |
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395 /** |
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396 * @} |
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397 */ |
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398 |
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399 /** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge |
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400 * @{ |
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401 */ |
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402 #define DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0 /*!< External rising edge */ |
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403 #define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1 /*!< External falling edge */ |
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404 #define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN /*!< External rising and falling edges */ |
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405 /** |
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406 * @} |
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407 */ |
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408 |
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409 /** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order |
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410 * @{ |
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411 */ |
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412 #define DFSDM_FILTER_FASTSINC_ORDER 0x00000000U /*!< FastSinc filter type */ |
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413 #define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0 /*!< Sinc 1 filter type */ |
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414 #define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1 /*!< Sinc 2 filter type */ |
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415 #define DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */ |
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416 #define DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2 /*!< Sinc 4 filter type */ |
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417 #define DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) /*!< Sinc 5 filter type */ |
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418 /** |
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419 * @} |
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420 */ |
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421 |
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422 /** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source |
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423 * @{ |
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424 */ |
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425 #define DFSDM_FILTER_AWD_FILTER_DATA 0x00000000U /*!< From digital filter */ |
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426 #define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL /*!< From analog watchdog channel */ |
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427 /** |
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428 * @} |
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429 */ |
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430 |
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431 /** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code |
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432 * @{ |
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433 */ |
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434 #define DFSDM_FILTER_ERROR_NONE 0x00000000U /*!< No error */ |
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435 #define DFSDM_FILTER_ERROR_REGULAR_OVERRUN 0x00000001U /*!< Overrun occurs during regular conversion */ |
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436 #define DFSDM_FILTER_ERROR_INJECTED_OVERRUN 0x00000002U /*!< Overrun occurs during injected conversion */ |
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437 #define DFSDM_FILTER_ERROR_DMA 0x00000003U /*!< DMA error occurs */ |
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438 /** |
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439 * @} |
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440 */ |
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441 |
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442 /** @defgroup DFSDM_BreakSignals DFSDM break signals |
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443 * @{ |
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444 */ |
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445 #define DFSDM_NO_BREAK_SIGNAL 0x00000000U /*!< No break signal */ |
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446 #define DFSDM_BREAK_SIGNAL_0 0x00000001U /*!< Break signal 0 */ |
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447 #define DFSDM_BREAK_SIGNAL_1 0x00000002U /*!< Break signal 1 */ |
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448 #define DFSDM_BREAK_SIGNAL_2 0x00000004U /*!< Break signal 2 */ |
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449 #define DFSDM_BREAK_SIGNAL_3 0x00000008U /*!< Break signal 3 */ |
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450 /** |
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451 * @} |
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452 */ |
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453 |
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454 /** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection |
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455 * @{ |
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456 */ |
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457 /* DFSDM Channels ------------------------------------------------------------*/ |
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458 /* The DFSDM channels are defined as follows: |
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459 - in 16-bit LSB the channel mask is set |
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460 - in 16-bit MSB the channel number is set |
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461 e.g. for channel 3 definition: |
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462 - the channel mask is 0x00000008 (bit 3 is set) |
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463 - the channel number 3 is 0x00030000 |
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464 --> Consequently, channel 3 definition is 0x00000008 | 0x00030000 = 0x00030008 */ |
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465 #define DFSDM_CHANNEL_0 0x00000001U |
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466 #define DFSDM_CHANNEL_1 0x00010002U |
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467 #define DFSDM_CHANNEL_2 0x00020004U |
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468 #define DFSDM_CHANNEL_3 0x00030008U |
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469 #define DFSDM_CHANNEL_4 0x00040010U /* only for stmm32f413xx and stm32f423xx devices */ |
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470 #define DFSDM_CHANNEL_5 0x00050020U /* only for stmm32f413xx and stm32f423xx devices */ |
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471 #define DFSDM_CHANNEL_6 0x00060040U /* only for stmm32f413xx and stm32f423xx devices */ |
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472 #define DFSDM_CHANNEL_7 0x00070080U /* only for stmm32f413xx and stm32f423xx devices */ |
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473 /** |
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474 * @} |
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475 */ |
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476 |
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477 /** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode |
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478 * @{ |
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479 */ |
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480 #define DFSDM_CONTINUOUS_CONV_OFF 0x00000000U /*!< Conversion are not continuous */ |
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481 #define DFSDM_CONTINUOUS_CONV_ON 0x00000001U /*!< Conversion are continuous */ |
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482 /** |
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483 * @} |
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484 */ |
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485 |
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486 /** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold |
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487 * @{ |
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488 */ |
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489 #define DFSDM_AWD_HIGH_THRESHOLD 0x00000000U /*!< Analog watchdog high threshold */ |
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490 #define DFSDM_AWD_LOW_THRESHOLD 0x00000001U /*!< Analog watchdog low threshold */ |
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491 /** |
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492 * @} |
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493 */ |
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494 |
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495 #if defined(SYSCFG_MCHDLYCR_BSCKSEL) |
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496 /** @defgroup DFSDM_1_CLOCKOUT_SELECTION DFSDM1 ClockOut Selection |
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497 * @{ |
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498 */ |
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499 #define DFSDM1_CKOUT_DFSDM2_CKOUT 0x00000080U |
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500 #define DFSDM1_CKOUT_DFSDM1 0x00000000U |
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501 /** |
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502 * @} |
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503 */ |
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504 |
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505 /** @defgroup DFSDM_2_CLOCKOUT_SELECTION DFSDM2 ClockOut Selection |
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506 * @{ |
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507 */ |
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508 #define DFSDM2_CKOUT_DFSDM2_CKOUT 0x00040000U |
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509 #define DFSDM2_CKOUT_DFSDM2 0x00000000U |
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510 /** |
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511 * @} |
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512 */ |
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513 |
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514 /** @defgroup DFSDM_1_CLOCKIN_SELECTION DFSDM1 ClockIn Selection |
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515 * @{ |
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516 */ |
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517 #define DFSDM1_CKIN_DFSDM2_CKOUT 0x00000040U |
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518 #define DFSDM1_CKIN_PAD 0x00000000U |
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519 /** |
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520 * @} |
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521 */ |
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522 |
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523 /** @defgroup DFSDM_2_CLOCKIN_SELECTION DFSDM2 ClockIn Selection |
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524 * @{ |
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525 */ |
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526 #define DFSDM2_CKIN_DFSDM2_CKOUT 0x00020000U |
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527 #define DFSDM2_CKIN_PAD 0x00000000U |
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528 /** |
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529 * @} |
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530 */ |
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531 |
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532 /** @defgroup DFSDM_1_BIT_STREAM_DISTRIBUTION DFSDM1 Bit Stream Distribution |
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533 * @{ |
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534 */ |
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535 #define DFSDM1_T4_OC2_BITSTREAM_CKIN0 0x00000000U /* TIM4_OC2 to CLKIN0 */ |
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536 #define DFSDM1_T4_OC2_BITSTREAM_CKIN2 SYSCFG_MCHDLYCR_DFSDM1CK02SEL /* TIM4_OC2 to CLKIN2 */ |
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537 #define DFSDM1_T4_OC1_BITSTREAM_CKIN3 SYSCFG_MCHDLYCR_DFSDM1CK13SEL /* TIM4_OC1 to CLKIN3 */ |
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538 #define DFSDM1_T4_OC1_BITSTREAM_CKIN1 0x00000000U /* TIM4_OC1 to CLKIN1 */ |
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539 /** |
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540 * @} |
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541 */ |
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542 |
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543 /** @defgroup DFSDM_2_BIT_STREAM_DISTRIBUTION DFSDM12 Bit Stream Distribution |
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544 * @{ |
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545 */ |
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546 #define DFSDM2_T3_OC4_BITSTREAM_CKIN0 0x00000000U /* TIM3_OC4 to CKIN0 */ |
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547 #define DFSDM2_T3_OC4_BITSTREAM_CKIN4 SYSCFG_MCHDLYCR_DFSDM2CK04SEL /* TIM3_OC4 to CKIN4 */ |
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548 #define DFSDM2_T3_OC3_BITSTREAM_CKIN5 SYSCFG_MCHDLYCR_DFSDM2CK15SEL /* TIM3_OC3 to CKIN5 */ |
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549 #define DFSDM2_T3_OC3_BITSTREAM_CKIN1 0x00000000U /* TIM3_OC3 to CKIN1 */ |
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550 #define DFSDM2_T3_OC2_BITSTREAM_CKIN6 SYSCFG_MCHDLYCR_DFSDM2CK26SEL /* TIM3_OC2to CKIN6 */ |
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551 #define DFSDM2_T3_OC2_BITSTREAM_CKIN2 0x00000000U /* TIM3_OC2 to CKIN2 */ |
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552 #define DFSDM2_T3_OC1_BITSTREAM_CKIN3 0x00000000U /* TIM3_OC1 to CKIN3 */ |
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553 #define DFSDM2_T3_OC1_BITSTREAM_CKIN7 SYSCFG_MCHDLYCR_DFSDM2CK37SEL /* TIM3_OC1 to CKIN7 */ |
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554 /** |
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555 * @} |
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556 */ |
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557 |
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558 /** @defgroup DFSDM_1_DATA_DISTRIBUTION DFSDM1 Data Distribution |
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559 * @{ |
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560 */ |
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561 #define DFSDM1_DATIN0_TO_DATIN0_PAD 0x00000000U |
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562 #define DFSDM1_DATIN0_TO_DATIN1_PAD SYSCFG_MCHDLYCR_DFSDM1D0SEL |
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563 #define DFSDM1_DATIN2_TO_DATIN2_PAD 0x00000000U |
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564 #define DFSDM1_DATIN2_TO_DATIN3_PAD SYSCFG_MCHDLYCR_DFSDM1D2SEL |
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565 /** |
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566 * @} |
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567 */ |
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568 |
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569 /** @defgroup DFSDM_2_DATA_DISTRIBUTION DFSDM2 Data Distribution |
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570 * @{ |
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571 */ |
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572 #define DFSDM2_DATIN0_TO_DATIN0_PAD 0x00000000U |
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573 #define DFSDM2_DATIN0_TO_DATIN1_PAD SYSCFG_MCHDLYCR_DFSDM2D0SEL |
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574 #define DFSDM2_DATIN2_TO_DATIN2_PAD 0x00000000U |
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575 #define DFSDM2_DATIN2_TO_DATIN3_PAD SYSCFG_MCHDLYCR_DFSDM2D2SEL |
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576 #define DFSDM2_DATIN4_TO_DATIN4_PAD 0x00000000U |
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577 #define DFSDM2_DATIN4_TO_DATIN5_PAD SYSCFG_MCHDLYCR_DFSDM2D4SEL |
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578 #define DFSDM2_DATIN6_TO_DATIN6_PAD 0x00000000U |
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579 #define DFSDM2_DATIN6_TO_DATIN7_PAD SYSCFG_MCHDLYCR_DFSDM2D6SEL |
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580 /** |
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581 * @} |
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582 */ |
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583 |
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584 /** @defgroup HAL_MCHDLY_CLOCK HAL MCHDLY Clock enable |
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585 * @{ |
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586 */ |
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587 #define HAL_MCHDLY_CLOCK_DFSDM2 SYSCFG_MCHDLYCR_MCHDLY2EN |
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588 #define HAL_MCHDLY_CLOCK_DFSDM1 SYSCFG_MCHDLYCR_MCHDLY1EN |
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589 /** |
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590 * @} |
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591 */ |
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592 |
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593 /** @defgroup DFSDM_CLOCKIN_SOURCE DFSDM Clock In Source Selection |
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594 * @{ |
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595 */ |
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596 #define HAL_DFSDM2_CKIN_PAD 0x00040000U |
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597 #define HAL_DFSDM2_CKIN_DM SYSCFG_MCHDLYCR_DFSDM2CFG |
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598 #define HAL_DFSDM1_CKIN_PAD 0x00000000U |
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599 #define HAL_DFSDM1_CKIN_DM SYSCFG_MCHDLYCR_DFSDM1CFG |
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600 /** |
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601 * @} |
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602 */ |
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|
603 |
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|
604 /** @defgroup DFSDM_CLOCKOUT_SOURCE DFSDM Clock Source Selection |
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605 * @{ |
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606 */ |
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607 #define HAL_DFSDM2_CKOUT_DFSDM2 0x10000000U |
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608 #define HAL_DFSDM2_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM2CKOSEL |
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609 #define HAL_DFSDM1_CKOUT_DFSDM1 0x00000000U |
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610 #define HAL_DFSDM1_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM1CKOSEL |
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611 /** |
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612 * @} |
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613 */ |
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614 |
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615 /** @defgroup DFSDM_DATAIN0_SOURCE DFSDM Source Selection For DATAIN0 |
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616 * @{ |
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617 */ |
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618 #define HAL_DATAIN0_DFSDM2_PAD 0x10000000U |
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619 #define HAL_DATAIN0_DFSDM2_DATAIN1 SYSCFG_MCHDLYCR_DFSDM2D0SEL |
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620 #define HAL_DATAIN0_DFSDM1_PAD 0x00000000U |
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621 #define HAL_DATAIN0_DFSDM1_DATAIN1 SYSCFG_MCHDLYCR_DFSDM1D0SEL |
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622 /** |
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623 * @} |
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624 */ |
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625 |
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626 /** @defgroup DFSDM_DATAIN2_SOURCE DFSDM Source Selection For DATAIN2 |
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627 * @{ |
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628 */ |
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629 #define HAL_DATAIN2_DFSDM2_PAD 0x10000000U |
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630 #define HAL_DATAIN2_DFSDM2_DATAIN3 SYSCFG_MCHDLYCR_DFSDM2D2SEL |
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631 #define HAL_DATAIN2_DFSDM1_PAD 0x00000000U |
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632 #define HAL_DATAIN2_DFSDM1_DATAIN3 SYSCFG_MCHDLYCR_DFSDM1D2SEL |
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633 /** |
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634 * @} |
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635 */ |
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636 |
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637 /** @defgroup DFSDM_DATAIN4_SOURCE DFSDM Source Selection For DATAIN4 |
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638 * @{ |
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639 */ |
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640 #define HAL_DATAIN4_DFSDM2_PAD 0x00000000U |
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641 #define HAL_DATAIN4_DFSDM2_DATAIN5 SYSCFG_MCHDLYCR_DFSDM2D4SEL |
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642 /** |
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643 * @} |
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644 */ |
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645 |
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646 /** @defgroup DFSDM_DATAIN6_SOURCE DFSDM Source Selection For DATAIN6 |
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647 * @{ |
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648 */ |
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649 #define HAL_DATAIN6_DFSDM2_PAD 0x00000000U |
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650 #define HAL_DATAIN6_DFSDM2_DATAIN7 SYSCFG_MCHDLYCR_DFSDM2D6SEL |
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651 /** |
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652 * @} |
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653 */ |
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654 |
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655 /** @defgroup DFSDM1_CLKIN_SOURCE DFSDM1 Source Selection For CLKIN |
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656 * @{ |
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657 */ |
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658 #define HAL_DFSDM1_CLKIN0_TIM4OC2 0x01000000U |
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659 #define HAL_DFSDM1_CLKIN2_TIM4OC2 SYSCFG_MCHDLYCR_DFSDM1CK02SEL |
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660 #define HAL_DFSDM1_CLKIN1_TIM4OC1 0x02000000U |
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661 #define HAL_DFSDM1_CLKIN3_TIM4OC1 SYSCFG_MCHDLYCR_DFSDM1CK13SEL |
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662 /** |
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663 * @} |
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664 */ |
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665 |
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666 /** @defgroup DFSDM2_CLKIN_SOURCE DFSDM2 Source Selection For CLKIN |
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667 * @{ |
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668 */ |
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669 #define HAL_DFSDM2_CLKIN0_TIM3OC4 0x04000000U |
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670 #define HAL_DFSDM2_CLKIN4_TIM3OC4 SYSCFG_MCHDLYCR_DFSDM2CK04SEL |
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671 #define HAL_DFSDM2_CLKIN1_TIM3OC3 0x08000000U |
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672 #define HAL_DFSDM2_CLKIN5_TIM3OC3 SYSCFG_MCHDLYCR_DFSDM2CK15SEL |
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673 #define HAL_DFSDM2_CLKIN2_TIM3OC2 0x10000000U |
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674 #define HAL_DFSDM2_CLKIN6_TIM3OC2 SYSCFG_MCHDLYCR_DFSDM2CK26SEL |
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675 #define HAL_DFSDM2_CLKIN3_TIM3OC1 0x00000000U |
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676 #define HAL_DFSDM2_CLKIN7_TIM3OC1 SYSCFG_MCHDLYCR_DFSDM2CK37SEL |
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677 /** |
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678 * @} |
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679 */ |
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680 |
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681 #endif /* SYSCFG_MCHDLYCR_BSCKSEL*/ |
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682 /** |
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683 * @} |
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684 */ |
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685 /* End of exported constants -------------------------------------------------*/ |
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686 |
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687 /* Exported macros -----------------------------------------------------------*/ |
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688 /** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros |
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689 * @{ |
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690 */ |
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691 |
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692 /** @brief Reset DFSDM channel handle state. |
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693 * @param __HANDLE__ DFSDM channel handle. |
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694 * @retval None |
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695 */ |
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696 #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET) |
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697 |
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698 /** @brief Reset DFSDM filter handle state. |
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699 * @param __HANDLE__ DFSDM filter handle. |
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700 * @retval None |
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701 */ |
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702 #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET) |
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703 |
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704 /** |
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705 * @} |
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706 */ |
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707 /* End of exported macros ----------------------------------------------------*/ |
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708 |
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709 /* Exported functions --------------------------------------------------------*/ |
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710 /** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions |
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711 * @{ |
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712 */ |
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713 |
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714 /** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions |
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715 * @{ |
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716 */ |
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717 /* Channel initialization and de-initialization functions *********************/ |
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718 HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
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719 HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
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720 void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
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721 void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
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722 /** |
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723 * @} |
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724 */ |
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725 |
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726 /** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions |
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727 * @{ |
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728 */ |
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729 /* Channel operation functions ************************************************/ |
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730 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
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731 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
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732 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
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733 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
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734 |
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735 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal); |
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736 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal); |
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737 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
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738 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
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739 |
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740 int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
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741 HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset); |
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742 |
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743 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); |
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744 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); |
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745 |
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746 void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
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747 void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
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748 /** |
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749 * @} |
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750 */ |
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751 |
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752 /** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function |
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753 * @{ |
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754 */ |
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755 /* Channel state function *****************************************************/ |
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756 HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
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757 /** |
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758 * @} |
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759 */ |
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760 |
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761 /** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions |
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762 * @{ |
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763 */ |
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764 /* Filter initialization and de-initialization functions *********************/ |
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765 HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
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766 HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
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767 void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
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768 void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
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769 /** |
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770 * @} |
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771 */ |
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772 |
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773 /** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions |
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774 * @{ |
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775 */ |
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776 /* Filter control functions *********************/ |
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777 HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, |
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778 uint32_t Channel, |
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779 uint32_t ContinuousMode); |
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780 HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, |
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781 uint32_t Channel); |
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782 /** |
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783 * @} |
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784 */ |
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785 |
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786 /** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions |
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787 * @{ |
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788 */ |
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789 /* Filter operation functions *********************/ |
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790 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
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791 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
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792 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length); |
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793 HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length); |
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794 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
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795 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
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796 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
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797 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
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798 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
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799 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length); |
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800 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length); |
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801 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
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802 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
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803 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
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804 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, |
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805 DFSDM_Filter_AwdParamTypeDef* awdParam); |
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806 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
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807 HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel); |
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808 HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
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809 |
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810 int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); |
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811 int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); |
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812 int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); |
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813 int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); |
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814 uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
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815 |
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816 void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
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817 |
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818 HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout); |
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819 HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout); |
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820 |
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821 void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
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822 void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
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823 void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
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824 void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
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825 void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold); |
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826 void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
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827 /** |
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828 * @} |
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829 */ |
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830 |
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831 /** @addtogroup DFSDM_Exported_Functions_Group4_Filter Filter state functions |
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832 * @{ |
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833 */ |
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834 /* Filter state functions *****************************************************/ |
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835 HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
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836 uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
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837 /** |
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838 * @} |
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839 */ |
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840 /** @addtogroup DFSDM_Exported_Functions_Group5_Filter MultiChannel operation functions |
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841 * @{ |
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842 */ |
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843 #if defined(SYSCFG_MCHDLYCR_BSCKSEL) |
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844 void HAL_DFSDM_ConfigMultiChannelDelay(DFSDM_MultiChannelConfigTypeDef* mchdlystruct); |
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845 void HAL_DFSDM_BitstreamClock_Start(void); |
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846 void HAL_DFSDM_BitstreamClock_Stop(void); |
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847 void HAL_DFSDM_DisableDelayClock(uint32_t MCHDLY); |
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848 void HAL_DFSDM_EnableDelayClock(uint32_t MCHDLY); |
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849 void HAL_DFSDM_ClockIn_SourceSelection(uint32_t source); |
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850 void HAL_DFSDM_ClockOut_SourceSelection(uint32_t source); |
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851 void HAL_DFSDM_DataIn0_SourceSelection(uint32_t source); |
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852 void HAL_DFSDM_DataIn2_SourceSelection(uint32_t source); |
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853 void HAL_DFSDM_DataIn4_SourceSelection(uint32_t source); |
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854 void HAL_DFSDM_DataIn6_SourceSelection(uint32_t source); |
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855 void HAL_DFSDM_BitStreamClkDistribution_Config(uint32_t source); |
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856 #endif /* SYSCFG_MCHDLYCR_BSCKSEL */ |
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857 /** |
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858 * @} |
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859 */ |
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860 /** |
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861 * @} |
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862 */ |
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863 /* End of exported functions -------------------------------------------------*/ |
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864 |
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865 /* Private macros ------------------------------------------------------------*/ |
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866 /** @defgroup DFSDM_Private_Macros DFSDM Private Macros |
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867 * @{ |
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868 */ |
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869 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK) (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \ |
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|
870 ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO)) |
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871 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2U <= (DIVIDER)) && ((DIVIDER) <= 256U)) |
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|
872 #define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \ |
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|
873 ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER)) |
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Added current STM32 standandard libraries in version independend folder structure
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diff
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|
874 #define IS_DFSDM_CHANNEL_DATA_PACKING(MODE) (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \ |
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|
875 ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \ |
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|
876 ((MODE) == DFSDM_CHANNEL_DUAL_MODE)) |
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diff
changeset
|
877 #define IS_DFSDM_CHANNEL_INPUT_PINS(PINS) (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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|
878 ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS)) |
c78bcbd5deda
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diff
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|
879 #define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE) (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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|
880 ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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|
881 ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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|
882 ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING)) |
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diff
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|
883 #define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE) (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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|
884 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \ |
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|
885 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \ |
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|
886 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING)) |
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Added current STM32 standandard libraries in version independend folder structure
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|
887 #define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER) (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \ |
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|
888 ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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|
889 ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \ |
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|
890 ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER)) |
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|
891 #define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 32U)) |
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Added current STM32 standandard libraries in version independend folder structure
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|
892 #define IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) |
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|
893 #define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1FU) |
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894 #define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFFU) |
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|
895 #define IS_DFSDM_FILTER_REG_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \ |
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|
896 ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER)) |
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|
897 #define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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|
898 ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \ |
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|
899 ((TRIG) == DFSDM_FILTER_EXT_TRIGGER)) |
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Added current STM32 standandard libraries in version independend folder structure
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|
900 #if defined (STM32F413xx) || defined (STM32F423xx) |
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|
901 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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|
902 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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|
903 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \ |
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|
904 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM10_OC1) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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|
905 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM2_TRGO) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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|
906 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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|
907 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM11_OC1) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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|
908 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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|
909 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \ |
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|
910 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15)) |
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Added current STM32 standandard libraries in version independend folder structure
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|
911 #define IS_DFSDM_DELAY_CLOCK(CLOCK) (((CLOCK) == HAL_MCHDLY_CLOCK_DFSDM2) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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|
912 ((CLOCK) == HAL_MCHDLY_CLOCK_DFSDM1)) |
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Added current STM32 standandard libraries in version independend folder structure
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|
913 #else |
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Added current STM32 standandard libraries in version independend folder structure
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|
914 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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|
915 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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|
916 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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|
917 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM10_OC1) || \ |
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|
918 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \ |
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|
919 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \ |
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|
920 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \ |
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|
921 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15)) |
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|
922 #endif |
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|
923 #define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE) (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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|
924 ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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|
925 ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES)) |
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|
926 #define IS_DFSDM_FILTER_SINC_ORDER(ORDER) (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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|
927 ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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|
928 ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \ |
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|
929 ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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|
930 ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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|
931 ((ORDER) == DFSDM_FILTER_SINC5_ORDER)) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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|
932 #define IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 1024U)) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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|
933 #define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 256U)) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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|
934 #define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA) (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA) || \ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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|
935 ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA)) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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|
936 #define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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|
937 #define IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0x0FU) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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|
938 #if defined(DFSDM2_Channel0) |
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Added current STM32 standandard libraries in version independend folder structure
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|
939 #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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|
940 ((CHANNEL) == DFSDM_CHANNEL_1) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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|
941 ((CHANNEL) == DFSDM_CHANNEL_2) || \ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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|
942 ((CHANNEL) == DFSDM_CHANNEL_3) || \ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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|
943 ((CHANNEL) == DFSDM_CHANNEL_4) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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|
944 ((CHANNEL) == DFSDM_CHANNEL_5) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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|
945 ((CHANNEL) == DFSDM_CHANNEL_6) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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|
946 ((CHANNEL) == DFSDM_CHANNEL_7)) |
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Added current STM32 standandard libraries in version independend folder structure
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|
947 #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F00FFU)) |
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Added current STM32 standandard libraries in version independend folder structure
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|
948 #else |
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|
949 #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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|
950 ((CHANNEL) == DFSDM_CHANNEL_1) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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|
951 ((CHANNEL) == DFSDM_CHANNEL_2) || \ |
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|
952 ((CHANNEL) == DFSDM_CHANNEL_3)) |
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|
953 #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x0003000FU)) |
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|
954 #endif |
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|
955 #define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) || \ |
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|
956 ((MODE) == DFSDM_CONTINUOUS_CONV_ON)) |
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|
957 #if defined(DFSDM2_Channel0) |
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|
958 #define IS_DFSDM1_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \ |
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|
959 ((INSTANCE) == DFSDM1_Channel1) || \ |
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|
960 ((INSTANCE) == DFSDM1_Channel2) || \ |
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|
961 ((INSTANCE) == DFSDM1_Channel3)) |
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|
962 #define IS_DFSDM1_FILTER_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \ |
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|
963 ((INSTANCE) == DFSDM1_Filter1)) |
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|
964 #endif /* DFSDM2_Channel0 */ |
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|
965 |
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|
966 #if defined(SYSCFG_MCHDLYCR_BSCKSEL) |
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|
967 #define IS_DFSDM_CLOCKIN_SELECTION(SELECTION) (((SELECTION) == HAL_DFSDM2_CKIN_PAD) || \ |
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|
968 ((SELECTION) == HAL_DFSDM2_CKIN_DM) || \ |
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|
969 ((SELECTION) == HAL_DFSDM1_CKIN_PAD) || \ |
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|
970 ((SELECTION) == HAL_DFSDM1_CKIN_DM)) |
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|
971 #define IS_DFSDM_CLOCKOUT_SELECTION(SELECTION) (((SELECTION) == HAL_DFSDM2_CKOUT_DFSDM2) || \ |
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|
972 ((SELECTION) == HAL_DFSDM2_CKOUT_M27) || \ |
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|
973 ((SELECTION) == HAL_DFSDM1_CKOUT_DFSDM1) || \ |
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|
974 ((SELECTION) == HAL_DFSDM1_CKOUT_M27)) |
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|
975 #define IS_DFSDM_DATAIN0_SRC_SELECTION(SELECTION) (((SELECTION) == HAL_DATAIN0_DFSDM2_PAD) || \ |
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|
976 ((SELECTION) == HAL_DATAIN0_DFSDM2_DATAIN1) || \ |
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977 ((SELECTION) == HAL_DATAIN0_DFSDM1_PAD) || \ |
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978 ((SELECTION) == HAL_DATAIN0_DFSDM1_DATAIN1)) |
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979 #define IS_DFSDM_DATAIN2_SRC_SELECTION(SELECTION) (((SELECTION) == HAL_DATAIN2_DFSDM2_PAD) || \ |
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980 ((SELECTION) == HAL_DATAIN2_DFSDM2_DATAIN3) || \ |
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981 ((SELECTION) == HAL_DATAIN2_DFSDM1_PAD) || \ |
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982 ((SELECTION) == HAL_DATAIN2_DFSDM1_DATAIN3)) |
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983 #define IS_DFSDM_DATAIN4_SRC_SELECTION(SELECTION) (((SELECTION) == HAL_DATAIN4_DFSDM2_PAD) || \ |
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984 ((SELECTION) == HAL_DATAIN4_DFSDM2_DATAIN5)) |
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985 #define IS_DFSDM_DATAIN6_SRC_SELECTION(SELECTION) (((SELECTION) == HAL_DATAIN6_DFSDM2_PAD) || \ |
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986 ((SELECTION) == HAL_DATAIN6_DFSDM2_DATAIN7)) |
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987 #define IS_DFSDM_BITSTREM_CLK_DISTRIBUTION(DISTRIBUTION) (((DISTRIBUTION) == HAL_DFSDM1_CLKIN0_TIM4OC2) || \ |
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988 ((DISTRIBUTION) == HAL_DFSDM1_CLKIN2_TIM4OC2) || \ |
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989 ((DISTRIBUTION) == HAL_DFSDM1_CLKIN1_TIM4OC1) || \ |
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990 ((DISTRIBUTION) == HAL_DFSDM1_CLKIN3_TIM4OC1) || \ |
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991 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN0_TIM3OC4) || \ |
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992 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN4_TIM3OC4) || \ |
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993 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN1_TIM3OC3)|| \ |
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994 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN5_TIM3OC3) || \ |
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995 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN2_TIM3OC2) || \ |
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996 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN6_TIM3OC2) || \ |
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997 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN3_TIM3OC1)|| \ |
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998 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN7_TIM3OC1)) |
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999 #define IS_DFSDM_DFSDM1_CLKOUT(CLKOUT) (((CLKOUT) == DFSDM1_CKOUT_DFSDM2_CKOUT) || \ |
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1000 ((CLKOUT) == DFSDM1_CKOUT_DFSDM1)) |
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1001 #define IS_DFSDM_DFSDM2_CLKOUT(CLKOUT) (((CLKOUT) == DFSDM2_CKOUT_DFSDM2_CKOUT) || \ |
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1002 ((CLKOUT) == DFSDM2_CKOUT_DFSDM2)) |
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1003 #define IS_DFSDM_DFSDM1_CLKIN(CLKIN) (((CLKIN) == DFSDM1_CKIN_DFSDM2_CKOUT) || \ |
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1004 ((CLKIN) == DFSDM1_CKIN_PAD)) |
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1005 #define IS_DFSDM_DFSDM2_CLKIN(CLKIN) (((CLKIN) == DFSDM2_CKIN_DFSDM2_CKOUT) || \ |
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1006 ((CLKIN) == DFSDM2_CKIN_PAD)) |
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1007 #define IS_DFSDM_DFSDM1_BIT_CLK(CLK) (((CLK) == DFSDM1_T4_OC2_BITSTREAM_CKIN0) || \ |
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1008 ((CLK) == DFSDM1_T4_OC2_BITSTREAM_CKIN2) || \ |
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1009 ((CLK) == DFSDM1_T4_OC1_BITSTREAM_CKIN3) || \ |
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1010 ((CLK) == DFSDM1_T4_OC1_BITSTREAM_CKIN1) || \ |
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1011 ((CLK) <= 0x30U)) |
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1012 |
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1013 #define IS_DFSDM_DFSDM2_BIT_CLK(CLK) (((CLK) == DFSDM2_T3_OC4_BITSTREAM_CKIN0) || \ |
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1014 ((CLK) == DFSDM2_T3_OC4_BITSTREAM_CKIN4) || \ |
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1015 ((CLK) == DFSDM2_T3_OC3_BITSTREAM_CKIN5) || \ |
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1016 ((CLK) == DFSDM2_T3_OC3_BITSTREAM_CKIN1) || \ |
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1017 ((CLK) == DFSDM2_T3_OC2_BITSTREAM_CKIN6) || \ |
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1018 ((CLK) == DFSDM2_T3_OC2_BITSTREAM_CKIN2) || \ |
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1019 ((CLK) == DFSDM2_T3_OC1_BITSTREAM_CKIN3) || \ |
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1020 ((CLK) == DFSDM2_T3_OC1_BITSTREAM_CKIN7)|| \ |
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1021 ((CLK) <= 0x1E000U)) |
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1022 |
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1023 #define IS_DFSDM_DFSDM1_DATA_DISTRIBUTION(DISTRIBUTION)(((DISTRIBUTION) == DFSDM1_DATIN0_TO_DATIN0_PAD )|| \ |
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1024 ((DISTRIBUTION) == DFSDM1_DATIN0_TO_DATIN1_PAD) || \ |
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1025 ((DISTRIBUTION) == DFSDM1_DATIN2_TO_DATIN2_PAD) || \ |
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1026 ((DISTRIBUTION) == DFSDM1_DATIN2_TO_DATIN3_PAD)|| \ |
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1027 ((DISTRIBUTION) <= 0xCU)) |
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1028 |
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1029 #define IS_DFSDM_DFSDM2_DATA_DISTRIBUTION(DISTRIBUTION)(((DISTRIBUTION) == DFSDM2_DATIN0_TO_DATIN0_PAD)|| \ |
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1030 ((DISTRIBUTION) == DFSDM2_DATIN0_TO_DATIN1_PAD)|| \ |
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1031 ((DISTRIBUTION) == DFSDM2_DATIN2_TO_DATIN2_PAD)|| \ |
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1032 ((DISTRIBUTION) == DFSDM2_DATIN2_TO_DATIN3_PAD)|| \ |
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1033 ((DISTRIBUTION) == DFSDM2_DATIN4_TO_DATIN4_PAD)|| \ |
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1034 ((DISTRIBUTION) == DFSDM2_DATIN4_TO_DATIN5_PAD)|| \ |
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1035 ((DISTRIBUTION) == DFSDM2_DATIN6_TO_DATIN6_PAD)|| \ |
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1036 ((DISTRIBUTION) == DFSDM2_DATIN6_TO_DATIN7_PAD)|| \ |
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1037 ((DISTRIBUTION) <= 0x1D00U)) |
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1038 #endif /* (SYSCFG_MCHDLYCR_BSCKSEL) */ |
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1039 /** |
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1040 * @} |
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1041 */ |
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1042 /* End of private macros -----------------------------------------------------*/ |
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1043 |
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1044 /** |
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1045 * @} |
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1046 */ |
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1047 |
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1048 /** |
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1049 * @} |
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1050 */ |
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1051 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ |
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1052 #ifdef __cplusplus |
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1053 } |
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1054 #endif |
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1055 |
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1056 #endif /* __STM32F4xx_HAL_DFSDM_H */ |
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1057 |
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1058 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |