Mercurial > public > ostc4
annotate Common/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c @ 528:a9c195be907e
Added new option to gas configuration: "Off":
Added functionality needed to handle the new state
author | Ideenmodellierer |
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date | Sun, 13 Sep 2020 20:59:38 +0200 |
parents | c78bcbd5deda |
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rev | line source |
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128
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1 /** |
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2 ****************************************************************************** |
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3 * @file stm32f4xx_hal_cortex.c |
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4 * @author MCD Application Team |
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5 * @brief CORTEX HAL module driver. |
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6 * This file provides firmware functions to manage the following |
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7 * functionalities of the CORTEX: |
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8 * + Initialization and de-initialization functions |
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9 * + Peripheral Control functions |
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10 * |
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11 @verbatim |
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12 ============================================================================== |
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13 ##### How to use this driver ##### |
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14 ============================================================================== |
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15 |
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16 [..] |
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17 *** How to configure Interrupts using CORTEX HAL driver *** |
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18 =========================================================== |
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19 [..] |
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20 This section provides functions allowing to configure the NVIC interrupts (IRQ). |
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21 The Cortex-M4 exceptions are managed by CMSIS functions. |
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22 |
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23 (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() |
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24 function according to the following table. |
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25 (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). |
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26 (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). |
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27 (#) please refer to programming manual for details in how to configure priority. |
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28 |
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29 -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. |
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30 The pending IRQ priority will be managed only by the sub priority. |
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31 |
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32 -@- IRQ priority order (sorted by highest to lowest priority): |
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33 (+@) Lowest preemption priority |
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34 (+@) Lowest sub priority |
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35 (+@) Lowest hardware priority (IRQ number) |
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36 |
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37 [..] |
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38 *** How to configure Systick using CORTEX HAL driver *** |
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39 ======================================================== |
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40 [..] |
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41 Setup SysTick Timer for time base. |
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42 |
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43 (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which |
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44 is a CMSIS function that: |
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45 (++) Configures the SysTick Reload register with value passed as function parameter. |
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46 (++) Configures the SysTick IRQ priority to the lowest value 0x0F. |
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47 (++) Resets the SysTick Counter register. |
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48 (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). |
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49 (++) Enables the SysTick Interrupt. |
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50 (++) Starts the SysTick Counter. |
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51 |
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52 (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro |
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53 __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the |
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54 HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined |
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55 inside the stm32f4xx_hal_cortex.h file. |
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56 |
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57 (+) You can change the SysTick IRQ priority by calling the |
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58 HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function |
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59 call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. |
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60 |
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61 (+) To adjust the SysTick time base, use the following formula: |
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62 |
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63 Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) |
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64 (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function |
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65 (++) Reload Value should not exceed 0xFFFFFF |
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66 |
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67 @endverbatim |
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68 ****************************************************************************** |
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69 * @attention |
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70 * |
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71 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
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72 * |
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73 * Redistribution and use in source and binary forms, with or without modification, |
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74 * are permitted provided that the following conditions are met: |
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75 * 1. Redistributions of source code must retain the above copyright notice, |
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76 * this list of conditions and the following disclaimer. |
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77 * 2. Redistributions in binary form must reproduce the above copyright notice, |
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78 * this list of conditions and the following disclaimer in the documentation |
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79 * and/or other materials provided with the distribution. |
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80 * 3. Neither the name of STMicroelectronics nor the names of its contributors |
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81 * may be used to endorse or promote products derived from this software |
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82 * without specific prior written permission. |
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83 * |
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84 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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85 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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86 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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87 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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88 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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89 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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90 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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91 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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92 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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93 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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94 * |
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95 ****************************************************************************** |
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96 */ |
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97 |
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98 /* Includes ------------------------------------------------------------------*/ |
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99 #include "stm32f4xx_hal.h" |
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100 |
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101 /** @addtogroup STM32F4xx_HAL_Driver |
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102 * @{ |
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103 */ |
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104 |
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105 /** @defgroup CORTEX CORTEX |
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106 * @brief CORTEX HAL module driver |
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107 * @{ |
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108 */ |
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109 |
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110 #ifdef HAL_CORTEX_MODULE_ENABLED |
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111 |
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112 /* Private types -------------------------------------------------------------*/ |
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113 /* Private variables ---------------------------------------------------------*/ |
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114 /* Private constants ---------------------------------------------------------*/ |
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115 /* Private macros ------------------------------------------------------------*/ |
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116 /* Private functions ---------------------------------------------------------*/ |
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117 /* Exported functions --------------------------------------------------------*/ |
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118 |
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119 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions |
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120 * @{ |
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121 */ |
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122 |
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123 |
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124 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions |
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125 * @brief Initialization and Configuration functions |
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126 * |
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127 @verbatim |
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128 ============================================================================== |
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129 ##### Initialization and de-initialization functions ##### |
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130 ============================================================================== |
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131 [..] |
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132 This section provides the CORTEX HAL driver functions allowing to configure Interrupts |
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133 Systick functionalities |
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134 |
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135 @endverbatim |
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136 * @{ |
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137 */ |
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138 |
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139 |
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140 /** |
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141 * @brief Sets the priority grouping field (preemption priority and subpriority) |
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142 * using the required unlock sequence. |
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143 * @param PriorityGroup The priority grouping bits length. |
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144 * This parameter can be one of the following values: |
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145 * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority |
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146 * 4 bits for subpriority |
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147 * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority |
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148 * 3 bits for subpriority |
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149 * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority |
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150 * 2 bits for subpriority |
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151 * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority |
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152 * 1 bits for subpriority |
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153 * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority |
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154 * 0 bits for subpriority |
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155 * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. |
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156 * The pending IRQ priority will be managed only by the subpriority. |
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157 * @retval None |
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158 */ |
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159 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) |
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160 { |
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161 /* Check the parameters */ |
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162 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); |
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163 |
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164 /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ |
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165 NVIC_SetPriorityGrouping(PriorityGroup); |
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166 } |
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167 |
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168 /** |
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169 * @brief Sets the priority of an interrupt. |
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170 * @param IRQn External interrupt number. |
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171 * This parameter can be an enumerator of IRQn_Type enumeration |
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172 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) |
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173 * @param PreemptPriority The preemption priority for the IRQn channel. |
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174 * This parameter can be a value between 0 and 15 |
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175 * A lower priority value indicates a higher priority |
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176 * @param SubPriority the subpriority level for the IRQ channel. |
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177 * This parameter can be a value between 0 and 15 |
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178 * A lower priority value indicates a higher priority. |
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179 * @retval None |
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180 */ |
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181 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) |
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182 { |
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183 uint32_t prioritygroup = 0x00U; |
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184 |
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185 /* Check the parameters */ |
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186 assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); |
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187 assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); |
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188 |
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189 prioritygroup = NVIC_GetPriorityGrouping(); |
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190 |
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191 NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); |
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192 } |
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193 |
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194 /** |
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195 * @brief Enables a device specific interrupt in the NVIC interrupt controller. |
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196 * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() |
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197 * function should be called before. |
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198 * @param IRQn External interrupt number. |
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199 * This parameter can be an enumerator of IRQn_Type enumeration |
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200 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) |
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201 * @retval None |
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202 */ |
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203 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) |
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204 { |
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205 /* Check the parameters */ |
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206 assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); |
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207 |
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208 /* Enable interrupt */ |
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209 NVIC_EnableIRQ(IRQn); |
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210 } |
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211 |
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212 /** |
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213 * @brief Disables a device specific interrupt in the NVIC interrupt controller. |
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214 * @param IRQn External interrupt number. |
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215 * This parameter can be an enumerator of IRQn_Type enumeration |
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216 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) |
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217 * @retval None |
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218 */ |
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219 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) |
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220 { |
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221 /* Check the parameters */ |
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222 assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); |
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223 |
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224 /* Disable interrupt */ |
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225 NVIC_DisableIRQ(IRQn); |
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226 } |
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227 |
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228 /** |
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229 * @brief Initiates a system reset request to reset the MCU. |
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230 * @retval None |
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231 */ |
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232 void HAL_NVIC_SystemReset(void) |
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233 { |
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234 /* System Reset */ |
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235 NVIC_SystemReset(); |
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236 } |
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237 |
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238 /** |
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239 * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. |
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240 * Counter is in free running mode to generate periodic interrupts. |
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241 * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. |
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242 * @retval status: - 0 Function succeeded. |
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243 * - 1 Function failed. |
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244 */ |
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245 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) |
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246 { |
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247 return SysTick_Config(TicksNumb); |
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248 } |
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249 /** |
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250 * @} |
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251 */ |
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252 |
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253 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions |
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254 * @brief Cortex control functions |
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255 * |
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256 @verbatim |
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257 ============================================================================== |
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258 ##### Peripheral Control functions ##### |
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259 ============================================================================== |
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260 [..] |
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261 This subsection provides a set of functions allowing to control the CORTEX |
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262 (NVIC, SYSTICK, MPU) functionalities. |
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263 |
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264 |
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265 @endverbatim |
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266 * @{ |
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267 */ |
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268 |
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269 #if (__MPU_PRESENT == 1U) |
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270 /** |
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271 * @brief Disables the MPU |
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272 * @retval None |
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273 */ |
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274 void HAL_MPU_Disable(void) |
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275 { |
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276 /* Make sure outstanding transfers are done */ |
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277 __DMB(); |
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278 |
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279 /* Disable fault exceptions */ |
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280 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; |
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281 |
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282 /* Disable the MPU and clear the control register*/ |
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283 MPU->CTRL = 0U; |
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284 } |
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285 |
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286 /** |
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287 * @brief Enable the MPU. |
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288 * @param MPU_Control Specifies the control mode of the MPU during hard fault, |
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289 * NMI, FAULTMASK and privileged access to the default memory |
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290 * This parameter can be one of the following values: |
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291 * @arg MPU_HFNMI_PRIVDEF_NONE |
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292 * @arg MPU_HARDFAULT_NMI |
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293 * @arg MPU_PRIVILEGED_DEFAULT |
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294 * @arg MPU_HFNMI_PRIVDEF |
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295 * @retval None |
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296 */ |
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297 void HAL_MPU_Enable(uint32_t MPU_Control) |
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298 { |
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299 /* Enable the MPU */ |
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300 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; |
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301 |
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302 /* Enable fault exceptions */ |
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303 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; |
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304 |
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305 /* Ensure MPU setting take effects */ |
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306 __DSB(); |
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307 __ISB(); |
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308 } |
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309 |
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310 /** |
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311 * @brief Initializes and configures the Region and the memory to be protected. |
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312 * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains |
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313 * the initialization and configuration information. |
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314 * @retval None |
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315 */ |
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316 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) |
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317 { |
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318 /* Check the parameters */ |
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319 assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); |
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320 assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); |
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321 |
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322 /* Set the Region number */ |
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323 MPU->RNR = MPU_Init->Number; |
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324 |
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325 if ((MPU_Init->Enable) != RESET) |
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326 { |
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327 /* Check the parameters */ |
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328 assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); |
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329 assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); |
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330 assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); |
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331 assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); |
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332 assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); |
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333 assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); |
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334 assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); |
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335 assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); |
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336 |
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337 MPU->RBAR = MPU_Init->BaseAddress; |
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338 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | |
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339 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | |
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340 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | |
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341 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | |
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342 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | |
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343 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | |
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344 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | |
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345 ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | |
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346 ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); |
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347 } |
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348 else |
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349 { |
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350 MPU->RBAR = 0x00U; |
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351 MPU->RASR = 0x00U; |
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352 } |
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353 } |
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354 #endif /* __MPU_PRESENT */ |
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355 |
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356 /** |
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357 * @brief Gets the priority grouping field from the NVIC Interrupt Controller. |
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358 * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) |
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359 */ |
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360 uint32_t HAL_NVIC_GetPriorityGrouping(void) |
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361 { |
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362 /* Get the PRIGROUP[10:8] field value */ |
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363 return NVIC_GetPriorityGrouping(); |
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364 } |
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365 |
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366 /** |
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367 * @brief Gets the priority of an interrupt. |
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368 * @param IRQn External interrupt number. |
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369 * This parameter can be an enumerator of IRQn_Type enumeration |
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370 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) |
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371 * @param PriorityGroup the priority grouping bits length. |
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372 * This parameter can be one of the following values: |
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373 * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority |
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374 * 4 bits for subpriority |
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375 * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority |
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376 * 3 bits for subpriority |
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377 * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority |
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378 * 2 bits for subpriority |
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379 * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority |
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380 * 1 bits for subpriority |
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381 * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority |
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382 * 0 bits for subpriority |
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383 * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0). |
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384 * @param pSubPriority Pointer on the Subpriority value (starting from 0). |
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385 * @retval None |
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386 */ |
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387 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) |
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388 { |
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389 /* Check the parameters */ |
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390 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); |
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391 /* Get priority for Cortex-M system or device specific interrupts */ |
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392 NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); |
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393 } |
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394 |
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395 /** |
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396 * @brief Sets Pending bit of an external interrupt. |
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397 * @param IRQn External interrupt number |
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398 * This parameter can be an enumerator of IRQn_Type enumeration |
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399 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) |
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400 * @retval None |
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401 */ |
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402 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) |
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403 { |
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404 /* Check the parameters */ |
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405 assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); |
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406 |
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407 /* Set interrupt pending */ |
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408 NVIC_SetPendingIRQ(IRQn); |
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409 } |
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410 |
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411 /** |
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412 * @brief Gets Pending Interrupt (reads the pending register in the NVIC |
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413 * and returns the pending bit for the specified interrupt). |
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414 * @param IRQn External interrupt number. |
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415 * This parameter can be an enumerator of IRQn_Type enumeration |
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416 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) |
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417 * @retval status: - 0 Interrupt status is not pending. |
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418 * - 1 Interrupt status is pending. |
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419 */ |
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420 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) |
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421 { |
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422 /* Check the parameters */ |
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423 assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); |
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424 |
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425 /* Return 1 if pending else 0 */ |
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426 return NVIC_GetPendingIRQ(IRQn); |
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427 } |
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428 |
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429 /** |
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430 * @brief Clears the pending bit of an external interrupt. |
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431 * @param IRQn External interrupt number. |
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432 * This parameter can be an enumerator of IRQn_Type enumeration |
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433 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) |
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434 * @retval None |
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435 */ |
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436 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
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437 { |
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438 /* Check the parameters */ |
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439 assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); |
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440 |
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441 /* Clear pending interrupt */ |
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442 NVIC_ClearPendingIRQ(IRQn); |
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443 } |
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444 |
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445 /** |
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446 * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit). |
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447 * @param IRQn External interrupt number |
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448 * This parameter can be an enumerator of IRQn_Type enumeration |
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449 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) |
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450 * @retval status: - 0 Interrupt status is not pending. |
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451 * - 1 Interrupt status is pending. |
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452 */ |
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453 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) |
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454 { |
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455 /* Check the parameters */ |
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456 assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); |
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457 |
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458 /* Return 1 if active else 0 */ |
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459 return NVIC_GetActive(IRQn); |
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460 } |
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461 |
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462 /** |
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463 * @brief Configures the SysTick clock source. |
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464 * @param CLKSource specifies the SysTick clock source. |
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465 * This parameter can be one of the following values: |
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466 * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. |
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467 * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. |
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468 * @retval None |
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469 */ |
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470 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) |
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471 { |
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472 /* Check the parameters */ |
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473 assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); |
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474 if (CLKSource == SYSTICK_CLKSOURCE_HCLK) |
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475 { |
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476 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; |
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477 } |
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478 else |
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479 { |
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480 SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; |
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481 } |
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482 } |
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483 |
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484 /** |
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485 * @brief This function handles SYSTICK interrupt request. |
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486 * @retval None |
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487 */ |
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488 void HAL_SYSTICK_IRQHandler(void) |
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489 { |
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490 HAL_SYSTICK_Callback(); |
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491 } |
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492 |
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493 /** |
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494 * @brief SYSTICK callback. |
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495 * @retval None |
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496 */ |
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497 __weak void HAL_SYSTICK_Callback(void) |
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498 { |
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499 /* NOTE : This function Should not be modified, when the callback is needed, |
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500 the HAL_SYSTICK_Callback could be implemented in the user file |
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501 */ |
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502 } |
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503 |
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504 /** |
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505 * @} |
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506 */ |
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507 |
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508 /** |
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509 * @} |
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510 */ |
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511 |
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512 #endif /* HAL_CORTEX_MODULE_ENABLED */ |
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513 /** |
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514 * @} |
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515 */ |
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516 |
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517 /** |
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518 * @} |
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519 */ |
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520 |
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521 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |