annotate Common/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h @ 151:a98f91cca107 FlipDisplay

Bugfix ButtonResponsiveness
author Ideenmodellierer
date Sun, 03 Mar 2019 12:16:54 +0100
parents c78bcbd5deda
children
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1 /**
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2 ******************************************************************************
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3 * @file stm32f4xx_hal_dma.h
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4 * @author MCD Application Team
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5 * @brief Header file of DMA HAL module.
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6 ******************************************************************************
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7 * @attention
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8 *
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9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
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10 *
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11 * Redistribution and use in source and binary forms, with or without modification,
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12 * are permitted provided that the following conditions are met:
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13 * 1. Redistributions of source code must retain the above copyright notice,
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14 * this list of conditions and the following disclaimer.
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15 * 2. Redistributions in binary form must reproduce the above copyright notice,
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16 * this list of conditions and the following disclaimer in the documentation
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17 * and/or other materials provided with the distribution.
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18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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19 * may be used to endorse or promote products derived from this software
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20 * without specific prior written permission.
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21 *
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22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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32 *
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33 ******************************************************************************
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34 */
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35
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36 /* Define to prevent recursive inclusion -------------------------------------*/
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37 #ifndef __STM32F4xx_HAL_DMA_H
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38 #define __STM32F4xx_HAL_DMA_H
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39
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40 #ifdef __cplusplus
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41 extern "C" {
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42 #endif
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43
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44 /* Includes ------------------------------------------------------------------*/
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45 #include "stm32f4xx_hal_def.h"
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46
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47 /** @addtogroup STM32F4xx_HAL_Driver
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48 * @{
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49 */
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50
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51 /** @addtogroup DMA
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52 * @{
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53 */
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54
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55 /* Exported types ------------------------------------------------------------*/
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56
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57 /** @defgroup DMA_Exported_Types DMA Exported Types
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58 * @brief DMA Exported Types
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59 * @{
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60 */
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61
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62 /**
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63 * @brief DMA Configuration Structure definition
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64 */
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65 typedef struct
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66 {
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67 uint32_t Channel; /*!< Specifies the channel used for the specified stream.
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68 This parameter can be a value of @ref DMA_Channel_selection */
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69
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70 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
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71 from memory to memory or from peripheral to memory.
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72 This parameter can be a value of @ref DMA_Data_transfer_direction */
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73
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74 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
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75 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
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76
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77 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
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78 This parameter can be a value of @ref DMA_Memory_incremented_mode */
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79
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80 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
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81 This parameter can be a value of @ref DMA_Peripheral_data_size */
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82
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83 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
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84 This parameter can be a value of @ref DMA_Memory_data_size */
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85
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86 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx.
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87 This parameter can be a value of @ref DMA_mode
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88 @note The circular buffer mode cannot be used if the memory-to-memory
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89 data transfer is configured on the selected Stream */
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90
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91 uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx.
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92 This parameter can be a value of @ref DMA_Priority_level */
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93
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94 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
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95 This parameter can be a value of @ref DMA_FIFO_direct_mode
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96 @note The Direct mode (FIFO mode disabled) cannot be used if the
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97 memory-to-memory data transfer is configured on the selected stream */
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98
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99 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
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100 This parameter can be a value of @ref DMA_FIFO_threshold_level */
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101
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102 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
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103 It specifies the amount of data to be transferred in a single non interruptible
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104 transaction.
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105 This parameter can be a value of @ref DMA_Memory_burst
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106 @note The burst mode is possible only if the address Increment mode is enabled. */
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107
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108 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
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109 It specifies the amount of data to be transferred in a single non interruptible
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110 transaction.
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111 This parameter can be a value of @ref DMA_Peripheral_burst
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112 @note The burst mode is possible only if the address Increment mode is enabled. */
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113 }DMA_InitTypeDef;
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114
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115
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116 /**
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117 * @brief HAL DMA State structures definition
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118 */
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119 typedef enum
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120 {
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121 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
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122 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
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123 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
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124 HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
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125 HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */
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126 HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */
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127 }HAL_DMA_StateTypeDef;
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128
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129 /**
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130 * @brief HAL DMA Error Code structure definition
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131 */
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132 typedef enum
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133 {
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134 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
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135 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
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136 }HAL_DMA_LevelCompleteTypeDef;
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137
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138 /**
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139 * @brief HAL DMA Error Code structure definition
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140 */
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141 typedef enum
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142 {
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143 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
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144 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */
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145 HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */
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146 HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */
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147 HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */
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148 HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */
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149 HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */
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150 }HAL_DMA_CallbackIDTypeDef;
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151
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152 /**
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153 * @brief DMA handle Structure definition
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154 */
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155 typedef struct __DMA_HandleTypeDef
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156 {
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157 DMA_Stream_TypeDef *Instance; /*!< Register base address */
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158
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159 DMA_InitTypeDef Init; /*!< DMA communication parameters */
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160
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161 HAL_LockTypeDef Lock; /*!< DMA locking object */
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162
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163 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
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164
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165 void *Parent; /*!< Parent object state */
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166
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167 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
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168
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169 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
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170
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171 void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */
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172
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173 void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */
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174
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175 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
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176
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177 void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */
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178
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179 __IO uint32_t ErrorCode; /*!< DMA Error code */
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180
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181 uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */
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182
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183 uint32_t StreamIndex; /*!< DMA Stream Index */
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184
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185 }DMA_HandleTypeDef;
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186
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187 /**
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188 * @}
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189 */
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190
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191 /* Exported constants --------------------------------------------------------*/
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192
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193 /** @defgroup DMA_Exported_Constants DMA Exported Constants
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194 * @brief DMA Exported constants
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195 * @{
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196 */
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197
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198 /** @defgroup DMA_Error_Code DMA Error Code
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199 * @brief DMA Error Code
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200 * @{
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201 */
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202 #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */
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203 #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */
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204 #define HAL_DMA_ERROR_FE 0x00000002U /*!< FIFO error */
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205 #define HAL_DMA_ERROR_DME 0x00000004U /*!< Direct Mode error */
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206 #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
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207 #define HAL_DMA_ERROR_PARAM 0x00000040U /*!< Parameter error */
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208 #define HAL_DMA_ERROR_NO_XFER 0x00000080U /*!< Abort requested with no Xfer ongoing */
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209 #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */
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210 /**
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211 * @}
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212 */
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213
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214 /** @defgroup DMA_Channel_selection DMA Channel selection
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215 * @brief DMA channel selection
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216 * @{
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217 */
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218 #define DMA_CHANNEL_0 0x00000000U /*!< DMA Channel 0 */
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219 #define DMA_CHANNEL_1 0x02000000U /*!< DMA Channel 1 */
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220 #define DMA_CHANNEL_2 0x04000000U /*!< DMA Channel 2 */
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221 #define DMA_CHANNEL_3 0x06000000U /*!< DMA Channel 3 */
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222 #define DMA_CHANNEL_4 0x08000000U /*!< DMA Channel 4 */
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223 #define DMA_CHANNEL_5 0x0A000000U /*!< DMA Channel 5 */
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224 #define DMA_CHANNEL_6 0x0C000000U /*!< DMA Channel 6 */
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225 #define DMA_CHANNEL_7 0x0E000000U /*!< DMA Channel 7 */
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226 #if defined (DMA_SxCR_CHSEL_3)
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227 #define DMA_CHANNEL_8 0x10000000U /*!< DMA Channel 8 */
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228 #define DMA_CHANNEL_9 0x12000000U /*!< DMA Channel 9 */
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229 #define DMA_CHANNEL_10 0x14000000U /*!< DMA Channel 10 */
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230 #define DMA_CHANNEL_11 0x16000000U /*!< DMA Channel 11 */
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231 #define DMA_CHANNEL_12 0x18000000U /*!< DMA Channel 12 */
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232 #define DMA_CHANNEL_13 0x1A000000U /*!< DMA Channel 13 */
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233 #define DMA_CHANNEL_14 0x1C000000U /*!< DMA Channel 14 */
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234 #define DMA_CHANNEL_15 0x1E000000U /*!< DMA Channel 15 */
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235 #endif /* DMA_SxCR_CHSEL_3 */
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236 /**
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237 * @}
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238 */
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239
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240 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
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241 * @brief DMA data transfer direction
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242 * @{
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243 */
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244 #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
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245 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */
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246 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */
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247 /**
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248 * @}
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249 */
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250
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251 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
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252 * @brief DMA peripheral incremented mode
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253 * @{
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254 */
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255 #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */
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256 #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode disable */
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257 /**
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258 * @}
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259 */
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260
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261 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
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262 * @brief DMA memory incremented mode
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263 * @{
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264 */
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265 #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */
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266 #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode disable */
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267 /**
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268 * @}
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269 */
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270
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271 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
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272 * @brief DMA peripheral data size
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273 * @{
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274 */
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275 #define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */
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276 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
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277 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */
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278 /**
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279 * @}
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280 */
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281
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282 /** @defgroup DMA_Memory_data_size DMA Memory data size
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283 * @brief DMA memory data size
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284 * @{
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285 */
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286 #define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */
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287 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
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288 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */
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289 /**
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290 * @}
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291 */
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292
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293 /** @defgroup DMA_mode DMA mode
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294 * @brief DMA mode
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295 * @{
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296 */
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297 #define DMA_NORMAL 0x00000000U /*!< Normal mode */
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298 #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */
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299 #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */
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300 /**
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301 * @}
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302 */
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303
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304 /** @defgroup DMA_Priority_level DMA Priority level
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305 * @brief DMA priority levels
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306 * @{
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307 */
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308 #define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level: Low */
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309 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */
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310 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */
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311 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */
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312 /**
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313 * @}
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314 */
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315
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316 /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
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317 * @brief DMA FIFO direct mode
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318 * @{
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319 */
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320 #define DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */
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321 #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */
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322 /**
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323 * @}
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324 */
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325
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326 /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
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327 * @brief DMA FIFO level
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328 * @{
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329 */
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330 #define DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00000000U /*!< FIFO threshold 1 quart full configuration */
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331 #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */
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332 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */
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333 #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */
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334 /**
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335 * @}
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336 */
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337
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338 /** @defgroup DMA_Memory_burst DMA Memory burst
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339 * @brief DMA memory burst
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340 * @{
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341 */
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342 #define DMA_MBURST_SINGLE 0x00000000U
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343 #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
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344 #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
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345 #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
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346 /**
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347 * @}
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348 */
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349
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350 /** @defgroup DMA_Peripheral_burst DMA Peripheral burst
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351 * @brief DMA peripheral burst
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352 * @{
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353 */
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354 #define DMA_PBURST_SINGLE 0x00000000U
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355 #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
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356 #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
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357 #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
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358 /**
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359 * @}
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360 */
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361
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362 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
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363 * @brief DMA interrupts definition
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364 * @{
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365 */
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366 #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
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367 #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
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368 #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
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369 #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
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370 #define DMA_IT_FE 0x00000080U
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371 /**
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372 * @}
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373 */
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374
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375 /** @defgroup DMA_flag_definitions DMA flag definitions
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376 * @brief DMA flag definitions
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377 * @{
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378 */
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379 #define DMA_FLAG_FEIF0_4 0x00000001U
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380 #define DMA_FLAG_DMEIF0_4 0x00000004U
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381 #define DMA_FLAG_TEIF0_4 0x00000008U
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382 #define DMA_FLAG_HTIF0_4 0x00000010U
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383 #define DMA_FLAG_TCIF0_4 0x00000020U
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384 #define DMA_FLAG_FEIF1_5 0x00000040U
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385 #define DMA_FLAG_DMEIF1_5 0x00000100U
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386 #define DMA_FLAG_TEIF1_5 0x00000200U
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387 #define DMA_FLAG_HTIF1_5 0x00000400U
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388 #define DMA_FLAG_TCIF1_5 0x00000800U
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389 #define DMA_FLAG_FEIF2_6 0x00010000U
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390 #define DMA_FLAG_DMEIF2_6 0x00040000U
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391 #define DMA_FLAG_TEIF2_6 0x00080000U
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392 #define DMA_FLAG_HTIF2_6 0x00100000U
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393 #define DMA_FLAG_TCIF2_6 0x00200000U
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394 #define DMA_FLAG_FEIF3_7 0x00400000U
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395 #define DMA_FLAG_DMEIF3_7 0x01000000U
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396 #define DMA_FLAG_TEIF3_7 0x02000000U
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397 #define DMA_FLAG_HTIF3_7 0x04000000U
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398 #define DMA_FLAG_TCIF3_7 0x08000000U
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399 /**
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400 * @}
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401 */
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402
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403 /**
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404 * @}
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405 */
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406
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407 /* Exported macro ------------------------------------------------------------*/
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408
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409 /** @brief Reset DMA handle state
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410 * @param __HANDLE__ specifies the DMA handle.
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411 * @retval None
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412 */
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413 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
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414
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415 /**
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416 * @brief Return the current DMA Stream FIFO filled level.
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417 * @param __HANDLE__ DMA handle
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418 * @retval The FIFO filling state.
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419 * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
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420 * and not empty.
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421 * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
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422 * - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
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423 * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
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424 * - DMA_FIFOStatus_Empty: when FIFO is empty
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425 * - DMA_FIFOStatus_Full: when FIFO is full
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426 */
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427 #define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
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428
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429 /**
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430 * @brief Enable the specified DMA Stream.
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431 * @param __HANDLE__ DMA handle
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432 * @retval None
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433 */
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434 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
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435
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436 /**
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437 * @brief Disable the specified DMA Stream.
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438 * @param __HANDLE__ DMA handle
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439 * @retval None
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440 */
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441 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
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442
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443 /* Interrupt & Flag management */
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444
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445 /**
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446 * @brief Return the current DMA Stream transfer complete flag.
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447 * @param __HANDLE__ DMA handle
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448 * @retval The specified transfer complete flag index.
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449 */
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450 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
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451 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
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452 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
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453 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
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454 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
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455 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
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456 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
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457 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
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458 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
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459 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
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460 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
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461 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
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462 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
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463 DMA_FLAG_TCIF3_7)
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464
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465 /**
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466 * @brief Return the current DMA Stream half transfer complete flag.
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467 * @param __HANDLE__ DMA handle
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468 * @retval The specified half transfer complete flag index.
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469 */
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470 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
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471 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
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472 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
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473 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
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474 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
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475 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
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476 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
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477 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
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478 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
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479 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
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480 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
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481 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
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482 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
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483 DMA_FLAG_HTIF3_7)
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484
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485 /**
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486 * @brief Return the current DMA Stream transfer error flag.
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487 * @param __HANDLE__ DMA handle
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488 * @retval The specified transfer error flag index.
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489 */
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490 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
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491 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
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492 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
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493 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
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494 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
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495 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
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496 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
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497 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
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498 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
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499 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
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500 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
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501 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
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502 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
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503 DMA_FLAG_TEIF3_7)
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504
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505 /**
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506 * @brief Return the current DMA Stream FIFO error flag.
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507 * @param __HANDLE__ DMA handle
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508 * @retval The specified FIFO error flag index.
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509 */
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510 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
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511 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
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512 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
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513 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
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514 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
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515 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
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516 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
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517 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
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518 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
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519 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
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520 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
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521 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
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522 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
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523 DMA_FLAG_FEIF3_7)
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524
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525 /**
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526 * @brief Return the current DMA Stream direct mode error flag.
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527 * @param __HANDLE__ DMA handle
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528 * @retval The specified direct mode error flag index.
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529 */
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530 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
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531 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
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532 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
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533 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
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534 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
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535 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
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536 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
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537 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
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538 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
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539 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
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540 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
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541 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
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542 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
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543 DMA_FLAG_DMEIF3_7)
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544
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545 /**
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546 * @brief Get the DMA Stream pending flags.
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547 * @param __HANDLE__ DMA handle
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548 * @param __FLAG__ Get the specified flag.
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549 * This parameter can be any combination of the following values:
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550 * @arg DMA_FLAG_TCIFx: Transfer complete flag.
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551 * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
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552 * @arg DMA_FLAG_TEIFx: Transfer error flag.
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553 * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
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554 * @arg DMA_FLAG_FEIFx: FIFO error flag.
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555 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
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556 * @retval The state of FLAG (SET or RESET).
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557 */
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558 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
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559 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
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560 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
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561 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
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562
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563 /**
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564 * @brief Clear the DMA Stream pending flags.
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565 * @param __HANDLE__ DMA handle
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566 * @param __FLAG__ specifies the flag to clear.
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567 * This parameter can be any combination of the following values:
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568 * @arg DMA_FLAG_TCIFx: Transfer complete flag.
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569 * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
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570 * @arg DMA_FLAG_TEIFx: Transfer error flag.
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571 * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
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572 * @arg DMA_FLAG_FEIFx: FIFO error flag.
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573 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
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574 * @retval None
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575 */
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576 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
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577 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
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578 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
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579 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
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580
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581 /**
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582 * @brief Enable the specified DMA Stream interrupts.
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583 * @param __HANDLE__ DMA handle
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584 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
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585 * This parameter can be any combination of the following values:
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586 * @arg DMA_IT_TC: Transfer complete interrupt mask.
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587 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
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588 * @arg DMA_IT_TE: Transfer error interrupt mask.
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589 * @arg DMA_IT_FE: FIFO error interrupt mask.
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590 * @arg DMA_IT_DME: Direct mode error interrupt.
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591 * @retval None
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592 */
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593 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
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594 ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
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595
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596 /**
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597 * @brief Disable the specified DMA Stream interrupts.
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598 * @param __HANDLE__ DMA handle
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599 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
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600 * This parameter can be any combination of the following values:
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601 * @arg DMA_IT_TC: Transfer complete interrupt mask.
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602 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
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603 * @arg DMA_IT_TE: Transfer error interrupt mask.
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604 * @arg DMA_IT_FE: FIFO error interrupt mask.
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605 * @arg DMA_IT_DME: Direct mode error interrupt.
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606 * @retval None
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607 */
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608 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
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609 ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
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610
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611 /**
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612 * @brief Check whether the specified DMA Stream interrupt is enabled or disabled.
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613 * @param __HANDLE__ DMA handle
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614 * @param __INTERRUPT__ specifies the DMA interrupt source to check.
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615 * This parameter can be one of the following values:
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616 * @arg DMA_IT_TC: Transfer complete interrupt mask.
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617 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
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618 * @arg DMA_IT_TE: Transfer error interrupt mask.
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619 * @arg DMA_IT_FE: FIFO error interrupt mask.
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620 * @arg DMA_IT_DME: Direct mode error interrupt.
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621 * @retval The state of DMA_IT.
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622 */
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623 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
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624 ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
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625 ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
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626
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627 /**
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628 * @brief Writes the number of data units to be transferred on the DMA Stream.
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629 * @param __HANDLE__ DMA handle
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630 * @param __COUNTER__ Number of data units to be transferred (from 0 to 65535)
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631 * Number of data items depends only on the Peripheral data format.
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632 *
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633 * @note If Peripheral data format is Bytes: number of data units is equal
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634 * to total number of bytes to be transferred.
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635 *
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636 * @note If Peripheral data format is Half-Word: number of data units is
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637 * equal to total number of bytes to be transferred / 2.
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638 *
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639 * @note If Peripheral data format is Word: number of data units is equal
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640 * to total number of bytes to be transferred / 4.
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641 *
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642 * @retval The number of remaining data units in the current DMAy Streamx transfer.
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643 */
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644 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
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645
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646 /**
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647 * @brief Returns the number of remaining data units in the current DMAy Streamx transfer.
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648 * @param __HANDLE__ DMA handle
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649 *
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650 * @retval The number of remaining data units in the current DMA Stream transfer.
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651 */
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652 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
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653
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654
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655 /* Include DMA HAL Extension module */
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656 #include "stm32f4xx_hal_dma_ex.h"
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657
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658 /* Exported functions --------------------------------------------------------*/
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659
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660 /** @defgroup DMA_Exported_Functions DMA Exported Functions
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661 * @brief DMA Exported functions
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662 * @{
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663 */
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664
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665 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
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666 * @brief Initialization and de-initialization functions
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667 * @{
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668 */
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669 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
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670 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
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671 /**
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672 * @}
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673 */
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674
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675 /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
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676 * @brief I/O operation functions
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677 * @{
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678 */
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679 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
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680 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
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681 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
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682 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
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683 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
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684 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
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685 HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma);
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686 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
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687 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
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688
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689 /**
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690 * @}
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691 */
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692
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693 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
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694 * @brief Peripheral State functions
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695 * @{
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696 */
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697 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
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698 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
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699 /**
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700 * @}
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701 */
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702 /**
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703 * @}
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704 */
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705 /* Private Constants -------------------------------------------------------------*/
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706 /** @defgroup DMA_Private_Constants DMA Private Constants
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707 * @brief DMA private defines and constants
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708 * @{
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709 */
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710 /**
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711 * @}
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712 */
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713
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714 /* Private macros ------------------------------------------------------------*/
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715 /** @defgroup DMA_Private_Macros DMA Private Macros
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716 * @brief DMA private macros
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717 * @{
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718 */
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719 #if defined (DMA_SxCR_CHSEL_3)
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720 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
721 ((CHANNEL) == DMA_CHANNEL_1) || \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
722 ((CHANNEL) == DMA_CHANNEL_2) || \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
723 ((CHANNEL) == DMA_CHANNEL_3) || \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
724 ((CHANNEL) == DMA_CHANNEL_4) || \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
725 ((CHANNEL) == DMA_CHANNEL_5) || \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
726 ((CHANNEL) == DMA_CHANNEL_6) || \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
727 ((CHANNEL) == DMA_CHANNEL_7) || \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
728 ((CHANNEL) == DMA_CHANNEL_8) || \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
729 ((CHANNEL) == DMA_CHANNEL_9) || \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
730 ((CHANNEL) == DMA_CHANNEL_10)|| \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff changeset
731 ((CHANNEL) == DMA_CHANNEL_11)|| \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff changeset
732 ((CHANNEL) == DMA_CHANNEL_12)|| \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
733 ((CHANNEL) == DMA_CHANNEL_13)|| \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
734 ((CHANNEL) == DMA_CHANNEL_14)|| \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff changeset
735 ((CHANNEL) == DMA_CHANNEL_15))
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
736 #else
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
737 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
738 ((CHANNEL) == DMA_CHANNEL_1) || \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff changeset
739 ((CHANNEL) == DMA_CHANNEL_2) || \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
740 ((CHANNEL) == DMA_CHANNEL_3) || \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff changeset
741 ((CHANNEL) == DMA_CHANNEL_4) || \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
742 ((CHANNEL) == DMA_CHANNEL_5) || \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
743 ((CHANNEL) == DMA_CHANNEL_6) || \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
744 ((CHANNEL) == DMA_CHANNEL_7))
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
745 #endif /* DMA_SxCR_CHSEL_3 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
746
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
747 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff changeset
748 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff changeset
749 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
750
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff changeset
751 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
752
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff changeset
753 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
754 ((STATE) == DMA_PINC_DISABLE))
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
755
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
756 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
757 ((STATE) == DMA_MINC_DISABLE))
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
758
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
759 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
760 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
761 ((SIZE) == DMA_PDATAALIGN_WORD))
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
762
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
763 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
764 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
765 ((SIZE) == DMA_MDATAALIGN_WORD ))
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
766
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
767 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
768 ((MODE) == DMA_CIRCULAR) || \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
769 ((MODE) == DMA_PFCTRL))
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
770
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
771 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
772 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
773 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
774 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
775
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
776 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
777 ((STATE) == DMA_FIFOMODE_ENABLE))
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
778
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
779 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
780 ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
781 ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
782 ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
783
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
784 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
785 ((BURST) == DMA_MBURST_INC4) || \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
786 ((BURST) == DMA_MBURST_INC8) || \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
787 ((BURST) == DMA_MBURST_INC16))
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
788
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
789 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
790 ((BURST) == DMA_PBURST_INC4) || \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
791 ((BURST) == DMA_PBURST_INC8) || \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
792 ((BURST) == DMA_PBURST_INC16))
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
793 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
794 * @}
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
795 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
796
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
797 /* Private functions ---------------------------------------------------------*/
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
798 /** @defgroup DMA_Private_Functions DMA Private Functions
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
799 * @brief DMA private functions
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
800 * @{
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
801 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
802 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
803 * @}
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
804 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
805
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
806 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff changeset
807 * @}
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
808 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
809
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
810 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
811 * @}
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
812 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
813
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
814 #ifdef __cplusplus
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
815 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
816 #endif
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
817
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
818 #endif /* __STM32F4xx_HAL_DMA_H */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
819
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
820 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/