annotate Common/Drivers/CMSIS/Include/core_cm4.h @ 388:a848e22bc527 maintain-1

Added tag v1.5.1 release for changeset afa55a50cc72 Signed-off-by: Jan Mulder <jlmulder@xs4all.nl>
author Jan Mulder <jlmulder@xs4all.nl>
date Sun, 01 Dec 2019 17:12:27 +0100
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1 /**************************************************************************//**
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2 * @file core_cm4.h
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3 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
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4 * @version V4.30
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5 * @date 20. October 2015
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6 ******************************************************************************/
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7 /* Copyright (c) 2009 - 2015 ARM LIMITED
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8
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9 All rights reserved.
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10 Redistribution and use in source and binary forms, with or without
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11 modification, are permitted provided that the following conditions are met:
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12 - Redistributions of source code must retain the above copyright
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13 notice, this list of conditions and the following disclaimer.
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14 - Redistributions in binary form must reproduce the above copyright
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15 notice, this list of conditions and the following disclaimer in the
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16 documentation and/or other materials provided with the distribution.
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17 - Neither the name of ARM nor the names of its contributors may be used
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18 to endorse or promote products derived from this software without
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19 specific prior written permission.
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20 *
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21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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24 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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31 POSSIBILITY OF SUCH DAMAGE.
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32 ---------------------------------------------------------------------------*/
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33
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34
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35 #if defined ( __ICCARM__ )
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36 #pragma system_include /* treat file as system include file for MISRA check */
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37 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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38 #pragma clang system_header /* treat file as system include file */
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39 #endif
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40
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41 #ifndef __CORE_CM4_H_GENERIC
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42 #define __CORE_CM4_H_GENERIC
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43
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44 #include <stdint.h>
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45
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46 #ifdef __cplusplus
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47 extern "C" {
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48 #endif
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49
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50 /**
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51 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
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52 CMSIS violates the following MISRA-C:2004 rules:
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53
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54 \li Required Rule 8.5, object/function definition in header file.<br>
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55 Function definitions in header files are used to allow 'inlining'.
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56
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57 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
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58 Unions are used for effective representation of core registers.
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59
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60 \li Advisory Rule 19.7, Function-like macro defined.<br>
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61 Function-like macros are used to allow more efficient code.
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62 */
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63
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64
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65 /*******************************************************************************
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66 * CMSIS definitions
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67 ******************************************************************************/
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68 /**
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69 \ingroup Cortex_M4
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70 @{
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71 */
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72
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73 /* CMSIS CM4 definitions */
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74 #define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
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75 #define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
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76 #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
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77 __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
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78
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79 #define __CORTEX_M (0x04U) /*!< Cortex-M Core */
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80
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81
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82 #if defined ( __CC_ARM )
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83 #define __ASM __asm /*!< asm keyword for ARM Compiler */
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84 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
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85 #define __STATIC_INLINE static __inline
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86
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87 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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88 #define __ASM __asm /*!< asm keyword for ARM Compiler */
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89 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
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90 #define __STATIC_INLINE static __inline
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91
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92 #elif defined ( __GNUC__ )
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93 #define __ASM __asm /*!< asm keyword for GNU Compiler */
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94 #define __INLINE inline /*!< inline keyword for GNU Compiler */
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95 #define __STATIC_INLINE static inline
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96
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97 #elif defined ( __ICCARM__ )
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98 #define __ASM __asm /*!< asm keyword for IAR Compiler */
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99 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
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100 #define __STATIC_INLINE static inline
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101
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102 #elif defined ( __TMS470__ )
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103 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
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104 #define __STATIC_INLINE static inline
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105
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106 #elif defined ( __TASKING__ )
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107 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
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108 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
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109 #define __STATIC_INLINE static inline
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110
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111 #elif defined ( __CSMC__ )
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112 #define __packed
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113 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
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114 #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
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115 #define __STATIC_INLINE static inline
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116
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117 #else
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118 #error Unknown compiler
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119 #endif
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120
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121 /** __FPU_USED indicates whether an FPU is used or not.
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122 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
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123 */
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124 #if defined ( __CC_ARM )
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125 #if defined __TARGET_FPU_VFP
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126 #if (__FPU_PRESENT == 1U)
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127 #define __FPU_USED 1U
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128 #else
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129 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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130 #define __FPU_USED 0U
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131 #endif
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132 #else
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133 #define __FPU_USED 0U
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134 #endif
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135
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136 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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137 #if defined __ARM_PCS_VFP
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138 #if (__FPU_PRESENT == 1)
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139 #define __FPU_USED 1U
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140 #else
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141 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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142 #define __FPU_USED 0U
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143 #endif
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144 #else
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145 #define __FPU_USED 0U
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146 #endif
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147
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148 #elif defined ( __GNUC__ )
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149 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
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150 #if (__FPU_PRESENT == 1U)
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151 #define __FPU_USED 1U
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152 #else
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153 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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154 #define __FPU_USED 0U
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155 #endif
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156 #else
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157 #define __FPU_USED 0U
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158 #endif
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159
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160 #elif defined ( __ICCARM__ )
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161 #if defined __ARMVFP__
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162 #if (__FPU_PRESENT == 1U)
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163 #define __FPU_USED 1U
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164 #else
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165 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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166 #define __FPU_USED 0U
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167 #endif
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168 #else
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169 #define __FPU_USED 0U
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170 #endif
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171
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172 #elif defined ( __TMS470__ )
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173 #if defined __TI_VFP_SUPPORT__
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174 #if (__FPU_PRESENT == 1U)
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175 #define __FPU_USED 1U
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176 #else
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177 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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178 #define __FPU_USED 0U
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179 #endif
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180 #else
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181 #define __FPU_USED 0U
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182 #endif
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183
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184 #elif defined ( __TASKING__ )
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185 #if defined __FPU_VFP__
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186 #if (__FPU_PRESENT == 1U)
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187 #define __FPU_USED 1U
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188 #else
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189 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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190 #define __FPU_USED 0U
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191 #endif
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192 #else
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193 #define __FPU_USED 0U
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194 #endif
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195
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196 #elif defined ( __CSMC__ )
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197 #if ( __CSMC__ & 0x400U)
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198 #if (__FPU_PRESENT == 1U)
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199 #define __FPU_USED 1U
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200 #else
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201 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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202 #define __FPU_USED 0U
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203 #endif
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204 #else
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205 #define __FPU_USED 0U
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206 #endif
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207
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208 #endif
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209
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210 #include "core_cmInstr.h" /* Core Instruction Access */
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211 #include "core_cmFunc.h" /* Core Function Access */
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212 #include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */
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213
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214 #ifdef __cplusplus
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215 }
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216 #endif
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217
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218 #endif /* __CORE_CM4_H_GENERIC */
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219
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220 #ifndef __CMSIS_GENERIC
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221
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222 #ifndef __CORE_CM4_H_DEPENDANT
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223 #define __CORE_CM4_H_DEPENDANT
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224
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225 #ifdef __cplusplus
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226 extern "C" {
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227 #endif
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228
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229 /* check device defines and use defaults */
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230 #if defined __CHECK_DEVICE_DEFINES
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231 #ifndef __CM4_REV
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232 #define __CM4_REV 0x0000U
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233 #warning "__CM4_REV not defined in device header file; using default!"
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234 #endif
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235
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236 #ifndef __FPU_PRESENT
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237 #define __FPU_PRESENT 0U
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238 #warning "__FPU_PRESENT not defined in device header file; using default!"
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239 #endif
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240
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241 #ifndef __MPU_PRESENT
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242 #define __MPU_PRESENT 0U
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243 #warning "__MPU_PRESENT not defined in device header file; using default!"
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244 #endif
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245
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246 #ifndef __NVIC_PRIO_BITS
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247 #define __NVIC_PRIO_BITS 4U
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248 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
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249 #endif
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250
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251 #ifndef __Vendor_SysTickConfig
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252 #define __Vendor_SysTickConfig 0U
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253 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
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254 #endif
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255 #endif
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256
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257 /* IO definitions (access restrictions to peripheral registers) */
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258 /**
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259 \defgroup CMSIS_glob_defs CMSIS Global Defines
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260
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261 <strong>IO Type Qualifiers</strong> are used
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262 \li to specify the access to peripheral variables.
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263 \li for automatic generation of peripheral register debug information.
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264 */
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265 #ifdef __cplusplus
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266 #define __I volatile /*!< Defines 'read only' permissions */
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267 #else
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268 #define __I volatile const /*!< Defines 'read only' permissions */
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269 #endif
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270 #define __O volatile /*!< Defines 'write only' permissions */
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271 #define __IO volatile /*!< Defines 'read / write' permissions */
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272
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273 /* following defines should be used for structure members */
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274 #define __IM volatile const /*! Defines 'read only' structure member permissions */
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275 #define __OM volatile /*! Defines 'write only' structure member permissions */
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276 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
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277
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278 /*@} end of group Cortex_M4 */
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279
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280
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281
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282 /*******************************************************************************
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283 * Register Abstraction
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284 Core Register contain:
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285 - Core Register
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286 - Core NVIC Register
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287 - Core SCB Register
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288 - Core SysTick Register
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289 - Core Debug Register
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290 - Core MPU Register
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291 - Core FPU Register
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292 ******************************************************************************/
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293 /**
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294 \defgroup CMSIS_core_register Defines and Type Definitions
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295 \brief Type definitions and defines for Cortex-M processor based devices.
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296 */
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297
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298 /**
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299 \ingroup CMSIS_core_register
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300 \defgroup CMSIS_CORE Status and Control Registers
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301 \brief Core Register type definitions.
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302 @{
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303 */
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304
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305 /**
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306 \brief Union type to access the Application Program Status Register (APSR).
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307 */
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308 typedef union
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309 {
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310 struct
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311 {
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312 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
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313 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
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314 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
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315 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
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316 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
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317 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
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318 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
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319 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
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320 } b; /*!< Structure used for bit access */
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321 uint32_t w; /*!< Type used for word access */
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322 } APSR_Type;
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323
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324 /* APSR Register Definitions */
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325 #define APSR_N_Pos 31U /*!< APSR: N Position */
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326 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
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327
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328 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
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329 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
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330
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331 #define APSR_C_Pos 29U /*!< APSR: C Position */
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332 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
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333
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334 #define APSR_V_Pos 28U /*!< APSR: V Position */
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335 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
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336
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337 #define APSR_Q_Pos 27U /*!< APSR: Q Position */
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338 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
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339
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340 #define APSR_GE_Pos 16U /*!< APSR: GE Position */
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341 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
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342
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343
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344 /**
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345 \brief Union type to access the Interrupt Program Status Register (IPSR).
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346 */
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347 typedef union
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348 {
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349 struct
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350 {
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351 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
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352 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
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353 } b; /*!< Structure used for bit access */
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354 uint32_t w; /*!< Type used for word access */
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355 } IPSR_Type;
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356
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357 /* IPSR Register Definitions */
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358 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
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359 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
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360
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361
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362 /**
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363 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
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364 */
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365 typedef union
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366 {
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367 struct
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368 {
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369 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
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370 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
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371 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
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372 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
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373 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
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374 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
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375 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
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376 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
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377 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
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378 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
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379 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
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380 } b; /*!< Structure used for bit access */
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381 uint32_t w; /*!< Type used for word access */
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382 } xPSR_Type;
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383
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384 /* xPSR Register Definitions */
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385 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
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386 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
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387
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388 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
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389 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
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390
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391 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
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392 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
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393
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394 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
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395 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
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396
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397 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
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398 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
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399
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400 #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
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401 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
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402
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403 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
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404 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
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405
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406 #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
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407 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
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408
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409 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
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410 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
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411
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412
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413 /**
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414 \brief Union type to access the Control Registers (CONTROL).
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415 */
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416 typedef union
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417 {
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418 struct
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419 {
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420 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
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421 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
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422 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
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423 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
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424 } b; /*!< Structure used for bit access */
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425 uint32_t w; /*!< Type used for word access */
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426 } CONTROL_Type;
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427
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428 /* CONTROL Register Definitions */
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429 #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
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430 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
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431
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432 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
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433 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
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434
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435 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
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436 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
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437
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438 /*@} end of group CMSIS_CORE */
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439
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440
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441 /**
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442 \ingroup CMSIS_core_register
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443 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
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444 \brief Type definitions for the NVIC Registers
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445 @{
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446 */
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447
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448 /**
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449 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
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450 */
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451 typedef struct
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452 {
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453 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
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454 uint32_t RESERVED0[24U];
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455 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
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456 uint32_t RSERVED1[24U];
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457 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
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458 uint32_t RESERVED2[24U];
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459 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
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460 uint32_t RESERVED3[24U];
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461 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
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462 uint32_t RESERVED4[56U];
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463 __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
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464 uint32_t RESERVED5[644U];
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465 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
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466 } NVIC_Type;
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467
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468 /* Software Triggered Interrupt Register Definitions */
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469 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
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470 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
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471
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472 /*@} end of group CMSIS_NVIC */
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473
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474
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475 /**
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476 \ingroup CMSIS_core_register
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477 \defgroup CMSIS_SCB System Control Block (SCB)
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478 \brief Type definitions for the System Control Block Registers
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479 @{
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480 */
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481
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482 /**
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483 \brief Structure type to access the System Control Block (SCB).
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484 */
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485 typedef struct
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486 {
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487 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
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488 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
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489 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
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490 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
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491 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
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492 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
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493 __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
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494 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
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495 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
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496 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
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497 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
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498 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
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499 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
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500 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
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501 __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
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502 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
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503 __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
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504 __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
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505 __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
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506 uint32_t RESERVED0[5U];
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507 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
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508 } SCB_Type;
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509
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510 /* SCB CPUID Register Definitions */
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511 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
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512 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
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513
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514 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
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515 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
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516
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517 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
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518 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
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519
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520 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
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521 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
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522
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523 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
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524 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
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525
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526 /* SCB Interrupt Control State Register Definitions */
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527 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
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528 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
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529
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530 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
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531 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
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532
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533 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
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534 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
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535
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536 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
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537 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
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538
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539 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
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540 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
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541
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542 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
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543 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
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544
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545 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
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546 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
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547
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548 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
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549 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
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550
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551 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
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552 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
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553
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554 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
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555 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
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556
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557 /* SCB Vector Table Offset Register Definitions */
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558 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
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559 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
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560
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561 /* SCB Application Interrupt and Reset Control Register Definitions */
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562 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
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563 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
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564
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565 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
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566 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
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567
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568 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
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569 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
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570
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571 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
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572 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
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573
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574 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
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575 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
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576
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577 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
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578 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
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579
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580 #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
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581 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
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582
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583 /* SCB System Control Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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584 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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585 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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586
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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587 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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588 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
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589
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
590 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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591 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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592
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
593 /* SCB Configuration Control Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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594 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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595 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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596
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
597 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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598 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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599
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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600 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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601 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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602
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
603 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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604 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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605
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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606 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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607 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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608
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
609 #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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610 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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611
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
612 /* SCB System Handler Control and State Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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613 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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614 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
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615
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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616 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
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617 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
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618
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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619 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
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620 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
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621
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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622 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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623 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
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624
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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625 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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626 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
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627
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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628 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
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629 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
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630
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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631 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
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632 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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633
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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634 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
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635 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
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636
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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637 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
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638 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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639
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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640 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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641 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
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642
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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643 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
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644 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
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645
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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646 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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647 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
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648
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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649 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
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650 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
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651
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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652 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
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653 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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654
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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655 /* SCB Configurable Fault Status Register Definitions */
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656 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
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657 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
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658
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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659 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
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660 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
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661
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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662 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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663 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
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664
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665 /* SCB Hard Fault Status Register Definitions */
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666 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
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667 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
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668
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669 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
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670 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
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671
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672 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
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673 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
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674
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675 /* SCB Debug Fault Status Register Definitions */
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676 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
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677 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
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678
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679 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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680 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
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681
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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682 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
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683 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
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684
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685 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
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686 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
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687
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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688 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
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689 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
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690
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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691 /*@} end of group CMSIS_SCB */
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692
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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693
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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694 /**
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695 \ingroup CMSIS_core_register
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696 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
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697 \brief Type definitions for the System Control and ID Register not in the SCB
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698 @{
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699 */
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700
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701 /**
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702 \brief Structure type to access the System Control and ID Register not in the SCB.
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703 */
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704 typedef struct
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705 {
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706 uint32_t RESERVED0[1U];
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707 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
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708 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
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709 } SCnSCB_Type;
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710
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711 /* Interrupt Controller Type Register Definitions */
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712 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
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713 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
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714
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715 /* Auxiliary Control Register Definitions */
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716 #define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
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717 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
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718
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719 #define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
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720 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
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721
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722 #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
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723 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
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724
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725 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
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726 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
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727
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728 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
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729 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
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730
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731 /*@} end of group CMSIS_SCnotSCB */
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732
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733
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734 /**
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735 \ingroup CMSIS_core_register
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736 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
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737 \brief Type definitions for the System Timer Registers.
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738 @{
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739 */
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740
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741 /**
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742 \brief Structure type to access the System Timer (SysTick).
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743 */
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744 typedef struct
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745 {
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746 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
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747 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
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748 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
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749 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
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750 } SysTick_Type;
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751
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752 /* SysTick Control / Status Register Definitions */
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753 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
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754 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
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755
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756 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
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757 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
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758
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759 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
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760 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
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761
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762 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
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763 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
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764
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765 /* SysTick Reload Register Definitions */
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766 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
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767 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
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768
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769 /* SysTick Current Register Definitions */
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770 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
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771 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
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772
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773 /* SysTick Calibration Register Definitions */
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774 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
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775 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
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776
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777 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
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778 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
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779
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780 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
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781 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
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782
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783 /*@} end of group CMSIS_SysTick */
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784
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785
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786 /**
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787 \ingroup CMSIS_core_register
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788 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
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789 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
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790 @{
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791 */
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792
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793 /**
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794 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
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795 */
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796 typedef struct
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797 {
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798 __OM union
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799 {
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800 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
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801 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
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802 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
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803 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
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804 uint32_t RESERVED0[864U];
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805 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
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806 uint32_t RESERVED1[15U];
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807 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
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808 uint32_t RESERVED2[15U];
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809 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
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810 uint32_t RESERVED3[29U];
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811 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
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812 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
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813 __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
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814 uint32_t RESERVED4[43U];
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815 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
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816 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
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817 uint32_t RESERVED5[6U];
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818 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
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819 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
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820 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
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821 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
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822 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
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823 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
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824 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
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825 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
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826 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
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827 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
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828 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
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829 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
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830 } ITM_Type;
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831
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832 /* ITM Trace Privilege Register Definitions */
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833 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
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834 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
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835
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836 /* ITM Trace Control Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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837 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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838 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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839
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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840 #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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841 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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842
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
843 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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844 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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845
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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846 #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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847 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
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848
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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849 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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850 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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851
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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852 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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853 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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854
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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855 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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856 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
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857
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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858 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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859 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
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860
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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861 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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862 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
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863
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
864 /* ITM Integration Write Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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865 #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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866 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
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867
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diff changeset
868 /* ITM Integration Read Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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869 #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
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870 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
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871
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
872 /* ITM Integration Mode Control Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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873 #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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874 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
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875
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876 /* ITM Lock Status Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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877 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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878 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
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879
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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880 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
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881 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
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882
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883 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
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884 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
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885
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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886 /*@}*/ /* end of group CMSIS_ITM */
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887
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
888
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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889 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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890 \ingroup CMSIS_core_register
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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891 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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892 \brief Type definitions for the Data Watchpoint and Trace (DWT)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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893 @{
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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894 */
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895
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896 /**
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897 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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898 */
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899 typedef struct
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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900 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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901 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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902 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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903 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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904 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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905 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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906 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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907 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
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908 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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909 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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910 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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911 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
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912 uint32_t RESERVED0[1U];
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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913 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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914 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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915 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
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916 uint32_t RESERVED1[1U];
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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917 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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918 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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919 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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920 uint32_t RESERVED2[1U];
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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921 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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922 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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923 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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924 } DWT_Type;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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925
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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926 /* DWT Control Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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927 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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928 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
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929
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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930 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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931 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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932
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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933 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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934 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
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935
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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936 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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937 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
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938
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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939 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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940 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
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941
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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942 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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943 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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944
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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945 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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946 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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947
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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948 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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949 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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950
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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951 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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952 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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953
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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954 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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955 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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956
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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957 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
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958 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
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959
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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960 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
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diff changeset
961 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
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962
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
963 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
964 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
965
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diff changeset
966 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
967 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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968
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
969 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
970 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
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971
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
972 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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973 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
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974
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
975 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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976 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
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977
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
978 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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979 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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980
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diff changeset
981 /* DWT CPI Count Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
982 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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983 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
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984
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diff changeset
985 /* DWT Exception Overhead Count Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
986 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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987 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
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988
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diff changeset
989 /* DWT Sleep Count Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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990 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
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991 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
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992
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diff changeset
993 /* DWT LSU Count Register Definitions */
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994 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
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995 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
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996
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diff changeset
997 /* DWT Folded-instruction Count Register Definitions */
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diff changeset
998 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
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999 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
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1000
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diff changeset
1001 /* DWT Comparator Mask Register Definitions */
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1002 #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1003 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
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1004
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1005 /* DWT Comparator Function Register Definitions */
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1006 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
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1007 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
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1008
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1009 #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
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1010 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
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1011
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1012 #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
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1013 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
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1014
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1015 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
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1016 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
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1017
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1018 #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
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1019 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
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1020
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1021 #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
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1022 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
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1023
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1024 #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
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1025 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
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1026
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1027 #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
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1028 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
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1029
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1030 #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
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1031 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
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1032
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1033 /*@}*/ /* end of group CMSIS_DWT */
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1034
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1035
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1036 /**
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1037 \ingroup CMSIS_core_register
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1038 \defgroup CMSIS_TPI Trace Port Interface (TPI)
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1039 \brief Type definitions for the Trace Port Interface (TPI)
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1040 @{
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1041 */
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1042
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1043 /**
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1044 \brief Structure type to access the Trace Port Interface Register (TPI).
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1045 */
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1046 typedef struct
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1047 {
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1048 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
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1049 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
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1050 uint32_t RESERVED0[2U];
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1051 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
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1052 uint32_t RESERVED1[55U];
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1053 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
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1054 uint32_t RESERVED2[131U];
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1055 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
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1056 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
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1057 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
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1058 uint32_t RESERVED3[759U];
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1059 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
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1060 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
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1061 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
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1062 uint32_t RESERVED4[1U];
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1063 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
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1064 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
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1065 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
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1066 uint32_t RESERVED5[39U];
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1067 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
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1068 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
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1069 uint32_t RESERVED7[8U];
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1070 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
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1071 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
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1072 } TPI_Type;
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1073
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1074 /* TPI Asynchronous Clock Prescaler Register Definitions */
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1075 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
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1076 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
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1077
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1078 /* TPI Selected Pin Protocol Register Definitions */
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1079 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
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1080 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
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1081
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1082 /* TPI Formatter and Flush Status Register Definitions */
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1083 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
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1084 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
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1085
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1086 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
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1087 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1088
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1089 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1090 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1091
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1092 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1093 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1094
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1095 /* TPI Formatter and Flush Control Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1096 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1097 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1098
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1099 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1100 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
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diff changeset
1101
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1102 /* TPI TRIGGER Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1103 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1104 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1105
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1106 /* TPI Integration ETM Data Register Definitions (FIFO0) */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1107 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1108 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1109
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1110 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1111 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1112
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1113 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1114 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1115
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1116 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1117 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1118
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1119 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1120 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1121
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1122 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1123 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1124
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1125 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1126 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1127
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1128 /* TPI ITATBCTR2 Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1129 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1130 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1131
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1132 /* TPI Integration ITM Data Register Definitions (FIFO1) */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1133 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1134 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1135
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1136 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1137 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1138
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1139 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1140 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1141
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1142 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1143 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1144
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1145 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1146 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1147
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1148 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1149 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1150
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1151 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1152 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1153
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1154 /* TPI ITATBCTR0 Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1155 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1156 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1157
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1158 /* TPI Integration Mode Control Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1159 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1160 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1161
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1162 /* TPI DEVID Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1163 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1164 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1165
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1166 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1167 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1168
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1169 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1170 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1171
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1172 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1173 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1174
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1175 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1176 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
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1177
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1178 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1179 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
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1180
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diff changeset
1181 /* TPI DEVTYPE Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1182 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1183 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
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1184
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1185 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1186 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
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1187
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1188 /*@}*/ /* end of group CMSIS_TPI */
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1189
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1190
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1191 #if (__MPU_PRESENT == 1U)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1192 /**
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1193 \ingroup CMSIS_core_register
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1194 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
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1195 \brief Type definitions for the Memory Protection Unit (MPU)
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1196 @{
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1197 */
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1198
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1199 /**
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1200 \brief Structure type to access the Memory Protection Unit (MPU).
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1201 */
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1202 typedef struct
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1203 {
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1204 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
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1205 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
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1206 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
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1207 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
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1208 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
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1209 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
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1210 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1211 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1212 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1213 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1214 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1215 } MPU_Type;
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1216
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1217 /* MPU Type Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1218 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1219 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
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1220
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1221 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1222 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
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1223
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1224 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1225 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1226
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1227 /* MPU Control Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1228 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1229 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
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1230
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1231 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1232 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
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1233
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1234 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1235 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
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1236
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1237 /* MPU Region Number Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1238 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1239 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
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1240
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1241 /* MPU Region Base Address Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1242 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1243 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
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1244
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1245 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1246 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
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1247
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1248 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1249 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1250
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1251 /* MPU Region Attribute and Size Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1252 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1253 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1254
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1255 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1256 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
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1257
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1258 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1259 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
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1260
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1261 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
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1262 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
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1263
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1264 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1265 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
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1266
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1267 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1268 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
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1269
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1270 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
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1271 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
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1272
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1273 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1274 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
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1275
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1276 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
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1277 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
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1278
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1279 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
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1280 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
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1281
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1282 /*@} end of group CMSIS_MPU */
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1283 #endif
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1284
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1285
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1286 #if (__FPU_PRESENT == 1U)
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1287 /**
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1288 \ingroup CMSIS_core_register
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1289 \defgroup CMSIS_FPU Floating Point Unit (FPU)
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1290 \brief Type definitions for the Floating Point Unit (FPU)
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1291 @{
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1292 */
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1293
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1294 /**
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1295 \brief Structure type to access the Floating Point Unit (FPU).
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1296 */
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1297 typedef struct
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1298 {
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1299 uint32_t RESERVED0[1U];
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1300 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
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1301 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
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1302 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
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1303 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
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1304 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
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1305 } FPU_Type;
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1306
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1307 /* Floating-Point Context Control Register Definitions */
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1308 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
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1309 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
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1310
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1311 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
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1312 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
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1313
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1314 #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
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1315 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
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1316
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1317 #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
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1318 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
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1319
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1320 #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
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1321 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
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1322
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1323 #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
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1324 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
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1325
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1326 #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
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1327 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
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1328
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1329 #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
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1330 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
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1331
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1332 #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
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1333 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
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1334
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diff changeset
1335 /* Floating-Point Context Address Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1336 #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1337 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1338
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
1339 /* Floating-Point Default Status Control Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1340 #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1341 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1342
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1343 #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1344 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1345
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1346 #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1347 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1348
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1349 #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1350 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1351
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
1352 /* Media and FP Feature Register 0 Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1353 #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1354 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1355
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1356 #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1357 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1358
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1359 #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1360 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1361
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1362 #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1363 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1364
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1365 #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1366 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1367
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1368 #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1369 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1370
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1371 #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1372 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1373
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1374 #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1375 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
1376
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
1377 /* Media and FP Feature Register 1 Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
1378 #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1379 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1380
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1381 #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1382 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1383
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1384 #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1385 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1386
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1387 #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1388 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1389
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1390 /*@} end of group CMSIS_FPU */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1391 #endif
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1392
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
1393
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1394 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1395 \ingroup CMSIS_core_register
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1396 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1397 \brief Type definitions for the Core Debug Registers
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1398 @{
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1399 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1400
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1401 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1402 \brief Structure type to access the Core Debug Register (CoreDebug).
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1403 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1404 typedef struct
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1405 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1406 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1407 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1408 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1409 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1410 } CoreDebug_Type;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1411
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1412 /* Debug Halting Control and Status Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1413 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1414 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1415
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1416 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1417 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1418
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1419 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1420 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1421
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1422 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1423 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1424
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1425 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1426 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1427
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1428 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1429 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1430
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1431 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1432 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1433
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1434 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1435 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1436
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1437 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1438 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1439
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1440 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1441 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1442
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1443 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1444 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1445
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1446 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1447 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1448
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1449 /* Debug Core Register Selector Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1450 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1451 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1452
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1453 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1454 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1455
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1456 /* Debug Exception and Monitor Control Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1457 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1458 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1459
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1460 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1461 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1462
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1463 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1464 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1465
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1466 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1467 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1468
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1469 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1470 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1471
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1472 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1473 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1474
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1475 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1476 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
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diff changeset
1477
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1478 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1479 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
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diff changeset
1480
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1481 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1482 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
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diff changeset
1483
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1484 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1485 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1486
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1487 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1488 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
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diff changeset
1489
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1490 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1491 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
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diff changeset
1492
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1493 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1494 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1495
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1496 /*@} end of group CMSIS_CoreDebug */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1497
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1498
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1499 /**
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diff changeset
1500 \ingroup CMSIS_core_register
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1501 \defgroup CMSIS_core_bitfield Core register bit field macros
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1502 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1503 @{
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1504 */
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diff changeset
1505
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1506 /**
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diff changeset
1507 \brief Mask and shift a bit field value for use in a register bit range.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1508 \param[in] field Name of the register bit field.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1509 \param[in] value Value of the bit field.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1510 \return Masked and shifted value.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1511 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1512 #define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1513
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1514 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1515 \brief Mask and shift a register value to extract a bit filed value.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1516 \param[in] field Name of the register bit field.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1517 \param[in] value Value of register.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1518 \return Masked and shifted bit field value.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1519 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1520 #define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1521
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1522 /*@} end of group CMSIS_core_bitfield */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1523
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1524
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1525 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1526 \ingroup CMSIS_core_register
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1527 \defgroup CMSIS_core_base Core Definitions
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1528 \brief Definitions for base addresses, unions, and structures.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1529 @{
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1530 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1531
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1532 /* Memory mapping of Cortex-M4 Hardware */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1533 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1534 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1535 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1536 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1537 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1538 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1539 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1540 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1541
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1542 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1543 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1544 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1545 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1546 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1547 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1548 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1549 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1550
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1551 #if (__MPU_PRESENT == 1U)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1552 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1553 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1554 #endif
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1555
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1556 #if (__FPU_PRESENT == 1U)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1557 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1558 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1559 #endif
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1560
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1561 /*@} */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1562
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1563
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1564
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1565 /*******************************************************************************
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1566 * Hardware Abstraction Layer
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1567 Core Function Interface contains:
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1568 - Core NVIC Functions
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1569 - Core SysTick Functions
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1570 - Core Debug Functions
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1571 - Core Register Access Functions
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1572 ******************************************************************************/
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1573 /**
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1574 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1575 */
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1576
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1577
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1578
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1579 /* ########################## NVIC functions #################################### */
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1580 /**
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1581 \ingroup CMSIS_Core_FunctionInterface
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1582 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
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1583 \brief Functions that manage interrupts and exceptions via the NVIC.
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1584 @{
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1585 */
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1586
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1587 /**
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1588 \brief Set Priority Grouping
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1589 \details Sets the priority grouping field using the required unlock sequence.
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1590 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
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1591 Only values from 0..7 are used.
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1592 In case of a conflict between priority grouping and available
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1593 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
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1594 \param [in] PriorityGroup Priority grouping field.
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1595 */
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1596 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
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1597 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1598 uint32_t reg_value;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1599 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
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1600
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1601 reg_value = SCB->AIRCR; /* read old register configuration */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1602 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1603 reg_value = (reg_value |
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1604 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1605 (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1606 SCB->AIRCR = reg_value;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1607 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1608
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1609
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1610 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1611 \brief Get Priority Grouping
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1612 \details Reads the priority grouping field from the NVIC Interrupt Controller.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1613 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1614 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1615 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1616 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1617 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1618 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1619
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1620
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1621 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1622 \brief Enable External Interrupt
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1623 \details Enables a device-specific interrupt in the NVIC interrupt controller.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1624 \param [in] IRQn External interrupt number. Value cannot be negative.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1625 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1626 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
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1627 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1628 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
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1629 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1630
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1631
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1632 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1633 \brief Disable External Interrupt
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1634 \details Disables a device-specific interrupt in the NVIC interrupt controller.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1635 \param [in] IRQn External interrupt number. Value cannot be negative.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1636 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1637 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1638 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1639 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1640 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1641
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1642
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1643 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1644 \brief Get Pending Interrupt
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1645 \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1646 \param [in] IRQn Interrupt number.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1647 \return 0 Interrupt status is not pending.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1648 \return 1 Interrupt status is pending.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1649 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1650 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1651 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1652 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1653 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1654
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1655
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1656 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1657 \brief Set Pending Interrupt
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1658 \details Sets the pending bit of an external interrupt.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1659 \param [in] IRQn Interrupt number. Value cannot be negative.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1660 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1661 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1662 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1663 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1664 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1665
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1666
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1667 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1668 \brief Clear Pending Interrupt
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1669 \details Clears the pending bit of an external interrupt.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1670 \param [in] IRQn External interrupt number. Value cannot be negative.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1671 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1672 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1673 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1674 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1675 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1676
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1677
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1678 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1679 \brief Get Active Interrupt
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1680 \details Reads the active register in NVIC and returns the active bit.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1681 \param [in] IRQn Interrupt number.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1682 \return 0 Interrupt status is not active.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1683 \return 1 Interrupt status is active.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1684 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1685 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1686 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1687 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1688 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1689
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1690
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1691 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1692 \brief Set Interrupt Priority
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1693 \details Sets the priority of an interrupt.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1694 \note The priority cannot be set for every core interrupt.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1695 \param [in] IRQn Interrupt number.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1696 \param [in] priority Priority to set.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1697 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1698 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1699 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1700 if ((int32_t)(IRQn) < 0)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1701 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1702 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1703 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1704 else
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1705 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1706 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
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1707 }
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1708 }
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1709
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1710
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1711 /**
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1712 \brief Get Interrupt Priority
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1713 \details Reads the priority of an interrupt.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1714 The interrupt number can be positive to specify an external (device specific) interrupt,
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1715 or negative to specify an internal (core) interrupt.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1716 \param [in] IRQn Interrupt number.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1717 \return Interrupt Priority.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1718 Value is aligned automatically to the implemented priority bits of the microcontroller.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1719 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1720 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
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1721 {
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1722
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1723 if ((int32_t)(IRQn) < 0)
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1724 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1725 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
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1726 }
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1727 else
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1728 {
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1729 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
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1730 }
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1731 }
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1732
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1733
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1734 /**
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1735 \brief Encode Priority
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1736 \details Encodes the priority for an interrupt with the given priority group,
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1737 preemptive priority value, and subpriority value.
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1738 In case of a conflict between priority grouping and available
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1739 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
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1740 \param [in] PriorityGroup Used priority group.
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1741 \param [in] PreemptPriority Preemptive priority value (starting from 0).
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1742 \param [in] SubPriority Subpriority value (starting from 0).
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1743 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
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1744 */
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1745 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
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1746 {
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1747 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
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1748 uint32_t PreemptPriorityBits;
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1749 uint32_t SubPriorityBits;
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1750
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diff changeset
1751 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
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1752 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
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1753
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1754 return (
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1755 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
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1756 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1757 );
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diff changeset
1758 }
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diff changeset
1759
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diff changeset
1760
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diff changeset
1761 /**
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1762 \brief Decode Priority
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1763 \details Decodes an interrupt priority value with a given priority group to
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1764 preemptive priority value and subpriority value.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1765 In case of a conflict between priority grouping and available
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1766 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
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1767 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
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1768 \param [in] PriorityGroup Used priority group.
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1769 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
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1770 \param [out] pSubPriority Subpriority value (starting from 0).
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1771 */
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1772 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
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1773 {
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1774 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
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1775 uint32_t PreemptPriorityBits;
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1776 uint32_t SubPriorityBits;
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1777
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1778 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
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1779 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
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1780
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1781 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
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1782 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
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1783 }
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1784
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diff changeset
1785
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1786 /**
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1787 \brief System Reset
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1788 \details Initiates a system reset request to reset the MCU.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1789 */
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1790 __STATIC_INLINE void NVIC_SystemReset(void)
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1791 {
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1792 __DSB(); /* Ensure all outstanding memory accesses included
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1793 buffered write are completed before reset */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1794 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
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1795 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
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1796 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
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1797 __DSB(); /* Ensure completion of memory access */
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1798
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1799 for(;;) /* wait until reset */
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1800 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1801 __NOP();
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1802 }
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1803 }
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1804
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1805 /*@} end of CMSIS_Core_NVICFunctions */
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1806
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1807
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1808
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1809 /* ################################## SysTick function ############################################ */
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1810 /**
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1811 \ingroup CMSIS_Core_FunctionInterface
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1812 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
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1813 \brief Functions that configure the System.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1814 @{
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1815 */
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1816
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1817 #if (__Vendor_SysTickConfig == 0U)
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1818
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1819 /**
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1820 \brief System Tick Configuration
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1821 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
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1822 Counter is in free running mode to generate periodic interrupts.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1823 \param [in] ticks Number of ticks between two interrupts.
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1824 \return 0 Function succeeded.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1825 \return 1 Function failed.
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1826 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1827 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
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1828 must contain a vendor-specific implementation of this function.
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1829 */
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1830 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
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1831 {
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1832 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
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1833 {
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1834 return (1UL); /* Reload value impossible */
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1835 }
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1836
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1837 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
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1838 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
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1839 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
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1840 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
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1841 SysTick_CTRL_TICKINT_Msk |
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1842 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
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1843 return (0UL); /* Function successful */
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1844 }
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1845
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1846 #endif
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1847
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1848 /*@} end of CMSIS_Core_SysTickFunctions */
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1849
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1850
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1851
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1852 /* ##################################### Debug In/Output function ########################################### */
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1853 /**
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1854 \ingroup CMSIS_Core_FunctionInterface
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1855 \defgroup CMSIS_core_DebugFunctions ITM Functions
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1856 \brief Functions that access the ITM debug interface.
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1857 @{
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1858 */
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1859
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1860 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
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1861 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
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1862
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1863
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1864 /**
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1865 \brief ITM Send Character
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1866 \details Transmits a character via the ITM channel 0, and
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1867 \li Just returns when no debugger is connected that has booked the output.
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1868 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
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1869 \param [in] ch Character to transmit.
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1870 \returns Character to transmit.
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1871 */
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1872 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
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1873 {
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1874 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
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1875 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
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1876 {
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1877 while (ITM->PORT[0U].u32 == 0UL)
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1878 {
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1879 __NOP();
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1880 }
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1881 ITM->PORT[0U].u8 = (uint8_t)ch;
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1882 }
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1883 return (ch);
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1884 }
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1885
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1886
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1887 /**
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1888 \brief ITM Receive Character
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1889 \details Inputs a character via the external variable \ref ITM_RxBuffer.
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1890 \return Received character.
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1891 \return -1 No character pending.
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1892 */
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1893 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
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1894 {
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1895 int32_t ch = -1; /* no character available */
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1896
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1897 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
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1898 {
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1899 ch = ITM_RxBuffer;
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1900 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
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1901 }
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1902
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1903 return (ch);
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1904 }
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1905
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1906
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1907 /**
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1908 \brief ITM Check Character
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1909 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
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1910 \return 0 No character available.
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1911 \return 1 Character available.
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1912 */
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1913 __STATIC_INLINE int32_t ITM_CheckChar (void)
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1914 {
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1915
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1916 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
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1917 {
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1918 return (0); /* no character available */
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1919 }
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1920 else
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1921 {
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1922 return (1); /* character available */
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1923 }
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1924 }
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1925
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1926 /*@} end of CMSIS_core_DebugFunctions */
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1927
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1928
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1929
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1930
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1931 #ifdef __cplusplus
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1932 }
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1933 #endif
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1934
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1935 #endif /* __CORE_CM4_H_DEPENDANT */
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1936
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1937 #endif /* __CMSIS_GENERIC */