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annotate Common/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sram.h @ 301:a09b1855d656 cleanup-4

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cleanup, RTE: factor out scheduleCheck_pressure_reached_dive_mode_level The detection of the start of dive mode is conceptually simple (when the pressure sensor reaches a certain threshold, we are diving). This said, there are multiple implementations over the entire code base to answer the question: are we diving? This commit factors out scheduleCheck_pressure_reached_dive_mode_level used only in the RTE, in favor of is_ambient_pressure_close_to_surface, which is used in both RTE and CPU1 firmware. I had a little hope that is would fix the 1 second difference between the initial stopwatch and the divetime, but it does not. Signed-off-by: Jan Mulder <jlmulder@xs4all.nl>
author Jan Mulder <jlmulder@xs4all.nl>
date Mon, 20 May 2019 10:05:27 +0200
parents c78bcbd5deda
children
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1 /**
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2 ******************************************************************************
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3 * @file stm32f4xx_hal_sram.h
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4 * @author MCD Application Team
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5 * @brief Header file of SRAM HAL module.
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6 ******************************************************************************
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7 * @attention
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8 *
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9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
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10 *
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11 * Redistribution and use in source and binary forms, with or without modification,
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12 * are permitted provided that the following conditions are met:
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13 * 1. Redistributions of source code must retain the above copyright notice,
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14 * this list of conditions and the following disclaimer.
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15 * 2. Redistributions in binary form must reproduce the above copyright notice,
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16 * this list of conditions and the following disclaimer in the documentation
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17 * and/or other materials provided with the distribution.
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18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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19 * may be used to endorse or promote products derived from this software
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20 * without specific prior written permission.
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21 *
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22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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32 *
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33 ******************************************************************************
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34 */
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35
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36 /* Define to prevent recursive inclusion -------------------------------------*/
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37 #ifndef __STM32F4xx_HAL_SRAM_H
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38 #define __STM32F4xx_HAL_SRAM_H
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39
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40 #ifdef __cplusplus
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41 extern "C" {
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42 #endif
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43
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44 /* Includes ------------------------------------------------------------------*/
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45 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
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46 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
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47 #include "stm32f4xx_ll_fsmc.h"
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48 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
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49
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50 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
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51 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
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52 #include "stm32f4xx_ll_fmc.h"
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53 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
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54
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55
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56 /** @addtogroup STM32F4xx_HAL_Driver
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57 * @{
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58 */
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59
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60 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
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61 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
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62 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
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63 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
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64
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65 /** @addtogroup SRAM
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66 * @{
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67 */
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68
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69 /* Exported typedef ----------------------------------------------------------*/
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70
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71 /** @defgroup SRAM_Exported_Types SRAM Exported Types
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72 * @{
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73 */
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74 /**
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75 * @brief HAL SRAM State structures definition
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76 */
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77 typedef enum
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78 {
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79 HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */
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80 HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */
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81 HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */
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82 HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */
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83 HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */
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84
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85 }HAL_SRAM_StateTypeDef;
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86
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87 /**
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88 * @brief SRAM handle Structure definition
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89 */
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90 typedef struct
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91 {
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92 FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
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93
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94 FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
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95
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96 FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */
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97
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98 HAL_LockTypeDef Lock; /*!< SRAM locking object */
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99
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100 __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */
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101
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102 DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
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103
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104 }SRAM_HandleTypeDef;
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105
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106 /**
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107 * @}
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108 */
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109
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110 /* Exported constants --------------------------------------------------------*/
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111 /* Exported macro ------------------------------------------------------------*/
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112
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113 /** @defgroup SRAM_Exported_Macros SRAM Exported Macros
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114 * @{
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115 */
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116 /** @brief Reset SRAM handle state
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117 * @param __HANDLE__ SRAM handle
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118 * @retval None
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119 */
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120 #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
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121
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122 /**
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123 * @}
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124 */
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125 /* Exported functions --------------------------------------------------------*/
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126
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127 /** @addtogroup SRAM_Exported_Functions
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128 * @{
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129 */
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130
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131 /** @addtogroup SRAM_Exported_Functions_Group1
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132 * @{
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133 */
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134 /* Initialization/de-initialization functions **********************************/
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135 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
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136 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
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137 void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
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138 void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
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139
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140 void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
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141 void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
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142 /**
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143 * @}
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144 */
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145
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146 /** @addtogroup SRAM_Exported_Functions_Group2
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147 * @{
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148 */
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149 /* I/O operation functions *****************************************************/
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150 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
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151 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
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152 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
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153 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
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154 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
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155 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
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156 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
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157 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
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158 /**
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159 * @}
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160 */
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161
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162 /** @addtogroup SRAM_Exported_Functions_Group3
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163 * @{
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164 */
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165 /* SRAM Control functions ******************************************************/
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166 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
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167 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
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168 /**
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169 * @}
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170 */
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171
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172 /** @addtogroup SRAM_Exported_Functions_Group4
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173 * @{
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174 */
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175 /* SRAM State functions *********************************************************/
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176 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
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177 /**
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178 * @}
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179 */
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180
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181 /**
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182 * @}
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183 */
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184
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185 /* Private types -------------------------------------------------------------*/
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186 /* Private variables ---------------------------------------------------------*/
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187 /* Private constants ---------------------------------------------------------*/
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188 /* Private macros ------------------------------------------------------------*/
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189 /* Private functions ---------------------------------------------------------*/
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190 /**
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191 * @}
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192 */
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193
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194 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
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195 STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
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196 STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
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197 /**
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198 * @}
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199 */
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200 #ifdef __cplusplus
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201 }
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202 #endif
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203
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204 #endif /* __STM32F4xx_HAL_SRAM_H */
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205
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206 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/