Mercurial > public > ostc4
annotate Common/Drivers/CMSIS/Include/cmsis_armcc.h @ 301:a09b1855d656 cleanup-4
cleanup, RTE: factor out scheduleCheck_pressure_reached_dive_mode_level
The detection of the start of dive mode is conceptually simple (when the
pressure sensor reaches a certain threshold, we are diving). This said,
there are multiple implementations over the entire code base to answer
the question: are we diving?
This commit factors out scheduleCheck_pressure_reached_dive_mode_level used
only in the RTE, in favor of is_ambient_pressure_close_to_surface, which
is used in both RTE and CPU1 firmware.
I had a little hope that is would fix the 1 second difference between
the initial stopwatch and the divetime, but it does not.
Signed-off-by: Jan Mulder <jlmulder@xs4all.nl>
author | Jan Mulder <jlmulder@xs4all.nl> |
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date | Mon, 20 May 2019 10:05:27 +0200 |
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rev | line source |
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1 /**************************************************************************//** |
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2 * @file cmsis_armcc.h |
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3 * @brief CMSIS Cortex-M Core Function/Instruction Header File |
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4 * @version V4.30 |
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5 * @date 20. October 2015 |
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6 ******************************************************************************/ |
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7 /* Copyright (c) 2009 - 2015 ARM LIMITED |
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8 |
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9 All rights reserved. |
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10 Redistribution and use in source and binary forms, with or without |
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11 modification, are permitted provided that the following conditions are met: |
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12 - Redistributions of source code must retain the above copyright |
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13 notice, this list of conditions and the following disclaimer. |
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14 - Redistributions in binary form must reproduce the above copyright |
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15 notice, this list of conditions and the following disclaimer in the |
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16 documentation and/or other materials provided with the distribution. |
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17 - Neither the name of ARM nor the names of its contributors may be used |
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18 to endorse or promote products derived from this software without |
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19 specific prior written permission. |
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20 * |
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21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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24 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
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25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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31 POSSIBILITY OF SUCH DAMAGE. |
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32 ---------------------------------------------------------------------------*/ |
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33 |
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34 |
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35 #ifndef __CMSIS_ARMCC_H |
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36 #define __CMSIS_ARMCC_H |
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37 |
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38 |
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39 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) |
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40 #error "Please use ARM Compiler Toolchain V4.0.677 or later!" |
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41 #endif |
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42 |
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43 /* ########################### Core Function Access ########################### */ |
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44 /** \ingroup CMSIS_Core_FunctionInterface |
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45 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions |
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46 @{ |
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47 */ |
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48 |
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49 /* intrinsic void __enable_irq(); */ |
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50 /* intrinsic void __disable_irq(); */ |
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51 |
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52 /** |
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53 \brief Get Control Register |
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54 \details Returns the content of the Control Register. |
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55 \return Control Register value |
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56 */ |
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57 __STATIC_INLINE uint32_t __get_CONTROL(void) |
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58 { |
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59 register uint32_t __regControl __ASM("control"); |
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60 return(__regControl); |
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61 } |
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62 |
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63 |
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64 /** |
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65 \brief Set Control Register |
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66 \details Writes the given value to the Control Register. |
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67 \param [in] control Control Register value to set |
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68 */ |
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69 __STATIC_INLINE void __set_CONTROL(uint32_t control) |
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70 { |
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71 register uint32_t __regControl __ASM("control"); |
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72 __regControl = control; |
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73 } |
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74 |
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75 |
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76 /** |
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77 \brief Get IPSR Register |
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78 \details Returns the content of the IPSR Register. |
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79 \return IPSR Register value |
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80 */ |
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81 __STATIC_INLINE uint32_t __get_IPSR(void) |
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82 { |
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83 register uint32_t __regIPSR __ASM("ipsr"); |
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84 return(__regIPSR); |
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85 } |
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86 |
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87 |
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88 /** |
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89 \brief Get APSR Register |
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90 \details Returns the content of the APSR Register. |
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91 \return APSR Register value |
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92 */ |
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93 __STATIC_INLINE uint32_t __get_APSR(void) |
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94 { |
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95 register uint32_t __regAPSR __ASM("apsr"); |
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96 return(__regAPSR); |
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97 } |
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98 |
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99 |
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100 /** |
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101 \brief Get xPSR Register |
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102 \details Returns the content of the xPSR Register. |
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103 \return xPSR Register value |
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104 */ |
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105 __STATIC_INLINE uint32_t __get_xPSR(void) |
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106 { |
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107 register uint32_t __regXPSR __ASM("xpsr"); |
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108 return(__regXPSR); |
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109 } |
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110 |
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111 |
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112 /** |
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113 \brief Get Process Stack Pointer |
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114 \details Returns the current value of the Process Stack Pointer (PSP). |
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115 \return PSP Register value |
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116 */ |
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117 __STATIC_INLINE uint32_t __get_PSP(void) |
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118 { |
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119 register uint32_t __regProcessStackPointer __ASM("psp"); |
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120 return(__regProcessStackPointer); |
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121 } |
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122 |
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123 |
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124 /** |
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125 \brief Set Process Stack Pointer |
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126 \details Assigns the given value to the Process Stack Pointer (PSP). |
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127 \param [in] topOfProcStack Process Stack Pointer value to set |
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128 */ |
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129 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) |
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130 { |
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131 register uint32_t __regProcessStackPointer __ASM("psp"); |
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132 __regProcessStackPointer = topOfProcStack; |
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133 } |
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134 |
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135 |
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136 /** |
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137 \brief Get Main Stack Pointer |
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138 \details Returns the current value of the Main Stack Pointer (MSP). |
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139 \return MSP Register value |
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140 */ |
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141 __STATIC_INLINE uint32_t __get_MSP(void) |
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142 { |
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143 register uint32_t __regMainStackPointer __ASM("msp"); |
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144 return(__regMainStackPointer); |
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145 } |
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146 |
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147 |
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148 /** |
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149 \brief Set Main Stack Pointer |
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150 \details Assigns the given value to the Main Stack Pointer (MSP). |
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151 \param [in] topOfMainStack Main Stack Pointer value to set |
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152 */ |
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153 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) |
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154 { |
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155 register uint32_t __regMainStackPointer __ASM("msp"); |
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156 __regMainStackPointer = topOfMainStack; |
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157 } |
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158 |
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159 |
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160 /** |
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161 \brief Get Priority Mask |
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162 \details Returns the current state of the priority mask bit from the Priority Mask Register. |
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163 \return Priority Mask value |
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164 */ |
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165 __STATIC_INLINE uint32_t __get_PRIMASK(void) |
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166 { |
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167 register uint32_t __regPriMask __ASM("primask"); |
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168 return(__regPriMask); |
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169 } |
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170 |
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171 |
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172 /** |
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173 \brief Set Priority Mask |
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174 \details Assigns the given value to the Priority Mask Register. |
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175 \param [in] priMask Priority Mask |
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176 */ |
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177 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) |
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178 { |
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179 register uint32_t __regPriMask __ASM("primask"); |
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180 __regPriMask = (priMask); |
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181 } |
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182 |
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183 |
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184 #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) |
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185 |
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186 /** |
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187 \brief Enable FIQ |
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188 \details Enables FIQ interrupts by clearing the F-bit in the CPSR. |
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189 Can only be executed in Privileged modes. |
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190 */ |
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191 #define __enable_fault_irq __enable_fiq |
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192 |
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193 |
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194 /** |
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195 \brief Disable FIQ |
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196 \details Disables FIQ interrupts by setting the F-bit in the CPSR. |
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197 Can only be executed in Privileged modes. |
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198 */ |
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199 #define __disable_fault_irq __disable_fiq |
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200 |
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201 |
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202 /** |
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203 \brief Get Base Priority |
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204 \details Returns the current value of the Base Priority register. |
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205 \return Base Priority register value |
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206 */ |
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207 __STATIC_INLINE uint32_t __get_BASEPRI(void) |
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208 { |
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209 register uint32_t __regBasePri __ASM("basepri"); |
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210 return(__regBasePri); |
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211 } |
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212 |
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213 |
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214 /** |
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215 \brief Set Base Priority |
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216 \details Assigns the given value to the Base Priority register. |
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217 \param [in] basePri Base Priority value to set |
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218 */ |
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219 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) |
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220 { |
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221 register uint32_t __regBasePri __ASM("basepri"); |
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222 __regBasePri = (basePri & 0xFFU); |
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223 } |
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224 |
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225 |
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226 /** |
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227 \brief Set Base Priority with condition |
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228 \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, |
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229 or the new value increases the BASEPRI priority level. |
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230 \param [in] basePri Base Priority value to set |
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231 */ |
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232 __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) |
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233 { |
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234 register uint32_t __regBasePriMax __ASM("basepri_max"); |
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235 __regBasePriMax = (basePri & 0xFFU); |
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236 } |
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237 |
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238 |
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239 /** |
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240 \brief Get Fault Mask |
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241 \details Returns the current value of the Fault Mask register. |
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242 \return Fault Mask register value |
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243 */ |
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244 __STATIC_INLINE uint32_t __get_FAULTMASK(void) |
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245 { |
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246 register uint32_t __regFaultMask __ASM("faultmask"); |
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247 return(__regFaultMask); |
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248 } |
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249 |
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250 |
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251 /** |
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252 \brief Set Fault Mask |
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253 \details Assigns the given value to the Fault Mask register. |
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254 \param [in] faultMask Fault Mask value to set |
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255 */ |
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256 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) |
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257 { |
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258 register uint32_t __regFaultMask __ASM("faultmask"); |
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259 __regFaultMask = (faultMask & (uint32_t)1); |
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260 } |
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261 |
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262 #endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ |
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263 |
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264 |
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265 #if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) |
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266 |
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267 /** |
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268 \brief Get FPSCR |
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269 \details Returns the current value of the Floating Point Status/Control register. |
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270 \return Floating Point Status/Control register value |
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271 */ |
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272 __STATIC_INLINE uint32_t __get_FPSCR(void) |
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273 { |
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274 #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) |
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275 register uint32_t __regfpscr __ASM("fpscr"); |
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276 return(__regfpscr); |
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277 #else |
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278 return(0U); |
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279 #endif |
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280 } |
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281 |
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282 |
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283 /** |
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284 \brief Set FPSCR |
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285 \details Assigns the given value to the Floating Point Status/Control register. |
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286 \param [in] fpscr Floating Point Status/Control value to set |
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287 */ |
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288 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) |
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289 { |
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290 #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) |
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291 register uint32_t __regfpscr __ASM("fpscr"); |
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292 __regfpscr = (fpscr); |
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293 #endif |
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294 } |
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295 |
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296 #endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ |
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297 |
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298 |
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299 |
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300 /*@} end of CMSIS_Core_RegAccFunctions */ |
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301 |
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302 |
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303 /* ########################## Core Instruction Access ######################### */ |
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304 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface |
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305 Access to dedicated instructions |
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306 @{ |
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307 */ |
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308 |
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309 /** |
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310 \brief No Operation |
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311 \details No Operation does nothing. This instruction can be used for code alignment purposes. |
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312 */ |
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313 #define __NOP __nop |
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314 |
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315 |
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316 /** |
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317 \brief Wait For Interrupt |
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318 \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. |
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319 */ |
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320 #define __WFI __wfi |
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321 |
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322 |
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323 /** |
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324 \brief Wait For Event |
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325 \details Wait For Event is a hint instruction that permits the processor to enter |
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326 a low-power state until one of a number of events occurs. |
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327 */ |
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328 #define __WFE __wfe |
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329 |
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330 |
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331 /** |
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332 \brief Send Event |
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333 \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. |
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334 */ |
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335 #define __SEV __sev |
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336 |
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337 |
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338 /** |
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339 \brief Instruction Synchronization Barrier |
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340 \details Instruction Synchronization Barrier flushes the pipeline in the processor, |
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341 so that all instructions following the ISB are fetched from cache or memory, |
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342 after the instruction has been completed. |
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343 */ |
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344 #define __ISB() do {\ |
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345 __schedule_barrier();\ |
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346 __isb(0xF);\ |
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347 __schedule_barrier();\ |
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348 } while (0U) |
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349 |
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350 /** |
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351 \brief Data Synchronization Barrier |
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352 \details Acts as a special kind of Data Memory Barrier. |
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353 It completes when all explicit memory accesses before this instruction complete. |
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354 */ |
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355 #define __DSB() do {\ |
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356 __schedule_barrier();\ |
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357 __dsb(0xF);\ |
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358 __schedule_barrier();\ |
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359 } while (0U) |
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360 |
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361 /** |
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362 \brief Data Memory Barrier |
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363 \details Ensures the apparent order of the explicit memory operations before |
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364 and after the instruction, without ensuring their completion. |
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365 */ |
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366 #define __DMB() do {\ |
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367 __schedule_barrier();\ |
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368 __dmb(0xF);\ |
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369 __schedule_barrier();\ |
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370 } while (0U) |
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371 |
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372 /** |
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373 \brief Reverse byte order (32 bit) |
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374 \details Reverses the byte order in integer value. |
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375 \param [in] value Value to reverse |
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376 \return Reversed value |
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377 */ |
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378 #define __REV __rev |
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379 |
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380 |
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381 /** |
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382 \brief Reverse byte order (16 bit) |
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383 \details Reverses the byte order in two unsigned short values. |
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384 \param [in] value Value to reverse |
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385 \return Reversed value |
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386 */ |
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387 #ifndef __NO_EMBEDDED_ASM |
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388 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) |
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389 { |
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390 rev16 r0, r0 |
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391 bx lr |
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392 } |
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393 #endif |
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394 |
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395 /** |
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396 \brief Reverse byte order in signed short value |
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397 \details Reverses the byte order in a signed short value with sign extension to integer. |
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398 \param [in] value Value to reverse |
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399 \return Reversed value |
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400 */ |
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401 #ifndef __NO_EMBEDDED_ASM |
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402 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) |
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403 { |
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404 revsh r0, r0 |
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405 bx lr |
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406 } |
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407 #endif |
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408 |
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409 |
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410 /** |
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411 \brief Rotate Right in unsigned value (32 bit) |
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412 \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. |
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413 \param [in] value Value to rotate |
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414 \param [in] value Number of Bits to rotate |
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415 \return Rotated value |
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416 */ |
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417 #define __ROR __ror |
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418 |
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419 |
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420 /** |
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421 \brief Breakpoint |
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422 \details Causes the processor to enter Debug state. |
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423 Debug tools can use this to investigate system state when the instruction at a particular address is reached. |
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424 \param [in] value is ignored by the processor. |
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425 If required, a debugger can use it to store additional information about the breakpoint. |
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426 */ |
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427 #define __BKPT(value) __breakpoint(value) |
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428 |
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429 |
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430 /** |
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431 \brief Reverse bit order of value |
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432 \details Reverses the bit order of the given value. |
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433 \param [in] value Value to reverse |
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434 \return Reversed value |
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435 */ |
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436 #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) |
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437 #define __RBIT __rbit |
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438 #else |
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439 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) |
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440 { |
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441 uint32_t result; |
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442 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ |
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443 |
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444 result = value; /* r will be reversed bits of v; first get LSB of v */ |
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445 for (value >>= 1U; value; value >>= 1U) |
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446 { |
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447 result <<= 1U; |
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448 result |= value & 1U; |
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449 s--; |
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450 } |
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451 result <<= s; /* shift when v's highest bits are zero */ |
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452 return(result); |
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453 } |
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454 #endif |
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455 |
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456 |
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457 /** |
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458 \brief Count leading zeros |
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459 \details Counts the number of leading zeros of a data value. |
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460 \param [in] value Value to count the leading zeros |
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461 \return number of leading zeros in value |
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462 */ |
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463 #define __CLZ __clz |
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464 |
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465 |
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466 #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) |
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467 |
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468 /** |
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469 \brief LDR Exclusive (8 bit) |
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470 \details Executes a exclusive LDR instruction for 8 bit value. |
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471 \param [in] ptr Pointer to data |
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472 \return value of type uint8_t at (*ptr) |
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473 */ |
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474 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) |
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475 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) |
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476 #else |
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477 #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") |
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478 #endif |
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479 |
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480 |
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481 /** |
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482 \brief LDR Exclusive (16 bit) |
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483 \details Executes a exclusive LDR instruction for 16 bit values. |
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484 \param [in] ptr Pointer to data |
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485 \return value of type uint16_t at (*ptr) |
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486 */ |
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487 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) |
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488 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) |
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489 #else |
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490 #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") |
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491 #endif |
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492 |
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493 |
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494 /** |
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495 \brief LDR Exclusive (32 bit) |
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496 \details Executes a exclusive LDR instruction for 32 bit values. |
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497 \param [in] ptr Pointer to data |
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498 \return value of type uint32_t at (*ptr) |
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499 */ |
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500 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) |
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501 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) |
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502 #else |
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503 #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") |
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504 #endif |
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505 |
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506 |
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507 /** |
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508 \brief STR Exclusive (8 bit) |
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509 \details Executes a exclusive STR instruction for 8 bit values. |
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510 \param [in] value Value to store |
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511 \param [in] ptr Pointer to location |
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512 \return 0 Function succeeded |
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513 \return 1 Function failed |
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514 */ |
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515 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) |
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516 #define __STREXB(value, ptr) __strex(value, ptr) |
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517 #else |
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518 #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") |
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519 #endif |
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520 |
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521 |
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522 /** |
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523 \brief STR Exclusive (16 bit) |
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524 \details Executes a exclusive STR instruction for 16 bit values. |
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525 \param [in] value Value to store |
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526 \param [in] ptr Pointer to location |
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527 \return 0 Function succeeded |
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528 \return 1 Function failed |
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529 */ |
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530 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) |
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531 #define __STREXH(value, ptr) __strex(value, ptr) |
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532 #else |
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533 #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") |
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534 #endif |
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535 |
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536 |
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537 /** |
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538 \brief STR Exclusive (32 bit) |
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539 \details Executes a exclusive STR instruction for 32 bit values. |
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540 \param [in] value Value to store |
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541 \param [in] ptr Pointer to location |
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542 \return 0 Function succeeded |
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543 \return 1 Function failed |
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544 */ |
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545 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) |
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546 #define __STREXW(value, ptr) __strex(value, ptr) |
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547 #else |
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548 #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") |
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549 #endif |
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550 |
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551 |
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552 /** |
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553 \brief Remove the exclusive lock |
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554 \details Removes the exclusive lock which is created by LDREX. |
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555 */ |
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556 #define __CLREX __clrex |
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557 |
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558 |
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559 /** |
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560 \brief Signed Saturate |
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561 \details Saturates a signed value. |
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562 \param [in] value Value to be saturated |
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563 \param [in] sat Bit position to saturate to (1..32) |
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564 \return Saturated value |
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565 */ |
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566 #define __SSAT __ssat |
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567 |
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568 |
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569 /** |
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570 \brief Unsigned Saturate |
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571 \details Saturates an unsigned value. |
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572 \param [in] value Value to be saturated |
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573 \param [in] sat Bit position to saturate to (0..31) |
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574 \return Saturated value |
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575 */ |
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576 #define __USAT __usat |
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577 |
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578 |
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579 /** |
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580 \brief Rotate Right with Extend (32 bit) |
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581 \details Moves each bit of a bitstring right by one bit. |
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582 The carry input is shifted in at the left end of the bitstring. |
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583 \param [in] value Value to rotate |
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584 \return Rotated value |
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585 */ |
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586 #ifndef __NO_EMBEDDED_ASM |
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587 __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) |
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588 { |
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589 rrx r0, r0 |
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590 bx lr |
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591 } |
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592 #endif |
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593 |
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594 |
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595 /** |
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596 \brief LDRT Unprivileged (8 bit) |
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597 \details Executes a Unprivileged LDRT instruction for 8 bit value. |
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598 \param [in] ptr Pointer to data |
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599 \return value of type uint8_t at (*ptr) |
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600 */ |
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601 #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) |
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602 |
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603 |
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604 /** |
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605 \brief LDRT Unprivileged (16 bit) |
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606 \details Executes a Unprivileged LDRT instruction for 16 bit values. |
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607 \param [in] ptr Pointer to data |
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608 \return value of type uint16_t at (*ptr) |
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609 */ |
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610 #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) |
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611 |
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612 |
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613 /** |
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614 \brief LDRT Unprivileged (32 bit) |
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615 \details Executes a Unprivileged LDRT instruction for 32 bit values. |
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616 \param [in] ptr Pointer to data |
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617 \return value of type uint32_t at (*ptr) |
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618 */ |
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619 #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) |
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620 |
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621 |
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622 /** |
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623 \brief STRT Unprivileged (8 bit) |
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624 \details Executes a Unprivileged STRT instruction for 8 bit values. |
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625 \param [in] value Value to store |
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626 \param [in] ptr Pointer to location |
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627 */ |
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628 #define __STRBT(value, ptr) __strt(value, ptr) |
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629 |
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630 |
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631 /** |
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632 \brief STRT Unprivileged (16 bit) |
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633 \details Executes a Unprivileged STRT instruction for 16 bit values. |
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634 \param [in] value Value to store |
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635 \param [in] ptr Pointer to location |
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636 */ |
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637 #define __STRHT(value, ptr) __strt(value, ptr) |
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638 |
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639 |
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640 /** |
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641 \brief STRT Unprivileged (32 bit) |
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642 \details Executes a Unprivileged STRT instruction for 32 bit values. |
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643 \param [in] value Value to store |
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644 \param [in] ptr Pointer to location |
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645 */ |
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646 #define __STRT(value, ptr) __strt(value, ptr) |
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647 |
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648 #endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ |
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649 |
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650 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ |
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651 |
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652 |
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653 /* ################### Compiler specific Intrinsics ########################### */ |
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654 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics |
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655 Access to dedicated SIMD instructions |
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656 @{ |
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657 */ |
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658 |
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659 #if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ |
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660 |
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661 #define __SADD8 __sadd8 |
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662 #define __QADD8 __qadd8 |
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663 #define __SHADD8 __shadd8 |
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664 #define __UADD8 __uadd8 |
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665 #define __UQADD8 __uqadd8 |
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666 #define __UHADD8 __uhadd8 |
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667 #define __SSUB8 __ssub8 |
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668 #define __QSUB8 __qsub8 |
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669 #define __SHSUB8 __shsub8 |
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670 #define __USUB8 __usub8 |
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671 #define __UQSUB8 __uqsub8 |
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672 #define __UHSUB8 __uhsub8 |
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673 #define __SADD16 __sadd16 |
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674 #define __QADD16 __qadd16 |
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675 #define __SHADD16 __shadd16 |
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676 #define __UADD16 __uadd16 |
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677 #define __UQADD16 __uqadd16 |
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678 #define __UHADD16 __uhadd16 |
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679 #define __SSUB16 __ssub16 |
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680 #define __QSUB16 __qsub16 |
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681 #define __SHSUB16 __shsub16 |
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682 #define __USUB16 __usub16 |
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683 #define __UQSUB16 __uqsub16 |
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684 #define __UHSUB16 __uhsub16 |
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685 #define __SASX __sasx |
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686 #define __QASX __qasx |
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687 #define __SHASX __shasx |
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688 #define __UASX __uasx |
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689 #define __UQASX __uqasx |
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690 #define __UHASX __uhasx |
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691 #define __SSAX __ssax |
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692 #define __QSAX __qsax |
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693 #define __SHSAX __shsax |
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694 #define __USAX __usax |
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695 #define __UQSAX __uqsax |
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696 #define __UHSAX __uhsax |
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697 #define __USAD8 __usad8 |
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698 #define __USADA8 __usada8 |
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699 #define __SSAT16 __ssat16 |
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700 #define __USAT16 __usat16 |
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701 #define __UXTB16 __uxtb16 |
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702 #define __UXTAB16 __uxtab16 |
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703 #define __SXTB16 __sxtb16 |
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704 #define __SXTAB16 __sxtab16 |
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705 #define __SMUAD __smuad |
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706 #define __SMUADX __smuadx |
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707 #define __SMLAD __smlad |
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708 #define __SMLADX __smladx |
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709 #define __SMLALD __smlald |
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710 #define __SMLALDX __smlaldx |
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711 #define __SMUSD __smusd |
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712 #define __SMUSDX __smusdx |
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713 #define __SMLSD __smlsd |
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714 #define __SMLSDX __smlsdx |
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715 #define __SMLSLD __smlsld |
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716 #define __SMLSLDX __smlsldx |
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717 #define __SEL __sel |
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718 #define __QADD __qadd |
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719 #define __QSUB __qsub |
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720 |
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721 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ |
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722 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) |
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723 |
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724 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ |
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725 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) |
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726 |
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727 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ |
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728 ((int64_t)(ARG3) << 32U) ) >> 32U)) |
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729 |
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730 #endif /* (__CORTEX_M >= 0x04) */ |
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731 /*@} end of group CMSIS_SIMD_intrinsics */ |
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732 |
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733 |
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734 #endif /* __CMSIS_ARMCC_H */ |