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annotate Common/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma2d.h @ 441:9a9e4908ce2e
fix potential issue with >255 dives in the logbook
author | heinrichsweikamp |
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date | Sun, 01 Mar 2020 10:06:45 +0100 |
parents | c78bcbd5deda |
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rev | line source |
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128
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1 /** |
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2 ****************************************************************************** |
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3 * @file stm32f4xx_hal_dma2d.h |
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4 * @author MCD Application Team |
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5 * @brief Header file of DMA2D HAL module. |
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6 ****************************************************************************** |
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7 * @attention |
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8 * |
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9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
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10 * |
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11 * Redistribution and use in source and binary forms, with or without modification, |
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12 * are permitted provided that the following conditions are met: |
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13 * 1. Redistributions of source code must retain the above copyright notice, |
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14 * this list of conditions and the following disclaimer. |
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15 * 2. Redistributions in binary form must reproduce the above copyright notice, |
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16 * this list of conditions and the following disclaimer in the documentation |
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17 * and/or other materials provided with the distribution. |
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18 * 3. Neither the name of STMicroelectronics nor the names of its contributors |
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19 * may be used to endorse or promote products derived from this software |
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20 * without specific prior written permission. |
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21 * |
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22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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32 * |
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33 ****************************************************************************** |
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34 */ |
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35 |
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36 /* Define to prevent recursive inclusion -------------------------------------*/ |
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37 #ifndef __STM32F4xx_HAL_DMA2D_H |
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38 #define __STM32F4xx_HAL_DMA2D_H |
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39 |
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40 #ifdef __cplusplus |
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41 extern "C" { |
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42 #endif |
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43 |
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44 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ |
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45 defined(STM32F469xx) || defined(STM32F479xx) |
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46 /* Includes ------------------------------------------------------------------*/ |
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47 #include "stm32f4xx_hal_def.h" |
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48 |
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49 /** @addtogroup STM32F4xx_HAL_Driver |
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50 * @{ |
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51 */ |
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52 |
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53 /** @addtogroup DMA2D DMA2D |
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54 * @brief DMA2D HAL module driver |
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55 * @{ |
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56 */ |
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57 |
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58 /* Exported types ------------------------------------------------------------*/ |
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59 /** @defgroup DMA2D_Exported_Types DMA2D Exported Types |
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60 * @{ |
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61 */ |
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62 #define MAX_DMA2D_LAYER 2U |
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63 |
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64 /** |
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65 * @brief DMA2D color Structure definition |
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66 */ |
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67 typedef struct |
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68 { |
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69 uint32_t Blue; /*!< Configures the blue value. |
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70 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ |
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71 |
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72 uint32_t Green; /*!< Configures the green value. |
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73 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ |
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74 |
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75 uint32_t Red; /*!< Configures the red value. |
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76 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ |
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77 } DMA2D_ColorTypeDef; |
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78 |
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79 /** |
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80 * @brief DMA2D CLUT Structure definition |
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81 */ |
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82 typedef struct |
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83 { |
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84 uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/ |
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85 |
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86 uint32_t CLUTColorMode; /*!< Configures the DMA2D CLUT color mode. |
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87 This parameter can be one value of @ref DMA2D_CLUT_CM. */ |
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88 |
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89 uint32_t Size; /*!< Configures the DMA2D CLUT size. |
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90 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/ |
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91 } DMA2D_CLUTCfgTypeDef; |
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92 |
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93 /** |
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94 * @brief DMA2D Init structure definition |
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95 */ |
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96 typedef struct |
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97 { |
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98 uint32_t Mode; /*!< Configures the DMA2D transfer mode. |
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99 This parameter can be one value of @ref DMA2D_Mode. */ |
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100 |
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101 uint32_t ColorMode; /*!< Configures the color format of the output image. |
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102 This parameter can be one value of @ref DMA2D_Output_Color_Mode. */ |
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103 |
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104 uint32_t OutputOffset; /*!< Specifies the Offset value. |
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105 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */ |
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106 |
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107 } DMA2D_InitTypeDef; |
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108 |
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109 /** |
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110 * @brief DMA2D Layer structure definition |
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111 */ |
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112 typedef struct |
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113 { |
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114 uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset. |
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115 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */ |
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116 |
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117 uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode. |
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118 This parameter can be one value of @ref DMA2D_Input_Color_Mode. */ |
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119 |
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120 uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode. |
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121 This parameter can be one value of @ref DMA2D_Alpha_Mode. */ |
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122 |
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123 uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode. |
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124 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF except for the color modes detailed below. |
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125 @note In case of A8 or A4 color mode (ARGB), this parameter must be a number between |
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126 Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where |
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127 - InputAlpha[24:31] is the alpha value ALPHA[0:7] |
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128 - InputAlpha[16:23] is the red value RED[0:7] |
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129 - InputAlpha[8:15] is the green value GREEN[0:7] |
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130 - InputAlpha[0:7] is the blue value BLUE[0:7]. */ |
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131 |
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132 } DMA2D_LayerCfgTypeDef; |
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133 |
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134 /** |
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135 * @brief HAL DMA2D State structures definition |
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136 */ |
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137 typedef enum |
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138 { |
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139 HAL_DMA2D_STATE_RESET = 0x00U, /*!< DMA2D not yet initialized or disabled */ |
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140 HAL_DMA2D_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ |
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141 HAL_DMA2D_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ |
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142 HAL_DMA2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ |
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143 HAL_DMA2D_STATE_ERROR = 0x04U, /*!< DMA2D state error */ |
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144 HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */ |
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145 }HAL_DMA2D_StateTypeDef; |
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146 |
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147 /** |
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148 * @brief DMA2D handle Structure definition |
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149 */ |
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150 typedef struct __DMA2D_HandleTypeDef |
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151 { |
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152 DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */ |
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153 |
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154 DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */ |
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155 |
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156 void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback. */ |
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157 |
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158 void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback. */ |
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159 |
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160 DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */ |
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161 |
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162 HAL_LockTypeDef Lock; /*!< DMA2D lock. */ |
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163 |
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164 __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */ |
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165 |
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166 __IO uint32_t ErrorCode; /*!< DMA2D error code. */ |
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167 } DMA2D_HandleTypeDef; |
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168 /** |
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169 * @} |
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170 */ |
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171 |
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172 /* Exported constants --------------------------------------------------------*/ |
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173 /** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants |
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174 * @{ |
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175 */ |
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176 |
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177 /** @defgroup DMA2D_Error_Code DMA2D Error Code |
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178 * @{ |
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179 */ |
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180 #define HAL_DMA2D_ERROR_NONE 0x00000000U /*!< No error */ |
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181 #define HAL_DMA2D_ERROR_TE 0x00000001U /*!< Transfer error */ |
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182 #define HAL_DMA2D_ERROR_CE 0x00000002U /*!< Configuration error */ |
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183 #define HAL_DMA2D_ERROR_CAE 0x00000004U /*!< CLUT access error */ |
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184 #define HAL_DMA2D_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ |
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185 /** |
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186 * @} |
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187 */ |
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188 |
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189 /** @defgroup DMA2D_Mode DMA2D Mode |
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190 * @{ |
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191 */ |
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192 #define DMA2D_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */ |
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193 #define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */ |
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194 #define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */ |
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195 #define DMA2D_R2M DMA2D_CR_MODE /*!< DMA2D register to memory transfer mode */ |
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196 /** |
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197 * @} |
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198 */ |
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199 |
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200 /** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode |
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201 * @{ |
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202 */ |
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203 #define DMA2D_OUTPUT_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D color mode */ |
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204 #define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 DMA2D color mode */ |
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205 #define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 DMA2D color mode */ |
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206 #define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */ |
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207 #define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 DMA2D color mode */ |
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208 /** |
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209 * @} |
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210 */ |
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211 |
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212 /** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode |
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213 * @{ |
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214 */ |
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215 #define DMA2D_INPUT_ARGB8888 0x00000000U /*!< ARGB8888 color mode */ |
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216 #define DMA2D_INPUT_RGB888 0x00000001U /*!< RGB888 color mode */ |
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217 #define DMA2D_INPUT_RGB565 0x00000002U /*!< RGB565 color mode */ |
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218 #define DMA2D_INPUT_ARGB1555 0x00000003U /*!< ARGB1555 color mode */ |
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219 #define DMA2D_INPUT_ARGB4444 0x00000004U /*!< ARGB4444 color mode */ |
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220 #define DMA2D_INPUT_L8 0x00000005U /*!< L8 color mode */ |
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221 #define DMA2D_INPUT_AL44 0x00000006U /*!< AL44 color mode */ |
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222 #define DMA2D_INPUT_AL88 0x00000007U /*!< AL88 color mode */ |
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223 #define DMA2D_INPUT_L4 0x00000008U /*!< L4 color mode */ |
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224 #define DMA2D_INPUT_A8 0x00000009U /*!< A8 color mode */ |
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225 #define DMA2D_INPUT_A4 0x0000000AU /*!< A4 color mode */ |
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226 /** |
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227 * @} |
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228 */ |
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229 |
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230 /** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode |
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231 * @{ |
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232 */ |
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233 #define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */ |
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234 #define DMA2D_REPLACE_ALPHA 0x00000001U /*!< Replace original alpha channel value by programmed alpha value */ |
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235 #define DMA2D_COMBINE_ALPHA 0x00000002U /*!< Replace original alpha channel value by programmed alpha value |
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236 with original alpha channel value */ |
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237 /** |
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238 * @} |
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239 */ |
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240 |
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241 /** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode |
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242 * @{ |
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243 */ |
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244 #define DMA2D_CCM_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D CLUT color mode */ |
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245 #define DMA2D_CCM_RGB888 0x00000001U /*!< RGB888 DMA2D CLUT color mode */ |
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246 /** |
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247 * @} |
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248 */ |
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249 |
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250 /** @defgroup DMA2D_Interrupts DMA2D Interrupts |
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251 * @{ |
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252 */ |
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253 #define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */ |
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254 #define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */ |
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255 #define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */ |
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256 #define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */ |
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257 #define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */ |
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258 #define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */ |
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259 /** |
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260 * @} |
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261 */ |
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262 |
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263 /** @defgroup DMA2D_Flags DMA2D Flags |
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264 * @{ |
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265 */ |
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266 #define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */ |
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267 #define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */ |
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268 #define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */ |
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269 #define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */ |
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270 #define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */ |
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271 #define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */ |
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272 /** |
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273 * @} |
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274 */ |
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275 |
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276 /** @defgroup DMA2D_Aliases DMA2D API Aliases |
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277 * @{ |
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278 */ |
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279 #define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort for compatibility with legacy code */ |
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280 /** |
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281 * @} |
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282 */ |
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283 |
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284 /** |
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285 * @} |
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286 */ |
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287 /* Exported macros ------------------------------------------------------------*/ |
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288 /** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros |
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289 * @{ |
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290 */ |
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291 |
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292 /** @brief Reset DMA2D handle state |
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293 * @param __HANDLE__ specifies the DMA2D handle. |
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294 * @retval None |
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295 */ |
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296 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET) |
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297 |
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298 /** |
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299 * @brief Enable the DMA2D. |
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300 * @param __HANDLE__ DMA2D handle |
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301 * @retval None. |
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302 */ |
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303 #define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START) |
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304 |
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305 /* Interrupt & Flag management */ |
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306 /** |
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307 * @brief Get the DMA2D pending flags. |
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308 * @param __HANDLE__ DMA2D handle |
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309 * @param __FLAG__ flag to check. |
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310 * This parameter can be any combination of the following values: |
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311 * @arg DMA2D_FLAG_CE: Configuration error flag |
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312 * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag |
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313 * @arg DMA2D_FLAG_CAE: CLUT access error flag |
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314 * @arg DMA2D_FLAG_TW: Transfer Watermark flag |
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315 * @arg DMA2D_FLAG_TC: Transfer complete flag |
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316 * @arg DMA2D_FLAG_TE: Transfer error flag |
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317 * @retval The state of FLAG. |
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318 */ |
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319 #define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) |
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320 |
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321 /** |
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322 * @brief Clear the DMA2D pending flags. |
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323 * @param __HANDLE__ DMA2D handle |
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324 * @param __FLAG__ specifies the flag to clear. |
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325 * This parameter can be any combination of the following values: |
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326 * @arg DMA2D_FLAG_CE: Configuration error flag |
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327 * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag |
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328 * @arg DMA2D_FLAG_CAE: CLUT access error flag |
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329 * @arg DMA2D_FLAG_TW: Transfer Watermark flag |
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330 * @arg DMA2D_FLAG_TC: Transfer complete flag |
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331 * @arg DMA2D_FLAG_TE: Transfer error flag |
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332 * @retval None |
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333 */ |
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334 #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__)) |
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335 |
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336 /** |
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337 * @brief Enable the specified DMA2D interrupts. |
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338 * @param __HANDLE__ DMA2D handle |
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339 * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be enabled. |
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340 * This parameter can be any combination of the following values: |
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341 * @arg DMA2D_IT_CE: Configuration error interrupt mask |
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342 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask |
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343 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask |
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344 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask |
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345 * @arg DMA2D_IT_TC: Transfer complete interrupt mask |
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346 * @arg DMA2D_IT_TE: Transfer error interrupt mask |
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347 * @retval None |
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348 */ |
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349 #define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) |
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350 |
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351 /** |
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352 * @brief Disable the specified DMA2D interrupts. |
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353 * @param __HANDLE__ DMA2D handle |
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354 * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be disabled. |
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355 * This parameter can be any combination of the following values: |
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356 * @arg DMA2D_IT_CE: Configuration error interrupt mask |
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357 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask |
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358 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask |
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359 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask |
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360 * @arg DMA2D_IT_TC: Transfer complete interrupt mask |
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361 * @arg DMA2D_IT_TE: Transfer error interrupt mask |
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362 * @retval None |
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363 */ |
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364 #define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) |
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365 |
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366 /** |
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367 * @brief Check whether the specified DMA2D interrupt source is enabled or not. |
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368 * @param __HANDLE__ DMA2D handle |
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369 * @param __INTERRUPT__ specifies the DMA2D interrupt source to check. |
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370 * This parameter can be one of the following values: |
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371 * @arg DMA2D_IT_CE: Configuration error interrupt mask |
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372 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask |
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373 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask |
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374 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask |
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375 * @arg DMA2D_IT_TC: Transfer complete interrupt mask |
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376 * @arg DMA2D_IT_TE: Transfer error interrupt mask |
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377 * @retval The state of INTERRUPT source. |
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378 */ |
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379 #define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) |
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380 |
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381 /** |
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382 * @} |
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383 */ |
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384 |
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385 /* Exported functions --------------------------------------------------------*/ |
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386 /** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions |
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387 * @{ |
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388 */ |
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389 |
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390 /** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions |
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391 * @{ |
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392 */ |
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393 |
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394 /* Initialization and de-initialization functions *******************************/ |
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395 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d); |
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396 HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d); |
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397 void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d); |
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398 void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d); |
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399 |
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400 /** |
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401 * @} |
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402 */ |
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403 |
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404 /** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions |
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405 * @{ |
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406 */ |
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407 |
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408 /* IO operation functions *******************************************************/ |
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409 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height); |
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410 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height); |
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411 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height); |
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412 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height); |
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413 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d); |
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414 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d); |
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415 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d); |
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416 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); |
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417 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); |
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418 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); |
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419 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); |
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420 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); |
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421 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); |
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422 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout); |
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423 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d); |
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424 void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d); |
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425 void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d); |
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426 |
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427 /** |
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428 * @} |
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429 */ |
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430 |
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431 /** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions |
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432 * @{ |
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433 */ |
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434 |
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435 /* Peripheral Control functions *************************************************/ |
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436 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); |
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437 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); |
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438 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line); |
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439 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d); |
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440 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d); |
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441 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime); |
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442 |
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443 /** |
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444 * @} |
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445 */ |
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446 |
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447 /** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions |
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448 * @{ |
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449 */ |
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450 |
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451 /* Peripheral State functions ***************************************************/ |
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452 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d); |
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453 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); |
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454 |
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455 /** |
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456 * @} |
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457 */ |
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458 |
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459 /** |
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460 * @} |
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461 */ |
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462 |
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463 /* Private constants ---------------------------------------------------------*/ |
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464 |
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465 /** @addtogroup DMA2D_Private_Constants DMA2D Private Constants |
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466 * @{ |
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467 */ |
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468 |
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469 /** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark |
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470 * @{ |
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471 */ |
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472 #define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW /*!< DMA2D maximum line watermark */ |
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473 /** |
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474 * @} |
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475 */ |
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476 |
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477 /** @defgroup DMA2D_Color_Value DMA2D Color Value |
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478 * @{ |
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479 */ |
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480 #define DMA2D_COLOR_VALUE 0x000000FFU /*!< Color value mask */ |
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481 /** |
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482 * @} |
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483 */ |
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484 |
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485 /** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers |
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486 * @{ |
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487 */ |
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488 #define DMA2D_MAX_LAYER 2U /*!< DMA2D maximum number of layers */ |
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489 /** |
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490 * @} |
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491 */ |
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492 |
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493 /** @defgroup DMA2D_Offset DMA2D Offset |
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494 * @{ |
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495 */ |
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496 #define DMA2D_OFFSET DMA2D_FGOR_LO /*!< Line Offset */ |
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497 /** |
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498 * @} |
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499 */ |
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500 |
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501 /** @defgroup DMA2D_Size DMA2D Size |
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502 * @{ |
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503 */ |
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504 #define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D number of pixels per line */ |
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505 #define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D number of lines */ |
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506 /** |
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507 * @} |
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508 */ |
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509 |
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510 /** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size |
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511 * @{ |
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512 */ |
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513 #define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8U) /*!< DMA2D CLUT size */ |
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514 /** |
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515 * @} |
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516 */ |
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517 |
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518 /** |
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519 * @} |
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520 */ |
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521 |
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522 /* Private macros ------------------------------------------------------------*/ |
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523 /** @defgroup DMA2D_Private_Macros DMA2D Private Macros |
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524 * @{ |
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525 */ |
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526 #define IS_DMA2D_LAYER(LAYER) ((LAYER) <= DMA2D_MAX_LAYER) |
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527 #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ |
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528 ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M)) |
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529 #define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \ |
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530 ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \ |
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531 ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444)) |
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532 #define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE) |
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533 #define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE) |
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534 #define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL) |
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535 #define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET) |
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536 #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888) || \ |
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537 ((INPUT_CM) == DMA2D_INPUT_RGB565) || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \ |
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538 ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8) || \ |
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539 ((INPUT_CM) == DMA2D_INPUT_AL44) || ((INPUT_CM) == DMA2D_INPUT_AL88) || \ |
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540 ((INPUT_CM) == DMA2D_INPUT_L4) || ((INPUT_CM) == DMA2D_INPUT_A8) || \ |
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541 ((INPUT_CM) == DMA2D_INPUT_A4)) |
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542 #define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \ |
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543 ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \ |
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544 ((AlphaMode) == DMA2D_COMBINE_ALPHA)) |
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545 |
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546 #define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888)) |
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547 #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE) |
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548 #define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX) |
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549 #define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \ |
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550 ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \ |
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551 ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE)) |
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552 #define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \ |
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553 ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \ |
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554 ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE)) |
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555 /** |
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556 * @} |
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557 */ |
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558 |
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559 /** |
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560 * @} |
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561 */ |
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562 |
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563 /** |
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564 * @} |
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565 */ |
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566 |
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567 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ |
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568 |
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569 #ifdef __cplusplus |
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570 } |
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571 #endif |
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572 |
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573 #endif /* __STM32F4xx_HAL_DMA2D_H */ |
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574 |
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575 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |