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1 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
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2 ;* File Name : startup_stm32f437xx.s
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3 ;* Author : MCD Application Team
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4 ;* Version : V2.2.0
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5 ;* Date : 15-December-2014
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6 ;* Description : STM32F437x devices vector table for MDK-ARM toolchain.
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7 ;* This module performs:
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8 ;* - Set the initial SP
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9 ;* - Set the initial PC == Reset_Handler
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10 ;* - Set the vector table entries with the exceptions ISR address
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11 ;* - Branches to __main in the C library (which eventually
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12 ;* calls main()).
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13 ;* After Reset the CortexM4 processor is in Thread mode,
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14 ;* priority is Privileged, and the Stack is set to Main.
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15 ;* <<< Use Configuration Wizard in Context Menu >>>
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16 ;*******************************************************************************
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17 ;
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18 ;* Redistribution and use in source and binary forms, with or without modification,
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19 ;* are permitted provided that the following conditions are met:
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20 ;* 1. Redistributions of source code must retain the above copyright notice,
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21 ;* this list of conditions and the following disclaimer.
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22 ;* 2. Redistributions in binary form must reproduce the above copyright notice,
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23 ;* this list of conditions and the following disclaimer in the documentation
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24 ;* and/or other materials provided with the distribution.
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25 ;* 3. Neither the name of STMicroelectronics nor the names of its contributors
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26 ;* may be used to endorse or promote products derived from this software
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27 ;* without specific prior written permission.
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28 ;*
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29 ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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30 ;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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31 ;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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32 ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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33 ;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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34 ;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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35 ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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36 ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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37 ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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38 ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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39 ;
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40 ;*******************************************************************************
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41
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42 ; Amount of memory (in bytes) allocated for Stack
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43 ; Tailor this value to your application needs
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44 ; <h> Stack Configuration
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45 ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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46 ; </h>
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47
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48 Stack_Size EQU 0x00000400
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49
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50 AREA STACK, NOINIT, READWRITE, ALIGN=3
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51 Stack_Mem SPACE Stack_Size
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52 __initial_sp
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53
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54
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55 ; <h> Heap Configuration
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56 ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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57 ; </h>
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58
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59 Heap_Size EQU 0x00000200
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60
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61 AREA HEAP, NOINIT, READWRITE, ALIGN=3
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62 __heap_base
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63 Heap_Mem SPACE Heap_Size
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64 __heap_limit
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65
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66 PRESERVE8
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67 THUMB
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68
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69
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70 ; Vector Table Mapped to Address 0 at Reset
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71 AREA RESET, DATA, READONLY
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72 EXPORT __Vectors
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73 EXPORT __Vectors_End
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74 EXPORT __Vectors_Size
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75
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76 __Vectors DCD __initial_sp ; Top of Stack
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77 DCD Reset_Handler ; Reset Handler
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78 DCD NMI_Handler ; NMI Handler
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79 DCD HardFault_Handler ; Hard Fault Handler
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80 DCD MemManage_Handler ; MPU Fault Handler
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81 DCD BusFault_Handler ; Bus Fault Handler
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82 DCD UsageFault_Handler ; Usage Fault Handler
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83 DCD 0 ; Reserved
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84 DCD 0 ; Reserved
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85 DCD 0 ; Reserved
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86 DCD 0 ; Reserved
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87 DCD SVC_Handler ; SVCall Handler
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88 DCD DebugMon_Handler ; Debug Monitor Handler
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89 DCD 0 ; Reserved
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90 DCD PendSV_Handler ; PendSV Handler
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91 DCD SysTick_Handler ; SysTick Handler
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92
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93 ; External Interrupts
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94 DCD WWDG_IRQHandler ; Window WatchDog
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95 DCD PVD_IRQHandler ; PVD through EXTI Line detection
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96 DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
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97 DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
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98 DCD FLASH_IRQHandler ; FLASH
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99 DCD RCC_IRQHandler ; RCC
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100 DCD EXTI0_IRQHandler ; EXTI Line0
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101 DCD EXTI1_IRQHandler ; EXTI Line1
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102 DCD EXTI2_IRQHandler ; EXTI Line2
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103 DCD EXTI3_IRQHandler ; EXTI Line3
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104 DCD EXTI4_IRQHandler ; EXTI Line4
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105 DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
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106 DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
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107 DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
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108 DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
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109 DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
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110 DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
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111 DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
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112 DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
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113 DCD CAN1_TX_IRQHandler ; CAN1 TX
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114 DCD CAN1_RX0_IRQHandler ; CAN1 RX0
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115 DCD CAN1_RX1_IRQHandler ; CAN1 RX1
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116 DCD CAN1_SCE_IRQHandler ; CAN1 SCE
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117 DCD EXTI9_5_IRQHandler ; External Line[9:5]s
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118 DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
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119 DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
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120 DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
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121 DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
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122 DCD TIM2_IRQHandler ; TIM2
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123 DCD TIM3_IRQHandler ; TIM3
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124 DCD TIM4_IRQHandler ; TIM4
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125 DCD I2C1_EV_IRQHandler ; I2C1 Event
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126 DCD I2C1_ER_IRQHandler ; I2C1 Error
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127 DCD I2C2_EV_IRQHandler ; I2C2 Event
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128 DCD I2C2_ER_IRQHandler ; I2C2 Error
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129 DCD SPI1_IRQHandler ; SPI1
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130 DCD SPI2_IRQHandler ; SPI2
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131 DCD USART1_IRQHandler ; USART1
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132 DCD USART2_IRQHandler ; USART2
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133 DCD USART3_IRQHandler ; USART3
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134 DCD EXTI15_10_IRQHandler ; External Line[15:10]s
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135 DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
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136 DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
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137 DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
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138 DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
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139 DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
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140 DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
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141 DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
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142 DCD FMC_IRQHandler ; FMC
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143 DCD SDIO_IRQHandler ; SDIO
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144 DCD TIM5_IRQHandler ; TIM5
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145 DCD SPI3_IRQHandler ; SPI3
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146 DCD UART4_IRQHandler ; UART4
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147 DCD UART5_IRQHandler ; UART5
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148 DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
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149 DCD TIM7_IRQHandler ; TIM7
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150 DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
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151 DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
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152 DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
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153 DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
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154 DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
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155 DCD ETH_IRQHandler ; Ethernet
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156 DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
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157 DCD CAN2_TX_IRQHandler ; CAN2 TX
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158 DCD CAN2_RX0_IRQHandler ; CAN2 RX0
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159 DCD CAN2_RX1_IRQHandler ; CAN2 RX1
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160 DCD CAN2_SCE_IRQHandler ; CAN2 SCE
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161 DCD OTG_FS_IRQHandler ; USB OTG FS
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162 DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
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163 DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
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164 DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
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165 DCD USART6_IRQHandler ; USART6
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166 DCD I2C3_EV_IRQHandler ; I2C3 event
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167 DCD I2C3_ER_IRQHandler ; I2C3 error
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168 DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
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169 DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
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170 DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
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171 DCD OTG_HS_IRQHandler ; USB OTG HS
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172 DCD DCMI_IRQHandler ; DCMI
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173 DCD CRYP_IRQHandler ; CRYPTO
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174 DCD HASH_RNG_IRQHandler ; Hash and Rng
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175 DCD FPU_IRQHandler ; FPU
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176 DCD UART7_IRQHandler ; UART7
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177 DCD UART8_IRQHandler ; UART8
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178 DCD SPI4_IRQHandler ; SPI4
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179 DCD SPI5_IRQHandler ; SPI5
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180 DCD SPI6_IRQHandler ; SPI6
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181 DCD SAI1_IRQHandler ; SAI1
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182 DCD 0 ; Reserved
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183 DCD 0 ; Reserved
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184 DCD DMA2D_IRQHandler ; DMA2D
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185
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186 __Vectors_End
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187
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188 __Vectors_Size EQU __Vectors_End - __Vectors
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189
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190 AREA |.text|, CODE, READONLY
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191
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192 ; Reset handler
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193 Reset_Handler PROC
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194 EXPORT Reset_Handler [WEAK]
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195 IMPORT SystemInit
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196 IMPORT __main
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197
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198 LDR R0, =SystemInit
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199 BLX R0
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200 LDR R0, =__main
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201 BX R0
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202 ENDP
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203
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204 ; Dummy Exception Handlers (infinite loops which can be modified)
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205
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206 NMI_Handler PROC
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207 EXPORT NMI_Handler [WEAK]
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208 B .
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209 ENDP
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210 HardFault_Handler\
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211 PROC
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212 EXPORT HardFault_Handler [WEAK]
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213 B .
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214 ENDP
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215 MemManage_Handler\
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216 PROC
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217 EXPORT MemManage_Handler [WEAK]
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218 B .
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219 ENDP
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220 BusFault_Handler\
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221 PROC
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222 EXPORT BusFault_Handler [WEAK]
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223 B .
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224 ENDP
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225 UsageFault_Handler\
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226 PROC
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227 EXPORT UsageFault_Handler [WEAK]
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228 B .
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229 ENDP
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230 SVC_Handler PROC
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231 EXPORT SVC_Handler [WEAK]
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232 B .
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233 ENDP
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234 DebugMon_Handler\
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235 PROC
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236 EXPORT DebugMon_Handler [WEAK]
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237 B .
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238 ENDP
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239 PendSV_Handler PROC
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240 EXPORT PendSV_Handler [WEAK]
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241 B .
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242 ENDP
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243 SysTick_Handler PROC
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244 EXPORT SysTick_Handler [WEAK]
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245 B .
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246 ENDP
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247
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248 Default_Handler PROC
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249
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250 EXPORT WWDG_IRQHandler [WEAK]
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251 EXPORT PVD_IRQHandler [WEAK]
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252 EXPORT TAMP_STAMP_IRQHandler [WEAK]
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253 EXPORT RTC_WKUP_IRQHandler [WEAK]
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254 EXPORT FLASH_IRQHandler [WEAK]
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255 EXPORT RCC_IRQHandler [WEAK]
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256 EXPORT EXTI0_IRQHandler [WEAK]
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257 EXPORT EXTI1_IRQHandler [WEAK]
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258 EXPORT EXTI2_IRQHandler [WEAK]
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259 EXPORT EXTI3_IRQHandler [WEAK]
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260 EXPORT EXTI4_IRQHandler [WEAK]
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261 EXPORT DMA1_Stream0_IRQHandler [WEAK]
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262 EXPORT DMA1_Stream1_IRQHandler [WEAK]
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263 EXPORT DMA1_Stream2_IRQHandler [WEAK]
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264 EXPORT DMA1_Stream3_IRQHandler [WEAK]
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265 EXPORT DMA1_Stream4_IRQHandler [WEAK]
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266 EXPORT DMA1_Stream5_IRQHandler [WEAK]
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267 EXPORT DMA1_Stream6_IRQHandler [WEAK]
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268 EXPORT ADC_IRQHandler [WEAK]
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269 EXPORT CAN1_TX_IRQHandler [WEAK]
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270 EXPORT CAN1_RX0_IRQHandler [WEAK]
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271 EXPORT CAN1_RX1_IRQHandler [WEAK]
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272 EXPORT CAN1_SCE_IRQHandler [WEAK]
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273 EXPORT EXTI9_5_IRQHandler [WEAK]
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274 EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
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275 EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
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276 EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
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277 EXPORT TIM1_CC_IRQHandler [WEAK]
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278 EXPORT TIM2_IRQHandler [WEAK]
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279 EXPORT TIM3_IRQHandler [WEAK]
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280 EXPORT TIM4_IRQHandler [WEAK]
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281 EXPORT I2C1_EV_IRQHandler [WEAK]
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282 EXPORT I2C1_ER_IRQHandler [WEAK]
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283 EXPORT I2C2_EV_IRQHandler [WEAK]
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284 EXPORT I2C2_ER_IRQHandler [WEAK]
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285 EXPORT SPI1_IRQHandler [WEAK]
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286 EXPORT SPI2_IRQHandler [WEAK]
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287 EXPORT USART1_IRQHandler [WEAK]
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288 EXPORT USART2_IRQHandler [WEAK]
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289 EXPORT USART3_IRQHandler [WEAK]
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290 EXPORT EXTI15_10_IRQHandler [WEAK]
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291 EXPORT RTC_Alarm_IRQHandler [WEAK]
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292 EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
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293 EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
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294 EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
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295 EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
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296 EXPORT TIM8_CC_IRQHandler [WEAK]
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297 EXPORT DMA1_Stream7_IRQHandler [WEAK]
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298 EXPORT FMC_IRQHandler [WEAK]
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299 EXPORT SDIO_IRQHandler [WEAK]
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300 EXPORT TIM5_IRQHandler [WEAK]
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301 EXPORT SPI3_IRQHandler [WEAK]
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302 EXPORT UART4_IRQHandler [WEAK]
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303 EXPORT UART5_IRQHandler [WEAK]
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304 EXPORT TIM6_DAC_IRQHandler [WEAK]
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305 EXPORT TIM7_IRQHandler [WEAK]
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306 EXPORT DMA2_Stream0_IRQHandler [WEAK]
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307 EXPORT DMA2_Stream1_IRQHandler [WEAK]
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308 EXPORT DMA2_Stream2_IRQHandler [WEAK]
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309 EXPORT DMA2_Stream3_IRQHandler [WEAK]
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310 EXPORT DMA2_Stream4_IRQHandler [WEAK]
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311 EXPORT ETH_IRQHandler [WEAK]
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312 EXPORT ETH_WKUP_IRQHandler [WEAK]
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313 EXPORT CAN2_TX_IRQHandler [WEAK]
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314 EXPORT CAN2_RX0_IRQHandler [WEAK]
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315 EXPORT CAN2_RX1_IRQHandler [WEAK]
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316 EXPORT CAN2_SCE_IRQHandler [WEAK]
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317 EXPORT OTG_FS_IRQHandler [WEAK]
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318 EXPORT DMA2_Stream5_IRQHandler [WEAK]
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319 EXPORT DMA2_Stream6_IRQHandler [WEAK]
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320 EXPORT DMA2_Stream7_IRQHandler [WEAK]
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321 EXPORT USART6_IRQHandler [WEAK]
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322 EXPORT I2C3_EV_IRQHandler [WEAK]
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323 EXPORT I2C3_ER_IRQHandler [WEAK]
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324 EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
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325 EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
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326 EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
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327 EXPORT OTG_HS_IRQHandler [WEAK]
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328 EXPORT DCMI_IRQHandler [WEAK]
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329 EXPORT CRYP_IRQHandler [WEAK]
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330 EXPORT HASH_RNG_IRQHandler [WEAK]
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331 EXPORT FPU_IRQHandler [WEAK]
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332 EXPORT UART7_IRQHandler [WEAK]
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333 EXPORT UART8_IRQHandler [WEAK]
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334 EXPORT SPI4_IRQHandler [WEAK]
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335 EXPORT SPI5_IRQHandler [WEAK]
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336 EXPORT SPI6_IRQHandler [WEAK]
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337 EXPORT SAI1_IRQHandler [WEAK]
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338 EXPORT DMA2D_IRQHandler [WEAK]
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339
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340 WWDG_IRQHandler
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341 PVD_IRQHandler
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342 TAMP_STAMP_IRQHandler
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343 RTC_WKUP_IRQHandler
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344 FLASH_IRQHandler
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345 RCC_IRQHandler
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346 EXTI0_IRQHandler
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347 EXTI1_IRQHandler
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348 EXTI2_IRQHandler
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349 EXTI3_IRQHandler
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350 EXTI4_IRQHandler
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351 DMA1_Stream0_IRQHandler
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352 DMA1_Stream1_IRQHandler
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353 DMA1_Stream2_IRQHandler
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354 DMA1_Stream3_IRQHandler
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355 DMA1_Stream4_IRQHandler
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356 DMA1_Stream5_IRQHandler
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357 DMA1_Stream6_IRQHandler
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358 ADC_IRQHandler
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359 CAN1_TX_IRQHandler
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360 CAN1_RX0_IRQHandler
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361 CAN1_RX1_IRQHandler
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362 CAN1_SCE_IRQHandler
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363 EXTI9_5_IRQHandler
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364 TIM1_BRK_TIM9_IRQHandler
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365 TIM1_UP_TIM10_IRQHandler
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366 TIM1_TRG_COM_TIM11_IRQHandler
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367 TIM1_CC_IRQHandler
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368 TIM2_IRQHandler
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369 TIM3_IRQHandler
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370 TIM4_IRQHandler
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371 I2C1_EV_IRQHandler
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372 I2C1_ER_IRQHandler
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373 I2C2_EV_IRQHandler
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374 I2C2_ER_IRQHandler
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375 SPI1_IRQHandler
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376 SPI2_IRQHandler
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377 USART1_IRQHandler
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378 USART2_IRQHandler
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379 USART3_IRQHandler
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380 EXTI15_10_IRQHandler
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381 RTC_Alarm_IRQHandler
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382 OTG_FS_WKUP_IRQHandler
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383 TIM8_BRK_TIM12_IRQHandler
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384 TIM8_UP_TIM13_IRQHandler
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385 TIM8_TRG_COM_TIM14_IRQHandler
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386 TIM8_CC_IRQHandler
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387 DMA1_Stream7_IRQHandler
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388 FMC_IRQHandler
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389 SDIO_IRQHandler
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390 TIM5_IRQHandler
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391 SPI3_IRQHandler
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392 UART4_IRQHandler
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393 UART5_IRQHandler
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394 TIM6_DAC_IRQHandler
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395 TIM7_IRQHandler
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396 DMA2_Stream0_IRQHandler
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397 DMA2_Stream1_IRQHandler
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398 DMA2_Stream2_IRQHandler
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399 DMA2_Stream3_IRQHandler
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400 DMA2_Stream4_IRQHandler
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401 ETH_IRQHandler
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402 ETH_WKUP_IRQHandler
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403 CAN2_TX_IRQHandler
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404 CAN2_RX0_IRQHandler
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405 CAN2_RX1_IRQHandler
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406 CAN2_SCE_IRQHandler
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407 OTG_FS_IRQHandler
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408 DMA2_Stream5_IRQHandler
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409 DMA2_Stream6_IRQHandler
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410 DMA2_Stream7_IRQHandler
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411 USART6_IRQHandler
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412 I2C3_EV_IRQHandler
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413 I2C3_ER_IRQHandler
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414 OTG_HS_EP1_OUT_IRQHandler
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415 OTG_HS_EP1_IN_IRQHandler
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416 OTG_HS_WKUP_IRQHandler
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417 OTG_HS_IRQHandler
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418 DCMI_IRQHandler
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419 CRYP_IRQHandler
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420 HASH_RNG_IRQHandler
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421 FPU_IRQHandler
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422 UART7_IRQHandler
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423 UART8_IRQHandler
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424 SPI4_IRQHandler
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425 SPI5_IRQHandler
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426 SPI6_IRQHandler
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427 SAI1_IRQHandler
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428 DMA2D_IRQHandler
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429 B .
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430
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431 ENDP
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432
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433 ALIGN
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434
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435 ;*******************************************************************************
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436 ; User Stack and Heap initialization
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437 ;*******************************************************************************
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438 IF :DEF:__MICROLIB
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439
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440 EXPORT __initial_sp
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441 EXPORT __heap_base
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442 EXPORT __heap_limit
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443
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444 ELSE
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445
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446 IMPORT __use_two_region_memory
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447 EXPORT __user_initial_stackheap
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448
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449 __user_initial_stackheap
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450
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451 LDR R0, = Heap_Mem
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452 LDR R1, =(Stack_Mem + Stack_Size)
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453 LDR R2, = (Heap_Mem + Heap_Size)
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454 LDR R3, = Stack_Mem
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455 BX LR
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456
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457 ALIGN
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458
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459 ENDIF
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460
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461 END
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462
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463 ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
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