annotate Common/Drivers/STM32F4xx_HAL_DRIVER_v120/Inc/stm32f4xx_hal_nand.h @ 85:923c4566a2a1 kittz

increased interCPU baudrate, cpu2: i2c in SPI1 IRQ
author Dmitry Romanov <kitt@bk.ru>
date Wed, 21 Nov 2018 12:49:54 +0300
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children
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1 /**
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2 ******************************************************************************
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3 * @file stm32f4xx_hal_nand.h
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4 * @author MCD Application Team
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5 * @version V1.2.0
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6 * @date 26-December-2014
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7 * @brief Header file of NAND HAL module.
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8 ******************************************************************************
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9 * @attention
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10 *
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11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
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12 *
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13 * Redistribution and use in source and binary forms, with or without modification,
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14 * are permitted provided that the following conditions are met:
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15 * 1. Redistributions of source code must retain the above copyright notice,
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16 * this list of conditions and the following disclaimer.
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17 * 2. Redistributions in binary form must reproduce the above copyright notice,
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18 * this list of conditions and the following disclaimer in the documentation
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19 * and/or other materials provided with the distribution.
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20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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21 * may be used to endorse or promote products derived from this software
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22 * without specific prior written permission.
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23 *
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24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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34 *
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35 ******************************************************************************
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36 */
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37
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38 /* Define to prevent recursive inclusion -------------------------------------*/
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39 #ifndef __STM32F4xx_HAL_NAND_H
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40 #define __STM32F4xx_HAL_NAND_H
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41
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42 #ifdef __cplusplus
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43 extern "C" {
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44 #endif
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45
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46 /* Includes ------------------------------------------------------------------*/
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47 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
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48 #include "stm32f4xx_ll_fsmc.h"
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49 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
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50
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51 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
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52 #include "stm32f4xx_ll_fmc.h"
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53 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
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54
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55 /** @addtogroup STM32F4xx_HAL_Driver
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56 * @{
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57 */
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58
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59 /** @addtogroup NAND
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60 * @{
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61 */
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62
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63 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
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64 /* Exported typedef ----------------------------------------------------------*/
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65 /* Exported types ------------------------------------------------------------*/
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66 /** @defgroup NAND_Exported_Types NAND Exported Types
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67 * @{
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68 */
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69
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70 /**
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71 * @brief HAL NAND State structures definition
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72 */
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73 typedef enum
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74 {
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75 HAL_NAND_STATE_RESET = 0x00, /*!< NAND not yet initialized or disabled */
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76 HAL_NAND_STATE_READY = 0x01, /*!< NAND initialized and ready for use */
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77 HAL_NAND_STATE_BUSY = 0x02, /*!< NAND internal process is ongoing */
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78 HAL_NAND_STATE_ERROR = 0x03 /*!< NAND error state */
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79 }HAL_NAND_StateTypeDef;
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80
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81 /**
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82 * @brief NAND Memory electronic signature Structure definition
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83 */
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84 typedef struct
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85 {
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86 /*<! NAND memory electronic signature maker and device IDs */
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87
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88 uint8_t Maker_Id;
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89
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90 uint8_t Device_Id;
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91
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92 uint8_t Third_Id;
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93
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94 uint8_t Fourth_Id;
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95 }NAND_IDTypeDef;
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96
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97 /**
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98 * @brief NAND Memory address Structure definition
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99 */
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100 typedef struct
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101 {
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102 uint16_t Page; /*!< NAND memory Page address */
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103
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104 uint16_t Zone; /*!< NAND memory Zone address */
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105
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106 uint16_t Block; /*!< NAND memory Block address */
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107
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108 }NAND_AddressTypeDef;
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109
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110 /**
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111 * @brief NAND Memory info Structure definition
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112 */
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113 typedef struct
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114 {
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115 uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in K. bytes */
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116
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117 uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in K. bytes */
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118
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119 uint32_t BlockSize; /*!< NAND memory block size number of pages */
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120
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121 uint32_t BlockNbr; /*!< NAND memory number of blocks */
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122
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123 uint32_t ZoneSize; /*!< NAND memory zone size measured in number of blocks */
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124 }NAND_InfoTypeDef;
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125
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126 /**
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127 * @brief NAND handle Structure definition
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128 */
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129 typedef struct
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130 {
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131 FMC_NAND_TypeDef *Instance; /*!< Register base address */
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132
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133 FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */
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134
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135 HAL_LockTypeDef Lock; /*!< NAND locking object */
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136
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137 __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
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138
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139 NAND_InfoTypeDef Info; /*!< NAND characteristic information structure */
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140 }NAND_HandleTypeDef;
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141 /**
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142 * @}
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143 */
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144
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145 /* Exported constants --------------------------------------------------------*/
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146 /* Exported macro ------------------------------------------------------------*/
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147 /** @defgroup NAND_Exported_Macros NAND Exported Macros
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148 * @{
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149 */
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150
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151 /** @brief Reset NAND handle state
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152 * @param __HANDLE__: specifies the NAND handle.
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153 * @retval None
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154 */
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155 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
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156
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157 /**
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158 * @}
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159 */
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160
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161 /* Exported functions --------------------------------------------------------*/
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162 /** @addtogroup NAND_Exported_Functions NAND Exported Functions
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163 * @{
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164 */
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165
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166 /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
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167 * @{
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168 */
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169
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170 /* Initialization/de-initialization functions ********************************/
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171 HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
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172 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
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173 void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
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174 void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
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175 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
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176 void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
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177
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178 /**
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179 * @}
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180 */
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181
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182 /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
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183 * @{
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184 */
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185
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186 /* IO operation functions ****************************************************/
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187 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
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188 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
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189 HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
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190 HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
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191 HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
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192 HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
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193 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
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194 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
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195 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
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196
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197 /**
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198 * @}
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199 */
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200
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201 /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
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202 * @{
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203 */
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204
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205 /* NAND Control functions ****************************************************/
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206 HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
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207 HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
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208 HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
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209
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210 /**
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211 * @}
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212 */
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213
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214 /** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
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215 * @{
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216 */
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217 /* NAND State functions *******************************************************/
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218 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
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219 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
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220 /**
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221 * @}
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222 */
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223
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224 /**
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225 * @}
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226 */
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227
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228 /* Private types -------------------------------------------------------------*/
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229 /* Private variables ---------------------------------------------------------*/
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230 /* Private constants ---------------------------------------------------------*/
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231 /** @defgroup NAND_Private_Constants NAND Private Constants
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232 * @{
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233 */
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234 #define NAND_DEVICE1 ((uint32_t)0x70000000)
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235 #define NAND_DEVICE2 ((uint32_t)0x80000000)
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236 #define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000)
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237
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238 #define CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */
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239 #define ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */
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240
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241 #define NAND_CMD_AREA_A ((uint8_t)0x00)
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242 #define NAND_CMD_AREA_B ((uint8_t)0x01)
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243 #define NAND_CMD_AREA_C ((uint8_t)0x50)
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244 #define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
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245
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246 #define NAND_CMD_WRITE0 ((uint8_t)0x80)
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247 #define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
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248 #define NAND_CMD_ERASE0 ((uint8_t)0x60)
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249 #define NAND_CMD_ERASE1 ((uint8_t)0xD0)
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250 #define NAND_CMD_READID ((uint8_t)0x90)
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251 #define NAND_CMD_STATUS ((uint8_t)0x70)
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252 #define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
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253 #define NAND_CMD_RESET ((uint8_t)0xFF)
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254
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255 /* NAND memory status */
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256 #define NAND_VALID_ADDRESS ((uint32_t)0x00000100)
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257 #define NAND_INVALID_ADDRESS ((uint32_t)0x00000200)
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258 #define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400)
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259 #define NAND_BUSY ((uint32_t)0x00000000)
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260 #define NAND_ERROR ((uint32_t)0x00000001)
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261 #define NAND_READY ((uint32_t)0x00000040)
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262 /**
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263 * @}
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264 */
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265
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266 /* Private macros ------------------------------------------------------------*/
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267 /** @defgroup NAND_Private_Macros NAND Private Macros
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268 * @{
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269 */
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270
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271 /**
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272 * @brief NAND memory address computation.
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273 * @param __ADDRESS__: NAND memory address.
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274 * @param __HANDLE__ : NAND handle.
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275 * @retval NAND Raw address value
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276 */
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277 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
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278 (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.ZoneSize)))* ((__HANDLE__)->Info.BlockSize)))
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279
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280 /**
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281 * @brief NAND memory address cycling.
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282 * @param __ADDRESS__: NAND memory address.
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283 * @retval NAND address cycling value.
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284 */
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285 #define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
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286 #define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
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287 #define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
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288 #define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */
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289 /**
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290 * @}
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291 */
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292 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
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293
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294 /**
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295 * @}
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296 */
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297 /**
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298 * @}
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299 */
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300
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301 /**
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302 * @}
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303 */
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304
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305 #ifdef __cplusplus
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306 }
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307 #endif
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308
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309 #endif /* __STM32F4xx_HAL_NAND_H */
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310
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311 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/