Mercurial > public > ostc4

annotate Documentations/OSTC4_CPU2_F411.ioc @ 571:91a8f9893e68

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
Reactivate compass parameter stored in NVM: The calibration parameters are stored in NVM but the automatic restore function during startup was no longer active. As result the compass needed to be calibration after every RTE update. In addition compass HW was detected at every startup causing some i2c "trouble" because of adressing not available devices. The compass HW info is now stored together with the calibration parameters to avoid i2C problems.
author Ideenmodellierer
date Wed, 25 Nov 2020 20:16:20 +0100
parents 7d1b61176708
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
1
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
1 #MicroXplorer Configuration settings - do not modify
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
2 #Fri May 22 12:37:15 CEST 2015
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
3 ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_8
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
4 ADC1.IPParameters=Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,Rank-0\#ChannelRegularConversion,master
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
5 ADC1.Rank-0\#ChannelRegularConversion=1
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
6 ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
7 ADC1.master=1
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
8 Dma.Request0=SPI1_RX
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
9 Dma.Request1=SPI1_TX
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
10 Dma.RequestsNb=2
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
11 Dma.SPI1_RX.0.Channel=DMA_CHANNEL_3
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
12 Dma.SPI1_RX.0.Direction=DMA_PERIPH_TO_MEMORY
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
13 Dma.SPI1_RX.0.FIFOMode=DMA_FIFOMODE_DISABLE
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
14 Dma.SPI1_RX.0.Instance=DMA2_Stream0
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
15 Dma.SPI1_RX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
16 Dma.SPI1_RX.0.MemInc=DMA_MINC_DISABLE
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
17 Dma.SPI1_RX.0.Mode=DMA_NORMAL
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
18 Dma.SPI1_RX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
19 Dma.SPI1_RX.0.PeriphInc=DMA_PINC_DISABLE
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
20 Dma.SPI1_RX.0.Priority=DMA_PRIORITY_HIGH
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
21 Dma.SPI1_RX.0.RequestParameters=Instance,Channel,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
22 Dma.SPI1_TX.1.Channel=DMA_CHANNEL_2
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
23 Dma.SPI1_TX.1.Direction=DMA_MEMORY_TO_PERIPH
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
24 Dma.SPI1_TX.1.FIFOMode=DMA_FIFOMODE_DISABLE
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
25 Dma.SPI1_TX.1.Instance=DMA2_Stream2
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
26 Dma.SPI1_TX.1.MemDataAlignment=DMA_MDATAALIGN_BYTE
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
27 Dma.SPI1_TX.1.MemInc=DMA_MINC_DISABLE
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
28 Dma.SPI1_TX.1.Mode=DMA_NORMAL
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
29 Dma.SPI1_TX.1.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
30 Dma.SPI1_TX.1.PeriphInc=DMA_PINC_DISABLE
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
31 Dma.SPI1_TX.1.Priority=DMA_PRIORITY_HIGH
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
32 Dma.SPI1_TX.1.RequestParameters=Instance,Channel,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
33 File.Version=5
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
34 KeepUserPlacement=false
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
35 Mcu.Family=STM32F4
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
36 Mcu.IP0=ADC1
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
37 Mcu.IP1=CRC
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
38 Mcu.IP2=DMA
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
39 Mcu.IP3=I2C1
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
40 Mcu.IP4=NVIC
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
41 Mcu.IP5=RCC
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
42 Mcu.IP6=RTC
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
43 Mcu.IP7=SPI1
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
44 Mcu.IP8=SPI3
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
45 Mcu.IP9=SYS
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
46 Mcu.IPNb=10
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
47 Mcu.Name=STM32F411R(C-E)Tx
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
48 Mcu.Package=LQFP64
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
49 Mcu.Pin0=PC14-OSC32_IN
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
50 Mcu.Pin1=PC15-OSC32_OUT
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
51 Mcu.Pin10=PA6
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
52 Mcu.Pin11=PA7
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
53 Mcu.Pin12=PB0
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
54 Mcu.Pin13=PB12
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
55 Mcu.Pin14=PB13
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
56 Mcu.Pin15=PB14
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
57 Mcu.Pin16=PB15
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
58 Mcu.Pin17=PA9
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
59 Mcu.Pin18=PA10
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
60 Mcu.Pin19=PA13
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
61 Mcu.Pin2=PC0
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
62 Mcu.Pin20=PA14
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
63 Mcu.Pin21=PA15
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
64 Mcu.Pin22=PC10
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
65 Mcu.Pin23=PC11
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
66 Mcu.Pin24=PC12
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
67 Mcu.Pin25=PB3
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
68 Mcu.Pin26=PB8
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
69 Mcu.Pin27=PB9
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
70 Mcu.Pin28=VP_CRC_VS_CRC
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
71 Mcu.Pin29=VP_RTC_VS_RTC_Alarm_A_Intern
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
72 Mcu.Pin3=PC1
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
73 Mcu.Pin4=PC2
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
74 Mcu.Pin5=PC3
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
75 Mcu.Pin6=PA0-WKUP
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
76 Mcu.Pin7=PA1
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
77 Mcu.Pin8=PA4
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
78 Mcu.Pin9=PA5
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
79 Mcu.PinsNb=30
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
80 Mcu.UserName=STM32F411RETx
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
81 MxCube.Version=4.7.1
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
82 MxDb.Version=DB.4.0.71
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
83 NVIC.DMA2_Stream0_IRQn=true\:0\:0\:false
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
84 NVIC.DMA2_Stream2_IRQn=true\:0\:0\:false
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
85 NVIC.PriorityGroup=NVIC_PRIORITYGROUP_0
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
86 NVIC.SysTick_IRQn=true\:0\:0\:true
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
87 PA0-WKUP.Locked=true
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
88 PA0-WKUP.Signal=GPIO_Input
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
89 PA1.Locked=true
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
90 PA1.Signal=GPIO_Analog
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
91 PA10.Signal=USART1_RX
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
92 PA13.Mode=Trace-Asynchronous_SW
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
93 PA13.Signal=SYS_JTMS-SWDIO
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
94 PA14.Mode=Trace-Asynchronous_SW
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
95 PA14.Signal=SYS_JTCK-SWCLK
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
96 PA15.Mode=NSS_Signal_Hard
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
97 PA15.Signal=SPI3_NSS
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
98 PA4.Locked=true
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
99 PA4.Mode=NSS_Signal_Hard
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
100 PA4.Signal=SPI1_NSS
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
101 PA5.Mode=Full_Duplex_Slave
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
102 PA5.Signal=SPI1_SCK
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
103 PA6.Mode=Full_Duplex_Slave
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
104 PA6.Signal=SPI1_MISO
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
105 PA7.Mode=Full_Duplex_Slave
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
106 PA7.Signal=SPI1_MOSI
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
107 PA9.Signal=USART1_TX
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
108 PB0.Locked=true
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
109 PB0.Signal=ADCx_IN8
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
110 PB12.Locked=true
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
111 PB12.Signal=GPIO_Analog
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
112 PB13.Locked=true
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
113 PB13.Signal=GPIO_Input
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
114 PB14.Locked=true
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
115 PB14.Signal=GPIO_Analog
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
116 PB15.Locked=true
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
117 PB15.Signal=GPIO_Output
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
118 PB3.Mode=Trace-Asynchronous_SW
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
119 PB3.Signal=SYS_JTDO-SWO
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
120 PB8.Locked=true
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
121 PB8.Mode=I2C
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
122 PB8.Signal=I2C1_SCL
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
123 PB9.Locked=true
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
124 PB9.Mode=I2C
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
125 PB9.Signal=I2C1_SDA
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
126 PC0.Locked=true
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
127 PC0.Signal=GPIO_Output
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
128 PC1.Locked=true
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
129 PC1.Signal=GPIO_Output
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
130 PC10.Mode=Full_Duplex_Master
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
131 PC10.Signal=SPI3_SCK
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
132 PC11.Mode=Full_Duplex_Master
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
133 PC11.Signal=SPI3_MISO
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
134 PC12.Mode=Full_Duplex_Master
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
135 PC12.Signal=SPI3_MOSI
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
136 PC14-OSC32_IN.Mode=LSE-External-Oscillator
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
137 PC14-OSC32_IN.Signal=RCC_OSC32_IN
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
138 PC15-OSC32_OUT.Mode=LSE-External-Oscillator
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
139 PC15-OSC32_OUT.Signal=RCC_OSC32_OUT
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
140 PC2.Locked=true
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
141 PC2.Signal=GPIO_Input
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
142 PC3.Locked=true
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
143 PC3.Signal=GPIO_Output
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
144 PCC.Battery=Li-SOCL2(A3400)
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
145 PCC.Battery.Capacity=3400.0
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
146 PCC.Battery.Compatibility=Yes
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
147 PCC.Battery.InParallel=1
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
148 PCC.Battery.InSeries=1
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
149 PCC.Battery.MaxContinuous=100.0
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
150 PCC.Battery.MaxPulseCurrent=200.0
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
151 PCC.Battery.NominalVoltage=3.6
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
152 PCC.Battery.SelfDischarge=0.08
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
153 PCC.Checker=false
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
154 PCC.Family=STM32F4
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
155 PCC.MCU=STM32F411R(C-E)Tx
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
156 PCC.MXVersion=4.7.1
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
157 PCC.PartNumber=STM32F411RETx
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
158 PCC.Seq0=3
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
159 PCC.Seq0.Step0.Average_Current=19 \u00B5A
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
160 PCC.Seq0.Step0.CPU_Frequency=0 Hz
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
161 PCC.Seq0.Step0.DMIPS=0.0
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
162 PCC.Seq0.Step0.Duration=2 s
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
163 PCC.Seq0.Step0.Frequency=0 Hz
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
164 PCC.Seq0.Step0.Memory=n/a
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
165 PCC.Seq0.Step0.Mode=STOP
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
166 PCC.Seq0.Step0.Oscillator=Regulator_LP Flash-PwrDwn
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
167 PCC.Seq0.Step0.Peripherals=PVD* RTC*
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
168 PCC.Seq0.Step0.User's_Consumption=5 \u00B5A
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
169 PCC.Seq0.Step0.Vcore=No Scale
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
170 PCC.Seq0.Step0.Vdd=3.6
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
171 PCC.Seq0.Step0.Voltage_Source=Battery
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
172 PCC.Seq0.Step1.Average_Current=20.83 mA
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
173 PCC.Seq0.Step1.CPU_Frequency=100.0 MHz
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
174 PCC.Seq0.Step1.DMIPS=125.0
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
175 PCC.Seq0.Step1.Duration=2 ms
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
176 PCC.Seq0.Step1.Frequency=4.0 MHz
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
177 PCC.Seq0.Step1.Memory=FLASH
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
178 PCC.Seq0.Step1.Mode=RUN
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
179 PCC.Seq0.Step1.Oscillator=HSE PLL
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
180 PCC.Seq0.Step1.Peripherals=GPIOB I2C1
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
181 PCC.Seq0.Step1.User's_Consumption=120 \u00B5A
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
182 PCC.Seq0.Step1.Vcore=Scale1-Medium
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
183 PCC.Seq0.Step1.Vdd=3.6
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
184 PCC.Seq0.Step1.Voltage_Source=Battery
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
185 PCC.Seq0.Step2.Average_Current=3.31 mA
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
186 PCC.Seq0.Step2.CPU_Frequency=100.0 MHz
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
187 PCC.Seq0.Step2.DMIPS=125.0
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
188 PCC.Seq0.Step2.Duration=22 ms
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
189 PCC.Seq0.Step2.Frequency=4.0 MHz
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
190 PCC.Seq0.Step2.Memory=RAM/FLASH
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
191 PCC.Seq0.Step2.Mode=SLEEP
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
192 PCC.Seq0.Step2.Oscillator=HSE PLL
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
193 PCC.Seq0.Step2.Peripherals=GPIOB I2C1
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
194 PCC.Seq0.Step2.User's_Consumption=0 mA
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
195 PCC.Seq0.Step2.Vcore=Scale1-Medium
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
196 PCC.Seq0.Step2.Vdd=3.6
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
197 PCC.Seq0.Step2.Voltage_Source=Battery
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
198 PCC.SubFamily=STM32F411
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
199 PCC.Temperature=25
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
200 PCC.Vdd=3.6
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
201 ProjectManager.AskForMigrate=true
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
202 ProjectManager.BackupPrevious=false
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
203 ProjectManager.CompilerOptimize=2
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
204 ProjectManager.ComputerToolchain=false
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
205 ProjectManager.CoupleFile=false
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
206 ProjectManager.DeletePrevious=true
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
207 ProjectManager.DeviceId=STM32F411RETx
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
208 ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.5.0
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
209 ProjectManager.FreePins=true
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
210 ProjectManager.HalAssertFull=false
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
211 ProjectManager.KeepUserCode=true
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
212 ProjectManager.LastFirmware=true
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
213 ProjectManager.LibraryCopy=0
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
214 ProjectManager.ProjectBuild=false
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
215 ProjectManager.ProjectFileName=OSTC4 CPU2 F411.ioc
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
216 ProjectManager.ProjectName=OSTC4 CPU2 F411
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
217 ProjectManager.TargetToolchain=MDK-ARM 4.73
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
218 ProjectManager.ToolChainLocation=
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
219 RCC.48MHZClocksFreq_Value=100000000
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
220 RCC.AHBFreq_Value=100000000
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
221 RCC.APB1CLKDivider=RCC_HCLK_DIV2
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
222 RCC.APB1Freq_Value=50000000
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
223 RCC.APB1TimFreq_Value=100000000
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
224 RCC.APB2Freq_Value=100000000
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
225 RCC.APB2TimFreq_Value=100000000
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
226 RCC.CortexFreq_Value=12500000
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
227 RCC.EthernetFreq_Value=100000000
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
228 RCC.FCLKCortexFreq_Value=100000000
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
229 RCC.FamilyName=M
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
230 RCC.HCLKFreq_Value=100000000
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
231 RCC.HSE_VALUE=25000000
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
232 RCC.HSI_VALUE=16000000
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
233 RCC.I2SClocksFreq_Value=96000000
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
234 RCC.IPParameters=LSI_VALUE,APB1TimFreq_Value,APB2Freq_Value,MCO2PinFreq_Value,APB1CLKDivider,FCLKCortexFreq_Value,RCC_RTC_Clock_SourceVirtual,AHBFreq_Value,48MHZClocksFreq_Value,VCOInputFreq_Value,I2SClocksFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,PLLP,HSE_VALUE,HSI_VALUE,VCOI2SOutputFreq_Value,PLLCLKFreq_Value,VCOInputMFreq_Value,RTCFreq_Value,FamilyName,HCLKFreq_Value,EthernetFreq_Value,PLLN,VCOOutputFreq_Value,VcooutputI2S,CortexFreq_Value,APB1Freq_Value,RTCHSEDivFreq_Value,APB2TimFreq_Value
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
235 RCC.LSI_VALUE=32000
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
236 RCC.MCO2PinFreq_Value=100000000
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
237 RCC.PLLCLKFreq_Value=100000000
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
238 RCC.PLLN=400
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
239 RCC.PLLP=RCC_PLLP_DIV4
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
240 RCC.RCC_RTC_Clock_SourceVirtual=RCC_RTCCLKSOURCE_LSE
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
241 RCC.RTCFreq_Value=32768
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
242 RCC.RTCHSEDivFreq_Value=12500000
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
243 RCC.SYSCLKFreq_VALUE=100000000
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
244 RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
245 RCC.VCOI2SOutputFreq_Value=192000000
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
246 RCC.VCOInputFreq_Value=1000000
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
247 RCC.VCOInputMFreq_Value=1000000
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
248 RCC.VCOOutputFreq_Value=400000000
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
249 RCC.VcooutputI2S=96000000
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
250 SH.ADCx_IN8.0=ADC1_IN8,IN8
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
251 SH.ADCx_IN8.ConfNb=1
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
252 SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_2
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
253 SPI1.CalculateBaudRate=50.0 MBits/s
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
254 SPI1.IPParameters=BaudRatePrescaler,NSS-Full_Duplex_Slave,VirtualNSS,VirtualType,CalculateBaudRate
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
255 SPI1.NSS-Full_Duplex_Slave=SPI_NSS_SOFT
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
256 SPI1.VirtualNSS=VM_NSSHARD
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
257 SPI1.VirtualType=VM_SLAVE
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
258 SPI3.CalculateBaudRate=25.0 MBits/s
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
259 SPI3.IPParameters=VirtualNSS,Mode,CalculateBaudRate
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
260 SPI3.Mode=SPI_MODE_MASTER
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
261 SPI3.VirtualNSS=VM_NSSHARD
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
262 VP_CRC_VS_CRC.Mode=CRC_Activate
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
263 VP_CRC_VS_CRC.Signal=CRC_VS_CRC
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
264 VP_RTC_VS_RTC_Alarm_A_Intern.Mode=Alarm A
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
265 VP_RTC_VS_RTC_Alarm_A_Intern.Signal=RTC_VS_RTC_Alarm_A_Intern