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annotate Common/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_dma.c @ 303:90e65971f15d cleanup-4

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bugfix, cleanup: simplify stopwatch logic and fix fallout The previous 2 commits (making the depth switch between surface and diving consistent) increased the time difference (in the simulator) to about 4 seconds. This commit fixes this again, and we are back at 1 sec. difference between the 2 timers (notice: in the simulator). Still not the wanted 0 sec. difference, but the old stopwatch logic logic was rather convoluted. Resetting to 1 second (instead of 0), and second-1 logic. Basically, this feels like a bug fixed with a second bug on top to mask it. The code is now much more logic and consistent (despite the fact that the real reason for the 1 sec. difference is not yet found). Signed-off-by: Jan Mulder <jlmulder@xs4all.nl>
author Jan Mulder <jlmulder@xs4all.nl>
date Mon, 20 May 2019 12:57:31 +0200
parents c78bcbd5deda
children
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1 /**
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2 ******************************************************************************
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3 * @file stm32f4xx_ll_dma.c
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4 * @author MCD Application Team
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5 * @brief DMA LL module driver.
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6 ******************************************************************************
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7 * @attention
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8 *
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9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
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10 *
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11 * Redistribution and use in source and binary forms, with or without modification,
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12 * are permitted provided that the following conditions are met:
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13 * 1. Redistributions of source code must retain the above copyright notice,
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14 * this list of conditions and the following disclaimer.
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15 * 2. Redistributions in binary form must reproduce the above copyright notice,
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16 * this list of conditions and the following disclaimer in the documentation
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17 * and/or other materials provided with the distribution.
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18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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19 * may be used to endorse or promote products derived from this software
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20 * without specific prior written permission.
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21 *
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22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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32 *
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33 ******************************************************************************
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34 */
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35 #if defined(USE_FULL_LL_DRIVER)
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36
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37 /* Includes ------------------------------------------------------------------*/
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38 #include "stm32f4xx_ll_dma.h"
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39 #include "stm32f4xx_ll_bus.h"
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40 #ifdef USE_FULL_ASSERT
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41 #include "stm32_assert.h"
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42 #else
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43 #define assert_param(expr) ((void)0U)
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44 #endif
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45
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46 /** @addtogroup STM32F4xx_LL_Driver
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47 * @{
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48 */
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49
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50 #if defined (DMA1) || defined (DMA2)
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51
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52 /** @defgroup DMA_LL DMA
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53 * @{
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54 */
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55
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56 /* Private types -------------------------------------------------------------*/
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57 /* Private variables ---------------------------------------------------------*/
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58 /* Private constants ---------------------------------------------------------*/
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59 /* Private macros ------------------------------------------------------------*/
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60 /** @addtogroup DMA_LL_Private_Macros
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61 * @{
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62 */
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63 #define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
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64 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
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65 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
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66
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67 #define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
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68 ((__VALUE__) == LL_DMA_MODE_CIRCULAR) || \
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69 ((__VALUE__) == LL_DMA_MODE_PFCTRL))
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70
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71 #define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
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72 ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
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73
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74 #define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
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75 ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
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76
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77 #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
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78 ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
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79 ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
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80
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81 #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
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82 ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
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83 ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
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84
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85 #define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
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86
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87 #define IS_LL_DMA_CHANNEL(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_0) || \
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88 ((__VALUE__) == LL_DMA_CHANNEL_1) || \
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89 ((__VALUE__) == LL_DMA_CHANNEL_2) || \
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90 ((__VALUE__) == LL_DMA_CHANNEL_3) || \
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91 ((__VALUE__) == LL_DMA_CHANNEL_4) || \
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92 ((__VALUE__) == LL_DMA_CHANNEL_5) || \
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93 ((__VALUE__) == LL_DMA_CHANNEL_6) || \
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94 ((__VALUE__) == LL_DMA_CHANNEL_7))
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95
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96 #define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
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97 ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
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98 ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
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99 ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
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100
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101 #define IS_LL_DMA_ALL_STREAM_INSTANCE(INSTANCE, STREAM) ((((INSTANCE) == DMA1) && \
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102 (((STREAM) == LL_DMA_STREAM_0) || \
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103 ((STREAM) == LL_DMA_STREAM_1) || \
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104 ((STREAM) == LL_DMA_STREAM_2) || \
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105 ((STREAM) == LL_DMA_STREAM_3) || \
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106 ((STREAM) == LL_DMA_STREAM_4) || \
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107 ((STREAM) == LL_DMA_STREAM_5) || \
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108 ((STREAM) == LL_DMA_STREAM_6) || \
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109 ((STREAM) == LL_DMA_STREAM_7) || \
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110 ((STREAM) == LL_DMA_STREAM_ALL))) ||\
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111 (((INSTANCE) == DMA2) && \
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112 (((STREAM) == LL_DMA_STREAM_0) || \
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113 ((STREAM) == LL_DMA_STREAM_1) || \
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114 ((STREAM) == LL_DMA_STREAM_2) || \
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115 ((STREAM) == LL_DMA_STREAM_3) || \
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116 ((STREAM) == LL_DMA_STREAM_4) || \
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117 ((STREAM) == LL_DMA_STREAM_5) || \
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118 ((STREAM) == LL_DMA_STREAM_6) || \
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119 ((STREAM) == LL_DMA_STREAM_7) || \
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120 ((STREAM) == LL_DMA_STREAM_ALL))))
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121
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122 #define IS_LL_DMA_FIFO_MODE_STATE(STATE) (((STATE) == LL_DMA_FIFOMODE_DISABLE ) || \
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123 ((STATE) == LL_DMA_FIFOMODE_ENABLE))
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124
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125 #define IS_LL_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_4) || \
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126 ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_2) || \
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127 ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_3_4) || \
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128 ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_FULL))
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129
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130 #define IS_LL_DMA_MEMORY_BURST(BURST) (((BURST) == LL_DMA_MBURST_SINGLE) || \
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131 ((BURST) == LL_DMA_MBURST_INC4) || \
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132 ((BURST) == LL_DMA_MBURST_INC8) || \
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133 ((BURST) == LL_DMA_MBURST_INC16))
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134
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135 #define IS_LL_DMA_PERIPHERAL_BURST(BURST) (((BURST) == LL_DMA_PBURST_SINGLE) || \
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136 ((BURST) == LL_DMA_PBURST_INC4) || \
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137 ((BURST) == LL_DMA_PBURST_INC8) || \
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138 ((BURST) == LL_DMA_PBURST_INC16))
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139
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140 /**
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141 * @}
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142 */
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143
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144 /* Private function prototypes -----------------------------------------------*/
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145
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146 /* Exported functions --------------------------------------------------------*/
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147 /** @addtogroup DMA_LL_Exported_Functions
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148 * @{
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149 */
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150
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151 /** @addtogroup DMA_LL_EF_Init
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152 * @{
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153 */
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154
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155 /**
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156 * @brief De-initialize the DMA registers to their default reset values.
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157 * @param DMAx DMAx Instance
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158 * @param Stream This parameter can be one of the following values:
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159 * @arg @ref LL_DMA_STREAM_0
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160 * @arg @ref LL_DMA_STREAM_1
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161 * @arg @ref LL_DMA_STREAM_2
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162 * @arg @ref LL_DMA_STREAM_3
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163 * @arg @ref LL_DMA_STREAM_4
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164 * @arg @ref LL_DMA_STREAM_5
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165 * @arg @ref LL_DMA_STREAM_6
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166 * @arg @ref LL_DMA_STREAM_7
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167 * @arg @ref LL_DMA_STREAM_ALL
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168 * @retval An ErrorStatus enumeration value:
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169 * - SUCCESS: DMA registers are de-initialized
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170 * - ERROR: DMA registers are not de-initialized
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171 */
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172 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream)
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173 {
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174 DMA_Stream_TypeDef *tmp = (DMA_Stream_TypeDef *)DMA1_Stream0;
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175 ErrorStatus status = SUCCESS;
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176
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177 /* Check the DMA Instance DMAx and Stream parameters*/
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178 assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
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179
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180 if (Stream == LL_DMA_STREAM_ALL)
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181 {
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182 if (DMAx == DMA1)
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183 {
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184 /* Force reset of DMA clock */
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185 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
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186
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187 /* Release reset of DMA clock */
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188 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
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189 }
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190 else if (DMAx == DMA2)
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191 {
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192 /* Force reset of DMA clock */
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193 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);
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194
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195 /* Release reset of DMA clock */
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196 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);
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197 }
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198 else
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199 {
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200 status = ERROR;
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201 }
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202 }
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203 else
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204 {
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205 /* Disable the selected Stream */
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206 LL_DMA_DisableStream(DMAx,Stream);
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207
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208 /* Get the DMA Stream Instance */
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209 tmp = (DMA_Stream_TypeDef *)(__LL_DMA_GET_STREAM_INSTANCE(DMAx, Stream));
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210
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211 /* Reset DMAx_Streamy configuration register */
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212 LL_DMA_WriteReg(tmp, CR, 0U);
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213
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214 /* Reset DMAx_Streamy remaining bytes register */
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215 LL_DMA_WriteReg(tmp, NDTR, 0U);
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216
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217 /* Reset DMAx_Streamy peripheral address register */
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218 LL_DMA_WriteReg(tmp, PAR, 0U);
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219
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220 /* Reset DMAx_Streamy memory address register */
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221 LL_DMA_WriteReg(tmp, M0AR, 0U);
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222
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223 /* Reset DMAx_Streamy memory address register */
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224 LL_DMA_WriteReg(tmp, M1AR, 0U);
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225
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226 /* Reset DMAx_Streamy FIFO control register */
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227 LL_DMA_WriteReg(tmp, FCR, 0x00000021U);
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228
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229 /* Reset Channel register field for DMAx Stream*/
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230 LL_DMA_SetChannelSelection(DMAx, Stream, LL_DMA_CHANNEL_0);
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231
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232 if(Stream == LL_DMA_STREAM_0)
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233 {
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234 /* Reset the Stream0 pending flags */
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235 DMAx->LIFCR = 0x0000003FU;
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236 }
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237 else if(Stream == LL_DMA_STREAM_1)
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238 {
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239 /* Reset the Stream1 pending flags */
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240 DMAx->LIFCR = 0x00000F40U;
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241 }
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242 else if(Stream == LL_DMA_STREAM_2)
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243 {
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244 /* Reset the Stream2 pending flags */
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245 DMAx->LIFCR = 0x003F0000U;
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246 }
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247 else if(Stream == LL_DMA_STREAM_3)
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248 {
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249 /* Reset the Stream3 pending flags */
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250 DMAx->LIFCR = 0x0F400000U;
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251 }
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252 else if(Stream == LL_DMA_STREAM_4)
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253 {
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254 /* Reset the Stream4 pending flags */
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255 DMAx->HIFCR = 0x0000003FU;
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256 }
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257 else if(Stream == LL_DMA_STREAM_5)
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258 {
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259 /* Reset the Stream5 pending flags */
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260 DMAx->HIFCR = 0x00000F40U;
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261 }
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262 else if(Stream == LL_DMA_STREAM_6)
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263 {
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264 /* Reset the Stream6 pending flags */
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265 DMAx->HIFCR = 0x003F0000U;
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266 }
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267 else if(Stream == LL_DMA_STREAM_7)
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268 {
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269 /* Reset the Stream7 pending flags */
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270 DMAx->HIFCR = 0x0F400000U;
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271 }
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272 else
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273 {
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274 status = ERROR;
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275 }
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276 }
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277
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278 return status;
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279 }
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280
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281 /**
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282 * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
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283 * @note To convert DMAx_Streamy Instance to DMAx Instance and Streamy, use helper macros :
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284 * @arg @ref __LL_DMA_GET_INSTANCE
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285 * @arg @ref __LL_DMA_GET_STREAM
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286 * @param DMAx DMAx Instance
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287 * @param Stream This parameter can be one of the following values:
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288 * @arg @ref LL_DMA_STREAM_0
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289 * @arg @ref LL_DMA_STREAM_1
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290 * @arg @ref LL_DMA_STREAM_2
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291 * @arg @ref LL_DMA_STREAM_3
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292 * @arg @ref LL_DMA_STREAM_4
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293 * @arg @ref LL_DMA_STREAM_5
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294 * @arg @ref LL_DMA_STREAM_6
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295 * @arg @ref LL_DMA_STREAM_7
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296 * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
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297 * @retval An ErrorStatus enumeration value:
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298 * - SUCCESS: DMA registers are initialized
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299 * - ERROR: Not applicable
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300 */
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301 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct)
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302 {
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303 /* Check the DMA Instance DMAx and Stream parameters*/
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304 assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
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305
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306 /* Check the DMA parameters from DMA_InitStruct */
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307 assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
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308 assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
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309 assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
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310 assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
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311 assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
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312 assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
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313 assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
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314 assert_param(IS_LL_DMA_CHANNEL(DMA_InitStruct->Channel));
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315 assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
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316 assert_param(IS_LL_DMA_FIFO_MODE_STATE(DMA_InitStruct->FIFOMode));
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317 /* Check the memory burst, peripheral burst and FIFO threshold parameters only
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318 when FIFO mode is enabled */
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319 if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
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320 {
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321 assert_param(IS_LL_DMA_FIFO_THRESHOLD(DMA_InitStruct->FIFOThreshold));
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322 assert_param(IS_LL_DMA_MEMORY_BURST(DMA_InitStruct->MemBurst));
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323 assert_param(IS_LL_DMA_PERIPHERAL_BURST(DMA_InitStruct->PeriphBurst));
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324 }
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325
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326 /*---------------------------- DMAx SxCR Configuration ------------------------
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327 * Configure DMAx_Streamy: data transfer direction, data transfer mode,
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328 * peripheral and memory increment mode,
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329 * data size alignment and priority level with parameters :
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330 * - Direction: DMA_SxCR_DIR[1:0] bits
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331 * - Mode: DMA_SxCR_CIRC bit
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332 * - PeriphOrM2MSrcIncMode: DMA_SxCR_PINC bit
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333 * - MemoryOrM2MDstIncMode: DMA_SxCR_MINC bit
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334 * - PeriphOrM2MSrcDataSize: DMA_SxCR_PSIZE[1:0] bits
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335 * - MemoryOrM2MDstDataSize: DMA_SxCR_MSIZE[1:0] bits
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336 * - Priority: DMA_SxCR_PL[1:0] bits
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337 */
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338 LL_DMA_ConfigTransfer(DMAx, Stream, DMA_InitStruct->Direction | \
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339 DMA_InitStruct->Mode | \
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340 DMA_InitStruct->PeriphOrM2MSrcIncMode | \
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341 DMA_InitStruct->MemoryOrM2MDstIncMode | \
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342 DMA_InitStruct->PeriphOrM2MSrcDataSize | \
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343 DMA_InitStruct->MemoryOrM2MDstDataSize | \
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344 DMA_InitStruct->Priority
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345 );
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346
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347 if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
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348 {
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349 /*---------------------------- DMAx SxFCR Configuration ------------------------
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350 * Configure DMAx_Streamy: fifo mode and fifo threshold with parameters :
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351 * - FIFOMode: DMA_SxFCR_DMDIS bit
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352 * - FIFOThreshold: DMA_SxFCR_FTH[1:0] bits
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353 */
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354 LL_DMA_ConfigFifo(DMAx, Stream, DMA_InitStruct->FIFOMode, DMA_InitStruct->FIFOThreshold);
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355
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356 /*---------------------------- DMAx SxCR Configuration --------------------------
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357 * Configure DMAx_Streamy: memory burst transfer with parameters :
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358 * - MemBurst: DMA_SxCR_MBURST[1:0] bits
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359 */
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360 LL_DMA_SetMemoryBurstxfer(DMAx,Stream,DMA_InitStruct->MemBurst);
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361
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362 /*---------------------------- DMAx SxCR Configuration --------------------------
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363 * Configure DMAx_Streamy: peripheral burst transfer with parameters :
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364 * - PeriphBurst: DMA_SxCR_PBURST[1:0] bits
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365 */
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366 LL_DMA_SetPeriphBurstxfer(DMAx,Stream,DMA_InitStruct->PeriphBurst);
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367 }
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368
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369 /*-------------------------- DMAx SxM0AR Configuration --------------------------
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370 * Configure the memory or destination base address with parameter :
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371 * - MemoryOrM2MDstAddress: DMA_SxM0AR_M0A[31:0] bits
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372 */
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373 LL_DMA_SetMemoryAddress(DMAx, Stream, DMA_InitStruct->MemoryOrM2MDstAddress);
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374
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375 /*-------------------------- DMAx SxPAR Configuration ---------------------------
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376 * Configure the peripheral or source base address with parameter :
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377 * - PeriphOrM2MSrcAddress: DMA_SxPAR_PA[31:0] bits
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378 */
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379 LL_DMA_SetPeriphAddress(DMAx, Stream, DMA_InitStruct->PeriphOrM2MSrcAddress);
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380
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381 /*--------------------------- DMAx SxNDTR Configuration -------------------------
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382 * Configure the peripheral base address with parameter :
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383 * - NbData: DMA_SxNDT[15:0] bits
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384 */
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385 LL_DMA_SetDataLength(DMAx, Stream, DMA_InitStruct->NbData);
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386
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387 /*--------------------------- DMA SxCR_CHSEL Configuration ----------------------
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388 * Configure the peripheral base address with parameter :
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389 * - PeriphRequest: DMA_SxCR_CHSEL[2:0] bits
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390 */
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391 LL_DMA_SetChannelSelection(DMAx, Stream, DMA_InitStruct->Channel);
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392
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393 return SUCCESS;
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394 }
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395
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396 /**
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397 * @brief Set each @ref LL_DMA_InitTypeDef field to default value.
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398 * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
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399 * @retval None
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400 */
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401 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
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402 {
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403 /* Set DMA_InitStruct fields to default values */
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404 DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
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405 DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
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406 DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
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407 DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
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408 DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
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409 DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
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410 DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
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411 DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
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412 DMA_InitStruct->NbData = 0x00000000U;
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413 DMA_InitStruct->Channel = LL_DMA_CHANNEL_0;
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414 DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
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415 DMA_InitStruct->FIFOMode = LL_DMA_FIFOMODE_DISABLE;
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416 DMA_InitStruct->FIFOThreshold = LL_DMA_FIFOTHRESHOLD_1_4;
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417 DMA_InitStruct->MemBurst = LL_DMA_MBURST_SINGLE;
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418 DMA_InitStruct->PeriphBurst = LL_DMA_PBURST_SINGLE;
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419 }
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420
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421 /**
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422 * @}
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423 */
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424
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425 /**
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426 * @}
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427 */
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428
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429 /**
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430 * @}
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431 */
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432
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433 #endif /* DMA1 || DMA2 */
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434
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435 /**
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436 * @}
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437 */
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438
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439 #endif /* USE_FULL_LL_DRIVER */
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440
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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441 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/