Mercurial > public > ostc4
annotate Common/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_spi.c @ 504:8428195a4967
Added worst case plausibility check (disabled by compile switch)
Just used in case of development activities which may cause negativ values resulting in errors / timeout in the deco calculation
author | Ideenmodellierer |
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date | Mon, 24 Aug 2020 19:59:28 +0200 |
parents | c78bcbd5deda |
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rev | line source |
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128
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1 /** |
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2 ****************************************************************************** |
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3 * @file stm32f4xx_ll_spi.c |
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4 * @author MCD Application Team |
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5 * @brief SPI LL module driver. |
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6 ****************************************************************************** |
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7 * @attention |
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8 * |
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9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
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10 * |
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11 * Redistribution and use in source and binary forms, with or without modification, |
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12 * are permitted provided that the following conditions are met: |
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13 * 1. Redistributions of source code must retain the above copyright notice, |
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14 * this list of conditions and the following disclaimer. |
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15 * 2. Redistributions in binary form must reproduce the above copyright notice, |
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16 * this list of conditions and the following disclaimer in the documentation |
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17 * and/or other materials provided with the distribution. |
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18 * 3. Neither the name of STMicroelectronics nor the names of its contributors |
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19 * may be used to endorse or promote products derived from this software |
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20 * without specific prior written permission. |
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21 * |
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22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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32 * |
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33 ****************************************************************************** |
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34 */ |
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35 #if defined(USE_FULL_LL_DRIVER) |
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36 |
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37 /* Includes ------------------------------------------------------------------*/ |
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38 #include "stm32f4xx_ll_spi.h" |
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39 #include "stm32f4xx_ll_bus.h" |
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40 #include "stm32f4xx_ll_rcc.h" |
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41 |
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42 #ifdef USE_FULL_ASSERT |
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43 #include "stm32_assert.h" |
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44 #else |
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45 #define assert_param(expr) ((void)0U) |
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46 #endif |
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47 |
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48 /** @addtogroup STM32F4xx_LL_Driver |
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49 * @{ |
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50 */ |
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51 |
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52 #if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6) |
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53 |
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54 /** @addtogroup SPI_LL |
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55 * @{ |
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56 */ |
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57 |
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58 /* Private types -------------------------------------------------------------*/ |
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59 /* Private variables ---------------------------------------------------------*/ |
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60 |
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61 /* Private constants ---------------------------------------------------------*/ |
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62 /** @defgroup SPI_LL_Private_Constants SPI Private Constants |
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63 * @{ |
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64 */ |
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65 /* SPI registers Masks */ |
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66 #define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \ |
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67 SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \ |
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68 SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_DFF | \ |
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69 SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \ |
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70 SPI_CR1_BIDIMODE) |
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71 /** |
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72 * @} |
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73 */ |
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74 |
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75 /* Private macros ------------------------------------------------------------*/ |
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76 /** @defgroup SPI_LL_Private_Macros SPI Private Macros |
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77 * @{ |
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78 */ |
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79 #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \ |
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80 || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \ |
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81 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \ |
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82 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX)) |
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83 |
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84 #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \ |
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85 || ((__VALUE__) == LL_SPI_MODE_SLAVE)) |
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86 |
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87 #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \ |
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88 || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT)) |
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89 |
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90 #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \ |
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91 || ((__VALUE__) == LL_SPI_POLARITY_HIGH)) |
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92 |
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93 #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \ |
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94 || ((__VALUE__) == LL_SPI_PHASE_2EDGE)) |
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95 |
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96 #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \ |
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97 || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \ |
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98 || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT)) |
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99 |
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100 #define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \ |
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101 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \ |
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102 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \ |
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103 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \ |
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104 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \ |
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105 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \ |
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106 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \ |
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107 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256)) |
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108 |
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109 #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \ |
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110 || ((__VALUE__) == LL_SPI_MSB_FIRST)) |
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111 |
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112 #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \ |
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113 || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE)) |
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114 |
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115 #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U) |
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116 |
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117 /** |
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118 * @} |
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119 */ |
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120 |
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121 /* Private function prototypes -----------------------------------------------*/ |
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122 |
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123 /* Exported functions --------------------------------------------------------*/ |
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124 /** @addtogroup SPI_LL_Exported_Functions |
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125 * @{ |
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126 */ |
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127 |
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128 /** @addtogroup SPI_LL_EF_Init |
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129 * @{ |
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130 */ |
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131 |
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132 /** |
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133 * @brief De-initialize the SPI registers to their default reset values. |
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134 * @param SPIx SPI Instance |
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135 * @retval An ErrorStatus enumeration value: |
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136 * - SUCCESS: SPI registers are de-initialized |
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137 * - ERROR: SPI registers are not de-initialized |
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138 */ |
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139 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) |
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140 { |
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141 ErrorStatus status = ERROR; |
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142 |
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143 /* Check the parameters */ |
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144 assert_param(IS_SPI_ALL_INSTANCE(SPIx)); |
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145 |
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146 #if defined(SPI1) |
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147 if (SPIx == SPI1) |
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148 { |
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149 /* Force reset of SPI clock */ |
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150 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1); |
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151 |
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152 /* Release reset of SPI clock */ |
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153 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1); |
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154 |
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155 status = SUCCESS; |
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156 } |
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157 #endif /* SPI1 */ |
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158 #if defined(SPI2) |
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159 if (SPIx == SPI2) |
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160 { |
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161 /* Force reset of SPI clock */ |
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162 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2); |
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163 |
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164 /* Release reset of SPI clock */ |
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165 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2); |
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166 |
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167 status = SUCCESS; |
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168 } |
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169 #endif /* SPI2 */ |
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170 #if defined(SPI3) |
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171 if (SPIx == SPI3) |
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172 { |
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173 /* Force reset of SPI clock */ |
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174 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3); |
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175 |
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176 /* Release reset of SPI clock */ |
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177 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3); |
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178 |
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179 status = SUCCESS; |
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180 } |
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181 #endif /* SPI3 */ |
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182 #if defined(SPI4) |
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183 if (SPIx == SPI4) |
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184 { |
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185 /* Force reset of SPI clock */ |
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186 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4); |
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187 |
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188 /* Release reset of SPI clock */ |
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189 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4); |
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190 |
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191 status = SUCCESS; |
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192 } |
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193 #endif /* SPI4 */ |
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194 #if defined(SPI5) |
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195 if (SPIx == SPI5) |
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196 { |
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197 /* Force reset of SPI clock */ |
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198 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI5); |
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199 |
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200 /* Release reset of SPI clock */ |
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201 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI5); |
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202 |
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203 status = SUCCESS; |
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204 } |
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205 #endif /* SPI5 */ |
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206 #if defined(SPI6) |
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207 if (SPIx == SPI6) |
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208 { |
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209 /* Force reset of SPI clock */ |
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210 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI6); |
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211 |
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212 /* Release reset of SPI clock */ |
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213 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI6); |
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214 |
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215 status = SUCCESS; |
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216 } |
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217 #endif /* SPI6 */ |
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218 |
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219 return status; |
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220 } |
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221 |
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222 /** |
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223 * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct. |
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224 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), |
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225 * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. |
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226 * @param SPIx SPI Instance |
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227 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure |
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228 * @retval An ErrorStatus enumeration value. (Return always SUCCESS) |
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229 */ |
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230 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct) |
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231 { |
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232 ErrorStatus status = ERROR; |
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233 |
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234 /* Check the SPI Instance SPIx*/ |
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235 assert_param(IS_SPI_ALL_INSTANCE(SPIx)); |
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236 |
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237 /* Check the SPI parameters from SPI_InitStruct*/ |
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238 assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection)); |
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239 assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode)); |
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240 assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth)); |
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241 assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity)); |
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242 assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase)); |
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243 assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS)); |
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244 assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate)); |
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245 assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder)); |
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246 assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation)); |
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247 |
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248 if (LL_SPI_IsEnabled(SPIx) == 0x00000000U) |
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249 { |
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250 /*---------------------------- SPIx CR1 Configuration ------------------------ |
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251 * Configure SPIx CR1 with parameters: |
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252 * - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits |
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253 * - Master/Slave Mode: SPI_CR1_MSTR bit |
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254 * - DataWidth: SPI_CR1_DFF bit |
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255 * - ClockPolarity: SPI_CR1_CPOL bit |
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256 * - ClockPhase: SPI_CR1_CPHA bit |
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257 * - NSS management: SPI_CR1_SSM bit |
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258 * - BaudRate prescaler: SPI_CR1_BR[2:0] bits |
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259 * - BitOrder: SPI_CR1_LSBFIRST bit |
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260 * - CRCCalculation: SPI_CR1_CRCEN bit |
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261 */ |
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262 MODIFY_REG(SPIx->CR1, |
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263 SPI_CR1_CLEAR_MASK, |
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264 SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode | SPI_InitStruct->DataWidth | |
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265 SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase | |
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266 SPI_InitStruct->NSS | SPI_InitStruct->BaudRate | |
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267 SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation); |
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268 |
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269 /*---------------------------- SPIx CR2 Configuration ------------------------ |
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270 * Configure SPIx CR2 with parameters: |
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271 * - NSS management: SSOE bit |
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272 */ |
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273 MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, (SPI_InitStruct->NSS >> 16U)); |
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274 |
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275 /*---------------------------- SPIx CRCPR Configuration ---------------------- |
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276 * Configure SPIx CRCPR with parameters: |
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277 * - CRCPoly: CRCPOLY[15:0] bits |
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278 */ |
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279 if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE) |
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280 { |
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281 assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly)); |
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282 LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly); |
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283 } |
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284 status = SUCCESS; |
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285 } |
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286 |
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287 /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ |
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288 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD); |
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289 return status; |
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290 } |
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291 |
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292 /** |
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293 * @brief Set each @ref LL_SPI_InitTypeDef field to default value. |
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294 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure |
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295 * whose fields will be set to default values. |
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296 * @retval None |
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297 */ |
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298 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct) |
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299 { |
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300 /* Set SPI_InitStruct fields to default values */ |
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301 SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX; |
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302 SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE; |
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303 SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT; |
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304 SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW; |
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305 SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE; |
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306 SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT; |
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307 SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2; |
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308 SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST; |
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309 SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; |
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310 SPI_InitStruct->CRCPoly = 7U; |
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311 } |
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312 |
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313 /** |
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314 * @} |
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315 */ |
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316 |
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317 /** |
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318 * @} |
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319 */ |
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320 |
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321 /** |
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322 * @} |
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323 */ |
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324 |
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325 /** @addtogroup I2S_LL |
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326 * @{ |
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327 */ |
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328 |
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329 /* Private types -------------------------------------------------------------*/ |
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330 /* Private variables ---------------------------------------------------------*/ |
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331 /* Private constants ---------------------------------------------------------*/ |
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332 /** @defgroup I2S_LL_Private_Constants I2S Private Constants |
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333 * @{ |
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334 */ |
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335 /* I2S registers Masks */ |
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336 #define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \ |
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337 SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \ |
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338 SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD ) |
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339 |
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340 #define I2S_I2SPR_CLEAR_MASK 0x0002U |
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341 /** |
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342 * @} |
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343 */ |
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344 /* Private macros ------------------------------------------------------------*/ |
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345 /** @defgroup I2S_LL_Private_Macros I2S Private Macros |
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346 * @{ |
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347 */ |
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348 |
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349 #define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \ |
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350 || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \ |
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351 || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \ |
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352 || ((__VALUE__) == LL_I2S_DATAFORMAT_32B)) |
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353 |
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354 #define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \ |
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355 || ((__VALUE__) == LL_I2S_POLARITY_HIGH)) |
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356 |
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357 #define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \ |
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358 || ((__VALUE__) == LL_I2S_STANDARD_MSB) \ |
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359 || ((__VALUE__) == LL_I2S_STANDARD_LSB) \ |
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360 || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \ |
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361 || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG)) |
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362 |
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363 #define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \ |
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364 || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \ |
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365 || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \ |
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366 || ((__VALUE__) == LL_I2S_MODE_MASTER_RX)) |
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367 |
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368 #define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \ |
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369 || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE)) |
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370 |
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371 #define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \ |
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372 && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \ |
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373 || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT)) |
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374 |
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375 #define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U) |
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376 |
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377 #define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \ |
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378 || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD)) |
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379 /** |
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380 * @} |
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381 */ |
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382 |
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383 /* Private function prototypes -----------------------------------------------*/ |
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384 |
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385 /* Exported functions --------------------------------------------------------*/ |
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386 /** @addtogroup I2S_LL_Exported_Functions |
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387 * @{ |
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388 */ |
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389 |
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390 /** @addtogroup I2S_LL_EF_Init |
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391 * @{ |
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392 */ |
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393 |
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394 /** |
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395 * @brief De-initialize the SPI/I2S registers to their default reset values. |
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396 * @param SPIx SPI Instance |
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397 * @retval An ErrorStatus enumeration value: |
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398 * - SUCCESS: SPI registers are de-initialized |
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399 * - ERROR: SPI registers are not de-initialized |
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400 */ |
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401 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx) |
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402 { |
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403 return LL_SPI_DeInit(SPIx); |
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404 } |
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405 |
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406 /** |
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407 * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct. |
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408 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), |
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409 * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. |
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410 * @param SPIx SPI Instance |
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411 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure |
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412 * @retval An ErrorStatus enumeration value: |
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413 * - SUCCESS: SPI registers are Initialized |
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414 * - ERROR: SPI registers are not Initialized |
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415 */ |
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416 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct) |
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417 { |
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418 uint16_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U; |
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419 uint32_t tmp = 0U; |
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420 uint32_t sourceclock = 0U; |
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421 ErrorStatus status = ERROR; |
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422 |
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423 /* Check the I2S parameters */ |
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424 assert_param(IS_I2S_ALL_INSTANCE(SPIx)); |
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425 assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode)); |
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426 assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard)); |
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427 assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat)); |
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428 assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput)); |
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429 assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq)); |
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430 assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity)); |
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431 |
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432 if (LL_I2S_IsEnabled(SPIx) == 0x00000000U) |
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433 { |
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434 /*---------------------------- SPIx I2SCFGR Configuration -------------------- |
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435 * Configure SPIx I2SCFGR with parameters: |
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436 * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit |
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437 * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits |
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438 * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits |
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439 * - ClockPolarity: SPI_I2SCFGR_CKPOL bit |
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440 */ |
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441 |
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442 /* Write to SPIx I2SCFGR */ |
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443 MODIFY_REG(SPIx->I2SCFGR, |
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444 I2S_I2SCFGR_CLEAR_MASK, |
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445 I2S_InitStruct->Mode | I2S_InitStruct->Standard | |
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446 I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity | |
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447 SPI_I2SCFGR_I2SMOD); |
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448 |
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449 /*---------------------------- SPIx I2SPR Configuration ---------------------- |
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450 * Configure SPIx I2SPR with parameters: |
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451 * - MCLKOutput: SPI_I2SPR_MCKOE bit |
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452 * - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits |
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453 */ |
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454 |
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455 /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv) |
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456 * else, default values are used: i2sodd = 0U, i2sdiv = 2U. |
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457 */ |
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458 if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT) |
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459 { |
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460 /* Check the frame length (For the Prescaler computing) |
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461 * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U). |
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462 */ |
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463 if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B) |
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464 { |
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465 /* Packet length is 32 bits */ |
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466 packetlength = 2U; |
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467 } |
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468 |
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469 /* If an external I2S clock has to be used, the specific define should be set |
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470 in the project configuration or in the stm32f4xx_ll_rcc.h file */ |
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471 /* Get the I2S source clock value */ |
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472 sourceclock = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE); |
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473 |
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474 /* Compute the Real divider depending on the MCLK output state with a floating point */ |
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475 if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE) |
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476 { |
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477 /* MCLK output is enabled */ |
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478 tmp = (uint16_t)(((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U); |
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479 } |
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480 else |
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481 { |
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482 /* MCLK output is disabled */ |
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483 tmp = (uint16_t)(((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U); |
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484 } |
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485 |
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486 /* Remove the floating point */ |
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487 tmp = tmp / 10U; |
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488 |
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489 /* Check the parity of the divider */ |
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490 i2sodd = (uint16_t)(tmp & (uint16_t)0x0001U); |
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491 |
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492 /* Compute the i2sdiv prescaler */ |
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493 i2sdiv = (uint16_t)((tmp - i2sodd) / 2U); |
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494 |
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495 /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ |
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496 i2sodd = (uint16_t)(i2sodd << 8U); |
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497 } |
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498 |
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499 /* Test if the divider is 1 or 0 or greater than 0xFF */ |
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500 if ((i2sdiv < 2U) || (i2sdiv > 0xFFU)) |
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501 { |
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502 /* Set the default values */ |
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503 i2sdiv = 2U; |
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504 i2sodd = 0U; |
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505 } |
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506 |
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507 /* Write to SPIx I2SPR register the computed value */ |
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508 WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput); |
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509 |
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510 status = SUCCESS; |
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511 } |
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512 return status; |
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513 } |
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514 |
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515 /** |
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516 * @brief Set each @ref LL_I2S_InitTypeDef field to default value. |
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517 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure |
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518 * whose fields will be set to default values. |
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519 * @retval None |
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520 */ |
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521 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct) |
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522 { |
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523 /*--------------- Reset I2S init structure parameters values -----------------*/ |
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524 I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX; |
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525 I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS; |
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526 I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B; |
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527 I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE; |
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528 I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT; |
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529 I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW; |
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530 } |
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531 |
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532 /** |
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533 * @brief Set linear and parity prescaler. |
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534 * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n |
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535 * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S). |
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536 * @param SPIx SPI Instance |
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537 * @param PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF. |
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538 * @param PrescalerParity This parameter can be one of the following values: |
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539 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN |
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540 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD |
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541 * @retval None |
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542 */ |
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543 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity) |
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544 { |
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545 /* Check the I2S parameters */ |
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546 assert_param(IS_I2S_ALL_INSTANCE(SPIx)); |
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547 assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear)); |
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548 assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity)); |
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549 |
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550 /* Write to SPIx I2SPR */ |
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551 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U)); |
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552 } |
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553 |
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554 #if defined (SPI_I2S_FULLDUPLEX_SUPPORT) |
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555 /** |
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556 * @brief Configures the full duplex mode for the I2Sx peripheral using its extension |
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557 * I2Sxext according to the specified parameters in the I2S_InitStruct. |
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558 * @note The structure pointed by I2S_InitStruct parameter should be the same |
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559 * used for the master I2S peripheral. In this case, if the master is |
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560 * configured as transmitter, the slave will be receiver and vice versa. |
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561 * Or you can force a different mode by modifying the field I2S_Mode to the |
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562 * value I2S_SlaveRx or I2S_SlaveTx independently of the master configuration. |
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563 * @param I2Sxext SPI Instance |
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564 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure |
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565 * @retval An ErrorStatus enumeration value: |
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566 * - SUCCESS: I2Sxext registers are Initialized |
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567 * - ERROR: I2Sxext registers are not Initialized |
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568 */ |
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569 ErrorStatus LL_I2S_InitFullDuplex(SPI_TypeDef *I2Sxext, LL_I2S_InitTypeDef *I2S_InitStruct) |
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570 { |
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571 uint16_t mode = 0U; |
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572 ErrorStatus status = ERROR; |
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573 |
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574 /* Check the I2S parameters */ |
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575 assert_param(IS_I2S_EXT_ALL_INSTANCE(I2Sxext)); |
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576 assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode)); |
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577 assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard)); |
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578 assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat)); |
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579 assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity)); |
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580 |
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581 if (LL_I2S_IsEnabled(I2Sxext) == 0x00000000U) |
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582 { |
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583 /*---------------------------- SPIx I2SCFGR Configuration -------------------- |
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584 * Configure SPIx I2SCFGR with parameters: |
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585 * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit |
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586 * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits |
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587 * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits |
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588 * - ClockPolarity: SPI_I2SCFGR_CKPOL bit |
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589 */ |
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590 |
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591 /* Reset I2SPR registers */ |
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592 WRITE_REG(I2Sxext->I2SPR, I2S_I2SPR_CLEAR_MASK); |
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593 |
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594 /* Get the mode to be configured for the extended I2S */ |
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595 if ((I2S_InitStruct->Mode == LL_I2S_MODE_MASTER_TX) || (I2S_InitStruct->Mode == LL_I2S_MODE_SLAVE_TX)) |
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596 { |
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597 mode = LL_I2S_MODE_SLAVE_RX; |
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598 } |
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599 else |
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600 { |
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601 if ((I2S_InitStruct->Mode == LL_I2S_MODE_MASTER_RX) || (I2S_InitStruct->Mode == LL_I2S_MODE_SLAVE_RX)) |
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602 { |
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603 mode = LL_I2S_MODE_SLAVE_TX; |
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604 } |
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605 } |
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606 |
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607 /* Write to SPIx I2SCFGR */ |
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608 MODIFY_REG(I2Sxext->I2SCFGR, |
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609 I2S_I2SCFGR_CLEAR_MASK, |
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610 I2S_InitStruct->Standard | |
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611 I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity | |
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612 SPI_I2SCFGR_I2SMOD | mode); |
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613 |
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614 status = SUCCESS; |
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615 } |
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616 return status; |
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617 } |
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618 #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */ |
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619 |
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620 /** |
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621 * @} |
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622 */ |
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623 |
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624 /** |
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625 * @} |
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626 */ |
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627 |
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628 /** |
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629 * @} |
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630 */ |
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631 |
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632 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6) */ |
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633 |
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634 /** |
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635 * @} |
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636 */ |
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637 |
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638 #endif /* USE_FULL_LL_DRIVER */ |
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639 |
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640 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |