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38
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1 /**
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2 ******************************************************************************
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3 * @file stm32f4xx_ll_fsmc.h
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4 * @author MCD Application Team
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5 * @version V1.2.0
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6 * @date 26-December-2014
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7 * @brief Header file of FSMC HAL module.
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8 ******************************************************************************
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9 * @attention
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10 *
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11 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
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12 *
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13 * Redistribution and use in source and binary forms, with or without modification,
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14 * are permitted provided that the following conditions are met:
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15 * 1. Redistributions of source code must retain the above copyright notice,
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16 * this list of conditions and the following disclaimer.
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17 * 2. Redistributions in binary form must reproduce the above copyright notice,
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18 * this list of conditions and the following disclaimer in the documentation
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19 * and/or other materials provided with the distribution.
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20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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21 * may be used to endorse or promote products derived from this software
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22 * without specific prior written permission.
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23 *
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24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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34 *
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35 ******************************************************************************
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36 */
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37
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38 /* Define to prevent recursive inclusion -------------------------------------*/
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39 #ifndef __STM32F4xx_LL_FSMC_H
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40 #define __STM32F4xx_LL_FSMC_H
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41
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42 #ifdef __cplusplus
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43 extern "C" {
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44 #endif
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45
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46 /* Includes ------------------------------------------------------------------*/
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47 #include "stm32f4xx_hal_def.h"
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48
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49 /** @addtogroup STM32F4xx_HAL_Driver
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50 * @{
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51 */
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52
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53 /** @addtogroup FSMC_LL
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54 * @{
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55 */
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56
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57 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
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58 /* Private types -------------------------------------------------------------*/
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59 /** @defgroup FSMC_LL_Private_Types FSMC Private Types
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60 * @{
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61 */
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62
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63 /**
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64 * @brief FSMC NORSRAM Configuration Structure definition
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65 */
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66 typedef struct
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67 {
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68 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
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69 This parameter can be a value of @ref FSMC_NORSRAM_Bank */
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70
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71 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
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72 multiplexed on the data bus or not.
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73 This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
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74
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75 uint32_t MemoryType; /*!< Specifies the type of external memory attached to
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76 the corresponding memory device.
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77 This parameter can be a value of @ref FSMC_Memory_Type */
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78
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79 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
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80 This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
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81
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82 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
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83 valid only with synchronous burst Flash memories.
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84 This parameter can be a value of @ref FSMC_Burst_Access_Mode */
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85
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86 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
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87 the Flash memory in burst mode.
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88 This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
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89
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90 uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
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91 memory, valid only when accessing Flash memories in burst mode.
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92 This parameter can be a value of @ref FSMC_Wrap_Mode */
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93
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94 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
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95 clock cycle before the wait state or during the wait state,
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96 valid only when accessing memories in burst mode.
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97 This parameter can be a value of @ref FSMC_Wait_Timing */
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98
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99 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC.
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100 This parameter can be a value of @ref FSMC_Write_Operation */
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101
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102 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
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103 signal, valid for Flash memory access in burst mode.
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104 This parameter can be a value of @ref FSMC_Wait_Signal */
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105
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106 uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
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107 This parameter can be a value of @ref FSMC_Extended_Mode */
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108
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109 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
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110 valid only with asynchronous Flash memories.
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111 This parameter can be a value of @ref FSMC_AsynchronousWait */
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112
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113 uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
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114 This parameter can be a value of @ref FSMC_Write_Burst */
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115
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116 }FSMC_NORSRAM_InitTypeDef;
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117
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118 /**
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119 * @brief FSMC NORSRAM Timing parameters structure definition
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120 */
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121 typedef struct
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122 {
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123 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
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124 the duration of the address setup time.
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125 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
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126 @note This parameter is not used with synchronous NOR Flash memories. */
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127
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128 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
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129 the duration of the address hold time.
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130 This parameter can be a value between Min_Data = 1 and Max_Data = 15.
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131 @note This parameter is not used with synchronous NOR Flash memories. */
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132
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133 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
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134 the duration of the data setup time.
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135 This parameter can be a value between Min_Data = 1 and Max_Data = 255.
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136 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
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137 NOR Flash memories. */
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138
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139 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
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140 the duration of the bus turnaround.
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141 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
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142 @note This parameter is only used for multiplexed NOR Flash memories. */
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143
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144 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
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145 HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
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146 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
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147 accesses. */
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148
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149 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
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150 to the memory before getting the first data.
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151 The parameter value depends on the memory type as shown below:
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152 - It must be set to 0 in case of a CRAM
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153 - It is don't care in asynchronous NOR, SRAM or ROM accesses
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154 - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
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155 with synchronous burst mode enable */
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156
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157 uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
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158 This parameter can be a value of @ref FSMC_Access_Mode */
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159
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160 }FSMC_NORSRAM_TimingTypeDef;
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161
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162 /**
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163 * @brief FSMC NAND Configuration Structure definition
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164 */
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165 typedef struct
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166 {
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167 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
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168 This parameter can be a value of @ref FSMC_NAND_Bank */
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169
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170 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
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171 This parameter can be any value of @ref FSMC_Wait_feature */
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172
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173 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
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174 This parameter can be any value of @ref FSMC_NAND_Data_Width */
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175
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176 uint32_t EccComputation; /*!< Enables or disables the ECC computation.
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177 This parameter can be any value of @ref FSMC_ECC */
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178
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179 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
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180 This parameter can be any value of @ref FSMC_ECC_Page_Size */
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181
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182 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
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183 delay between CLE low and RE low.
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184 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
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185
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186 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
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187 delay between ALE low and RE low.
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188 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
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189
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190 }FSMC_NAND_InitTypeDef;
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191
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192 /**
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193 * @brief FSMC NAND/PCCARD Timing parameters structure definition
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194 */
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195 typedef struct
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196 {
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197 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
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198 the command assertion for NAND-Flash read or write access
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199 to common/Attribute or I/O memory space (depending on
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200 the memory space timing to be configured).
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201 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
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202
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203 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
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204 command for NAND-Flash read or write access to
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205 common/Attribute or I/O memory space (depending on the
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206 memory space timing to be configured).
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207 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
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208
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209 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
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210 (and data for write access) after the command de-assertion
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211 for NAND-Flash read or write access to common/Attribute
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212 or I/O memory space (depending on the memory space timing
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213 to be configured).
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214 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
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215
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216 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
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217 data bus is kept in HiZ after the start of a NAND-Flash
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218 write access to common/Attribute or I/O memory space (depending
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219 on the memory space timing to be configured).
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220 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
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221
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222 }FSMC_NAND_PCC_TimingTypeDef;
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223
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224 /**
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225 * @brief FSMC NAND Configuration Structure definition
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226 */
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227 typedef struct
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228 {
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229 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
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230 This parameter can be any value of @ref FSMC_Wait_feature */
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231
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232 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
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233 delay between CLE low and RE low.
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234 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
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235
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236 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
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237 delay between ALE low and RE low.
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238 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
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239
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240 }FSMC_PCCARD_InitTypeDef;
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241 /**
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242 * @}
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243 */
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244
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245 /* Private constants ---------------------------------------------------------*/
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246 /** @defgroup FSMC_LL_Private_Constants FSMC Private Constants
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247 * @{
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248 */
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249
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250 /** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller
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251 * @{
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252 */
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253 /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
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254 * @{
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255 */
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256 #define FSMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
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257 #define FSMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
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258 #define FSMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
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259 #define FSMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
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260 /**
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261 * @}
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262 */
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263
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264 /** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
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265 * @{
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266 */
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267 #define FSMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
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268 #define FSMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
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269 /**
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270 * @}
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271 */
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272
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273 /** @defgroup FSMC_Memory_Type FSMC Memory Type
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274 * @{
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275 */
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276 #define FSMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
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277 #define FSMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
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278 #define FSMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
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279 /**
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280 * @}
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281 */
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282
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283 /** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width
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284 * @{
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285 */
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286 #define FSMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
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287 #define FSMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
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288 #define FSMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
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289 /**
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290 * @}
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291 */
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292
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293 /** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
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294 * @{
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295 */
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296 #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
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297 #define FSMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
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298 /**
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299 * @}
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300 */
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301
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302 /** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
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303 * @{
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304 */
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305 #define FSMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
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306 #define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
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307 /**
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308 * @}
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309 */
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310
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311 /** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
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312 * @{
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313 */
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314 #define FSMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
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315 #define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
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316 /**
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317 * @}
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318 */
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319
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320 /** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
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321 * @{
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322 */
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323 #define FSMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
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324 #define FSMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
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325 /**
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326 * @}
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327 */
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328
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329 /** @defgroup FSMC_Wait_Timing FSMC Wait Timing
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330 * @{
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331 */
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332 #define FSMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
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333 #define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
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334 /**
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335 * @}
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336 */
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337
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338 /** @defgroup FSMC_Write_Operation FSMC Write Operation
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339 * @{
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340 */
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341 #define FSMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
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342 #define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
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343 /**
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344 * @}
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345 */
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346
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347 /** @defgroup FSMC_Wait_Signal FSMC Wait Signal
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348 * @{
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349 */
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350 #define FSMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
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351 #define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
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352 /**
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353 * @}
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354 */
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355
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356 /** @defgroup FSMC_Extended_Mode FSMC Extended Mode
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357 * @{
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358 */
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359 #define FSMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
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360 #define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
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361 /**
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362 * @}
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363 */
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364
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365 /** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
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366 * @{
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367 */
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368 #define FSMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
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369 #define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
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370 /**
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371 * @}
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372 */
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373
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374 /** @defgroup FSMC_Write_Burst FSMC Write Burst
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375 * @{
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376 */
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377 #define FSMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
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378 #define FSMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
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379 /**
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380 * @}
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381 */
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382
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383 /** @defgroup FSMC_Continous_Clock FSMC Continous Clock
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384 * @{
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385 */
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386 #define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
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387 #define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
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388 /**
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389 * @}
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390 */
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391
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392 /** @defgroup FSMC_Access_Mode FSMC Access Mode
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393 * @{
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394 */
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395 #define FSMC_ACCESS_MODE_A ((uint32_t)0x00000000)
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396 #define FSMC_ACCESS_MODE_B ((uint32_t)0x10000000)
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397 #define FSMC_ACCESS_MODE_C ((uint32_t)0x20000000)
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398 #define FSMC_ACCESS_MODE_D ((uint32_t)0x30000000)
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399 /**
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400 * @}
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401 */
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402 /**
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403 * @}
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404 */
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405
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406 /** @defgroup FSMC_LL_NAND_Controller FSMC NAND and PCCARD Controller
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407 * @{
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408 */
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409 /** @defgroup FSMC_NAND_Bank FSMC NAND Bank
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410 * @{
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411 */
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412 #define FSMC_NAND_BANK2 ((uint32_t)0x00000010)
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413 #define FSMC_NAND_BANK3 ((uint32_t)0x00000100)
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414 /**
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415 * @}
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416 */
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417
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418 /** @defgroup FSMC_Wait_feature FSMC Wait feature
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419 * @{
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420 */
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421 #define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
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422 #define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
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423 /**
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424 * @}
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425 */
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426
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427 /** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type
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428 * @{
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429 */
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430 #define FSMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
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431 #define FSMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
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432 /**
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433 * @}
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434 */
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435
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436 /** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width
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437 * @{
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438 */
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439 #define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
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440 #define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
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441 /**
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442 * @}
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443 */
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444
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445 /** @defgroup FSMC_ECC FSMC ECC
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446 * @{
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447 */
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448 #define FSMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
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449 #define FSMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
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450 /**
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451 * @}
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452 */
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453
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454 /** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size
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455 * @{
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456 */
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457 #define FSMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
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458 #define FSMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
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459 #define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
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460 #define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
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461 #define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
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462 #define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
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463 /**
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464 * @}
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465 */
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466 /**
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467 * @}
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468 */
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469
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470 /** @defgroup FSMC_LL_Interrupt_definition FSMC Interrupt definition
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471 * @{
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472 */
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473 #define FSMC_IT_RISING_EDGE ((uint32_t)0x00000008)
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474 #define FSMC_IT_LEVEL ((uint32_t)0x00000010)
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475 #define FSMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
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476 #define FSMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
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477 /**
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478 * @}
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479 */
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480
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481 /** @defgroup FSMC_LL_Flag_definition FSMC Flag definition
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482 * @{
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483 */
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484 #define FSMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
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485 #define FSMC_FLAG_LEVEL ((uint32_t)0x00000002)
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486 #define FSMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
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487 #define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
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488 /**
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489 * @}
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490 */
|
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491
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492 /** @defgroup FSMC_LL_Alias_definition FSMC Alias definition
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493 * @{
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494 */
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495 #define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
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496 #define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
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497 #define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
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498 #define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
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499
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500 #define FSMC_NORSRAM_DEVICE FSMC_Bank1
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501 #define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
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502 #define FSMC_NAND_DEVICE FSMC_Bank2_3
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503 #define FSMC_PCCARD_DEVICE FSMC_Bank4
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504
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505 #define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
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506 #define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
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507 #define FMC_NORSRAM_InitTypeDef FSMC_NORSRAM_InitTypeDef
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508 #define FMC_NORSRAM_TimingTypeDef FSMC_NORSRAM_TimingTypeDef
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509
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510 #define FMC_NORSRAM_Init FSMC_NORSRAM_Init
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511 #define FMC_NORSRAM_Timing_Init FSMC_NORSRAM_Timing_Init
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|
512 #define FMC_NORSRAM_Extended_Timing_Init FSMC_NORSRAM_Extended_Timing_Init
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|
513 #define FMC_NORSRAM_DeInit FSMC_NORSRAM_DeInit
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|
514 #define FMC_NORSRAM_WriteOperation_Enable FSMC_NORSRAM_WriteOperation_Enable
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|
515 #define FMC_NORSRAM_WriteOperation_Disable FSMC_NORSRAM_WriteOperation_Disable
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516
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517 #define __FMC_NORSRAM_ENABLE __FSMC_NORSRAM_ENABLE
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|
518 #define __FMC_NORSRAM_DISABLE __FSMC_NORSRAM_DISABLE
|
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519
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520 #define FMC_NAND_InitTypeDef FSMC_NAND_InitTypeDef
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521 #define FMC_PCCARD_InitTypeDef FSMC_PCCARD_InitTypeDef
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|
522 #define FMC_NAND_PCC_TimingTypeDef FSMC_NAND_PCC_TimingTypeDef
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523
|
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|
524 #define FMC_NAND_Init FSMC_NAND_Init
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|
525 #define FMC_NAND_CommonSpace_Timing_Init FSMC_NAND_CommonSpace_Timing_Init
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|
526 #define FMC_NAND_AttributeSpace_Timing_Init FSMC_NAND_AttributeSpace_Timing_Init
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527 #define FMC_NAND_DeInit FSMC_NAND_DeInit
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|
528 #define FMC_NAND_ECC_Enable FSMC_NAND_ECC_Enable
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|
529 #define FMC_NAND_ECC_Disable FSMC_NAND_ECC_Disable
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|
530 #define FMC_NAND_GetECC FSMC_NAND_GetECC
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|
531 #define FMC_PCCARD_Init FSMC_PCCARD_Init
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|
|
532 #define FMC_PCCARD_CommonSpace_Timing_Init FSMC_PCCARD_CommonSpace_Timing_Init
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|
|
533 #define FMC_PCCARD_AttributeSpace_Timing_Init FSMC_PCCARD_AttributeSpace_Timing_Init
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|
|
534 #define FMC_PCCARD_IOSpace_Timing_Init FSMC_PCCARD_IOSpace_Timing_Init
|
|
|
535 #define FMC_PCCARD_DeInit FSMC_PCCARD_DeInit
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|
536
|
|
|
537 #define __FMC_NAND_ENABLE __FSMC_NAND_ENABLE
|
|
|
538 #define __FMC_NAND_DISABLE __FSMC_NAND_DISABLE
|
|
|
539 #define __FMC_PCCARD_ENABLE __FSMC_PCCARD_ENABLE
|
|
|
540 #define __FMC_PCCARD_DISABLE __FSMC_PCCARD_DISABLE
|
|
|
541 #define __FMC_NAND_ENABLE_IT __FSMC_NAND_ENABLE_IT
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|
|
542 #define __FMC_NAND_DISABLE_IT __FSMC_NAND_DISABLE_IT
|
|
|
543 #define __FMC_NAND_GET_FLAG __FSMC_NAND_GET_FLAG
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|
544 #define __FMC_NAND_CLEAR_FLAG __FSMC_NAND_CLEAR_FLAG
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|
545 #define __FMC_PCCARD_ENABLE_IT __FSMC_PCCARD_ENABLE_IT
|
|
|
546 #define __FMC_PCCARD_DISABLE_IT __FSMC_PCCARD_DISABLE_IT
|
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|
547 #define __FMC_PCCARD_GET_FLAG __FSMC_PCCARD_GET_FLAG
|
|
|
548 #define __FMC_PCCARD_CLEAR_FLAG __FSMC_PCCARD_CLEAR_FLAG
|
|
|
549
|
|
|
550 #define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
|
|
|
551 #define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
|
|
|
552 #define FMC_NAND_TypeDef FSMC_NAND_TypeDef
|
|
|
553 #define FMC_PCCARD_TypeDef FSMC_PCCARD_TypeDef
|
|
|
554
|
|
|
555 #define FMC_NORSRAM_DEVICE FSMC_NORSRAM_DEVICE
|
|
|
556 #define FMC_NORSRAM_EXTENDED_DEVICE FSMC_NORSRAM_EXTENDED_DEVICE
|
|
|
557 #define FMC_NAND_DEVICE FSMC_NAND_DEVICE
|
|
|
558 #define FMC_PCCARD_DEVICE FSMC_PCCARD_DEVICE
|
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|
559
|
|
|
560 #define FMC_NAND_BANK2 FSMC_NAND_BANK2
|
|
|
561
|
|
|
562 #define FMC_NORSRAM_BANK1 FSMC_NORSRAM_BANK1
|
|
|
563 #define FMC_NORSRAM_BANK2 FSMC_NORSRAM_BANK2
|
|
|
564 #define FMC_NORSRAM_BANK3 FSMC_NORSRAM_BANK3
|
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|
565
|
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|
566 #define FMC_IT_RISING_EDGE FSMC_IT_RISING_EDGE
|
|
|
567 #define FMC_IT_LEVEL FSMC_IT_LEVEL
|
|
|
568 #define FMC_IT_FALLING_EDGE FSMC_IT_FALLING_EDGE
|
|
|
569 #define FMC_IT_REFRESH_ERROR FSMC_IT_REFRESH_ERROR
|
|
|
570
|
|
|
571 #define FMC_FLAG_RISING_EDGE FSMC_FLAG_RISING_EDGE
|
|
|
572 #define FMC_FLAG_LEVEL FSMC_FLAG_LEVEL
|
|
|
573 #define FMC_FLAG_FALLING_EDGE FSMC_FLAG_FALLING_EDGE
|
|
|
574 #define FMC_FLAG_FEMPT FSMC_FLAG_FEMPT
|
|
|
575 /**
|
|
|
576 * @}
|
|
|
577 */
|
|
|
578
|
|
|
579 /**
|
|
|
580 * @}
|
|
|
581 */
|
|
|
582
|
|
|
583 /* Private macro -------------------------------------------------------------*/
|
|
|
584 /** @defgroup FSMC_LL_Private_Macros FSMC Private Macros
|
|
|
585 * @{
|
|
|
586 */
|
|
|
587
|
|
|
588 /** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Exported Macros
|
|
|
589 * @brief macros to handle NOR device enable/disable and read/write operations
|
|
|
590 * @{
|
|
|
591 */
|
|
|
592 /**
|
|
|
593 * @brief Enable the NORSRAM device access.
|
|
|
594 * @param __INSTANCE__: FSMC_NORSRAM Instance
|
|
|
595 * @param __BANK__: FSMC_NORSRAM Bank
|
|
|
596 * @retval none
|
|
|
597 */
|
|
|
598 #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FSMC_BCR1_MBKEN)
|
|
|
599
|
|
|
600 /**
|
|
|
601 * @brief Disable the NORSRAM device access.
|
|
|
602 * @param __INSTANCE__: FSMC_NORSRAM Instance
|
|
|
603 * @param __BANK__: FSMC_NORSRAM Bank
|
|
|
604 * @retval none
|
|
|
605 */
|
|
|
606 #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCR1_MBKEN)
|
|
|
607 /**
|
|
|
608 * @}
|
|
|
609 */
|
|
|
610
|
|
|
611 /** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros
|
|
|
612 * @brief macros to handle NAND device enable/disable
|
|
|
613 * @{
|
|
|
614 */
|
|
|
615 /**
|
|
|
616 * @brief Enable the NAND device access.
|
|
|
617 * @param __INSTANCE__: FSMC_NAND Instance
|
|
|
618 * @param __BANK__: FSMC_NAND Bank
|
|
|
619 * @retval none
|
|
|
620 */
|
|
|
621 #define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCR2_PBKEN): \
|
|
|
622 ((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN))
|
|
|
623
|
|
|
624 /**
|
|
|
625 * @brief Disable the NAND device access.
|
|
|
626 * @param __INSTANCE__: FSMC_NAND Instance
|
|
|
627 * @param __BANK__: FSMC_NAND Bank
|
|
|
628 * @retval none
|
|
|
629 */
|
|
|
630 #define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FSMC_PCR2_PBKEN): \
|
|
|
631 ((__INSTANCE__)->PCR3 &= ~FSMC_PCR3_PBKEN))
|
|
|
632 /**
|
|
|
633 * @}
|
|
|
634 */
|
|
|
635
|
|
|
636 /** @defgroup FSMC_LL_PCCARD_Macros FSMC PCCARD Macros
|
|
|
637 * @brief macros to handle SRAM read/write operations
|
|
|
638 * @{
|
|
|
639 */
|
|
|
640 /**
|
|
|
641 * @brief Enable the PCCARD device access.
|
|
|
642 * @param __INSTANCE__: FSMC_PCCARD Instance
|
|
|
643 * @retval none
|
|
|
644 */
|
|
|
645 #define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCR4_PBKEN)
|
|
|
646
|
|
|
647 /**
|
|
|
648 * @brief Disable the PCCARD device access.
|
|
|
649 * @param __INSTANCE__: FSMC_PCCARD Instance
|
|
|
650 * @retval none
|
|
|
651 */
|
|
|
652 #define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN)
|
|
|
653 /**
|
|
|
654 * @}
|
|
|
655 */
|
|
|
656
|
|
|
657 /** @defgroup FSMC_LL_Flag_Interrupt_Macros FSMC Flag&Interrupt Macros
|
|
|
658 * @brief macros to handle FSMC flags and interrupts
|
|
|
659 * @{
|
|
|
660 */
|
|
|
661 /**
|
|
|
662 * @brief Enable the NAND device interrupt.
|
|
|
663 * @param __INSTANCE__: FSMC_NAND Instance
|
|
|
664 * @param __BANK__: FSMC_NAND Bank
|
|
|
665 * @param __INTERRUPT__: FSMC_NAND interrupt
|
|
|
666 * This parameter can be any combination of the following values:
|
|
|
667 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
|
|
|
668 * @arg FSMC_IT_LEVEL: Interrupt level.
|
|
|
669 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
|
|
|
670 * @retval None
|
|
|
671 */
|
|
|
672 #define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
|
|
|
673 ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
|
|
|
674
|
|
|
675 /**
|
|
|
676 * @brief Disable the NAND device interrupt.
|
|
|
677 * @param __INSTANCE__: FSMC_NAND Instance
|
|
|
678 * @param __BANK__: FSMC_NAND Bank
|
|
|
679 * @param __INTERRUPT__: FSMC_NAND interrupt
|
|
|
680 * This parameter can be any combination of the following values:
|
|
|
681 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
|
|
|
682 * @arg FSMC_IT_LEVEL: Interrupt level.
|
|
|
683 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
|
|
|
684 * @retval None
|
|
|
685 */
|
|
|
686 #define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
|
|
|
687 ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
|
|
|
688
|
|
|
689 /**
|
|
|
690 * @brief Get flag status of the NAND device.
|
|
|
691 * @param __INSTANCE__: FSMC_NAND Instance
|
|
|
692 * @param __BANK__ : FSMC_NAND Bank
|
|
|
693 * @param __FLAG__ : FSMC_NAND flag
|
|
|
694 * This parameter can be any combination of the following values:
|
|
|
695 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
|
|
|
696 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
|
|
|
697 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
|
|
|
698 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
|
|
|
699 * @retval The state of FLAG (SET or RESET).
|
|
|
700 */
|
|
|
701 #define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
|
|
|
702 (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
|
|
|
703 /**
|
|
|
704 * @brief Clear flag status of the NAND device.
|
|
|
705 * @param __INSTANCE__: FSMC_NAND Instance
|
|
|
706 * @param __BANK__: FSMC_NAND Bank
|
|
|
707 * @param __FLAG__: FSMC_NAND flag
|
|
|
708 * This parameter can be any combination of the following values:
|
|
|
709 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
|
|
|
710 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
|
|
|
711 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
|
|
|
712 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
|
|
|
713 * @retval None
|
|
|
714 */
|
|
|
715 #define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
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|
|
716 ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
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|
|
717 /**
|
|
|
718 * @brief Enable the PCCARD device interrupt.
|
|
|
719 * @param __INSTANCE__: FSMC_PCCARD Instance
|
|
|
720 * @param __INTERRUPT__: FSMC_PCCARD interrupt
|
|
|
721 * This parameter can be any combination of the following values:
|
|
|
722 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
|
|
|
723 * @arg FSMC_IT_LEVEL: Interrupt level.
|
|
|
724 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
|
|
|
725 * @retval None
|
|
|
726 */
|
|
|
727 #define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
|
|
|
728
|
|
|
729 /**
|
|
|
730 * @brief Disable the PCCARD device interrupt.
|
|
|
731 * @param __INSTANCE__: FSMC_PCCARD Instance
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|
|
732 * @param __INTERRUPT__: FSMC_PCCARD interrupt
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|
|
733 * This parameter can be any combination of the following values:
|
|
|
734 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
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|
|
735 * @arg FSMC_IT_LEVEL: Interrupt level.
|
|
|
736 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
|
|
|
737 * @retval None
|
|
|
738 */
|
|
|
739 #define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
|
|
|
740
|
|
|
741 /**
|
|
|
742 * @brief Get flag status of the PCCARD device.
|
|
|
743 * @param __INSTANCE__: FSMC_PCCARD Instance
|
|
|
744 * @param __FLAG__: FSMC_PCCARD flag
|
|
|
745 * This parameter can be any combination of the following values:
|
|
|
746 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
|
|
|
747 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
|
|
|
748 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
|
|
|
749 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
|
|
|
750 * @retval The state of FLAG (SET or RESET).
|
|
|
751 */
|
|
|
752 #define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
|
|
|
753
|
|
|
754 /**
|
|
|
755 * @brief Clear flag status of the PCCARD device.
|
|
|
756 * @param __INSTANCE__: FSMC_PCCARD Instance
|
|
|
757 * @param __FLAG__: FSMC_PCCARD flag
|
|
|
758 * This parameter can be any combination of the following values:
|
|
|
759 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
|
|
|
760 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
|
|
|
761 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
|
|
|
762 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
|
|
|
763 * @retval None
|
|
|
764 */
|
|
|
765 #define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
|
|
|
766 /**
|
|
|
767 * @}
|
|
|
768 */
|
|
|
769
|
|
|
770 /** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
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|
|
771 * @{
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|
|
772 */
|
|
|
773 #define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \
|
|
|
774 ((__BANK__) == FSMC_NORSRAM_BANK2) || \
|
|
|
775 ((__BANK__) == FSMC_NORSRAM_BANK3) || \
|
|
|
776 ((__BANK__) == FSMC_NORSRAM_BANK4))
|
|
|
777
|
|
|
778 #define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
|
|
|
779 ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
|
|
|
780
|
|
|
781 #define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
|
|
|
782 ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
|
|
|
783 ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
|
|
|
784
|
|
|
785 #define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \
|
|
|
786 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
|
|
|
787 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
|
|
|
788
|
|
|
789 #define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
|
|
|
790 ((__MODE__) == FSMC_ACCESS_MODE_B) || \
|
|
|
791 ((__MODE__) == FSMC_ACCESS_MODE_C) || \
|
|
|
792 ((__MODE__) == FSMC_ACCESS_MODE_D))
|
|
|
793
|
|
|
794 #define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) || \
|
|
|
795 ((BANK) == FSMC_NAND_BANK3))
|
|
|
796
|
|
|
797 #define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
|
|
|
798 ((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
|
|
|
799
|
|
|
800 #define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
|
|
|
801 ((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
|
|
|
802
|
|
|
803 #define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) || \
|
|
|
804 ((STATE) == FSMC_NAND_ECC_ENABLE))
|
|
|
805
|
|
|
806 #define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
|
|
|
807 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
|
|
|
808 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
|
|
|
809 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
|
|
|
810 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
|
|
|
811 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
|
|
|
812
|
|
|
813 #define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255)
|
|
|
814
|
|
|
815 #define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255)
|
|
|
816
|
|
|
817 #define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255)
|
|
|
818
|
|
|
819 #define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255)
|
|
|
820
|
|
|
821 #define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255)
|
|
|
822
|
|
|
823 #define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255)
|
|
|
824
|
|
|
825 #define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
|
|
|
826
|
|
|
827 #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
|
|
|
828
|
|
|
829 #define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE)
|
|
|
830
|
|
|
831 #define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE)
|
|
|
832
|
|
|
833 #define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
|
|
|
834 ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
|
|
|
835
|
|
|
836 #define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
|
|
|
837 ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
|
|
|
838
|
|
|
839 #define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
|
|
|
840 ((__MODE__) == FSMC_WRAP_MODE_ENABLE))
|
|
|
841
|
|
|
842 #define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
|
|
|
843 ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
|
|
|
844
|
|
|
845 #define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
|
|
|
846 ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
|
|
|
847
|
|
|
848 #define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
|
|
|
849 ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
|
|
|
850
|
|
|
851 #define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
|
|
|
852 ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
|
|
|
853
|
|
|
854 #define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
|
|
|
855 ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
|
|
|
856
|
|
|
857 #define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
|
|
|
858
|
|
|
859 #define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
|
|
|
860 ((__BURST__) == FSMC_WRITE_BURST_ENABLE))
|
|
|
861
|
|
|
862 #define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
|
|
|
863
|
|
|
864 #define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
|
|
|
865
|
|
|
866 #define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
|
|
|
867
|
|
|
868 #define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
|
|
|
869
|
|
|
870 #define IS_FSMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
|
|
|
871 ((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
|
|
|
872
|
|
|
873 #define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
|
|
|
874
|
|
|
875 /**
|
|
|
876 * @}
|
|
|
877 */
|
|
|
878 /**
|
|
|
879 * @}
|
|
|
880 */
|
|
|
881
|
|
|
882 /* Private functions ---------------------------------------------------------*/
|
|
|
883 /** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions
|
|
|
884 * @{
|
|
|
885 */
|
|
|
886
|
|
|
887 /** @defgroup FSMC_LL_NORSRAM NOR SRAM
|
|
|
888 * @{
|
|
|
889 */
|
|
|
890
|
|
|
891 /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
|
|
|
892 * @{
|
|
|
893 */
|
|
|
894 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init);
|
|
|
895 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
|
|
|
896 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
|
|
|
897 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
|
|
|
898 /**
|
|
|
899 * @}
|
|
|
900 */
|
|
|
901
|
|
|
902 /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
|
|
|
903 * @{
|
|
|
904 */
|
|
|
905 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
|
|
|
906 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
|
|
|
907 /**
|
|
|
908 * @}
|
|
|
909 */
|
|
|
910 /**
|
|
|
911 * @}
|
|
|
912 */
|
|
|
913
|
|
|
914 /** @defgroup FSMC_LL_NAND NAND
|
|
|
915 * @{
|
|
|
916 */
|
|
|
917 /** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
|
|
|
918 * @{
|
|
|
919 */
|
|
|
920 HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init);
|
|
|
921 HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
|
|
|
922 HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
|
|
|
923 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
|
|
|
924 /**
|
|
|
925 * @}
|
|
|
926 */
|
|
|
927
|
|
|
928 /** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions
|
|
|
929 * @{
|
|
|
930 */
|
|
|
931 HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
|
|
|
932 HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
|
|
|
933 HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
|
|
|
934 /**
|
|
|
935 * @}
|
|
|
936 */
|
|
|
937 /**
|
|
|
938 * @}
|
|
|
939 */
|
|
|
940
|
|
|
941 /** @defgroup FSMC_LL_PCCARD PCCARD
|
|
|
942 * @{
|
|
|
943 */
|
|
|
944 /** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
|
|
|
945 * @{
|
|
|
946 */
|
|
|
947 HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init);
|
|
|
948 HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
|
|
|
949 HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
|
|
|
950 HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
|
|
|
951 HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
|
|
|
952 /**
|
|
|
953 * @}
|
|
|
954 */
|
|
|
955 /**
|
|
|
956 * @}
|
|
|
957 */
|
|
|
958
|
|
|
959 /**
|
|
|
960 * @}
|
|
|
961 */
|
|
|
962 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
|
|
|
963
|
|
|
964 /**
|
|
|
965 * @}
|
|
|
966 */
|
|
|
967
|
|
|
968 /**
|
|
|
969 * @}
|
|
|
970 */
|
|
|
971
|
|
|
972 #ifdef __cplusplus
|
|
|
973 }
|
|
|
974 #endif
|
|
|
975
|
|
|
976 #endif /* __STM32F4xx_LL_FSMC_H */
|
|
|
977
|
|
|
978 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
