annotate Common/Drivers/CMSIS_v210/core_cmFunc.h @ 90:83857eb3b12b kittz

+- stable
author Dmitry Romanov <kitt@bk.ru>
date Fri, 23 Nov 2018 18:14:56 +0300
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38
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1 /**************************************************************************//**
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2 * @file core_cmFunc.h
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3 * @brief CMSIS Cortex-M Core Function Access Header File
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4 * @version V2.10
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5 * @date 26. July 2011
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6 *
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7 * @note
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8 * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
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9 *
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10 * @par
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11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
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12 * processor based microcontrollers. This file can be freely distributed
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13 * within development tools that are supporting such ARM based processors.
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14 *
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15 * @par
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16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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21 *
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22 ******************************************************************************/
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23
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24 #ifndef __CORE_CMFUNC_H
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25 #define __CORE_CMFUNC_H
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26
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27
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28 /* ########################### Core Function Access ########################### */
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29 /** \ingroup CMSIS_Core_FunctionInterface
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30 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
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31 @{
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32 */
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33
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34 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
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35 /* ARM armcc specific functions */
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36
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37 #if (__ARMCC_VERSION < 400677)
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38 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
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39 #endif
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40
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41 /* intrinsic void __enable_irq(); */
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42 /* intrinsic void __disable_irq(); */
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43
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44 /** \brief Get Control Register
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45
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46 This function returns the content of the Control Register.
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47
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48 \return Control Register value
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49 */
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50 static __INLINE uint32_t __get_CONTROL(void)
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51 {
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52 register uint32_t __regControl __ASM("control");
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53 return(__regControl);
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54 }
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55
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56
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57 /** \brief Set Control Register
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58
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59 This function writes the given value to the Control Register.
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60
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61 \param [in] control Control Register value to set
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62 */
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63 static __INLINE void __set_CONTROL(uint32_t control)
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64 {
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65 register uint32_t __regControl __ASM("control");
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66 __regControl = control;
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67 }
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68
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69
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70 /** \brief Get ISPR Register
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71
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72 This function returns the content of the ISPR Register.
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73
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74 \return ISPR Register value
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75 */
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76 static __INLINE uint32_t __get_IPSR(void)
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77 {
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78 register uint32_t __regIPSR __ASM("ipsr");
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79 return(__regIPSR);
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80 }
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81
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82
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83 /** \brief Get APSR Register
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84
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85 This function returns the content of the APSR Register.
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86
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87 \return APSR Register value
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88 */
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89 static __INLINE uint32_t __get_APSR(void)
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90 {
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91 register uint32_t __regAPSR __ASM("apsr");
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92 return(__regAPSR);
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93 }
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94
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95
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96 /** \brief Get xPSR Register
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97
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98 This function returns the content of the xPSR Register.
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99
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100 \return xPSR Register value
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101 */
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102 static __INLINE uint32_t __get_xPSR(void)
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103 {
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104 register uint32_t __regXPSR __ASM("xpsr");
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105 return(__regXPSR);
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106 }
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107
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108
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109 /** \brief Get Process Stack Pointer
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110
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111 This function returns the current value of the Process Stack Pointer (PSP).
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112
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113 \return PSP Register value
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114 */
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115 static __INLINE uint32_t __get_PSP(void)
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116 {
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117 register uint32_t __regProcessStackPointer __ASM("psp");
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118 return(__regProcessStackPointer);
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119 }
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120
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121
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122 /** \brief Set Process Stack Pointer
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123
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124 This function assigns the given value to the Process Stack Pointer (PSP).
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125
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126 \param [in] topOfProcStack Process Stack Pointer value to set
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127 */
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128 static __INLINE void __set_PSP(uint32_t topOfProcStack)
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129 {
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130 register uint32_t __regProcessStackPointer __ASM("psp");
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131 __regProcessStackPointer = topOfProcStack;
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132 }
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133
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134
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135 /** \brief Get Main Stack Pointer
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136
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137 This function returns the current value of the Main Stack Pointer (MSP).
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138
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139 \return MSP Register value
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140 */
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141 static __INLINE uint32_t __get_MSP(void)
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142 {
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143 register uint32_t __regMainStackPointer __ASM("msp");
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144 return(__regMainStackPointer);
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145 }
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146
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147
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148 /** \brief Set Main Stack Pointer
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149
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150 This function assigns the given value to the Main Stack Pointer (MSP).
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151
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152 \param [in] topOfMainStack Main Stack Pointer value to set
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153 */
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154 static __INLINE void __set_MSP(uint32_t topOfMainStack)
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155 {
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156 register uint32_t __regMainStackPointer __ASM("msp");
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157 __regMainStackPointer = topOfMainStack;
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158 }
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159
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160
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161 /** \brief Get Priority Mask
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162
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163 This function returns the current state of the priority mask bit from the Priority Mask Register.
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164
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165 \return Priority Mask value
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166 */
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167 static __INLINE uint32_t __get_PRIMASK(void)
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168 {
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169 register uint32_t __regPriMask __ASM("primask");
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170 return(__regPriMask);
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171 }
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172
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173
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174 /** \brief Set Priority Mask
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175
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176 This function assigns the given value to the Priority Mask Register.
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177
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178 \param [in] priMask Priority Mask
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179 */
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180 static __INLINE void __set_PRIMASK(uint32_t priMask)
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181 {
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182 register uint32_t __regPriMask __ASM("primask");
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183 __regPriMask = (priMask);
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184 }
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185
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186
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187 #if (__CORTEX_M >= 0x03)
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188
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189 /** \brief Enable FIQ
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190
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191 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
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192 Can only be executed in Privileged modes.
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193 */
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194 #define __enable_fault_irq __enable_fiq
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195
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196
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197 /** \brief Disable FIQ
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198
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199 This function disables FIQ interrupts by setting the F-bit in the CPSR.
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200 Can only be executed in Privileged modes.
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201 */
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202 #define __disable_fault_irq __disable_fiq
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203
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204
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205 /** \brief Get Base Priority
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206
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207 This function returns the current value of the Base Priority register.
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208
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209 \return Base Priority register value
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210 */
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211 static __INLINE uint32_t __get_BASEPRI(void)
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212 {
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213 register uint32_t __regBasePri __ASM("basepri");
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214 return(__regBasePri);
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215 }
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216
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217
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218 /** \brief Set Base Priority
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219
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220 This function assigns the given value to the Base Priority register.
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221
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222 \param [in] basePri Base Priority value to set
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223 */
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224 static __INLINE void __set_BASEPRI(uint32_t basePri)
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225 {
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226 register uint32_t __regBasePri __ASM("basepri");
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227 __regBasePri = (basePri & 0xff);
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228 }
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229
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230
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231 /** \brief Get Fault Mask
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232
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233 This function returns the current value of the Fault Mask register.
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234
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235 \return Fault Mask register value
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236 */
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237 static __INLINE uint32_t __get_FAULTMASK(void)
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238 {
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239 register uint32_t __regFaultMask __ASM("faultmask");
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240 return(__regFaultMask);
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241 }
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242
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243
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244 /** \brief Set Fault Mask
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245
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246 This function assigns the given value to the Fault Mask register.
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247
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248 \param [in] faultMask Fault Mask value to set
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249 */
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250 static __INLINE void __set_FAULTMASK(uint32_t faultMask)
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251 {
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252 register uint32_t __regFaultMask __ASM("faultmask");
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253 __regFaultMask = (faultMask & (uint32_t)1);
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254 }
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255
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256 #endif /* (__CORTEX_M >= 0x03) */
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257
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258
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259 #if (__CORTEX_M == 0x04)
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260
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261 /** \brief Get FPSCR
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262
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263 This function returns the current value of the Floating Point Status/Control register.
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264
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265 \return Floating Point Status/Control register value
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266 */
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267 static __INLINE uint32_t __get_FPSCR(void)
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268 {
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269 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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270 register uint32_t __regfpscr __ASM("fpscr");
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271 return(__regfpscr);
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272 #else
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273 return(0);
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274 #endif
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275 }
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276
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277
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278 /** \brief Set FPSCR
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279
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280 This function assigns the given value to the Floating Point Status/Control register.
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281
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282 \param [in] fpscr Floating Point Status/Control value to set
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283 */
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284 static __INLINE void __set_FPSCR(uint32_t fpscr)
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285 {
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286 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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287 register uint32_t __regfpscr __ASM("fpscr");
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288 __regfpscr = (fpscr);
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289 #endif
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290 }
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291
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292 #endif /* (__CORTEX_M == 0x04) */
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293
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294
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295 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
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296 /* IAR iccarm specific functions */
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297
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298 #include <cmsis_iar.h>
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299
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300 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
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301 /* GNU gcc specific functions */
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302
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303 /** \brief Enable IRQ Interrupts
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304
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305 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
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306 Can only be executed in Privileged modes.
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307 */
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308 __attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
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309 {
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310 __ASM volatile ("cpsie i");
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311 }
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312
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313
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314 /** \brief Disable IRQ Interrupts
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315
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316 This function disables IRQ interrupts by setting the I-bit in the CPSR.
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317 Can only be executed in Privileged modes.
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318 */
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319 __attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
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320 {
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321 __ASM volatile ("cpsid i");
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322 }
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323
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324
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325 /** \brief Get Control Register
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326
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327 This function returns the content of the Control Register.
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328
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329 \return Control Register value
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330 */
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331 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
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332 {
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333 uint32_t result;
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334
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335 __ASM volatile ("MRS %0, control" : "=r" (result) );
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336 return(result);
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337 }
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338
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339
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340 /** \brief Set Control Register
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341
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342 This function writes the given value to the Control Register.
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343
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344 \param [in] control Control Register value to set
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345 */
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346 __attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
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347 {
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348 __ASM volatile ("MSR control, %0" : : "r" (control) );
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349 }
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350
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351
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352 /** \brief Get ISPR Register
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353
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354 This function returns the content of the ISPR Register.
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355
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356 \return ISPR Register value
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357 */
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358 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
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359 {
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360 uint32_t result;
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361
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362 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
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363 return(result);
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364 }
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365
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366
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367 /** \brief Get APSR Register
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368
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369 This function returns the content of the APSR Register.
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370
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371 \return APSR Register value
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372 */
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373 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
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374 {
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375 uint32_t result;
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376
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377 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
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378 return(result);
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379 }
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380
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381
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382 /** \brief Get xPSR Register
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383
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384 This function returns the content of the xPSR Register.
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385
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386 \return xPSR Register value
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387 */
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388 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
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389 {
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390 uint32_t result;
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391
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392 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
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393 return(result);
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394 }
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395
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396
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397 /** \brief Get Process Stack Pointer
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398
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399 This function returns the current value of the Process Stack Pointer (PSP).
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400
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401 \return PSP Register value
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402 */
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403 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
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404 {
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405 register uint32_t result;
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406
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407 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
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408 return(result);
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409 }
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410
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411
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412 /** \brief Set Process Stack Pointer
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413
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414 This function assigns the given value to the Process Stack Pointer (PSP).
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415
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416 \param [in] topOfProcStack Process Stack Pointer value to set
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417 */
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418 __attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
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419 {
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420 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
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421 }
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422
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423
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424 /** \brief Get Main Stack Pointer
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425
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426 This function returns the current value of the Main Stack Pointer (MSP).
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427
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428 \return MSP Register value
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429 */
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430 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
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431 {
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432 register uint32_t result;
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433
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434 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
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435 return(result);
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436 }
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437
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438
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439 /** \brief Set Main Stack Pointer
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440
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441 This function assigns the given value to the Main Stack Pointer (MSP).
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442
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443 \param [in] topOfMainStack Main Stack Pointer value to set
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444 */
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445 __attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
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446 {
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447 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
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448 }
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449
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450
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451 /** \brief Get Priority Mask
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452
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453 This function returns the current state of the priority mask bit from the Priority Mask Register.
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454
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455 \return Priority Mask value
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456 */
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457 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
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458 {
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459 uint32_t result;
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460
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461 __ASM volatile ("MRS %0, primask" : "=r" (result) );
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462 return(result);
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463 }
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464
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465
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466 /** \brief Set Priority Mask
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467
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468 This function assigns the given value to the Priority Mask Register.
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469
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470 \param [in] priMask Priority Mask
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471 */
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472 __attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
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473 {
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474 __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
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475 }
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476
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477
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478 #if (__CORTEX_M >= 0x03)
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479
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480 /** \brief Enable FIQ
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481
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482 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
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483 Can only be executed in Privileged modes.
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484 */
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485 __attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
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486 {
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487 __ASM volatile ("cpsie f");
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488 }
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489
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490
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491 /** \brief Disable FIQ
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492
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493 This function disables FIQ interrupts by setting the F-bit in the CPSR.
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494 Can only be executed in Privileged modes.
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495 */
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496 __attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
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497 {
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498 __ASM volatile ("cpsid f");
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499 }
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500
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501
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502 /** \brief Get Base Priority
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503
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504 This function returns the current value of the Base Priority register.
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505
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506 \return Base Priority register value
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507 */
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508 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
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509 {
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510 uint32_t result;
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511
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512 __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
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513 return(result);
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514 }
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515
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516
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517 /** \brief Set Base Priority
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518
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519 This function assigns the given value to the Base Priority register.
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520
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521 \param [in] basePri Base Priority value to set
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522 */
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523 __attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
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524 {
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525 __ASM volatile ("MSR basepri, %0" : : "r" (value) );
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526 }
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527
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528
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529 /** \brief Get Fault Mask
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530
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531 This function returns the current value of the Fault Mask register.
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532
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533 \return Fault Mask register value
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534 */
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535 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
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536 {
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537 uint32_t result;
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538
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539 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
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540 return(result);
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541 }
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parents:
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542
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543
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544 /** \brief Set Fault Mask
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parents:
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545
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546 This function assigns the given value to the Fault Mask register.
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547
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parents:
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548 \param [in] faultMask Fault Mask value to set
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parents:
diff changeset
549 */
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550 __attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
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parents:
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551 {
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parents:
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552 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
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553 }
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554
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555 #endif /* (__CORTEX_M >= 0x03) */
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parents:
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556
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557
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558 #if (__CORTEX_M == 0x04)
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559
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560 /** \brief Get FPSCR
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561
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562 This function returns the current value of the Floating Point Status/Control register.
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563
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parents:
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564 \return Floating Point Status/Control register value
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parents:
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565 */
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566 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
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parents:
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567 {
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568 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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569 uint32_t result;
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570
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571 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
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parents:
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572 return(result);
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573 #else
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parents:
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574 return(0);
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575 #endif
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parents:
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576 }
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parents:
diff changeset
577
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parents:
diff changeset
578
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579 /** \brief Set FPSCR
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580
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581 This function assigns the given value to the Floating Point Status/Control register.
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582
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583 \param [in] fpscr Floating Point Status/Control value to set
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584 */
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585 __attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
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586 {
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587 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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588 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
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589 #endif
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590 }
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591
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592 #endif /* (__CORTEX_M == 0x04) */
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593
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594
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595 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
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596 /* TASKING carm specific functions */
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597
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598 /*
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599 * The CMSIS functions have been implemented as intrinsics in the compiler.
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600 * Please use "carm -?i" to get an up to date list of all instrinsics,
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601 * Including the CMSIS ones.
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602 */
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603
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604 #endif
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605
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606 /*@} end of CMSIS_Core_RegAccFunctions */
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607
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608
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609 #endif /* __CORE_CMFUNC_H */