Mercurial > public > ostc4
annotate Small_CPU/Src/uart.c @ 946:80ae8ea7f0a0 Evo_2_23
GNSS set to full power at startup:
In case of an reset the module would continue in sleep mode if it was in this state. To avoid this the module will now always set to full power at startup of the RTE.
| author | Ideenmodellierer |
|---|---|
| date | Sun, 22 Dec 2024 20:52:08 +0100 |
| parents | 3029f0332f4f |
| children |
| rev | line source |
|---|---|
| 38 | 1 /** |
| 2 ****************************************************************************** | |
| 3 * @file uart.c | |
| 4 * @author heinrichs weikamp gmbh | |
| 5 * @version V0.0.1 | |
| 6 * @date 27-March-2014 | |
| 7 * @brief button control | |
| 8 * | |
| 9 @verbatim | |
| 10 ============================================================================== | |
| 11 ##### How to use ##### | |
| 12 ============================================================================== | |
| 13 @endverbatim | |
| 14 ****************************************************************************** | |
| 15 * @attention | |
| 16 * | |
| 17 * <h2><center>© COPYRIGHT(c) 2015 heinrichs weikamp</center></h2> | |
| 18 * | |
| 19 ****************************************************************************** | |
| 20 */ | |
| 21 /* Includes ------------------------------------------------------------------*/ | |
| 22 #include "uart.h" | |
| 794 | 23 #include "uartProtocol_O2.h" |
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24 #include "uartProtocol_Co2.h" |
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25 #include "uartProtocol_Sentinel.h" |
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26 #include "uartProtocol_GNSS.h" |
| 662 | 27 #include "externalInterface.h" |
| 28 #include "data_exchange.h" | |
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29 #include <string.h> /* memset */ |
| 38 | 30 |
| 922 | 31 #ifdef ENABLE_GPIO_V2 |
| 32 extern UART_HandleTypeDef huart6; | |
| 932 | 33 extern sUartComCtrl Uart6Ctrl; |
| 922 | 34 #endif |
| 889 | 35 |
| 38 | 36 /* Private variables ---------------------------------------------------------*/ |
| 37 | |
| 922 | 38 DMA_HandleTypeDef hdma_usart1_rx, hdma_usart1_tx; |
| 38 | 39 |
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40 uint8_t rxBuffer[CHUNK_SIZE * CHUNKS_PER_BUFFER]; /* The complete buffer has a X * chunk size to allow variations in buffer read time */ |
| 936 | 41 uint8_t txBuffer[TX_BUF_SIZE]; /* tx uses less bytes */ |
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42 uint8_t txBufferQue[TX_BUF_SIZE]; /* In MUX mode command may be send shortly after each other => allow q 1 entry que */ |
| 932 | 43 |
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44 |
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45 static uint8_t lastCmdIndex; /* Index of last command which has not been completely received */ |
| 932 | 46 |
| 47 sUartComCtrl Uart1Ctrl; | |
| 48 static sUartComCtrl* pGnssCtrl = NULL; | |
| 794 | 49 |
| 921 | 50 static uint32_t LastCmdRequestTick = 0; /* Used by ADC handler to avoid interferance with UART communication */ |
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51 |
| 38 | 52 /* Exported functions --------------------------------------------------------*/ |
| 53 | |
| 932 | 54 |
| 55 void UART_SetGnssCtrl(sUartComCtrl* pTarget) | |
| 56 { | |
| 57 pGnssCtrl = pTarget; | |
| 58 } | |
| 59 | |
| 60 sUartComCtrl* UART_GetGnssCtrl() | |
| 61 { | |
| 62 return pGnssCtrl; | |
| 63 } | |
| 64 | |
| 65 | |
| 66 void UART_clearRxBuffer(sUartComCtrl* pUartCtrl) | |
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67 { |
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68 uint16_t index = 0; |
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69 do |
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70 { |
| 932 | 71 pUartCtrl->pRxBuffer[index++] = BUFFER_NODATA_LOW; |
| 72 pUartCtrl->pRxBuffer[index++] = BUFFER_NODATA_HIGH; | |
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73 } while (index < sizeof(rxBuffer)); |
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74 |
| 932 | 75 pUartCtrl->rxReadIndex = 0; |
| 76 pUartCtrl->rxWriteIndex = 0; | |
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77 } |
| 794 | 78 |
| 662 | 79 void MX_USART1_UART_Init(void) |
| 38 | 80 { |
| 662 | 81 /* regular init */ |
| 82 huart1.Instance = USART1; | |
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83 huart1.Init.BaudRate = 19200; |
| 662 | 84 huart1.Init.WordLength = UART_WORDLENGTH_8B; |
| 85 huart1.Init.StopBits = UART_STOPBITS_1; | |
| 86 huart1.Init.Parity = UART_PARITY_NONE; | |
| 87 huart1.Init.Mode = UART_MODE_TX_RX; | |
| 88 huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; | |
| 89 huart1.Init.OverSampling = UART_OVERSAMPLING_16; | |
| 90 | |
| 91 HAL_UART_Init(&huart1); | |
| 92 | |
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93 MX_USART1_DMA_Init(); |
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94 |
| 932 | 95 UART_clearRxBuffer(&Uart1Ctrl); |
| 662 | 96 lastCmdIndex = 0; |
| 932 | 97 |
| 98 Uart1Ctrl.pHandle = &huart1; | |
| 99 Uart1Ctrl.rxWriteIndex = 0; | |
| 100 Uart1Ctrl.rxReadIndex = 0; | |
| 101 Uart1Ctrl.dmaRxActive = 0; | |
| 102 Uart1Ctrl.dmaTxActive = 0; | |
| 103 Uart1Ctrl.pRxBuffer = rxBuffer; | |
| 104 Uart1Ctrl.pTxBuffer = txBuffer; | |
| 105 Uart1Ctrl.txBufferQueLen = 0; | |
| 106 | |
| 107 #ifndef ENABLE_GPIO_V2 | |
| 108 UART_SetGnssCtrl(&Uart1Ctrl); | |
| 109 #endif | |
| 662 | 110 } |
| 38 | 111 |
| 889 | 112 |
| 113 | |
| 662 | 114 void MX_USART1_UART_DeInit(void) |
| 115 { | |
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116 HAL_DMA_Abort(&hdma_usart1_rx); |
| 662 | 117 HAL_DMA_DeInit(&hdma_usart1_rx); |
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118 HAL_DMA_Abort(&hdma_usart1_tx); |
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119 HAL_DMA_DeInit(&hdma_usart1_tx); |
| 662 | 120 HAL_UART_DeInit(&huart1); |
| 932 | 121 Uart1Ctrl.dmaRxActive = 0; |
| 122 Uart1Ctrl.dmaTxActive = 0; | |
| 123 Uart1Ctrl.txBufferQueLen = 0; | |
| 662 | 124 } |
| 125 | |
| 126 void MX_USART1_DMA_Init() | |
| 127 { | |
| 128 /* DMA controller clock enable */ | |
| 129 __DMA2_CLK_ENABLE(); | |
| 130 | |
| 131 /* Peripheral DMA init*/ | |
| 132 hdma_usart1_rx.Instance = DMA2_Stream5; | |
| 133 hdma_usart1_rx.Init.Channel = DMA_CHANNEL_4; | |
| 134 hdma_usart1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; //DMA_MEMORY_TO_PERIPH; | |
| 135 hdma_usart1_rx.Init.PeriphInc = DMA_PINC_DISABLE; | |
| 136 hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE; | |
| 137 hdma_usart1_rx.Init.PeriphDataAlignment = DMA_MDATAALIGN_BYTE; | |
| 138 hdma_usart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; | |
| 139 hdma_usart1_rx.Init.Mode = DMA_NORMAL; | |
| 140 hdma_usart1_rx.Init.Priority = DMA_PRIORITY_LOW; | |
| 141 hdma_usart1_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; | |
| 142 HAL_DMA_Init(&hdma_usart1_rx); | |
| 143 | |
| 144 __HAL_LINKDMA(&huart1,hdmarx,hdma_usart1_rx); | |
| 145 | |
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146 hdma_usart1_tx.Instance = DMA2_Stream7; |
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147 hdma_usart1_tx.Init.Channel = DMA_CHANNEL_4; |
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148 hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; |
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149 hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE; |
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150 hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE; |
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151 hdma_usart1_tx.Init.PeriphDataAlignment = DMA_MDATAALIGN_BYTE; |
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152 hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; |
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153 hdma_usart1_tx.Init.Mode = DMA_NORMAL; |
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154 hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW; |
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155 hdma_usart1_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; |
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156 HAL_DMA_Init(&hdma_usart1_tx); |
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157 |
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158 __HAL_LINKDMA(&huart1,hdmatx,hdma_usart1_tx); |
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159 |
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160 |
| 662 | 161 /* DMA interrupt init */ |
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162 HAL_NVIC_SetPriority(DMA2_Stream5_IRQn, 2, 2); |
| 662 | 163 HAL_NVIC_EnableIRQ(DMA2_Stream5_IRQn); |
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164 HAL_NVIC_SetPriority(DMA2_Stream7_IRQn, 2, 1); |
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165 HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn); |
| 38 | 166 } |
| 167 | |
| 932 | 168 void UART_MUX_SelectAddress(uint8_t muxAddress) |
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169 { |
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170 uint8_t indexstr[4]; |
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171 |
| 794 | 172 if(muxAddress <= MAX_MUX_CHANNEL) |
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173 { |
| 794 | 174 indexstr[0] = '~'; |
| 175 indexstr[1] = muxAddress; | |
| 176 indexstr[2] = 0x0D; | |
| 177 indexstr[3] = 0x0A; | |
| 932 | 178 if(!Uart1Ctrl.dmaTxActive) |
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179 { |
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180 memcpy(txBuffer, indexstr, 4); |
| 932 | 181 Uart1Ctrl.dmaTxActive = 0; |
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182 if(HAL_OK == HAL_UART_Transmit_DMA(&huart1,txBuffer,4)) |
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183 { |
| 932 | 184 Uart1Ctrl.dmaTxActive = 1; |
| 185 while(Uart1Ctrl.dmaTxActive) | |
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186 { |
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187 HAL_Delay(1); |
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188 } |
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189 } |
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190 } |
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191 else |
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192 { |
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193 memcpy(txBufferQue, indexstr, 4); |
| 932 | 194 Uart1Ctrl.txBufferQueLen = 4; |
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195 } |
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196 } |
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197 } |
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198 |
| 794 | 199 |
| 200 void UART_SendCmdString(uint8_t *cmdString) | |
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201 { |
| 794 | 202 uint8_t cmdLength = strlen((char*)cmdString); |
| 203 | |
| 932 | 204 if(Uart1Ctrl.dmaTxActive == 0) |
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205 { |
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206 if(cmdLength < TX_BUF_SIZE) /* A longer string is an indication for a missing 0 termination */ |
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207 { |
| 932 | 208 if(Uart1Ctrl.dmaRxActive == 0) |
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209 { |
| 932 | 210 UART_StartDMA_Receiption(&Uart1Ctrl); |
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211 } |
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212 memcpy(txBuffer, cmdString, cmdLength); |
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213 if(HAL_OK == HAL_UART_Transmit_DMA(&huart1,txBuffer,cmdLength)) |
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214 { |
| 932 | 215 Uart1Ctrl.dmaTxActive = 1; |
| 921 | 216 LastCmdRequestTick = HAL_GetTick(); |
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217 } |
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218 } |
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219 } |
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220 else |
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221 { |
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222 memcpy(txBufferQue, cmdString, cmdLength); |
| 932 | 223 Uart1Ctrl.txBufferQueLen = cmdLength; |
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224 } |
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225 } |
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226 |
| 933 | 227 void UART_AddFletcher(uint8_t* pBuffer, uint8_t length) |
| 228 { | |
| 229 uint8_t ck_A = 0; | |
| 230 uint8_t ck_B = 0; | |
| 231 uint8_t index = 0; | |
| 232 | |
| 233 | |
| 234 pBuffer += 2; /* skip sync chars */ | |
| 235 for(index = 2; index < length; index++) | |
| 236 { | |
| 237 ck_A += *pBuffer++; | |
| 238 ck_B += ck_A; | |
| 239 } | |
| 240 *pBuffer++ = ck_A; | |
| 241 *pBuffer++ = ck_B; | |
| 242 } | |
| 243 | |
| 922 | 244 void UART_SendCmdUbx(const uint8_t *cmd, uint8_t len) |
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245 { |
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246 if(len < TX_BUF_SIZE) /* A longer string is an indication for a missing 0 termination */ |
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247 { |
| 932 | 248 if(pGnssCtrl != NULL) |
| 794 | 249 { |
| 932 | 250 if(pGnssCtrl->dmaRxActive == 0) |
| 251 { | |
| 252 UART_StartDMA_Receiption(pGnssCtrl); | |
| 253 } | |
| 254 memcpy(pGnssCtrl->pTxBuffer, cmd, len); | |
| 933 | 255 UART_AddFletcher(pGnssCtrl->pTxBuffer, len); |
| 256 len += 2; | |
| 932 | 257 if(HAL_OK == HAL_UART_Transmit_DMA(pGnssCtrl->pHandle,pGnssCtrl->pTxBuffer,len)) |
| 258 { | |
| 259 pGnssCtrl->dmaTxActive = 1; | |
| 260 LastCmdRequestTick = HAL_GetTick(); | |
| 261 } | |
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262 } |
| 794 | 263 } |
| 264 } | |
| 265 | |
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266 |
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267 void StringToInt(char *pstr, uint32_t *puInt32) |
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268 { |
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269 uint8_t index = 0; |
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270 uint32_t result = 0; |
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271 while((pstr[index] >= '0') && (pstr[index] <= '9')) |
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272 { |
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273 result *=10; |
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274 result += pstr[index] - '0'; |
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275 index++; |
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276 } |
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277 *puInt32 = result; |
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278 } |
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279 |
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280 void StringToUInt64(char *pstr, uint64_t *puint64) |
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281 { |
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282 uint8_t index = 0; |
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283 uint64_t result = 0; |
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284 while((pstr[index] >= '0') && (pstr[index] <= '9')) |
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285 { |
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286 result *=10; |
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287 result += pstr[index] - '0'; |
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288 index++; |
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289 } |
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290 *puint64 = result; |
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291 } |
| 662 | 292 |
| 932 | 293 void UART_StartDMA_Receiption(sUartComCtrl* pUartCtrl) |
| 742 | 294 { |
| 932 | 295 if(pUartCtrl->dmaRxActive == 0) |
| 742 | 296 { |
| 932 | 297 if(((pUartCtrl->rxWriteIndex / CHUNK_SIZE) != (pUartCtrl->rxReadIndex / CHUNK_SIZE)) || ((UART_isEndIndication(pUartCtrl, pUartCtrl->rxWriteIndex)) && (UART_isEndIndication(pUartCtrl, pUartCtrl->rxWriteIndex + 1)))) /* start next transfer if we did not catch up with read index */ |
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298 { |
| 932 | 299 if(HAL_OK == HAL_UART_Receive_DMA (pUartCtrl->pHandle, &pUartCtrl->pRxBuffer[pUartCtrl->rxWriteIndex], CHUNK_SIZE)) |
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300 { |
| 932 | 301 pUartCtrl->dmaRxActive = 1; |
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302 } |
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303 } |
| 742 | 304 } |
| 305 } | |
| 690 | 306 |
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307 void UART_ChangeBaudrate(uint32_t newBaudrate) |
| 38 | 308 { |
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309 MX_USART1_UART_DeInit(); |
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310 huart1.Init.BaudRate = newBaudrate; |
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311 HAL_UART_Init(&huart1); |
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312 MX_USART1_DMA_Init(); |
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313 HAL_NVIC_SetPriority(USART1_IRQn, 1, 3); |
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314 HAL_NVIC_EnableIRQ(USART1_IRQn); |
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315 |
| 932 | 316 UART_clearRxBuffer(&Uart1Ctrl); |
| 317 Uart1Ctrl.rxReadIndex = 0; | |
| 318 Uart1Ctrl.rxWriteIndex = 0; | |
| 319 Uart1Ctrl.dmaRxActive = 0; | |
| 320 Uart1Ctrl.txBufferQueLen = 0; | |
| 38 | 321 } |
| 690 | 322 |
| 932 | 323 void UART_HandleRxComplete(sUartComCtrl* pUartCtrl) |
| 324 { | |
| 325 pUartCtrl->dmaRxActive = 0; | |
| 326 pUartCtrl->rxWriteIndex+=CHUNK_SIZE; | |
| 327 if(pUartCtrl->rxWriteIndex >= CHUNK_SIZE * CHUNKS_PER_BUFFER) | |
| 328 { | |
| 329 pUartCtrl->rxWriteIndex = 0; | |
| 330 } | |
| 331 UART_StartDMA_Receiption(pUartCtrl); | |
| 332 } | |
| 662 | 333 void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) |
| 38 | 334 { |
| 932 | 335 if(huart == &huart1) |
| 336 { | |
| 337 UART_HandleRxComplete(&Uart1Ctrl); | |
| 338 } | |
| 922 | 339 #ifdef ENABLE_GPIO_V2 |
| 932 | 340 if(huart == &huart6) |
| 341 { | |
| 342 UART_HandleRxComplete(&Uart6Ctrl); | |
| 343 } | |
| 922 | 344 #endif |
| 38 | 345 } |
| 932 | 346 |
| 347 void UART_HandleTxComplete(sUartComCtrl* pUartCtrl) | |
| 348 { | |
| 349 pUartCtrl->dmaTxActive = 0; | |
| 350 UART_WriteData(pUartCtrl); | |
| 351 if(pUartCtrl->txBufferQueLen) | |
| 352 { | |
| 353 memcpy(pUartCtrl->pTxBuffer, pUartCtrl->pTxQue, pUartCtrl->txBufferQueLen); | |
| 354 HAL_UART_Transmit_DMA(pUartCtrl->pHandle,pUartCtrl->pTxBuffer,pUartCtrl->txBufferQueLen); | |
| 355 pUartCtrl->dmaTxActive = 1; | |
| 356 pUartCtrl->txBufferQueLen = 0; | |
| 357 } | |
| 358 } | |
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359 void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) |
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360 { |
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361 if(huart == &huart1) |
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362 { |
| 932 | 363 UART_HandleTxComplete(&Uart1Ctrl); |
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364 } |
| 922 | 365 #ifdef ENABLE_GPIO_V2 |
| 366 if(huart == &huart6) | |
| 367 { | |
| 932 | 368 UART_HandleTxComplete(&Uart6Ctrl); |
| 922 | 369 } |
| 370 #endif | |
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371 } |
| 38 | 372 |
| 932 | 373 uint8_t UART_isEndIndication(sUartComCtrl* pCtrl, uint8_t index) |
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374 { |
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375 uint8_t ret = 0; |
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376 if(index % 2) |
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377 { |
| 932 | 378 if(pCtrl->pRxBuffer[index] == BUFFER_NODATA_HIGH) |
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379 { |
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380 ret = 1; |
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381 } |
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382 } |
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383 else |
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384 { |
| 932 | 385 if(pCtrl->pRxBuffer[index] == BUFFER_NODATA_LOW) |
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386 { |
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387 ret = 1; |
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388 } |
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389 } |
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390 |
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391 return ret; |
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392 } |
| 794 | 393 void UART_ReadData(uint8_t sensorType) |
| 394 { | |
| 932 | 395 uint8_t localRX; |
| 396 uint8_t futureIndex; | |
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397 uint8_t moreData = 0; |
| 38 | 398 |
| 932 | 399 sUartComCtrl* pUartCtrl; |
| 400 | |
| 401 if(sensorType == SENSOR_GNSS) | |
| 402 { | |
| 403 #ifdef ENABLE_GPIO_V2 | |
| 404 pUartCtrl = &Uart6Ctrl; | |
| 405 #else | |
| 406 pUartCtrl = &Uart1Ctrl; | |
| 407 #endif | |
| 408 } | |
| 409 else | |
| 410 { | |
| 411 pUartCtrl = &Uart1Ctrl; | |
| 412 } | |
| 413 localRX = pUartCtrl->rxReadIndex; | |
| 414 futureIndex = pUartCtrl->rxReadIndex + 1; | |
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415 if(futureIndex >= CHUNK_SIZE * CHUNKS_PER_BUFFER) |
| 794 | 416 { |
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417 futureIndex = 0; |
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418 } |
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419 |
| 932 | 420 if(!UART_isEndIndication(pUartCtrl, futureIndex)) |
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421 { |
| 932 | 422 moreData = 1; |
| 423 } | |
| 424 | |
| 425 //if((!isEndIndication(pUartCtrl, localRX)) || (!isEndIndication(pUartCtrl,futureIndex))) do | |
| 426 if((!UART_isEndIndication(pUartCtrl, localRX)) || (moreData)) | |
| 427 do | |
| 428 { | |
| 429 while((!UART_isEndIndication(pUartCtrl, localRX)) || (moreData)) | |
| 794 | 430 { |
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431 moreData = 0; |
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432 switch (sensorType) |
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433 { |
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434 case SENSOR_MUX: |
| 932 | 435 case SENSOR_DIGO2: uartO2_ProcessData(pUartCtrl->pRxBuffer[localRX]); |
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436 break; |
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437 #ifdef ENABLE_CO2_SUPPORT |
| 932 | 438 case SENSOR_CO2: uartCo2_ProcessData(pUartCtrl->pRxBuffer[localRX]); |
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439 break; |
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440 #endif |
| 932 | 441 #if defined ENABLE_GNSS_SUPPORT || defined ENABLE_GPIO_V2 |
| 442 case SENSOR_GNSS: uartGnss_ProcessData(pUartCtrl->pRxBuffer[localRX]); | |
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443 break; |
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444 #endif |
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445 #ifdef ENABLE_SENTINEL_MODE |
| 932 | 446 case SENSOR_SENTINEL: uartSentinel_ProcessData(pUartCtrl->pRxBuffer[localRX]); |
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447 break; |
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448 #endif |
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449 default: |
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450 break; |
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451 } |
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452 if(localRX % 2) |
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453 { |
| 932 | 454 pUartCtrl->pRxBuffer[localRX] = BUFFER_NODATA_HIGH; |
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455 } |
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456 else |
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457 { |
| 932 | 458 pUartCtrl->pRxBuffer[localRX] = BUFFER_NODATA_LOW; |
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459 } |
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460 |
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461 localRX++; |
| 932 | 462 pUartCtrl->rxReadIndex++; |
| 463 if(pUartCtrl->rxReadIndex >= CHUNK_SIZE * CHUNKS_PER_BUFFER) | |
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464 { |
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465 localRX = 0; |
| 932 | 466 pUartCtrl->rxReadIndex = 0; |
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467 } |
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468 futureIndex++; |
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469 if(futureIndex >= CHUNK_SIZE * CHUNKS_PER_BUFFER) |
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470 { |
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471 futureIndex = 0; |
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472 } |
| 794 | 473 } |
| 932 | 474 if(!UART_isEndIndication(pUartCtrl, futureIndex)) |
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475 { |
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476 moreData = 1; |
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477 } |
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478 } while(moreData); |
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479 } |
| 794 | 480 |
| 932 | 481 void UART_WriteData(sUartComCtrl* pUartCtrl) |
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482 { |
| 932 | 483 if(pUartCtrl->pHandle->hdmatx->State == HAL_DMA_STATE_READY) |
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484 { |
| 932 | 485 pUartCtrl->pHandle->gState = HAL_UART_STATE_READY; |
| 486 pUartCtrl->dmaTxActive = 0; | |
| 794 | 487 } |
| 932 | 488 if(pUartCtrl->pHandle->hdmarx->State == HAL_DMA_STATE_READY) |
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489 { |
| 932 | 490 pUartCtrl->pHandle->RxState = HAL_UART_STATE_READY; |
| 491 pUartCtrl->dmaRxActive = 0; | |
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492 } |
| 794 | 493 } |
| 494 | |
| 495 void UART_FlushRxBuffer(void) | |
| 496 { | |
| 932 | 497 uint8_t futureIndex = Uart1Ctrl.rxReadIndex + 1; |
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498 |
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499 if(futureIndex >= CHUNK_SIZE * CHUNKS_PER_BUFFER) |
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500 { |
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501 futureIndex = 0; |
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502 } |
| 932 | 503 while((rxBuffer[Uart1Ctrl.rxReadIndex] != BUFFER_NODATA_LOW) && (rxBuffer[futureIndex] != BUFFER_NODATA_HIGH)) |
| 794 | 504 { |
| 932 | 505 if(Uart1Ctrl.rxReadIndex % 2) |
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506 { |
| 932 | 507 rxBuffer[Uart1Ctrl.rxReadIndex++] = BUFFER_NODATA_HIGH; |
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508 } |
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509 else |
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510 { |
| 932 | 511 rxBuffer[Uart1Ctrl.rxReadIndex++] = BUFFER_NODATA_LOW; |
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512 } |
| 932 | 513 if(Uart1Ctrl.rxReadIndex >= CHUNK_SIZE * CHUNKS_PER_BUFFER) |
| 794 | 514 { |
| 932 | 515 Uart1Ctrl.rxReadIndex = 0; |
| 794 | 516 } |
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517 futureIndex++; |
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518 if(futureIndex >= CHUNK_SIZE * CHUNKS_PER_BUFFER) |
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519 { |
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520 futureIndex = 0; |
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521 } |
| 794 | 522 } |
| 523 } | |
| 662 | 524 |
| 861 | 525 uint8_t UART_isComActive(uint8_t sensorId) |
| 526 { | |
| 527 uint8_t active = 1; | |
| 809 | 528 |
| 921 | 529 if(time_elapsed_ms(LastCmdRequestTick, HAL_GetTick()) > 300) /* UART activity should be inactive 300ms after last command */ |
| 861 | 530 { |
| 531 active = 0; | |
| 532 } | |
| 533 return active; | |
| 534 } | |
| 809 | 535 |
| 921 | 536 |
| 38 | 537 /************************ (C) COPYRIGHT heinrichs weikamp *****END OF FILE****/ |