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annotate Common/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sdram.h @ 946:80ae8ea7f0a0 Evo_2_23

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GNSS set to full power at startup: In case of an reset the module would continue in sleep mode if it was in this state. To avoid this the module will now always set to full power at startup of the RTE.
author Ideenmodellierer
date Sun, 22 Dec 2024 20:52:08 +0100
parents c78bcbd5deda
children
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1 /**
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2 ******************************************************************************
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3 * @file stm32f4xx_hal_sdram.h
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4 * @author MCD Application Team
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5 * @brief Header file of SDRAM HAL module.
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6 ******************************************************************************
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7 * @attention
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8 *
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9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
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10 *
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11 * Redistribution and use in source and binary forms, with or without modification,
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12 * are permitted provided that the following conditions are met:
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13 * 1. Redistributions of source code must retain the above copyright notice,
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14 * this list of conditions and the following disclaimer.
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15 * 2. Redistributions in binary form must reproduce the above copyright notice,
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16 * this list of conditions and the following disclaimer in the documentation
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17 * and/or other materials provided with the distribution.
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18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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19 * may be used to endorse or promote products derived from this software
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20 * without specific prior written permission.
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21 *
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22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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32 *
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33 ******************************************************************************
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34 */
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35
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36 /* Define to prevent recursive inclusion -------------------------------------*/
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37 #ifndef __STM32F4xx_HAL_SDRAM_H
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38 #define __STM32F4xx_HAL_SDRAM_H
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39
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40 #ifdef __cplusplus
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41 extern "C" {
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42 #endif
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43
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44 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
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45 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
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46
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47 /* Includes ------------------------------------------------------------------*/
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48 #include "stm32f4xx_ll_fmc.h"
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49
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50 /** @addtogroup STM32F4xx_HAL_Driver
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51 * @{
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52 */
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53
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54 /** @addtogroup SDRAM
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55 * @{
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56 */
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57
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58 /* Exported typedef ----------------------------------------------------------*/
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59 /** @defgroup SDRAM_Exported_Types SDRAM Exported Types
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60 * @{
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61 */
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62
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63 /**
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64 * @brief HAL SDRAM State structure definition
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65 */
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66 typedef enum
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67 {
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68 HAL_SDRAM_STATE_RESET = 0x00U, /*!< SDRAM not yet initialized or disabled */
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69 HAL_SDRAM_STATE_READY = 0x01U, /*!< SDRAM initialized and ready for use */
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70 HAL_SDRAM_STATE_BUSY = 0x02U, /*!< SDRAM internal process is ongoing */
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71 HAL_SDRAM_STATE_ERROR = 0x03U, /*!< SDRAM error state */
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72 HAL_SDRAM_STATE_WRITE_PROTECTED = 0x04U, /*!< SDRAM device write protected */
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73 HAL_SDRAM_STATE_PRECHARGED = 0x05U /*!< SDRAM device precharged */
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74
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75 }HAL_SDRAM_StateTypeDef;
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76
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77 /**
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78 * @brief SDRAM handle Structure definition
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79 */
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80 typedef struct
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81 {
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82 FMC_SDRAM_TypeDef *Instance; /*!< Register base address */
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83
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84 FMC_SDRAM_InitTypeDef Init; /*!< SDRAM device configuration parameters */
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85
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86 __IO HAL_SDRAM_StateTypeDef State; /*!< SDRAM access state */
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87
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88 HAL_LockTypeDef Lock; /*!< SDRAM locking object */
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89
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90 DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
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91
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92 }SDRAM_HandleTypeDef;
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93 /**
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94 * @}
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95 */
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96
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97 /* Exported constants --------------------------------------------------------*/
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98 /* Exported macro ------------------------------------------------------------*/
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99 /** @defgroup SDRAM_Exported_Macros SDRAM Exported Macros
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100 * @{
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101 */
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102
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103 /** @brief Reset SDRAM handle state
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104 * @param __HANDLE__ specifies the SDRAM handle.
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105 * @retval None
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106 */
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107 #define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET)
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108 /**
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109 * @}
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110 */
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111
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112 /* Exported functions --------------------------------------------------------*/
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113 /** @addtogroup SDRAM_Exported_Functions SDRAM Exported Functions
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114 * @{
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115 */
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116
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117 /** @addtogroup SDRAM_Exported_Functions_Group1
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118 * @{
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119 */
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120
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121 /* Initialization/de-initialization functions *********************************/
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122 HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing);
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123 HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram);
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124 void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram);
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125 void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram);
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126
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127 void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram);
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128 void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram);
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129 void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
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130 void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
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131 /**
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132 * @}
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133 */
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134
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135 /** @addtogroup SDRAM_Exported_Functions_Group2
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136 * @{
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137 */
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138 /* I/O operation functions ****************************************************/
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139 HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
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140 HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
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141 HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
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142 HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
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143 HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
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144 HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
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145
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146 HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t * pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
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147 HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
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148 /**
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149 * @}
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150 */
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151
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152 /** @addtogroup SDRAM_Exported_Functions_Group3
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153 * @{
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154 */
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155 /* SDRAM Control functions *****************************************************/
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156 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram);
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157 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram);
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158 HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
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159 HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate);
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160 HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber);
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161 uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram);
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162 /**
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163 * @}
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164 */
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165
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166 /** @addtogroup SDRAM_Exported_Functions_Group4
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167 * @{
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168 */
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169 /* SDRAM State functions ********************************************************/
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170 HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram);
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171 /**
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172 * @}
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173 */
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174
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175 /**
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176 * @}
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177 */
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178
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179 /**
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180 * @}
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181 */
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182
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183 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
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184
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185 /**
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186 * @}
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187 */
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188
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189 #ifdef __cplusplus
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190 }
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191 #endif
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192
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193 #endif /* __STM32F4xx_HAL_SDRAM_H */
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194
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195 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/