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annotate Common/Drivers/STM32F4xx/Source/Templates/arm/startup_stm32f411xe.s @ 946:80ae8ea7f0a0 Evo_2_23

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GNSS set to full power at startup: In case of an reset the module would continue in sleep mode if it was in this state. To avoid this the module will now always set to full power at startup of the RTE.
author Ideenmodellierer
date Sun, 22 Dec 2024 20:52:08 +0100
parents c78bcbd5deda
children
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1 ;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
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2 ;* File Name : startup_stm32f411xe.s
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3 ;* Author : MCD Application Team
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4 ;* Description : STM32F411xExx devices vector table for MDK-ARM toolchain.
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5 ;* This module performs:
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6 ;* - Set the initial SP
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7 ;* - Set the initial PC == Reset_Handler
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8 ;* - Set the vector table entries with the exceptions ISR address
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9 ;* - Branches to __main in the C library (which eventually
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10 ;* calls main()).
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11 ;* After Reset the CortexM4 processor is in Thread mode,
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12 ;* priority is Privileged, and the Stack is set to Main.
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13 ;* <<< Use Configuration Wizard in Context Menu >>>
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14 ;*******************************************************************************
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15 ;
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16 ;* Redistribution and use in source and binary forms, with or without modification,
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17 ;* are permitted provided that the following conditions are met:
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18 ;* 1. Redistributions of source code must retain the above copyright notice,
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19 ;* this list of conditions and the following disclaimer.
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20 ;* 2. Redistributions in binary form must reproduce the above copyright notice,
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21 ;* this list of conditions and the following disclaimer in the documentation
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22 ;* and/or other materials provided with the distribution.
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23 ;* 3. Neither the name of STMicroelectronics nor the names of its contributors
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24 ;* may be used to endorse or promote products derived from this software
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25 ;* without specific prior written permission.
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26 ;*
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27 ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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28 ;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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29 ;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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30 ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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31 ;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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32 ;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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33 ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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34 ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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35 ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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36 ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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37 ;
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38 ;*******************************************************************************
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39
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40 ; Amount of memory (in bytes) allocated for Stack
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41 ; Tailor this value to your application needs
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42 ; <h> Stack Configuration
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43 ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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44 ; </h>
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45
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46 Stack_Size EQU 0x00000400
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47
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48 AREA STACK, NOINIT, READWRITE, ALIGN=3
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49 Stack_Mem SPACE Stack_Size
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50 __initial_sp
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51
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52
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53 ; <h> Heap Configuration
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54 ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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55 ; </h>
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56
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57 Heap_Size EQU 0x00000200
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58
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59 AREA HEAP, NOINIT, READWRITE, ALIGN=3
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60 __heap_base
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61 Heap_Mem SPACE Heap_Size
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62 __heap_limit
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63
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64 PRESERVE8
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65 THUMB
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66
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67
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68 ; Vector Table Mapped to Address 0 at Reset
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69 AREA RESET, DATA, READONLY
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70 EXPORT __Vectors
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71 EXPORT __Vectors_End
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72 EXPORT __Vectors_Size
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73
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74 __Vectors DCD __initial_sp ; Top of Stack
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75 DCD Reset_Handler ; Reset Handler
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76 DCD NMI_Handler ; NMI Handler
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77 DCD HardFault_Handler ; Hard Fault Handler
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78 DCD MemManage_Handler ; MPU Fault Handler
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79 DCD BusFault_Handler ; Bus Fault Handler
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80 DCD UsageFault_Handler ; Usage Fault Handler
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81 DCD 0 ; Reserved
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82 DCD 0 ; Reserved
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83 DCD 0 ; Reserved
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84 DCD 0 ; Reserved
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85 DCD SVC_Handler ; SVCall Handler
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86 DCD DebugMon_Handler ; Debug Monitor Handler
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87 DCD 0 ; Reserved
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88 DCD PendSV_Handler ; PendSV Handler
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89 DCD SysTick_Handler ; SysTick Handler
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90
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91 ; External Interrupts
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92 DCD WWDG_IRQHandler ; Window WatchDog
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93 DCD PVD_IRQHandler ; PVD through EXTI Line detection
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94 DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
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95 DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
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96 DCD FLASH_IRQHandler ; FLASH
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97 DCD RCC_IRQHandler ; RCC
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98 DCD EXTI0_IRQHandler ; EXTI Line0
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99 DCD EXTI1_IRQHandler ; EXTI Line1
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100 DCD EXTI2_IRQHandler ; EXTI Line2
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101 DCD EXTI3_IRQHandler ; EXTI Line3
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102 DCD EXTI4_IRQHandler ; EXTI Line4
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103 DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
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104 DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
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105 DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
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106 DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
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107 DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
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108 DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
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109 DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
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110 DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
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111 DCD 0 ; Reserved
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112 DCD 0 ; Reserved
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113 DCD 0 ; Reserved
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114 DCD 0 ; Reserved
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115 DCD EXTI9_5_IRQHandler ; External Line[9:5]s
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116 DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
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117 DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
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118 DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
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119 DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
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120 DCD TIM2_IRQHandler ; TIM2
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121 DCD TIM3_IRQHandler ; TIM3
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122 DCD TIM4_IRQHandler ; TIM4
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123 DCD I2C1_EV_IRQHandler ; I2C1 Event
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124 DCD I2C1_ER_IRQHandler ; I2C1 Error
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125 DCD I2C2_EV_IRQHandler ; I2C2 Event
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126 DCD I2C2_ER_IRQHandler ; I2C2 Error
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127 DCD SPI1_IRQHandler ; SPI1
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128 DCD SPI2_IRQHandler ; SPI2
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129 DCD USART1_IRQHandler ; USART1
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130 DCD USART2_IRQHandler ; USART2
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131 DCD 0 ; Reserved
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132 DCD EXTI15_10_IRQHandler ; External Line[15:10]s
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133 DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
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134 DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
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135 DCD 0 ; Reserved
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136 DCD 0 ; Reserved
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137 DCD 0 ; Reserved
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138 DCD 0 ; Reserved
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139 DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
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140 DCD 0 ; Reserved
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141 DCD SDIO_IRQHandler ; SDIO
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142 DCD TIM5_IRQHandler ; TIM5
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143 DCD SPI3_IRQHandler ; SPI3
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144 DCD 0 ; Reserved
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145 DCD 0 ; Reserved
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146 DCD 0 ; Reserved
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147 DCD 0 ; Reserved
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148 DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
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149 DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
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150 DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
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151 DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
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152 DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
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153 DCD 0 ; Reserved
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154 DCD 0 ; Reserved
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155 DCD 0 ; Reserved
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156 DCD 0 ; Reserved
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157 DCD 0 ; Reserved
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158 DCD 0 ; Reserved
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159 DCD OTG_FS_IRQHandler ; USB OTG FS
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160 DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
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161 DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
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162 DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
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163 DCD USART6_IRQHandler ; USART6
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164 DCD I2C3_EV_IRQHandler ; I2C3 event
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165 DCD I2C3_ER_IRQHandler ; I2C3 error
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166 DCD 0 ; Reserved
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167 DCD 0 ; Reserved
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168 DCD 0 ; Reserved
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169 DCD 0 ; Reserved
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170 DCD 0 ; Reserved
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171 DCD 0 ; Reserved
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172 DCD 0 ; Reserved
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173 DCD FPU_IRQHandler ; FPU
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174 DCD 0 ; Reserved
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175 DCD 0 ; Reserved
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176 DCD SPI4_IRQHandler ; SPI4
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177 DCD SPI5_IRQHandler ; SPI5
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178
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179 __Vectors_End
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180
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181 __Vectors_Size EQU __Vectors_End - __Vectors
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182
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183 AREA |.text|, CODE, READONLY
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184
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185 ; Reset handler
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186 Reset_Handler PROC
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187 EXPORT Reset_Handler [WEAK]
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188 IMPORT SystemInit
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189 IMPORT __main
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190
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191 LDR R0, =SystemInit
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192 BLX R0
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193 LDR R0, =__main
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194 BX R0
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195 ENDP
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196
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197 ; Dummy Exception Handlers (infinite loops which can be modified)
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198
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199 NMI_Handler PROC
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200 EXPORT NMI_Handler [WEAK]
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201 B .
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202 ENDP
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203 HardFault_Handler\
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204 PROC
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205 EXPORT HardFault_Handler [WEAK]
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206 B .
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207 ENDP
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208 MemManage_Handler\
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209 PROC
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210 EXPORT MemManage_Handler [WEAK]
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211 B .
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212 ENDP
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213 BusFault_Handler\
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214 PROC
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215 EXPORT BusFault_Handler [WEAK]
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216 B .
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217 ENDP
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218 UsageFault_Handler\
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219 PROC
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220 EXPORT UsageFault_Handler [WEAK]
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221 B .
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222 ENDP
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223 SVC_Handler PROC
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224 EXPORT SVC_Handler [WEAK]
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225 B .
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226 ENDP
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227 DebugMon_Handler\
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228 PROC
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229 EXPORT DebugMon_Handler [WEAK]
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230 B .
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231 ENDP
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232 PendSV_Handler PROC
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233 EXPORT PendSV_Handler [WEAK]
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234 B .
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235 ENDP
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236 SysTick_Handler PROC
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237 EXPORT SysTick_Handler [WEAK]
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238 B .
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239 ENDP
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240
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241 Default_Handler PROC
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242
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243 EXPORT WWDG_IRQHandler [WEAK]
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244 EXPORT PVD_IRQHandler [WEAK]
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245 EXPORT TAMP_STAMP_IRQHandler [WEAK]
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246 EXPORT RTC_WKUP_IRQHandler [WEAK]
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247 EXPORT FLASH_IRQHandler [WEAK]
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248 EXPORT RCC_IRQHandler [WEAK]
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249 EXPORT EXTI0_IRQHandler [WEAK]
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250 EXPORT EXTI1_IRQHandler [WEAK]
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251 EXPORT EXTI2_IRQHandler [WEAK]
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252 EXPORT EXTI3_IRQHandler [WEAK]
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253 EXPORT EXTI4_IRQHandler [WEAK]
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254 EXPORT DMA1_Stream0_IRQHandler [WEAK]
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255 EXPORT DMA1_Stream1_IRQHandler [WEAK]
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256 EXPORT DMA1_Stream2_IRQHandler [WEAK]
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257 EXPORT DMA1_Stream3_IRQHandler [WEAK]
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258 EXPORT DMA1_Stream4_IRQHandler [WEAK]
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259 EXPORT DMA1_Stream5_IRQHandler [WEAK]
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260 EXPORT DMA1_Stream6_IRQHandler [WEAK]
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261 EXPORT ADC_IRQHandler [WEAK]
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262 EXPORT EXTI9_5_IRQHandler [WEAK]
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263 EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
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264 EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
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265 EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
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266 EXPORT TIM1_CC_IRQHandler [WEAK]
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267 EXPORT TIM2_IRQHandler [WEAK]
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268 EXPORT TIM3_IRQHandler [WEAK]
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269 EXPORT TIM4_IRQHandler [WEAK]
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270 EXPORT I2C1_EV_IRQHandler [WEAK]
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271 EXPORT I2C1_ER_IRQHandler [WEAK]
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272 EXPORT I2C2_EV_IRQHandler [WEAK]
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273 EXPORT I2C2_ER_IRQHandler [WEAK]
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274 EXPORT SPI1_IRQHandler [WEAK]
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275 EXPORT SPI2_IRQHandler [WEAK]
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276 EXPORT USART1_IRQHandler [WEAK]
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277 EXPORT USART2_IRQHandler [WEAK]
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278 EXPORT EXTI15_10_IRQHandler [WEAK]
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279 EXPORT RTC_Alarm_IRQHandler [WEAK]
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280 EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
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281 EXPORT DMA1_Stream7_IRQHandler [WEAK]
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282 EXPORT SDIO_IRQHandler [WEAK]
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283 EXPORT TIM5_IRQHandler [WEAK]
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284 EXPORT SPI3_IRQHandler [WEAK]
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285 EXPORT DMA2_Stream0_IRQHandler [WEAK]
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286 EXPORT DMA2_Stream1_IRQHandler [WEAK]
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287 EXPORT DMA2_Stream2_IRQHandler [WEAK]
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288 EXPORT DMA2_Stream3_IRQHandler [WEAK]
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289 EXPORT DMA2_Stream4_IRQHandler [WEAK]
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290 EXPORT OTG_FS_IRQHandler [WEAK]
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291 EXPORT DMA2_Stream5_IRQHandler [WEAK]
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292 EXPORT DMA2_Stream6_IRQHandler [WEAK]
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293 EXPORT DMA2_Stream7_IRQHandler [WEAK]
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294 EXPORT USART6_IRQHandler [WEAK]
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295 EXPORT I2C3_EV_IRQHandler [WEAK]
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296 EXPORT I2C3_ER_IRQHandler [WEAK]
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297 EXPORT FPU_IRQHandler [WEAK]
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298 EXPORT SPI4_IRQHandler [WEAK]
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299 EXPORT SPI5_IRQHandler [WEAK]
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300
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301 WWDG_IRQHandler
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302 PVD_IRQHandler
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303 TAMP_STAMP_IRQHandler
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304 RTC_WKUP_IRQHandler
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305 FLASH_IRQHandler
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306 RCC_IRQHandler
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307 EXTI0_IRQHandler
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308 EXTI1_IRQHandler
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309 EXTI2_IRQHandler
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310 EXTI3_IRQHandler
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311 EXTI4_IRQHandler
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312 DMA1_Stream0_IRQHandler
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313 DMA1_Stream1_IRQHandler
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314 DMA1_Stream2_IRQHandler
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315 DMA1_Stream3_IRQHandler
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316 DMA1_Stream4_IRQHandler
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317 DMA1_Stream5_IRQHandler
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318 DMA1_Stream6_IRQHandler
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319 ADC_IRQHandler
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320 EXTI9_5_IRQHandler
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321 TIM1_BRK_TIM9_IRQHandler
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322 TIM1_UP_TIM10_IRQHandler
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323 TIM1_TRG_COM_TIM11_IRQHandler
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324 TIM1_CC_IRQHandler
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325 TIM2_IRQHandler
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326 TIM3_IRQHandler
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327 TIM4_IRQHandler
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328 I2C1_EV_IRQHandler
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329 I2C1_ER_IRQHandler
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330 I2C2_EV_IRQHandler
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331 I2C2_ER_IRQHandler
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332 SPI1_IRQHandler
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333 SPI2_IRQHandler
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334 USART1_IRQHandler
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335 USART2_IRQHandler
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336 EXTI15_10_IRQHandler
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337 RTC_Alarm_IRQHandler
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338 OTG_FS_WKUP_IRQHandler
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339 DMA1_Stream7_IRQHandler
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340 SDIO_IRQHandler
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341 TIM5_IRQHandler
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342 SPI3_IRQHandler
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343 DMA2_Stream0_IRQHandler
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344 DMA2_Stream1_IRQHandler
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345 DMA2_Stream2_IRQHandler
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346 DMA2_Stream3_IRQHandler
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347 DMA2_Stream4_IRQHandler
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348 OTG_FS_IRQHandler
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349 DMA2_Stream5_IRQHandler
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350 DMA2_Stream6_IRQHandler
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351 DMA2_Stream7_IRQHandler
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352 USART6_IRQHandler
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353 I2C3_EV_IRQHandler
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354 I2C3_ER_IRQHandler
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355 FPU_IRQHandler
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356 SPI4_IRQHandler
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357 SPI5_IRQHandler
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358
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359 B .
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360
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361 ENDP
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362
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363 ALIGN
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364
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365 ;*******************************************************************************
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366 ; User Stack and Heap initialization
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367 ;*******************************************************************************
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368 IF :DEF:__MICROLIB
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369
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370 EXPORT __initial_sp
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371 EXPORT __heap_base
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372 EXPORT __heap_limit
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373
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374 ELSE
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375
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376 IMPORT __use_two_region_memory
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377 EXPORT __user_initial_stackheap
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378
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379 __user_initial_stackheap
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380
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381 LDR R0, = Heap_Mem
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382 LDR R1, =(Stack_Mem + Stack_Size)
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383 LDR R2, = (Heap_Mem + Heap_Size)
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384 LDR R3, = Stack_Mem
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385 BX LR
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386
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387 ALIGN
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388
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389 ENDIF
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390
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391 END
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392
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393 ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****